A signal processing device and a low interference charge amplifier thereof

Abstract

The application discloses a charge amplifier for reducing interference, which comprises a first operational amplifier and a first capacitor for constituting a positive charge converter, a second operational amplifier and a second capacitor for constituting a negative charge converter, a differential superposition circuit connected with the output end of the first operational amplifier, the output end of the second operational amplifier and a reference end respectively and used for performing differential voltage summation, a differential mode negative feedback circuit connected with the output end of the differential superposition circuit and the inverting input end of the first operational amplifier and used for suppressing differential mode interference through negative feedback, and a common mode negative feedback circuit connected with the output end of the first operational amplifier, the output end of the second operational amplifier, the inverting input end of the first operational amplifier and the inverting input end of the second operational amplifier respectively and used for reducing common mode input current through the negative feedback current of the output. The application can effectively reduce common mode interference and differential mode interference, and has a simple structure. The application also discloses a signal processing device, which has corresponding technical effects.

Description

Technical Field

[0001] This invention relates to the field of circuit technology, and in particular to a signal processing device and its interference-reducing charge amplifier. Background Technology

[0002] Classical differential charge amplifiers suffer from significant operating point drift due to parameter asymmetry between the positive and negative charge amplifiers and thermal misalignment. Furthermore, when the piezoelectric sensor is independently mounted at the far end of the charge amplifier, common-mode interference from the environment can easily enter the subsequent charge amplifier through the distributed capacitances CZ1 and CZ2 between the cable connecting the piezoelectric sensor and the interfering electric field. This interference signal may directly limit the charge amplifier's output. Moreover, differential-mode interference can also occur when the distributed capacitance between the cable transmitting the piezoelectric sensor and the external interference source is asymmetrical.

[0003] Currently, low-frequency differential-mode interference is reduced by improving device precision and adding filters, but this is costly and cannot be widely used in engineering processes. Furthermore, filters increase the low-frequency response frequency when suppressing low-frequency differential-mode interference, thus reducing bandwidth.

[0004] In summary, how to effectively reduce common-mode interference and differential-mode interference is a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0005] The purpose of this invention is to provide a signal processing device and its interference-reducing charge amplifier to effectively reduce common-mode interference and differential-mode interference.

[0006] To solve the above-mentioned technical problems, the present invention provides the following technical solution:

[0007] An interference-reducing charge amplifier, comprising:

[0008] The first operational amplifier has an inverting input terminal as a positive charge input terminal and is connected to the first terminal of the preceding circuit and the first terminal of the first capacitor, respectively. The non-inverting input terminal is used as a reference terminal and is connected to the non-inverting input terminal of the second operational amplifier. The output terminal is connected to the second terminal of the first capacitor.

[0009] The second operational amplifier has an inverting input terminal as a negative charge input terminal and is connected to the first terminal of the pre-stage circuit and the second capacitor, respectively, and its output terminal is connected to the second terminal of the second capacitor.

[0010] The first capacitor, the second capacitor;

[0011] The first input terminal is connected to the output terminal of the first operational amplifier, the second input terminal is connected to the output terminal of the second operational amplifier, and the third input terminal is connected to the reference terminal, forming a differential superposition circuit for performing differential voltage summation;

[0012] The input terminal is connected to the output terminal of the differential superposition circuit, and the output terminal is connected to the inverting input terminal of the first operational amplifier, forming a differential mode negative feedback circuit for suppressing differential mode interference through negative feedback.

[0013] The first input terminal is connected to the output terminal of the first operational amplifier, the second input terminal is connected to the output terminal of the second operational amplifier, the first output terminal is connected to the inverting input terminal of the first operational amplifier, and the second output terminal is connected to the inverting input terminal of the second operational amplifier, forming a common-mode negative feedback circuit for reducing the common-mode input current through the output negative feedback current.

[0014] Preferably, the differential-mode negative feedback circuit includes:

[0015] The first terminal is connected to the inverting input terminal of the first operational amplifier, and the second terminal is connected to the fifth resistor at the output terminal of the differential superposition circuit.

[0016] Preferably, the differential-mode negative feedback circuit further includes:

[0017] The first end is connected to the second end of the fifth resistor, and the second end is connected to the sixth resistor, which is connected to the output end of the differential superposition circuit.

[0018] A first RC circuit, wherein the first terminal of the first RC circuit is connected to the second terminal of the fifth resistor and the first terminal of the sixth resistor respectively, and the second terminal of the first RC circuit is connected to the reference terminal.

[0019] Preferably, the first RC circuit includes:

[0020] The first end serves as the first end of the first RC circuit, and the second end is connected to the third capacitor, which is connected to the first end of the seventh resistor.

[0021] The seventh resistor serves as the second terminal of the first RC circuit.

[0022] Preferably, the differential superposition circuit includes:

[0023] The first terminal serves as the first input terminal of the differential superposition circuit, and the second terminal is connected to the eighth resistor, which is connected to the non-inverting input terminal of the third operational amplifier.

[0024] The first terminal serves as the third input terminal of the differential superposition circuit, and the second terminal is connected to the ninth resistor, which is connected to the non-inverting input terminal of the third operational amplifier.

[0025] The first terminal serves as the second input terminal of the differential superposition circuit, and the second terminal is connected to the tenth resistor of the inverting input terminal of the third operational amplifier.

[0026] The eleventh resistor, whose first end is connected to the second end of the tenth resistor;

[0027] The third operational amplifier has its output terminal connected to the second terminal of the eleventh resistor, and the connection terminal serves as the output terminal of the differential superposition circuit.

[0028] Preferably, the common-mode negative feedback circuit includes:

[0029] The first terminal is connected to the inverting input terminal of the first operational amplifier, and the second terminal is connected to the first terminal of the second resistor, the second terminal of the third resistor, and the first terminal of the fourth resistor, respectively.

[0030] The second terminal is connected to the second resistor, which is connected to the inverting input terminal of the second operational amplifier.

[0031] The third resistor whose first terminal is connected to the output terminal of the first operational amplifier;

[0032] The fourth resistor is connected at its second terminal to the output terminal of the second operational amplifier.

[0033] Preferred options also include:

[0034] A second RC circuit is disposed between the preamplifier circuit and the inverting input terminal of the first operational amplifier;

[0035] A third RC circuit is disposed between the preamplifier circuit and the inverting input of the second operational amplifier.

[0036] Preferably, the second RC circuit includes a fourth capacitor and a twelfth resistor, and the third RC circuit includes a fifth capacitor and a thirteenth resistor.

[0037] The first terminal of the fourth capacitor serves as the first terminal of the second RC circuit and is connected to the preamplifier circuit. The second terminal of the fourth capacitor is connected to the first terminal of the twelfth resistor. The second terminal of the twelfth resistor serves as the second terminal of the second RC circuit and is connected to the inverting input terminal of the first operational amplifier.

[0038] The first terminal of the fifth capacitor serves as the first terminal of the third RC circuit and is connected to the preamplifier circuit. The second terminal of the fifth capacitor is connected to the first terminal of the thirteenth resistor. The second terminal of the thirteenth resistor serves as the second terminal of the third RC circuit and is connected to the inverting input terminal of the second operational amplifier.

[0039] When the first terminal of the fourth capacitor is connected to the first terminal of the first resistor, the first terminal of the fifth capacitor is connected to the second terminal of the second resistor; when the second terminal of the fourth capacitor is connected to the first terminal of the first resistor, the second terminal of the fifth capacitor is connected to the second terminal of the second resistor; when the second terminal of the twelfth resistor is connected to the first terminal of the first resistor, the second terminal of the thirteenth resistor is connected to the second terminal of the second resistor.

[0040] Preferably, it also includes: a sixth capacitor and a seventh capacitor;

[0041] The second terminal of the sixth capacitor is connected to the first terminal of the seventh capacitor, the second terminal of the first resistor, the first terminal of the second resistor, the second terminal of the third resistor, and the first terminal of the fourth resistor, respectively.

[0042] When the first terminal of the sixth capacitor is connected to the first terminal of the fourth capacitor, the second terminal of the seventh capacitor is connected to the first terminal of the fifth capacitor;

[0043] When the first terminal of the sixth capacitor is connected to the second terminal of the fourth capacitor, the second terminal of the seventh capacitor is connected to the second terminal of the fifth capacitor;

[0044] When the first terminal of the sixth capacitor is connected to the second terminal of the twelfth resistor, the second terminal of the seventh capacitor is connected to the second terminal of the thirteenth resistor.

[0045] A signal processing device comprising an interference-reducing charge amplifier as described in any of the preceding claims.

[0046] Applying the technical solution provided in this invention, considering that differential superposition can eliminate common-mode interference, but when the common-mode interference exceeds the common-mode input range of the operational amplifier, a harmful differential-mode signal will be generated at the differential output terminal, i.e., the output terminal of the differential superposition circuit. Therefore, the solution of this application sets up a common-mode negative feedback circuit. Specifically, the first input terminal of the common-mode negative feedback circuit is connected to the output terminal of the first operational amplifier, the second input terminal is connected to the output terminal of the second operational amplifier, the first output terminal is connected to the inverting output terminal of the first operational amplifier, and the second output terminal is connected to the inverting output terminal of the second operational amplifier. The common-mode negative feedback circuit can reduce the common-mode voltage output by the first and second operational amplifiers, thus enabling the differential superposition circuit to more effectively eliminate common-mode interference through differential output. That is, the solution of this application can effectively reduce the common-mode interference signal of the final output through the design of the common-mode negative feedback circuit. Meanwhile, the solution in this application incorporates a differential-mode negative feedback circuit to suppress differential-mode interference. Furthermore, the design of the negative feedback resistor in the charge amplifier is eliminated, thereby improving the low-frequency response. Specifically, the positive charge amplifier in this application consists of a first operational amplifier and a first capacitor, while the negative charge amplifier consists of a second operational amplifier and a second capacitor, thus simplifying the structure and improving the low-frequency response. The negative feedback resistor originally designed into the charge amplifier stabilizes the DC operating point. By eliminating the negative feedback resistor in this application, and through the design of the differential-mode negative feedback circuit, whose input is connected to the output of the differential superposition circuit and whose output is connected to the inverting input of the first operational amplifier, the DC operating point can be stabilized. In summary, the solution in this application effectively reduces common-mode and differential-mode interference and has a simple structure. Attached Figure Description

[0047] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0048] Figure 1 This is a schematic diagram of the first structure of the charge amplifier for reducing interference in this invention;

[0049] Figure 2 This is a schematic diagram of the second structure of the charge amplifier for reducing interference in this invention;

[0050] Figure 3 This is a schematic diagram of the third structure of the charge amplifier for reducing interference in this invention;

[0051] Figure 4 This is a schematic diagram of the fourth structure of the charge amplifier for reducing interference in this invention;

[0052] Figure 5 This is a schematic diagram of the fifth structure of the charge amplifier for reducing interference in this invention;

[0053] Figure 6 This is a schematic diagram of the sixth structure of the charge amplifier for reducing interference in this invention;

[0054] Figure 7 This is a schematic diagram of the seventh structure of the charge amplifier for reducing interference in this invention;

[0055] Figure 8a The waveform diagram of the charge amplifier in this application for stabilizing the DC operating point and suppressing common-mode and differential-mode interference is shown when the DC operating point voltage of the charge amplifier is deviated.

[0056] Figure 8b A schematic diagram of the waveforms of a conventional charge amplifier at various detection positions when the DC operating point voltage of the charge amplifier is deviated.

[0057] Figure 9a This is a schematic diagram of the amplitude-frequency curve of the interference-reducing charge amplifier of this application;

[0058] Figure 9b This is a schematic diagram of the amplitude-frequency curve of a traditional charge amplifier.

[0059] Figure 10 A schematic diagram of adding common-mode or differential-mode negative feedback to a traditional charge amplifier; Detailed Implementation

[0060] The core of this invention is to provide a charge amplifier that reduces interference, effectively reducing common-mode and differential-mode interference, and has a simple structure.

[0061] To enable those skilled in the art to better understand the present invention, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. Obviously, the described embodiments are merely some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0062] Please refer to Figure 1 , Figure 1 This is a schematic diagram of the structure of a charge amplifier for reducing interference according to the present invention. The charge amplifier for reducing interference may include:

[0063] The inverting input terminal serves as the positive charge input terminal and is connected to the first terminal of the pre-amplifier circuit and the first terminal of the first capacitor C1, respectively. The non-inverting input terminal serves as the reference terminal and is connected to the non-inverting input terminal of the second operational amplifier OP2. The output terminal is connected to the second terminal of the first capacitor C1.

[0064] The second operational amplifier OP2 has an inverting input terminal as a negative charge input terminal and is connected to the first terminal of the pre-stage circuit and the second capacitor C2, respectively. Its output terminal is connected to the second terminal of the second capacitor C2.

[0065] First capacitor C1, second capacitor C2;

[0066] The first input terminal is connected to the output terminal of the first operational amplifier OP1, the second input terminal is connected to the output terminal of the second operational amplifier OP2, and the third input terminal is connected to the reference terminal, forming a differential superposition circuit 10 for performing differential voltage summation.

[0067] The input terminal is connected to the output terminal of the differential superposition circuit 10, and the output terminal is connected to the inverting input terminal of the first operational amplifier OP1, forming a differential mode negative feedback circuit 20 used to suppress differential mode interference through negative feedback;

[0068] The first input terminal is connected to the output terminal of the first operational amplifier OP1, the second input terminal is connected to the output terminal of the second operational amplifier OP2, the first output terminal is connected to the inverting input terminal of the first operational amplifier OP1, and the second output terminal is connected to the inverting input terminal of the second operational amplifier OP2, forming a common-mode negative feedback circuit 30 used to reduce the common-mode input current through the output negative feedback current.

[0069] Differential voltage output can be achieved through positive and negative charge converters, and then the differential voltages are summed through a differential superposition circuit 10. A typical charge converter usually includes an operational amplifier, a feedback capacitor, and a feedback resistor, for example... Figure 10 This is a schematic diagram of a traditional charge amplifier with added common-mode or differential-mode negative feedback. Figure 10 Resistors R3, R4, R5, and R6 are all feedback resistors, and capacitors C1 and C2 are both feedback capacitors.

[0070] The solution in this application eliminates the feedback resistor in the charge converter. Specifically, in this solution, the positive charge converter includes a first operational amplifier OP1 and a first capacitor C1, while the negative charge converter includes a second operational amplifier OP2 and a second capacitor C2. Compared to... Figure 10 In this application, the positive and negative charge converters have both reduced by two resistors.

[0071] Furthermore, the parameters are usually symmetrical, i.e., C1 = C2. This is because a conventional charge converter includes an operational amplifier, a feedback capacitor Cf, and a feedback resistor Rf. The low-frequency cutoff frequency f0 can be expressed as: f0 = 1 / (2πRfCf). However, in practical engineering, due to space constraints and other reasons, it is difficult to increase the resistance value of the resistor. Therefore, it can be seen that the feedback resistor limits the low-frequency response of the charge converter.

[0072] In this application, the feedback resistor that limits the low-frequency response of the charge converter is eliminated. As can be seen from f0=1 / (2πRfCf), it is equivalent to increasing the value of the feedback resistor Rf in the formula, thereby reducing the low-frequency cutoff frequency f0, which is beneficial to improving the low-frequency response of the charge converter.

[0073] However, removing the feedback resistor will cause a shift in the DC operating point of the charge converter output. To address this, the solution in this application includes a differential-mode negative feedback circuit 20. The input of the differential-mode negative feedback circuit 20 is connected to the output of the differential superposition circuit 10, and its output is connected to the inverting input of the first operational amplifier OP1, thus stabilizing the DC operating point. Furthermore, the differential-mode negative feedback circuit 20 also enhances the suppression of differential-mode DC interference.

[0074] The specific circuit configuration of the differential-mode negative feedback circuit 20 can be set and adjusted according to actual conditions. For example, in one specific embodiment of the present invention, please refer to... Figure 2 The differential negative feedback circuit 20 includes:

[0075] The first terminal is connected to the inverting input terminal of the first operational amplifier OP1, and the second terminal is connected to the fifth resistor R5, which is connected to the output terminal of the differential superposition circuit 10.

[0076] In this embodiment, the differential-mode negative feedback circuit 20 consists of a single resistor, resulting in a simple structure. Specifically, the output of the differential superposition circuit 10 is connected to the inverting input of the first operational amplifier OP1 via a fifth resistor R5, thus achieving differential-mode negative feedback. Furthermore, due to the simplicity of this implementation, compared to traditional charge converter designs that require a feedback resistor, this design effectively reduces the number of components needed, thereby improving circuit reliability.

[0077] Furthermore, in one specific embodiment of the present invention, the differential-mode negative feedback circuit 20 may further include:

[0078] The first end is connected to the second end of the fifth resistor R5, and the second end is connected to the sixth resistor R6, which is connected to the output end of the differential superposition circuit 10.

[0079] The first RC circuit has its first terminal connected to the second terminal of the fifth resistor R5 and the first terminal of the sixth resistor R6, respectively, and its second terminal connected to the reference terminal.

[0080] This implementation also introduces a first RC circuit, namely a low-frequency bootstrap bypass, which can effectively reduce the low-frequency cutoff frequency of the charge converter, expand the bandwidth, and thus effectively improve low-frequency performance, as discussed later. Figure 9a and Figure 9b This also reflects the effect of the first RC circuit in expanding the bandwidth. Furthermore, since the first RC circuit needs to be introduced, a sixth resistor R6 is also set in series with the fifth resistor R5. The two together form a negative feedback resistor, and the first RC circuit is introduced at the connection point of the two.

[0081] In one specific embodiment of the present invention, see [reference needed]. Figure 3 The first RC circuit may specifically include:

[0082] The first terminal serves as the first terminal of the first RC circuit, and the second terminal is connected to the first terminal of the seventh resistor R7 and the third capacitor C3.

[0083] The second terminal serves as the seventh resistor R7 in the second terminal of the first RC circuit.

[0084] In this embodiment, the first RC circuit is composed of a third capacitor C3 and a seventh resistor R7, which has a simple structure and high reliability.

[0085] Furthermore, it should be noted that the common-mode negative feedback circuit 30 and differential-mode negative feedback circuit 20 added in this application do not affect the transmission coefficient of the original wideband charge amplifier to the piezoelectric signal (normal signal).

[0086] The common-mode negative feedback circuit 30 is used to suppress common-mode interference. The common-mode negative feedback circuit 30 helps to ensure that the common-mode input voltage does not exceed the common-mode input range of the first op-amp OP1 and the second op-amp OP2, thereby reducing the common-mode voltage output by the first op-amp OP1 and the second op-amp OP2. This allows the differential superposition circuit 10 to more effectively eliminate common-mode interference through differential output.

[0087] In one specific embodiment of the present invention, see [reference needed]. Figure 2 The common-mode negative feedback circuit 30 may include:

[0088] The first terminal is connected to the inverting input terminal of the first operational amplifier OP1, and the second terminal is connected to the first terminal of the second resistor R2, the second terminal of the third resistor R3, and the first terminal of the fourth resistor R4 respectively.

[0089] The second terminal is connected to the second resistor R2, which is connected to the inverting input terminal of the second operational amplifier OP2.

[0090] The third resistor R3 is connected to the output terminal of the first operational amplifier OP1.

[0091] The second terminal is connected to the fourth resistor R4, which is connected to the output terminal of the second operational amplifier OP2.

[0092] exist Figure 2 In this embodiment, Z+ represents the positive charge input terminal of the interference-reducing charge amplifier of this application, Z- represents the negative charge input terminal of the interference-reducing charge amplifier of this application, and Vref represents the reference terminal. The specific voltage value of the reference terminal can be set according to actual needs. Furthermore, in this embodiment, the connection terminal between the first resistor R1 and the second resistor R2 is marked as J1, and the connection terminal between the third resistor R3 and the fourth resistor R4 is also marked as J1, to indicate that these two connection terminals are interconnected.

[0093] Typically, R1 = R2 and R3 = R4 can be set. When common-mode interference enters the charge amplifier through the distributed capacitance of the sensor charge transport cable, this application reduces the common-mode output voltage of the charge amplifier by adding a common-mode negative feedback circuit 30 from the output to the input of the charge amplifier. This allows the subsequent differential superposition circuit 10, used for limited common-mode interference rejection, to more effectively reduce or eliminate the final output common-mode interference signal, achieving wideband common-mode interference suppression. The specific circuit configuration of the differential superposition circuit 10 can be set and adjusted as needed. For example, in one specific embodiment of this invention, see [reference needed]. Figure 2 The differential superposition circuit 10 may include:

[0094] The first terminal serves as the first input terminal of the differential superposition circuit 10, and the second terminal is connected to the eighth resistor R8, which is connected to the non-inverting input terminal of the third operational amplifier OP3.

[0095] The first terminal serves as the third input terminal of the differential superposition circuit 10, and the second terminal is connected to the ninth resistor R9, which is connected to the non-inverting input terminal of the third operational amplifier OP3.

[0096] The first terminal serves as the second input terminal of the differential superposition circuit 10, and the second terminal is connected to the tenth resistor R10, which is connected to the inverting input terminal of the third operational amplifier OP3.

[0097] The first terminal is connected to the second terminal of the tenth resistor R10, which is the eleventh resistor R11;

[0098] The output terminal is connected to the second end of the eleventh resistor R11, and the connection terminal serves as the output terminal of the third operational amplifier OP3 of the differential superposition circuit 10.

[0099] In this embodiment, the differential superposition circuit 10 consists of four resistors and one operational amplifier. The circuit structure is easy to implement. The output terminal of the third operational amplifier OP3 serves as the output terminal of the differential superposition circuit 10, that is, the differential charge conversion signal is output through the output terminal of the third operational amplifier OP3. In addition, R8 = R10 and R9 = R11 are usually set.

[0100] In one specific embodiment of the present invention, it further includes:

[0101] A second RC circuit is set between the preamplifier circuit and the inverting input terminal of the first operational amplifier OP1;

[0102] A third RC circuit is set between the preamplifier circuit and the inverting input of the second operational amplifier OP2.

[0103] The pyroelectric suppression effect can be improved by using the second and third RC circuits. The specific circuit configuration can be selected according to actual needs. For example, in one specific embodiment of the present invention, please refer to... Figure 3 The second RC circuit includes the fourth capacitor C4 and the twelfth resistor R12, and the third RC circuit includes the fifth capacitor C5 and the thirteenth resistor R13.

[0104] The first terminal of the fourth capacitor C4 serves as the first terminal of the second RC circuit and is connected to the preceding stage circuit. The second terminal of the fourth capacitor C4 is connected to the first terminal of the twelfth resistor R12. The second terminal of the twelfth resistor R12 serves as the second terminal of the second RC circuit and is connected to the inverting input terminal of the first operational amplifier OP1.

[0105] The first terminal of the fifth capacitor C5 serves as the first terminal of the third RC circuit and is connected to the preceding stage circuit. The second terminal of the fifth capacitor C5 is connected to the first terminal of the thirteenth resistor R13. The second terminal of the thirteenth resistor R13 serves as the second terminal of the third RC circuit and is connected to the inverting input terminal of the second operational amplifier OP2.

[0106] When the first terminal of the fourth capacitor C4 is connected to the first terminal of the first resistor R1, the first terminal of the fifth capacitor C5 is connected to the second terminal of the second resistor R2; when the second terminal of the fourth capacitor C4 is connected to the first terminal of the first resistor R1, the second terminal of the fifth capacitor C5 is connected to the second terminal of the second resistor R2; when the second terminal of the twelfth resistor R12 is connected to the first terminal of the first resistor R1, the second terminal of the thirteenth resistor R13 is connected to the second terminal of the second resistor R2.

[0107] Figure 3 In the implementation method described, the second and third RC circuits are implemented using the fourth capacitor C4, the twelfth resistor R12, the fifth capacitor C5, and the thirteenth resistor R13, which is relatively simple and convenient. Furthermore, it is usually set that C4 = C5 and R12 = R13. Figure 3The diagram shows the connection between the second terminal of the twelfth resistor R12 and the first terminal of the first resistor R1, and the connection between the second terminal of the thirteenth resistor R13 and the second terminal of the second resistor R2. Figure 3 The other two connection methods are indicated by dashed lines.

[0108] In one specific embodiment of the present invention, it may further include: a sixth capacitor C6 and a seventh capacitor C7;

[0109] The second terminal of the sixth capacitor C6 is connected to the first terminal of the seventh capacitor C7, the second terminal of the first resistor R1, the first terminal of the second resistor R2, the second terminal of the third resistor R3, and the first terminal of the fourth resistor R4, respectively.

[0110] When the first terminal of the sixth capacitor C6 is connected to the first terminal of the fourth capacitor C4, the second terminal of the seventh capacitor C7 is connected to the first terminal of the fifth capacitor C5.

[0111] When the first terminal of the sixth capacitor C6 is connected to the second terminal of the fourth capacitor C4, the second terminal of the seventh capacitor C7 is connected to the second terminal of the fifth capacitor C5.

[0112] When the first terminal of the sixth capacitor C6 is connected to the second terminal of the twelfth resistor R12, the second terminal of the seventh capacitor C7 is connected to the second terminal of the thirteenth resistor R13.

[0113] This implementation takes into account the aforementioned implementation method, which has a strong ability to suppress common-mode interference in the low-frequency band. Based on this, by adding capacitor negative feedback, common-mode interference in the high-frequency band can be further reduced. Furthermore, it is usually necessary to set C6 = C7.

[0114] Figure 4 , Figure 5 , Figure 6 as well as Figure 7 The placement positions of the sixth capacitor C6 and the seventh capacitor C7 in different embodiments are shown, all of which can achieve the same interference suppression effect.

[0115] In addition, through Figure 8a , Figure 8b The simulation results also illustrate the suppression effect of differential-mode and common-mode interference in this application. Figure 8a The diagram illustrates the waveforms of the charge amplifier used in this application to stabilize the DC operating point and suppress common-mode and differential-mode interference, under conditions where the DC operating point voltage of the charge amplifier deviates due to the insulation resistance to ground at the charge input terminal, the operational amplifier offset voltage, and the asymmetry of the negative feedback capacitor parameters. Figure 8bThis represents a waveform diagram of a traditional charge amplifier at various detection positions, caused by the asymmetry of the charge input terminal insulation resistance to ground, operational amplifier offset voltage, and negative feedback capacitor parameters, resulting in a DC operating point voltage shift in the charge amplifier. Figure 8a and Figure 8b In the diagram, the curves on each coordinate axis from top to bottom represent: 0 - differential output voltage, 1 - output voltage of the first op-amp OP1, 2 - output voltage of the second op-amp OP2, and 3 - output common-mode voltage, which are... Figure 7 The voltages at positions 1, 2, and 3 marked in the middle are relative to the reference terminal. 4 - Charge simulation input voltage.

[0116] Simulation results show that the interference-reducing charge amplifier proposed in this application can effectively stabilize the DC operating point and suppress common-mode and differential-mode interference.

[0117] Figure 9b The amplitude-frequency curve of a conventional charge amplifier is shown. Figure 9a The amplitude-frequency curves of common-mode and differential-mode negative feedback charge amplifiers show that, while increasing the suppression of common-mode and differential-mode interference, the common-mode and differential-mode negative feedback charge amplifiers do not affect signal transmission and lower the low-frequency response cutoff frequency, thus expanding the signal bandwidth. In contrast, traditional charge amplifiers, with their negative feedback capacitors and resistors, limit the low-frequency response of the charge converter, making it difficult to improve its low-frequency response.

[0118] Corresponding to the above embodiments of the interference-reducing charge amplifier, this embodiment of the invention also provides a signal processing device that may include the interference-reducing charge amplifier in any of the above embodiments, which will not be described again here.

[0119] Applying the technical solution provided in this embodiment of the invention, considering that differential superposition can eliminate common-mode interference, but when the common-mode interference exceeds the common-mode input range of the operational amplifier, a harmful differential-mode signal will be generated at the differential output terminal, i.e., the output terminal of the differential superposition circuit 10. Therefore, the solution of this application sets up a common-mode negative feedback circuit 30. Specifically, the first input terminal of the common-mode negative feedback circuit 30 is connected to the output terminal of the first operational amplifier OP1, the second input terminal is connected to the output terminal of the second operational amplifier OP2, the first output terminal is connected to the inverting output terminal of the first operational amplifier OP1, and the second output terminal is connected to the inverting output terminal of the second operational amplifier OP2. The common-mode negative feedback circuit 30 can reduce the common-mode voltage output by the first operational amplifier OP1 and the second operational amplifier OP2, thus enabling the differential superposition circuit 10 to more effectively eliminate common-mode interference through differential output. That is, the solution of this application can effectively reduce the common-mode interference signal of the final output through the design of the common-mode negative feedback circuit 30. Meanwhile, the solution of this application includes a differential-mode negative feedback circuit 20 to suppress differential-mode interference. Furthermore, the design of the negative feedback resistor in the charge amplifier is eliminated, which improves the low-frequency response. Specifically, the positive charge amplifier in this application consists of a first operational amplifier OP1 and a first capacitor C1, while the negative charge amplifier consists of a second operational amplifier OP2 and a second capacitor C2. This simplifies the structure and improves the low-frequency response. The negative feedback resistor originally designed in the charge amplifier stabilizes the DC operating point. However, by eliminating the negative feedback resistor in this application, the differential-mode negative feedback circuit 20 is used. The input of the differential-mode negative feedback circuit 20 is connected to the output of the differential superposition circuit 10, and the output is connected to the inverting input of the first operational amplifier OP1. Therefore, the differential-mode negative feedback circuit 20 can stabilize the DC operating point. In summary, the solution of this application effectively reduces common-mode and differential-mode interference and has a simple structure.

[0120] It should also be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, article, or apparatus that includes said element.

[0121] This article uses specific examples to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the technical solutions and core ideas of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made to the present invention without departing from the principles of the present invention, and these improvements and modifications also fall within the protection scope of the claims of the present invention.

Claims

1. A charge amplifier with reduced interference, characterized in that, include: The first operational amplifier has an inverting input terminal as a positive charge input terminal and is connected to the first terminal of the preceding circuit and the first terminal of the first capacitor, respectively. The non-inverting input terminal is used as a reference terminal and is connected to the non-inverting input terminal of the second operational amplifier. The output terminal is connected to the second terminal of the first capacitor. The second operational amplifier has an inverting input terminal as a negative charge input terminal and is connected to the first terminal of the pre-stage circuit and the second capacitor, respectively, and its output terminal is connected to the second terminal of the second capacitor. The first capacitor, the second capacitor; The first input terminal is connected to the output terminal of the first operational amplifier, the second input terminal is connected to the output terminal of the second operational amplifier, and the third input terminal is connected to the reference terminal, forming a differential superposition circuit for performing differential voltage summation; The input terminal is connected to the output terminal of the differential superposition circuit, and the output terminal is connected to the inverting input terminal of the first operational amplifier, forming a differential mode negative feedback circuit for suppressing differential mode interference through negative feedback. The first input terminal is connected to the output terminal of the first operational amplifier, the second input terminal is connected to the output terminal of the second operational amplifier, the first output terminal is connected to the inverting input terminal of the first operational amplifier, and the second output terminal is connected to the inverting input terminal of the second operational amplifier, forming a common-mode negative feedback circuit for reducing the common-mode input current through the output negative feedback current; The differential-mode negative feedback circuit includes: The first terminal is connected to the inverting input terminal of the first operational amplifier, and the second terminal is connected to the fifth resistor at the output terminal of the differential superposition circuit. The differential-mode negative feedback circuit also includes: The first end is connected to the second end of the fifth resistor, and the second end is connected to the sixth resistor, which is connected to the output end of the differential superposition circuit. A first RC circuit, wherein the first terminal of the first RC circuit is connected to the second terminal of the fifth resistor and the first terminal of the sixth resistor respectively, and the second terminal of the first RC circuit is connected to the reference terminal; Wherein, the first operational amplifier does not have a feedback resistor connected in parallel with the first capacitor, and the second operational amplifier does not have a feedback resistor connected in parallel with the second capacitor.

2. The interference-reducing charge amplifier according to claim 1, characterized in that, The first RC circuit includes: The first end serves as the first end of the first RC circuit, and the second end is connected to the third capacitor, which is connected to the first end of the seventh resistor. The seventh resistor serves as the second terminal of the first RC circuit.

3. The interference-reducing charge amplifier according to claim 1, characterized in that, The differential superposition circuit includes: The first terminal serves as the first input terminal of the differential superposition circuit, and the second terminal is connected to the eighth resistor, which is connected to the non-inverting input terminal of the third operational amplifier. The first terminal serves as the third input terminal of the differential superposition circuit, and the second terminal is connected to the ninth resistor, which is connected to the non-inverting input terminal of the third operational amplifier. The first terminal serves as the second input terminal of the differential superposition circuit, and the second terminal is connected to the tenth resistor of the inverting input terminal of the third operational amplifier. The eleventh resistor is connected at its first end to the second end of the tenth resistor; The third operational amplifier has its output terminal connected to the second terminal of the eleventh resistor, and the connection terminal serves as the output terminal of the differential superposition circuit.

4. The interference-reducing charge amplifier according to claim 1, characterized in that, The common-mode negative feedback circuit includes: The first terminal is connected to the inverting input terminal of the first operational amplifier, and the second terminal is connected to the first terminal of the second resistor, the second terminal of the third resistor, and the first terminal of the fourth resistor, respectively. The second terminal is connected to the second resistor, which is connected to the inverting input terminal of the second operational amplifier. The third resistor whose first terminal is connected to the output terminal of the first operational amplifier; The fourth resistor is connected at its second terminal to the output terminal of the second operational amplifier.

5. The interference-reducing charge amplifier according to claim 4, characterized in that, Also includes: A second RC circuit is disposed between the preamplifier circuit and the inverting input terminal of the first operational amplifier; A third RC circuit is disposed between the preamplifier circuit and the inverting input of the second operational amplifier.

6. The interference-reducing charge amplifier according to claim 5, characterized in that, The second RC circuit includes a fourth capacitor and a twelfth resistor, and the third RC circuit includes a fifth capacitor and a thirteenth resistor. The first terminal of the fourth capacitor serves as the first terminal of the second RC circuit and is connected to the preamplifier circuit. The second terminal of the fourth capacitor is connected to the first terminal of the twelfth resistor. The second terminal of the twelfth resistor serves as the second terminal of the second RC circuit and is connected to the inverting input terminal of the first operational amplifier. The first terminal of the fifth capacitor serves as the first terminal of the third RC circuit and is connected to the preamplifier circuit. The second terminal of the fifth capacitor is connected to the first terminal of the thirteenth resistor. The second terminal of the thirteenth resistor serves as the second terminal of the third RC circuit and is connected to the inverting input terminal of the second operational amplifier. When the first terminal of the fourth capacitor is connected to the first terminal of the first resistor, the first terminal of the fifth capacitor is connected to the second terminal of the second resistor; when the second terminal of the fourth capacitor is connected to the first terminal of the first resistor, the second terminal of the fifth capacitor is connected to the second terminal of the second resistor; when the second terminal of the twelfth resistor is connected to the first terminal of the first resistor, the second terminal of the thirteenth resistor is connected to the second terminal of the second resistor.

7. The interference-reducing charge amplifier according to claim 6, characterized in that, It also includes: the sixth capacitor and the seventh capacitor; The second terminal of the sixth capacitor is connected to the first terminal of the seventh capacitor, the second terminal of the first resistor, the first terminal of the second resistor, the second terminal of the third resistor, and the first terminal of the fourth resistor, respectively. When the first terminal of the sixth capacitor is connected to the first terminal of the fourth capacitor, the second terminal of the seventh capacitor is connected to the first terminal of the fifth capacitor; When the first terminal of the sixth capacitor is connected to the second terminal of the fourth capacitor, the second terminal of the seventh capacitor is connected to the second terminal of the fifth capacitor; When the first terminal of the sixth capacitor is connected to the second terminal of the twelfth resistor, the second terminal of the seventh capacitor is connected to the second terminal of the thirteenth resistor.

8. A signal processing device, characterized in that, Including the interference-reducing charge amplifier as described in any one of claims 1 to 7.

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