A data communication method and system between FPGA and DSP

Abstract

The present invention belongs to the field of digital circuit design technology, and relates to a method and system for data communication between FPGA and DSP. The method overcomes the problems of easy data loss and low consistency of transmitted data in existing communication methods. A data transmitting module and a data receiving module are configured in the FPGA; a dual-port RAM is used as the data transmitting module, and the dual-port RAM is connected to the DSP via the Link-Port interface of the DSP, and a ping-pong operation mode is used to send the data in the FPGA to the DSP for processing; an asynchronous FIFO is used as the data receiving module, and the asynchronous FIFO is connected to the DSP via the Link-Port interface of the DSP, and the data sent by the DSP is received based on the asynchronous FIFO. Based on the present invention, uninterrupted communication between the FPGA and the DSP can be completed, which not only ensures that the received data is not lost, but also takes into account the consistency of the transmitted data, thereby ensuring data accuracy.

Description

Technical Field

[0001] The invention belongs to the technical field of digital circuit design and relates to a communication method between FPGA and DSP. Background Art

[0002] With the development of digital communication technology, digital signal processing has been widely applied in many fields, and the transmission speed of digital signals has also continued to increase. For example, the Link-Port built into Analog Devices' TigerSHARC chip TS101 has a throughput of 250MB / s. At the same time, in many cases, we often use simpler, lower-speed, and more accurate serial communication methods such as RS232. Due to the significant difference in speed between the two, many instabilities can arise during communication.

[0003] In the software-defined radio architecture, there are two options for communication between the DSP and the FPGA. The first is the data bus method, which requires a large number of I / O resources. However, the FPGA often has a limited number of I / O ports. In addition, the DSP's data bus may be occupied by other peripherals, so this method is less efficient in actual circuits. The second method is for the DSP and FPGA to communicate through the Link-Port. This can free up the bus and improve the utilization of chip pins. However, due to the high transmission rate of the Link-Port, the FPGA must have a corresponding cache to process the data. Most designs will choose asynchronous FIFO or dual-port RAM as cache, which will risk the loss of received data and affect the continuity of sent data. Summary of the Invention

[0004] The present invention aims to provide a method and system for data communication between an FPGA and a DSP, overcoming the problems of data loss and poor data transmission consistency in existing communication methods. This method enables uninterrupted communication between the FPGA and the DSP, ensuring that received data is not lost while also ensuring the consistency and accuracy of transmitted data.

[0005] The technical solution of the present invention is to provide a data communication method between FPGA and DSP, the special features of which are: configuring a data sending module and a data receiving module in the FPGA;

[0006] The dual-port RAM is used as a data transmission module. The dual-port RAM is connected to the DSP through the DSP's Link-Port interface and uses the ping-pong operation mode to send the data in the FPGA to the DSP for processing.

[0007] The asynchronous FIFO is used as a data receiving module. The asynchronous FIFO is connected to the DSP through the Link-Port interface of the DSP, and the data sent by the DSP is received based on the asynchronous FIFO.

[0008] Furthermore, the data in the FPGA is read to the DSP for processing using the ping-pong operation mode, as follows:

[0009] While the FPGA writes data into ram_a, the DSP reads the data written into ram_b at the previous moment through the Link-Port interface;

[0010] While the FPGA is writing data into ram_b, the DSP reads the data written into ram_a at the previous moment through the Link-Port interface;

[0011] The ram_a and ram_b are different memories in the dual-port RAM.

[0012] Furthermore, the write rate is lower than the read rate.

[0013] Furthermore, the write rate is 150KHz and the read rate is twice the Link-Port clock frequency, which is 100MHz.

[0014] Furthermore, when the DSP reads data through the Link-Port interface, it uses the LxCLKOUT of the Link-Port interface as the response clock. The specific process is as follows:

[0015] Before valid data arrives, the FPGA first controls LxCLKOUT to be low for more than 6 clock cycles; then the first set of data is sent to the DSP on the first rising edge of the clock, and the second set of data is sent to the DSP on the first falling edge of the clock, and so on, sending the data in the FPGA to the DSP.

[0016] Furthermore, in order to better receive the data processed by DSP, ALTDDIO_IN is configured in FPGA as a data pre-receiving module;

[0017] When the DSP sends data through the Link-Port interface, it uses the Link-Port interface's LxCLKOUT as the output clock and LxCLKIN as the response clock. The specific process is as follows:

[0018] Along with the LxCLKIN clock, the data lxdata entering the FPGA from the Link-Port is divided into two data paths dataout_l and dataout_h through ALTDDIO_IN, and then combined into one data path data_h_l and written into the cache;

[0019] Among them, dataout_l is the data corresponding to the falling edge of the LxCLKIN clock, and dataout_h is the data corresponding to the rising edge of the LxCLKIN clock.

[0020] Furthermore, the data sent by the DSP is received based on the asynchronous FIFO. The specific process is as follows:

[0021] The asynchronous FIFO receives the data data_h_l output by ALTDDIO_IN, converts it and outputs it.

[0022] The present invention also provides an FPGA and DSP data communication system for implementing the above method, which is special in that: the FPGA is configured with a dual-port RAM and an asynchronous FIFO, and both the dual-port RAM and the asynchronous FIFO are connected to the DSP through the DSP's Link-Port interface.

[0023] Furthermore, the above system also includes ALTDDIO_IN configured in the FPGA.

[0024] Furthermore, ADSP-TS101 of AD company can be selected as DSP chip, and EP3C120F780I7 chip of Altera company can be used as FPGA chip.

[0025] The beneficial effects of the present invention are:

[0026] This invention, based on the current mainstream hardware circuit FPGA+DSP design, achieves efficient and fast communication between the two. On the DSP side, only its Link-Port interface is used, conserving data pins. A dual-port RAM is designed on the FPGA side for data transmission, using a ping-pong operation for non-blocking data transmission, while an asynchronous FIFO is used for data reception. Throughout the entire process, the depth of the dual-port RAM and FIFO can be adjusted to meet the required data volume, ensuring data loss. The ping-pong operation also ensures data flow continuity. The entire structure is flexible and effective, with high efficiency and practical value. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 It is a direct connection diagram of the DSP in the present invention;

[0028] Figure 2 This is a schematic diagram of the Link-Port port transmission start sequence of the present invention;

[0029] Figure 3 This is a schematic diagram of the connection framework designed in the present invention;

[0030] Figure 4 This is a schematic diagram of data transmission accomplished by ping-pong operation of dual-port RAM in FPGA of the present invention;

[0031] Figure 5 This is a simulation diagram of the dual-port RAM ping-pong operation of the present invention;

[0032] Figure 6 This is a partial schematic diagram of the dual-port RAM ping-pong operation simulation of the present invention;

[0033] Figure 7 This is a timing diagram of the receiving port ALTDDIO_IN on the FPGA side of the present invention;

[0034] Figure 8 This is a simulation diagram of received data of the receiving port ALTDDIO_IN on the FPGA side of the present invention;

[0035] Figure 9 This is a simulation diagram of asynchronous FIFO data reading at the FPGA end of the present invention;

[0036] Figure 10 This is a schematic diagram of data writing inside the DSP of the present invention;

[0037] Figure 11 This is a schematic diagram of data received inside the FPGA of the present invention;

[0038] Figure 12 This is a diagram showing the inspection data being sent as displayed on the PC. DETAILED DESCRIPTION

[0039] The present invention will be further described below with reference to the accompanying drawings and specific embodiments.

[0040] Link-Port is an interface for communication between DSP chips and can also communicate with FPGAs. Because Link-Port communication has a high transmission rate and a simple and flexible protocol, it can be used to build multiprocessor systems.

[0041] The Link-Port communication data bus LxDAT is 8 bits wide and has three control lines: LxCLKIN, LxCLKOUT, and LxDIR. When receiving data, LxCLKIN is used as the clock input and LxCLKOUT is used as the response; when sending data, LxCLKIN is used as the response and LxCLKOUT is used as the clock output. The LxDIR pin indicates whether the Link-Port is receiving or sending. This pin is only used when the hardware is using a link buffer. In unbuffered mode, the hardware connection between the TigerSHARC processor and the FPGA design module is as follows: Figure 1 shown.

[0042] The communication sequence of Link-Port is as follows Figure 2As shown, the transmitter sets the LxCLKOUT signal to a low level and maintains it for more than six clock cycles (t ACK At the same time, if LxCLKIN is always high, data transmission begins. After the transmission process begins, the receiving end sets the sending end's LxCLKIN to low as a connection test (t CONNIW ), after 4 words, if the receiving end cannot receive any data, the receiving end will keep the LxCLKIN of the transmitting end low until it can receive data and then set it high. LXCLK It is the clock cycle of link port communication. 8 bits of data are sent on both the rising and falling edges of the sending clock.

[0043] Typical applications of the present invention can be as follows Figure 3 As shown, the signals collected by the AD are processed in the FPGA, and more complex multi-algorithm tasks are performed in the DSP. Finally, the processed data is returned to the FPGA for display through the serial port UART. The FPGA and DSP are connected by a Link-Port. The cache composed of dual-port RAM and asynchronous FIFO is the data transfer hub of the entire design. Uplink and downlink data communicate through it, so they are extremely important in the entire signal processing flow.

[0044] The designed hardware system clock is 25MHz, and the Link-Port's LxCLKOUT rate is set to 50MHz, so the clock control module needs to output a corresponding clock signal. In order to maintain data consistency, we designed two RAM "ping-pong operation" for buffering. The specific process is as follows Figure 4 As shown in the figure. After the design program starts, the 32-bit tx_idata_in and tx_qdata_in in the FPGA are combined into a 64-bit data stream and written to RAM_a. Since data typically comes from digital down-conversion at a lower rate, we write to RAM at 150 kHz. Once RAM_a is full, data is read out at a clock rate twice the Link-Port clock rate, or 100 MHz. As RAM_a fills, RAM_b is started and data is written. After RAM_b is full, RAM_a is empty, and new data can be written to RAM_a. This cycle continues, allowing for a continuous flow of data.

[0045] The design uses the dual-port RAM IP core provided by Altera. The parameters are filled in according to the design requirements. The depth of the dual-port RAM is 32, the write data width is 64 bits, and the read data width is 8 bits. That is, the data written once needs to be read 8 times before it can be read out. The final simulation results are as follows Figure 5As shown. The write enable aram_wren and bram_wren of the two RAMs are set high alternately to write data; after the write enable is set low, the data operation will be performed on the RAM that has been filled, and the corresponding read enable aram_rden and bram_rden will be set high. When not in operation, the address and data of the RAM default to 0. Figure 6 This is the result of partially enlarging the simulation diagram. You can see the values ​​of the read address aram_rdaddress and the read data aram_q. The 8 addresses 0x12 to 0x19 read a 64-bit data "0X00000002".

[0046] Data is read from RAM at 100MHz and sent to the DSP's Link-Port. According to communication rules, the FPGA's LxCLKOUT must be set low for at least six clock cycles before valid data arrives. The first 8-bit data set is then written to the DSP on the first rising clock edge, followed by the second 8-bit data set on the falling clock edge. This cycle continues, completing data communication.

[0047] The Link-Port communication method is quite special. It transmits 8 bits of data according to the trigger edge of the output clock LxCLKOUT. However, it is difficult to directly implement this communication method in the corresponding VHDL language. To solve this problem, the Altera IP core ALTDDIO_IN can be called in the Quartus II environment. ALTDDIO_IN is sensitive to both the rising and falling edges of the clock and can receive data. Figure 7 The input waveform timing diagram shows the datain signal is the data input signal of ALTDDIO_IN, dataout_l is the data on the falling edge of the corresponding clock, dataout_h is the data on the rising edge of the clock, and neg_reg_out is a temporary register of dataout_l.

[0048] After setting up the IP core of ALTDDIO_IN, simulate it in Modelsim software and you can get Figure 8 As shown in the figure, along with the clock LxCLKIN, the data lxdata entering the FPGA from the Link-Port is split into two data streams, data_h (8 bits) and data_l (8 bits), by ALTDDIO_IN. These are then combined into one data stream, data_h_l (16 bits), which is written into the cache for further processing.

[0049] The amount of data received is not large, but the rate is high, which does not match the serial port transmission rate in the next step. The present invention designs an asynchronous FIFO to solve this problem. The FIFO is designed using the IP core provided by Altera. The write is 16-bit data, and the clock is the accompanying clock of the Link-Port. The read data is 8 bits. In the serial communication, the start bit and stop bit are 10 bits. Therefore, the FIFO read clock is one tenth of the serial port baud rate. The baud rate in the design is 115200Hz, so the read clock is

[0050] 115200Hz / 10=11.52KHz

[0051] The data coming from ALTDDIO_IN passes through FIFO, and the 16-bit input becomes 8-bit output. Figure 9 As shown in the figure, when the output valid bit send_valid_reg is set high, the FIFO output data fifo_out is exactly the output data 0x59 to 0x68 of ALTDDIO_IN.

[0052] The present invention selects ADSP-TS101 of AD company as DSP chip, and FPGA adopts EP3C120F780I7 chip of Altera company. Under VisualDSP++Environment, data operation on DSP side is performed, and hexadecimal data 0x00~0x0F is written to Link-Port. Figure 10 The data within the red box is shown.

[0053] Use the SignalTap II Logic Analyzer tool in Quartus II to view the data received in the FPGA. Figure 11 As shown in the figure, dsp_LxCLKIN is the Link-Port clock, dsp_LxCLKOUT is high, indicating that the FPGA can receive data at any time, dsp_lxdata is the DSP data received in the FPGA, 0x00 to 0x0F indicates correct reception, and data is the combined data after passing through ALTDDIO_IN. From this observation, all data are correct. Finally, call the serial port debugging assistant and set the baud rate to 115200Hz. The result is as follows Figure 12 As shown in the figure, we can see that after multiple transmission tests, this design structure is stable and can accurately display the transmitted data, proving that the design of the present invention can serve as a bridge for rate conversion between Link-Port and serial port.

Claims

1. A method for data communication between FPGA and DSP, characterized by: Configure the data sending module and the data receiving module in the FPGA; The dual-port RAM is used as a data transmission module. The dual-port RAM is connected to the DSP through the DSP's Link-Port interface and uses the ping-pong operation mode to send the data in the FPGA to the DSP for processing. The asynchronous FIFO is used as a data receiving module, and the asynchronous FIFO is connected to the DSP through the Link-Port interface of the DSP, and the data sent by the DSP is received based on the asynchronous FIFO; The ping-pong operation mode is used to read the data in the FPGA to the DSP for processing, as follows: While the FPGA writes data into ram_a, the DSP reads the data written into ram_b at the previous moment through the Link-Port interface; While the FPGA is writing data into ram_b, the DSP reads the data written into ram_a at the previous moment through the Link-Port interface; Among them, ram_a and ram_b are different memories in the dual-port RAM; When the DSP reads data through the Link-Port interface, it uses the LxCLKOUT of the Link-Port interface as the response clock. The specific process is as follows: Before valid data arrives, the FPGA first controls LxCLKOUT to be low for more than 6 clock cycles; then the first set of data is sent to the DSP on the first rising edge of the clock, and the second set of data is sent to the DSP on the first falling edge of the clock, and so on, sending the data in the FPGA to the DSP.

2. The FPGA and DSP data communication method according to claim 1, wherein: The write rate is lower than the read rate.

3. The FPGA and DSP data communication method according to claim 2, wherein: The write rate is 150KHz and the read rate is twice the Link-Port clock frequency, which is 100MHz.

4. The FPGA and DSP data communication method according to claim 3, wherein: Configure ALTDDIO_IN in FPGA as a data pre-receiver module; When the DSP sends data through the Link-Port interface, it uses the Link-Port interface's LxCLKOUT as the output clock and LxCLKIN as the response clock. The specific process is as follows: Along with the LxCLKIN clock, the data lxdata entering the FPGA from the Link-Port is divided into two data paths dataout_l and dataout_h through ALTDDIO_IN, and then combined into one data path data_h_l and written into the cache; Among them, dataout_l is the data corresponding to the falling edge of the LxCLKIN clock, and dataout_h is the data corresponding to the rising edge of the LxCLKIN clock.

5. The FPGA and DSP data communication method according to claim 4, wherein: The data sent by DSP is received based on asynchronous FIFO. The specific process is as follows: The asynchronous FIFO receives the data data_h_l output by ALTDDIO_IN, converts it and outputs it.

6. An FPGA and DSP data communication system, used to implement the method according to any one of claims 1 to 5, characterized in that: The FPGA is equipped with dual-port RAM and asynchronous FIFO, which are connected to the DSP through the DSP's Link-Port interface.

7. The system according to claim 6, characterized in that: ALTDDIO_IN is also configured in the FPGA.

8. The system according to claim 7, characterized in that: ADSP-TS101 from AD company is selected as DSP chip, and EP3C120F780I7 chip from Altera company is used as FPGA chip.

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