A timing circuit arrangement for a flip-flop

Abstract

This application relates to sequential circuit arrangements for flip-flops. An integrated circuit includes a first time delay circuit, a second time delay circuit, and a master-slave flip-flop having a gated input circuit and a transmission gate. The first time delay circuit has a first input configured to receive a first clock signal and a first output configured to generate a second clock signal. The second time delay circuit has a second input configured to receive the second clock signal and a second output configured to generate a third clock signal. The transmission gate is configured to receive a first clock signal and a second clock signal for controlling the transmission state of the transmission gate. The gated input circuit is configured to have an input transmission state controlled by the third clock signal at the second output of the second time delay circuit.

Description

Technical Field

[0001] This disclosure relates to the arrangement of sequential circuits for triggers. Background Technology

[0002] The latest trend in integrated circuit (IC) miniaturization has resulted in smaller devices that consume less power but provide more functionality at higher speeds. Miniaturization processes have also created more stringent design and manufacturing specifications and reliability challenges. Various electronic design automation (EDA) tools generate, optimize, and verify standard cell layout designs for ICs, while ensuring that standard cell layout design and manufacturing specifications are met. Summary of the Invention

[0003] According to the first aspect of this disclosure, An integrated circuit includes: a first time delay circuit having a first input and a first output, the first input being configured to receive a first clock signal, and the first output being configured to generate a second clock signal based on the first clock signal; a second time delay circuit having a second input and a second output, the second input being configured to receive the second clock signal, and the second output being configured to generate a third clock signal based on the second clock signal; and a master-slave flip-flop having a gated input circuit, a master latch, a slave latch, and a transmission gate coupled between the master latch and the slave latch, wherein the master latch is coupled between the gated input circuit and the transmission gate; and wherein the transmission gate is configured to receive the first clock signal and the second clock signal to control the transmission state of the transmission gate, and the gated input circuit is configured to have an input transmission state controlled by the third clock signal at the second output of the second time delay circuit.

[0004] According to the second aspect of this disclosure, A method for operating a master-slave flip-flop, the master-slave flip-flop having a master latch coupled between a gated input circuit and a transmission gate, the method comprising: generating a second clock signal delayed relative to a first clock signal; generating a third clock signal delayed relative to the second clock signal; sending the first clock signal and the second clock signal to the transmission gate to change the transmission state of the transmission gate; and using the third clock signal to control the input transmission state of the gated input circuit.

[0005] According to the third aspect of this disclosure, the following is provided:An integrated circuit includes: a first time delay circuit having a first input terminal and a first output terminal, the first input terminal being configured to receive a first clock signal, and the first output terminal being configured to generate a second clock signal based on the first clock signal; wherein the first time delay circuit further includes a first gate conductor intersecting with a first type active region structure and a second type active region structure in a first region; and a second time delay circuit having a second input terminal and a second output terminal, the second input terminal being configured to receive the second clock signal, and the second output terminal being configured to generate a third clock signal based on the second clock signal; wherein the second time delay circuit further includes a second gate conductor intersecting with a first type active region structure and a second type active region structure in a second region; wherein the first time delay circuit includes a first gate via connection portion directly contacting the first gate conductor, the first gate conductor being located at the top of the first type active region structure in the first region; and wherein the second time delay circuit includes a second gate via connection portion directly contacting the second gate conductor, the second gate conductor being located at the top of the second type active region structure in the second region. Attached Figure Description

[0006] The various aspects of this disclosure can be best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, according to industry standard practice, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features can be arbitrarily increased or decreased.

[0007] Figure 1A-1B This is a circuit diagram of a master-slave flip-flop and a timing circuit for generating a clock signal for the master-slave flip-flop, according to some embodiments.

[0008] Figure 2 It is a timing diagram of various clock signals in a sequential circuit and various data signals in a master-slave flip-flop according to some embodiments.

[0009] Figures 3A-3B According to some embodiments Figure 1A-1B A circuit diagram of a specific implementation of the master-slave flip-flop and sequential circuit.

[0010] Figures 4A-4B According to some embodiments Figure 1A-1B A circuit diagram of a specific implementation of the master-slave flip-flop and sequential circuit.

[0011] Figure 5A According to some embodiments Figure 3B and Figure 4B The layout diagram of some parts of the sequential circuit.

[0012] Figures 5B-5D According to some embodiments Figure 5A The layout diagram in the figure is a cross-sectional view of the timing circuit specified in the figure.

[0013] Figure 5E According to some embodiments Figure 5A The equivalent circuit of a part of the layout diagram.

[0014] Figure 6A According to some embodiments Figure 3B and Figure 4B The layout diagram of some parts of the sequential circuit.

[0015] Figures 6B-6D According to some embodiments Figure 6A The layout diagram in the figure is a cross-sectional view of the timing circuit specified in the figure.

[0016] Figure 7A According to some embodiments Figure 3B and Figure 4B The layout diagram of some parts of the sequential circuit.

[0017] Figures 7B-7D According to some embodiments Figure 7A The layout diagram in the figure is a cross-sectional view of the timing circuit specified in the figure.

[0018] Figure 7E According to some embodiments Figure 7A The equivalent circuit of a part of the layout diagram.

[0019] Figures 8A-8B This is a circuit diagram of a master-slave flip-flop and a timing circuit 880 for providing a clock signal to drive the master-slave flip-flop, according to some embodiments.

[0020] Figure 8C It is a timing diagram of various clock signals in a sequential circuit and various data signals in a master-slave flip-flop according to some embodiments.

[0021] Figures 9A-9B This is a circuit diagram of a master-slave flip-flop according to some embodiments and a timing circuit for providing a clock signal to drive the master-slave flip-flop.

[0022] Figures 10A-10B This is a circuit diagram of a master-slave flip-flop according to some embodiments and a timing circuit for providing a clock signal to drive the master-slave flip-flop.

[0023] Figure 11A-11BThis is a circuit diagram of a master-slave flip-flop according to some embodiments and a timing circuit for providing a clock signal to drive the master-slave flip-flop.

[0024] Figure 12 This is a flowchart of a method for operating a master-slave trigger according to some embodiments.

[0025] Figure 13 This is a block diagram of an electronic design automation (EDA) system according to some embodiments.

[0026] Figure 14 This is a block diagram of an integrated circuit (IC) manufacturing system and the associated IC manufacturing process according to some embodiments. Detailed Implementation

[0027] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. To simplify this disclosure, specific examples of components, values, operations, materials, arrangements, etc., are described below. These are, of course, merely examples and intended to be limiting. Other components, values, operations, materials, arrangements, etc., are to be considered. For example, in the following description, forming a first feature on or over a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where an additional feature may be formed between the first and second features such that the first and second features may not be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. Such repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0028] Furthermore, this document may use spatially relevant terms (e.g., "below," "under," "down," "above," "up," etc.) to readily describe the relationship of one element or feature shown in the figure relative to another element(s) or feature(s). These spatially relevant terms are intended to cover different orientations of the device in use or operation other than those shown in the figure. The device may be oriented in other ways (rotated 90 degrees or otherwise), and the spatially relevant descriptors used herein may be interpreted accordingly.

[0029] The master-slave flip-flop includes a gated input circuit, a master latch, a slave latch, and a transmission gate coupled between the master latch and the slave latch. The master latch is coupled between the gated input circuit and the transmission gate. In some embodiments, a modified timing circuit for controlling the master-slave flip-flop improves the reliability of the operation sequence in which the transmission gate is disconnected before the gated input circuit becomes connected. In some embodiments, the modified timing circuit includes a first time delay circuit and a second time delay circuit. The output of the first time delay circuit is coupled to the input of the second time delay circuit. A clock signal at the output of the first time delay circuit is coupled to the transmission gate, and a clock signal at the output of the second time delay circuit is coupled to the gated input circuit. In some embodiments, at least a portion of the first gate conductor in the time delay circuit is located on top of a structure having an active region.

[0030] Figure 1A-1B This is a circuit diagram of a master-slave flip-flop 100 and a timing circuit 180 for generating a clock signal for the master-slave flip-flop 100, according to some embodiments. Figure 1B In this circuit, the sequential circuit 180 includes time delay circuits 182, 184, 186, 185, and 187. The sequential circuit 180 receives a base clock signal CP and generates various time-delayed clock signals clkb, clkbb, clkbbb, clkb_m, and clkbb_m. These time-delayed clock signals are coupled to the master-slave flip-flop 100 to control the operation of various components in the master-slave flip-flop 100. Figure 2 It is a timing diagram of various clock signals in the timing circuit 180 and various data signals in the master-slave flip-flop 100 according to some embodiments.

[0031] exist Figure 1B In this circuit, the basic clock signal CP is received at the input of the time delay circuit 182, and an inverted version of the basic clock signal CP with a certain time delay is generated at the output of the time delay circuit 182 as the first clock signal clkb. Because the first clock signal clkb is the inverted version of the basic clock signal CP, when the basic clock signal CP changes from logic low (LOW) to logic high (HIGH), the first clock signal clkb correspondingly changes from logic high to logic low, as shown below. Figure 2 As shown. The falling edge of the first clock signal clkb follows the rising edge of the base clock signal CP with a certain time delay. Similarly, as... Figure 2 As shown, when the base clock signal CP changes from logic high to logic low, the first clock signal clkb changes from logic low to logic high accordingly. The rising edge of the first clock signal clkb follows the falling edge of the base clock signal CP and also has a certain time delay.

[0032] exist Figure 1B In this circuit, the first clock signal clkb from the output of time delay circuit 182 is received at the input of time delay circuit 184, and an inverted version of the first clock signal clkb with a certain time delay is generated at the output of time delay circuit 184 as a second clock signal clkbb. Time delay circuit 185 receives the second clock signal clkbb at one input and a scan enable signal SE at the other input. If the scan enable signal SE is set to logic low, an inverted version of the second clock signal clkbb with a certain time delay is generated at the output of time delay circuit 185 as a third clock signal clkb_m. The output signal of time delay circuit 185 is coupled to the input of time delay circuit 187, and an inverted version of the third clock signal clkb_m is generated at the output of time delay circuit 187 as a clock signal clkbb_m. Furthermore, in Figure 1B In the process, the second clock signal clkbb is also received by the time delay circuit 186, and the inverted version of the second clock signal clkbb is generated at the output of the time delay circuit 186 as the clock signal clkbbbb.

[0033] exist Figure 2 In the timing diagram, the base clock signal CP has a time period T with a 50% duty cycle, and one of the falling edges of the base clock signal CP occurs at time t0, as shown in the figure. The first clock signal clkb is delayed relative to the base clock signal CP by a certain time. a, and at time t0+ Point a has a rising edge. Furthermore, the second clock signal clkbb is delayed relative to the first clock signal clkb by a certain time. b, and the clock signal clkbbbb is delayed relative to the second clock signal clkbb by a certain time. d. One of the falling edges of the second clock signal clkbb at time t0+ a+ At point b, and one of the rising edges of the clock signal clkbbb at time t0+ a+ b+ At point d. Furthermore, the third clock signal clkb_m is delayed relative to the second clock signal clkbb by a certain time. c, and the clock signal clkbb_m is delayed relative to the third clock signal clkb_m by a certain time. e. One of the rising edges of the third clock signal clkb_m at time t0+ a+ b+ At point c, and one of the falling edges of the clock signal clkbb_m at time t0+ a+ b+ c+ e.

[0034] In some embodiments, each of time delay circuits 182, 184, 186, and 187 is implemented as an inverter gate, and time delay circuit 185 is implemented as a NOR gate. Other implementations of the time delay circuits are within the scope of this disclosure. For example, in some alternative embodiments, one or more of time delay circuits 182, 184, 186, and 187 are implemented as three inverter gates connected in series. In some alternative embodiments, time delay circuit 185 is implemented as a NOR gate coupled to two inverter gates connected in series.

[0035] exist Figure 1A In this configuration, the master-slave flip-flop 100 includes a gated input circuit 110, a master latch 120, a transmission gate 130, a slave latch 140, and an inverter 150. The gated input circuit 110 receives input data D at the input terminals of the master-slave flip-flop 100 and receives clock signals clkb_m and clkbb_m from the timing circuit 180. The master latch 120, coupled between the gated input circuit 110 and the transmission gate 130, receives clock signals clkbb and clkbbb from the timing circuit 180. The transmission gate 130, coupled between the master latch 120 and the slave latch 140, receives clock signals clkbb and clkb from the timing circuit 180. The slave latch 140, coupled between the transmission gate 130 and the inverter 150, receives clock signals clkb and clkbb from the timing circuit 180.

[0036] exist Figure 1A In this circuit, the gated input circuit 110 is implemented as a clock inverter. The input transmission state of the gated input circuit 110 is controlled by clock signals clkb_m and clkbb_m received from the timing circuit 180. When the third clock signal clkb_m is at a logic high level and / or the clock signal clkbb_m is at a logic low level, the input transmission state of the gated input circuit 110 is set to the connected state, and an inverted input data D is generated at the output of the gated input circuit 110. The output of the gated input circuit 110 is coupled to the input node ml_ax of the main latch 120. Figure 2 In the time sequence diagram, from time t1=t0+ a+ b+ c to time t0+ a+ b+ c+ During a time interval of e+T / 2 and from time t4=t0+ a+ b+ c+T to time t0+ a+ b+ c+ During another time interval of e+3T / 2, the input transmission state of the gated input circuit 110 is driven to the connected state.

[0037] exist Figure 1A In the main latch 120, there are inverters 122 and clock inverters 124 driven by clock signals clkbb and clkbbbb. When the second clock signal clkbb is logic low and the clock signal clkbbbb is logic high, the main latch 120 is in a non-latched state, and the output signal of the clock inverter 124 is the inverted version of its input signal. When the second clock signal clkbb is logic high and / or the clock signal clkbbbb is logic low, the main latch 120 is in a latched state, and the signal at the output node ml_b is latched in the main latch 120. Figure 2 In the time sequence diagram, from time t2=t0+ a+ b+T / 2 to time t0+ a+ b+ During a time interval d+T and from time t5=t0+ a+ b+3T / 2 to time t0+ a+ b+ During another time interval d+2T, the master latch 120 is latched.

[0038] exist Figure 1A In this circuit, transmission gate 130 is controlled by a second clock signal clkbb and a first clock signal clkb received from timing circuit 180. When the second clock signal clkbb is at a logic high level and / or the first clock signal clkb is at a logic low level, the transmission state of transmission gate 130 is set to the connected state, and it is electrically connected from the input node sl_a of latch 140 to the output node ml_b of master latch 120. Figure 2 In the time series diagram, from time t0+ a+T / 2 to time t0+ a+ b+T is a time interval and from time t0+ a+3T / 2 to time t0+ a+ During another time interval b+2T, the transmission state of transmission gate 130 is driven to the connection state.

[0039] exist Figure 1A In this configuration, latch 140 includes an inverter 142 and a clock inverter 144 driven by clock signals clkb and clkbb. When the first clock signal clkb is logic low and the second clock signal clkbb is logic high, latch 140 is in a non-latched state, and the output signal of clock inverter 144 is the inverted version of its input signal. When the first clock signal clkb is logic high and / or the second clock signal clkbb is logic low, latch 140 is in a latched state, and the signal at output node sl_bx is latched in latch 140. Figure 2 In the time series diagram, from time t0+ a to time t0+ a+ During a time interval of b+T / 2 and from time t3=t0+ a+T to time t5=t0+ a+ During another time interval b+3T / 2, it is latched from latch 140.

[0040] In addition to the waveforms of various clock signals generated by the timing circuit 180, Figure 2 The input signal D(t), the output signal Q(t), and the signals at circuit nodes ml_ax, ml_b, sl_a, and sl_bx are also described. Figure 2 In this example, as a non-restrictive one, if the input signal D(t) has logic value D1 from time t0 to time t0+T and logic value D2 from time t0+T to time t0+2T, then the output signal Q(t) has logic value D1 from time t2 to time t2+T and logic value D2 from time t2+T to time t2+2T. Here, time t2 = t0 + a+ b+T / 2. The process of generating the output signal Q(t) based on the input signal D(t) is described below with reference to the signals at circuit nodes ml_ax, ml_b, sl_a, and sl_bx.

[0041] exist Figure 2 In the middle, from time t1=t0+ a+ b+ From c until time t1+ At the end of e+T / 2, the gated input circuit 110 is set to the connected state, and the signal at the input node ml_ax of the main latch 120 is ~D(T), where ~D(T) is the inverse of the input data D(T). At time t1, the main latch 120 is not latched, and the signal at the output node ml_b of the main latch 120 is... ml_ax(t), ml_ax(t) is the inverse of the signal ml_ax(t) at the input node ml_ax of the master latch 120. At time t1, the transmission gate 130 is in the open state, and the input node sl_a of the slave latch 140 is isolated from the output node ml_b of the master latch 120. At time t1, the slave latch 140 is in the latched state, and the signal at the output node sl_bx of the slave latch 140 is latched to the previous value. D0, the previous value D0 is the inverted signal of logic value D0. At time t1, the output signal Q(t) of master-slave flip-flop 100 remains at logic value D0.

[0042] exist Figure 2 In the expression, from time t1 to time t2, the signal ml_b(t) at the output node ml_b is equal to the inverse of the signal ml_ax(t), and the signal ml_ax(t) at the input node ml_ax is equal to the inverse of the input signal D(t). That is, ml_b(t) = ml_ax(t), and ml_ax(t) = D(t). Therefore, the signal at the output node ml_b is equal to the input data D(t), i.e., ml_b(t) = D(t). At time t2, the signal at the output node ml_b of the main latch 120 is equal to the logic value D1. From time t2 to time t2+ At time t2, the logic value D1 at the output node ml_b is latched. Furthermore, at time t2, transmission gate 130 is in a connected state, and the signal sl_a(t) at the input node sl_a of latch 140 is the same as the signal ml_b(t) at the output node ml_b of master latch 120, having the logic value D1. Starting from time t2, latch 140 is not latched, and the signal at the output node sl_bx is the inverse of the signal at the input node sl_a. At least during the time period from time t2 to time t3, the signal at the input node sl_a of latch 140 is the same as the logic value D1. Therefore, from time t2 to time t3, the signal at the output node sl_bx of latch 140 is the same as the logic value D1. D1 (the inverted version of logic signal D1) is the same. From time t3 to time t5 = t3 + b+T / 2, the logic value at the output node sl_bx of latch 140. D1 is latched. Therefore, from time t2 to time t5, the output node sl_bx is a logical value. D1, from time t2 to time t5 = t2 + T, the output signal Q(t) of the master-slave flip-flop 100 is logic value D1.

[0043] Similarly, in Figure 2 In the example, when the input signal D(t) has a logic value D2 from time t0+T to time t0+2T, in response, the output signal Q(t) of the master-slave flip-flop 100 generates a logic value D2 from time t5 to time t5+T. Specifically, in Figure 2 During the time period from t4 to t5, the gated input circuit 110 is in a connected state, the master latch 120 is in an unlatched state, and the signal at the output node ml_b of the master latch 120 is the logic value D2. Starting from time t5, the logic value D2 at the output node ml_b is latched. During the time period from t5 to t6, the output node ml_b of the master latch 120 remains with the logic value D2, the transmission gate 130 is in a connected state, the slave latch 140 is in an unlatched state, and the signal at the output node sl_bx of the slave latch 140 is the logic value D2. D2. From time t6 to time t5+T (not shown in the diagram), the output node sl_bx of latch 140 is latched as a logical value. D2. Therefore, from time t5 to time t5+T, the output signal Q(t) of the master-slave flip-flop 100 is D2, where D2 is the logic value at the output node sl_bx from time t5 to time t5+T. The inversion of D2.

[0044] Figures 3A-3B According to some embodiments Figure 1A-1B A circuit diagram of a specific embodiment of the master-slave flip-flop 100 and the timing circuit 180. Figure 3A middle, Figure 1A Each of the inverters 122, 142, and 150 includes a p-type transistor and an n-type transistor connected in series between two power supplies. Furthermore, in Figure 3A In the transmission gate 130, a p-type transistor and an n-type transistor are connected in parallel between the input and output terminals of the transmission gate 130. The gate terminals of the p-type and n-type transistors are respectively configured to receive two clock signals clkbb and clkb for controlling the transmission state of the transmission gate 130. When the clock signal clkbb is at a logic high level and / or the first clock signal clkb is at a logic low level, the transmission state of the transmission gate 130 is in the connected state, and the output terminal of the transmission gate 130 is conductively connected to the input terminal of the transmission gate 130. When the clock signal clkbb is at a logic low level and the first clock signal clkb is at a logic high level, the transmission state of the transmission gate 130 is in the disconnected state, and the signal at the output terminal of the transmission gate 130 does not respond to the signal change at the input terminal of the transmission gate 130.

[0045] exist Figure 3A middle, Figure 1A Each of the clock inverters 112, 124, and 144 includes two p-type transistors and two n-type transistors, each connected in series between two power supplies. In each of the clock inverters 112, 124, and 144, the gate terminals of the first p-type transistor and the first n-type transistor are connected together as inverter input terminals, while the gate terminals of the second p-type transistor and the second n-type transistor are respectively configured to receive two clock signals used to control the transmission state of the inverter. For example, in clock inverter 124, the gate terminals of the first p-type transistor and the first n-type transistor are connected together as inverter input terminals (which are connected to the output of inverter 122), the gate terminal of the second p-type transistor is configured to receive the clock signal clkbbb, and the gate terminal of the second n-type transistor is configured to receive the clock signal clkbb. When the clock signal clkbbb is logic low and / or the clock signal clkbb is logic high, clock inverter 124 acts as an inverter for latching the signal at the output node ml_b of master latch 120. When the clock signal clkbbb is at logic high and the clock signal clkbbb is at logic low, the clock inverter 124 is in the off state, and the output signal of the clock inverter 124 does not respond to the signal change at the input terminal of the clock inverter 124. When the clock inverter 124 is in the off state, the main latch 120 is not latched.

[0046] Similarly, in clock inverter 144, the gate terminals of the first p-type transistor and the first n-type transistor are connected together as inverter input terminals (which are connected to the output of inverter 142). The gate terminal of the second p-type transistor is configured to receive the clock signal clkbb, and the gate terminal of the second n-type transistor is configured to receive the clock signal clkb. When the clock signal clkbb is logic low and / or the clock signal clkb is logic high, clock inverter 144 acts as an inverter to latch the signal at the output node sl_bx of latch 140. When the clock signal clkbb is logic high and the clock signal clkb is logic low, clock inverter 144 is in the off state, and the output signal of clock inverter 144 does not respond to signal changes at the input terminals of clock inverter 144. When clock inverter 144 is in the off state, latch 140 is not latched.

[0047] exist Figure 3B middle, Figure 1B Each of the inverters INV1, INV2, INV3, and INV4 includes a p-type transistor and an n-type transistor connected in series between the two power supplies. Figure 1BThe NOR gate comprises two p-type transistors and two n-type transistors. The two p-type transistors are connected in series between the power supply VDD and the output node Z. The two n-type transistors are connected in parallel between the output node Z and the power supply VSS. The gate terminals of the first p-type transistor and the first n-type transistor in the NOR gate are connected together as a first input terminal, which is connected to the output of the inverter INV2. The gate terminals of the second p-type transistor and the second n-type transistor in the NOR gate constitute a second input terminal, which is configured to receive the scan enable signal SE.

[0048] exist Figure 3A In this embodiment, the gated input circuit 110 is implemented as a clock inverter 112. The gate terminals of the first p-type transistor and the first n-type transistor in the clock inverter 112 are connected together, serving as the input terminals of the gated input circuit 110. The gate terminal of the second p-type transistor in the clock inverter 112 is configured to receive the clock signal clkbb_m, and the gate terminal of the second n-type transistor in the clock inverter 112 is configured to receive the clock signal clkb_m. When the clock signal clkbb_m is at a logic low level and / or at a logic high level, the clock inverter 112 functions as an inverter to generate an inverted output signal that is the inverted version of the input data signal. When the clock signal clkbb_m is at a logic high level and at a logic low level, the clock inverter 112 is in an off state, and the output signal of the clock inverter 112 does not respond to signal changes at the input terminals of the clock inverter 112. When the clock inverter 112 is in the off state, the input node ml_ax of the main latch 120 is isolated from the input terminal D of the gated input circuit 110.

[0049] exist Figure 2 In the timing diagram, because the clock signal clkb_m is delayed relative to the second clock signal clkbb by a certain time... c, so before the gated input circuit 110 becomes connected (in Figure 2 At the rising edge of the clock signal clkb_m), transmission gate 130 is open (at Figure 2 The falling edge of the clock signal clkbb). Therefore, during the time interval from the falling edge of the base clock signal CP to the falling edge of the clock signal clkbb, the signal change at the input of the gated input circuit 110 will not propagate to the input node sl_a of the latch 140.

[0050] The timing circuit 180 provides improved reliability for operation sequences where the transmission gate 130 is disconnected before the gated input circuit 110 becomes connected. Using the timing circuit 180, the above-described operation sequence is ensured even if the falling edge of the clock signal clkbb varies significantly. In some other timing circuit designs, however, as the power supply voltage difference between VDD and VSS decreases and approaches a threshold, the variation in the falling edge of the clock signal clkbb may become too large, and these variations may negatively impact the reliability of the above-described operation sequence. In some embodiments, due to the improved reliability of the above-described operation sequence, the power supply voltage difference between VDD and VSS in the timing circuit 180 is lower than the power supply voltage difference in some other timing circuit designs.

[0051] Figures 4A-4B According to some embodiments Figure 1A-1B A circuit diagram of a specific embodiment of the master-slave flip-flop 100 and the sequential circuit 180. Regarding the sequential circuit 180, Figure 4B The implementation methods and Figure 3B The implementation method is the same as in the previous one. For master-slave trigger 100, Figure 4A The implementation method in is based on Figure 3A The implementation method is modified. Figure 3A The gated input circuit 110 is implemented as a single clock inverter 112, while Figure 4A The gated input circuit 110 includes two clock inverters 112A and 112B and another scan input circuit 116. The input terminals of clock inverters 112A and 112B are connected together to receive input data D for the gated input circuit 110. The output terminals of clock inverters 112A and 112B and the output terminal of scan input circuit 116 are connected together as the output terminals of the gated input circuit 110. Each of the two clock inverters 112A and 112B is controlled by two clock signals clkbb_m and clkb_m.

[0052] The scan input circuit 116 includes three p-type transistors and three n-type transistors, all connected in series between two power supplies. The three p-type transistors are connected in series between the power supply VDD and the output terminal of the scan input circuit 116 (which is directly connected to the input node ml_ax of the main latch 120). The three n-type transistors are connected in series between the output terminal of the scan input circuit 116 and the power supply VSS. The gate terminals of the first p-type transistor and the first n-type transistor in the scan input circuit 116 are configured to receive the scan input signal SI. The gate terminal of the second p-type transistor in the scan input circuit 116 is configured to receive the clock signal clkbb, and the gate terminal of the second n-type transistor in the scan input circuit 116 is configured to receive the clock signal clkb. The gate terminal of the third p-type transistor in the scan input circuit 116 is configured to receive the signal seb from the inverter 105, and the third n-type transistor in the scan input circuit 116 is configured to receive the scan enable signal SE. The input of inverter 105 is also configured to receive a scan enable signal SE, and the output signal seb of inverter 105 is the inverse of the scan enable signal SE.

[0053] During operation, when the scan enable signal SE is at a logic high level, both the third p-type transistor and the third n-type transistor in the scan input circuit 116 are turned on, and the scan input circuit 116 is enabled. When the scan input circuit 116 is enabled, it is equivalent to a clock inverter controlled by clock signals clkbb and clkb, and also receives the scan input signal SI as an input signal. Furthermore, when the scan enable signal SE is held at a logic high level, one of the inputs of the NOR gate is held at a logic high level. As a result, the clock signal clkb_m is held at a logic low level, and the clock signal clkbb_m is held at a logic high level. When clock signals clkb_m and clkbb_m are applied respectively to the gate terminals of the n-type transistor and the second p-type transistor in each of clock inverters 112A and 112B, the logic low level at the gate terminal of the n-type transistor (i.e., the clock signal clkb_m) and the logic high level at the gate terminal of the p-type transistor (i.e., the clock signal clkbb_m) set each of clock inverters 112A and 112B to the off state. This isolates the signal at the input node ml_ax of the master latch 129 from the data input signal D at the input terminal of the gated input circuit 110 during the period when the scan enable signal SE is held at the logic high level.

[0054] In the gated input circuit 110, when the scan enable signal SE is at a logic high level, the data input signal D is disabled and the scan input signal SI is enabled to generate an output signal at the output terminal of the gated input circuit 110. Conversely, when the scan enable signal SE is at a logic low level, the data input signal D is enabled and the scan input signal SI is disabled to generate an output signal at the output terminal of the gated input circuit 110.

[0055] Figure 5A According to some embodiments Figure 3B and Figure 4B The layout diagram of some parts of the sequential circuit 180 in the middle. Figures 5B-5D According to some embodiments Figure 5A The layout diagram shows a cross-sectional view of the sequential circuit 180 specified in the diagram. Figure 5E According to some embodiments Figure 5A The equivalent circuit of a part of the layout diagram.

[0056] exist Figure 3B and Figure 4B In the sequence circuit 180, four inverters INV1-INV4 and a NOR gate are included. Figure 5A In the sequential circuit 180 specified in the layout diagram, inverters INV1, INV2, and INV3 are fabricated in the first region 501 of the integrated circuit, and an NOR gate is fabricated in the second region 502. The location of inverter INV4 is not explicitly indicated in the layout diagram.

[0057] like Figure 5A As specified in the layout diagram, in the first region 501, each of the inverters INV1, INV2, and INV3 includes a corresponding gate conductor that intersects with the p-type active region structure 82p and the n-type active region structure 82n. In some embodiments, the p-type active region structure 82p and the n-type active region structure 82n are fin structures, and the transistors in the inverters INV1, INV2, and INV3 are fin transistors. In some embodiments, the p-type active region structure 82p and the n-type active region structure 82n are nanosheet structures, and the transistors in the inverters INV1, INV2, and INV3 are nanosheet transistors. In some embodiments, the p-type active region structure 82p and the n-type active region structure 82n are nanowire structures, and the transistors in the inverters INV1, INV2, and INV3 are nanowire transistors.

[0058] Gate conductor 551 intersects with p-type active region structures 82p and n-type active region structures 82n, and correspondingly forms channel regions in INV2 for p-type transistor T2p and n-type transistor T2n. Gate conductor 553 intersects with p-type active region structures 82p and n-type active region structures 82n, and correspondingly forms channel regions in INV1 for p-type transistor T1p and n-type transistor T1n. Gate conductor 555 intersects with p-type active region structures 82p and n-type active region structures 82n, and correspondingly forms channel regions in INV3 for p-type transistor T3p and n-type transistor T3n. Although each dummy gate conductor 552p, 554p, 556p, 552n, 554n, and 556n intersects with an active region structure, each intersection does not correspond to a channel of the operating transistor in the timing circuit 180. Figure 5E It is described Figure 5A The equivalent circuit formed by the three inverters (INV1, INV2, and INV3), the three p-type transistors (T1p, T2p, and T3p), and the three n-type transistors (T1n, T2n, and T3n).

[0059] exist Figure 5A and Figure 5E In the layout diagram shown, each of terminal conductors 531p, 533p, and 535p intersects with the p-type active region structure 82p at the corresponding source region of one of the p-type transistors T2p, T1p, and T3p. Each of terminal conductors 531n, 533n, and 535n intersects with the n-type active region structure 82n at the corresponding source region of one of the n-type transistors T2n, T1n, and T3n. Each of terminal conductors 531p, 533p, and 535p is connected to a power rail configured to provide power VDD. Figure 5A (Not shown in the image). Each of terminal conductors 531n, 533n, and 535n is connected to a power rail configured to provide power to VSS ( Figure 5A (Not shown in the image).

[0060] exist Figure 5A and Figure 5EIn the layout diagram shown, terminal conductor 534 intersects with p-type active region structure 82p at the drain region of p-type transistor T1p and with n-type active region structure 82n at the drain region of n-type transistor T1n. Terminal conductor 534 forms the output terminal of inverter INV1. Terminal conductor 534 is electrically connected to horizontal wire 540 through terminal via connection VD1. Horizontal wire 540 is electrically connected to gate conductor 551 through gate via connection VG2. Gate conductor 551 serves as the input terminal of inverter INV2. Terminal conductor 532 intersects with p-type active region structure 82p at the drain region of p-type transistor T2p and with n-type active region structure 82n at the drain region of n-type transistor T2n. Terminal conductor 532 forms the output terminal of inverter INV2. Terminal conductor 532 is electrically connected to horizontal wire 520 through terminal via connection VD2. The horizontal conductor 520 is electrically connected to the gate conductor 555 through the gate via connection VG3. The gate conductor 555 serves as the input terminal of the inverter INV3.

[0061] Apart from Figure 5A and Figure 5E Still Figure 5D The cross-sectional view shows the connection from the output terminal of inverter INV1 to the input terminal of inverter INV2, and... Figure 5C The cross-sectional view shows the connection from the output terminal of inverter INV2 to the input terminal of inverter INV3.

[0062] Figure 5C It is the cutting plane P-P' according to some embodiments Figure 5A A cross-sectional diagram of the circuit. In Figure 5C In this configuration, each of the gate conductors 551, 552n, 553, 554n, 555, and 556n intersects with the n-type active region structure 82n on the substrate 510. Terminal conductor 532 is electrically connected to horizontal conductor 520 via terminal via connection VD2. Horizontal conductor 520 is electrically connected to gate conductor 555 via gate via connection VG3. Horizontal conductor 520 is located in a first connection layer M0, which sits on top of the insulating material covering the gate conductors and terminal conductors.

[0063] Figure 5D It is the cutting plane Q-Q' according to some embodiments Figure 5A A cross-sectional diagram of the circuit. In Figure 5DIn this configuration, each of gate conductors 551, 552p, 553, 554p, 555, and 556p intersects with the p-type active region structure 82p on the substrate 510. Terminal conductor 534 is electrically connected to horizontal conductor 540 via terminal via connection VD1. Horizontal conductor 540 is electrically connected to gate conductor 551 via gate via connection VG2. Horizontal conductor 540 is located in a first connection layer M0, which sits on top of an insulating material covering the gate conductor and terminal conductor. Figure 5D As shown, the gate via connection VG2, used to connect the gate conductor 551 to the horizontal wire 540, is at least partially located on top of the p-type active region structure 82p. Figure 5B The diagram also depicts the position of the gate via connection VG2 relative to the p-type active region structure 82p.

[0064] Figure 5B It is the cutting plane S-S' according to some embodiments Figure 5A A cross-sectional diagram of the circuit. For example... Figure 5B As shown, the gate conductor 551 intersects with both the p-type active region structure 82p and the n-type active region structure 82n on the substrate 510. Horizontal wires 520 and 540 are located in the first interconnect layer M0 above the gate conductor 551. The horizontal wire 540 is electrically connected to the gate conductor 551 through the gate via connection portion VG2. Figure 5B and Figure 5D The combined cross-sectional view indicates that the entire gate via connection VG2 is located on top of the p-type active region structure 82p. In some alternative embodiments, only a portion of the gate via connection VG2 is located on top of the p-type active region structure 82p. Figures 6A-6D The diagram illustrates a non-limiting example of an integrated circuit implemented in an alternative embodiment.

[0065] Figure 6A According to some embodiments Figure 3B and Figure 4B The layout diagram of some parts of the sequential circuit 180 in the middle. Figure 6B It is the cutting plane S-S' according to some embodiments Figure 6A A cross-sectional view of the circuit. Figure 6C It is the cutting plane P-P' according to some embodiments Figure 6A A cross-sectional view of the circuit. Figure 6D It is the cutting plane Q-Q' according to some embodiments Figure 6A A cross-sectional view of the circuit.

[0066] By moving the gate via connection VG2, the terminal via connection VD1, and the horizontal wire 540 along the Y direction, only a portion of the gate via connection VG2 is positioned directly on top of the p-type active region structure 82p, thereby... Figure 5A Modify the layout diagram in the middle. Figure 6A The layout diagram. Figure 5A The equivalent circuit of the layout diagram in the diagram and Figure 6A The equivalent circuits of the layout diagrams in the diagrams are the same; therefore, according to some embodiments, Figure 5E still Figure 6A The equivalent circuit of some parts of the layout diagram.

[0067] In addition, due to Figure 6A The layout diagram in the middle is Figure 5A The layout diagram in the middle was modified, and therefore accordingly, Figure 6B and Figure 6D The cross-sectional view in the middle is based on Figure 5B and Figure 5D It was modified from the cross-sectional view in the image, and Figure 6C The cross-sectional view and Figure 5C The cross-sectional view is the same as that in the previous section.

[0068] exist Figure 6D In the middle, terminal conductor 534 is electrically connected to horizontal conductor 540 through terminal via connection portion VD1. Horizontal conductor 540 is electrically connected to gate conductor 551 through gate via connection portion VG2. Horizontal conductor 540 is in the first connection layer M0, which is on top of the isolation material covering the gate conductor and terminal conductor. Although the p-type active region structure 82p on substrate 510 is in Figure 5D In the cross-sectional view, however, the p-type active region structure 82p on the substrate 510 does not appear. Figure 6D In the cross-sectional view, this is because Figure 6A The cutting plane Q-Q' in the structure does not pass through the p-type active region structure 82p.

[0069] In 6B, the gate conductor 551 intersects with both the p-type active region structure 82p and the n-type active region structure 82n on the substrate 510. Horizontal wires 520 and 540 are located in the first interconnect layer M0 above the gate conductor 551. The horizontal wire 540 is electrically connected to the gate conductor 551 through the gate via connection portion VG2. Figure 6B and Figure 6D The combined cross-sectional view in the diagram indicates that only a portion of the gate via connection VG2 is located directly on top of the p-type active region structure 82p.

[0070] Figure 5A Another modification to the layout diagram is Figure 7A The layout diagram. Figure 7A According to some embodiments Figure 3B and Figure 4B The layout diagram of some parts of the sequential circuit 180 in the middle. Figure 7B It is the cutting plane S-S' according to some embodiments Figure 7AA cross-sectional view of the circuit. Figure 7C It is the cutting plane P-P' according to some embodiments Figure 7A A cross-sectional view of the circuit. Figure 7D It is the cutting plane Q-Q' according to some embodiments Figure 7A A cross-sectional view of the circuit. Figure 7E According to some embodiments Figure 7A The equivalent circuit of a part of the layout diagram.

[0071] By replacing the dummy gate conductors 552n and 552p with the gate conductor 552, thereby according to Figure 5A Modify the layout diagram in the middle. Figure 7A The layout diagram is shown in the image. The gate conductor 552 intersects with the p-type active region structure 82p and the n-type active region structure 82n, and correspondingly forms channel regions in the inverter INV2 for the p-type transistor T2Bp and the n-type transistor T2Bn. The gate conductor 552 is electrically connected to the horizontal conductor 540 through the gate via connection VG2b. Figure 7A and Figure 7E In, with Figure 5A and Figure 5E Compared to the inverter INV2 (formed by transistors T2p and T2n) in the original diagram, the inverter INV2 formed by transistors T2p, T2n, T2Bp, and T2Bn has improved drive strength. That is, Figure 7A The drive strength of inverter INV2 in the middle is greater than Figure 5A The driving strength of the inverter INV2 in the middle.

[0072] In addition, due to Figure 7A The layout diagram in the middle is Figure 5A The layout diagram in the middle was modified, and therefore accordingly, Figure 7C and Figure 7D The cross-sectional view in the middle is based on Figure 5C and Figure 5D It was modified from the cross-sectional view in the image, and Figure 7B The cross-sectional view and Figure 5B The cross-sectional views are the same. Figure 7C In the middle, the gate conductor 552 replaces Figure 5C The dummy gate conductor 552n intersects with the n-type active region structure 82n in the channel region of the n-type transient T2Bn. Figure 7D In the middle, the gate conductor 552 replaces Figure 5D The dummy gate conductor 552p intersects with the p-type active region structure 82p in the channel region of the p-type transient T2Bp. Figure 7D The gate conductor 552 is electrically connected to the horizontal wire 540 through the gate via connection portion VG2b. Figure 7DIn inverter INV1, terminal conductor 534 is electrically connected to gate conductors 551 and 552 in inverter INV2.

[0073] exist Figure 5A , Figure 6A and Figure 7A In the layout diagram, inverters INV1, INV2, and INV3 in the sequential circuit 180 are implemented in the first region 501, and the NOR gate in the sequential circuit 180 is implemented in the second region 502. The NOR gate includes two p-type transistors and two n-type transistors. Figure 5A , Figure 6A and Figure 7A In this configuration, gate conductor 558 intersects with p-type active region structure 84p and n-type active region structure 84n respectively at the channel regions of the first p-type transistor and the first n-type transistor. Gate conductor 559 intersects with p-type active region structure 84p and n-type active region structure 84n respectively at the channel regions of the second p-type transistor and the second n-type transistor. Gate via connection VG8 electrically connects gate conductor 558 to a first corresponding horizontal wire (not shown) in the first metal layer M0. In some embodiments, the entire gate conductor 558 is located on top of the n-type active region structure 84n in the second region 502. In some embodiments, only a portion of gate conductor 558 is located on top of the n-type active region structure 84n in the second region 502. Similarly, gate via connection VG9 electrically connects gate conductor 559 to a second corresponding horizontal wire (not shown). In some embodiments, the entire gate conductor 559 is located on top of the n-type active region structure 84n in the second region 502. In some embodiments, only a portion of the gate conductor 559 is located on top of the n-type active region structure 84n in the second region 502.

[0074] In some embodiments, the drive strength of the inverter INV2 in the sequential circuit 180 is greater than the drive strength of the NOR gate in the sequential circuit 180. In some embodiments, when the inverter INV2 (e.g., Figure 7A When the inverter INV2 is formed by transistors T2p, T2n, T2Bp, and T2Bn and includes two gate conductors 551 and 552, the ratio of the drive strength of the inverter INV2 to the drive strength of the NOR gate is greater than 1.0. In some embodiments, the ratio of the drive strength of the inverter INV2 to the drive strength of the NOR gate is inversely proportional to the ratio of the output impedance of the inverter INV2 to the output impedance of the NOR gate.

[0075] In some embodiments, the clock signal used to drive the master-slave flip-flop 100 is provided by... Figure 1B The timing circuitry 180 in the middle is provided. In some alternative embodiments, the clock signal for driving the master-slave flip-flop 100 is provided by... Figure 1B The timing circuits in the 180 series are provided by different timing circuits.

[0076] Figures 8A-8B This is a circuit diagram of a master-slave flip-flop 100 and a timing circuit 880 for providing a clock signal to drive the master-slave flip-flop 100, according to some embodiments. The timing circuit 880 still includes inverters INV1, INV2, and INV3 in the first region 501, as shown by... Figure 5A , Figure 6A or Figure 7A The layout diagram specified in the diagram. Figure 8A Master-slave trigger 100 and Figure 4A The master-slave trigger 100 in the code is the same. However, Figure 8B The timing circuit 880 in the middle is a Figure 1B Modification of the sequential circuit 180 in [the code / system]. Figure 8B In the middle, the time delay circuit 183 replaces Figure 1B The input terminals of time delay circuit 185 and time delay circuit 183 are directly connected to the output terminals of time delay circuit 182. In some embodiments, time delay circuit 183 is implemented as a NAND gate in the second region 502.

[0077] Figure 8C This is a timing diagram of various clock signals in the sequential circuit 880 and various data signals in the master-slave flip-flops 100 according to some embodiments. Although Figure 8C The waveforms of the clock signals clkb_m and clkbb_m are similar to those in the original text. Figure 2 The waveforms of the clock signals clkb_m and clkbb_m are different, but Figure 8C The waveforms of other clock signals and Figure 2 The corresponding waveforms are the same. Figure 8C The waveforms of various data signals in the data are also related to Figure 2 The corresponding waveforms are the same. Figure 8C In the clock signal clkbb_m, the clock signal is delayed relative to the first clock signal clkb by a certain time. f, and the clock signal clkb_m is delayed relative to the clock signal clkbb_m by a certain time. e. In comparison, Figure 2 In the middle, the clock signal clkb_m is delayed relative to the second clock signal clkbb by a certain time. c, and the clock signal clkbb_m is delayed relative to the clock signal clkb_m by a certain time. e.

[0078] exist Figure 8CIn the timing diagram, because both clock signals clkbb and clkbb_m are delayed relative to the same clock signal clkb, in some embodiments, the delay time introduced by the NAND gate is... f is greater than the delay time introduced by inverter INV2. b. To improve the reliability of the master-slave flip-flop 100. For example, in some embodiments, when the gate via connection VG2 is located on top of the p-type active region structure 82p in the first region 501 (e.g. Figure 5A , Figure 6A , Figure 7A As shown, the delay time of the inverter INV2 in the first region 501 decreases. In some embodiments, when the gate via connection VG8 and / or the gate via connection VG9 are located at the top of the n-type active region structure 84n, the delay time of the NAND gate in the second region 502 increases. Figure 8C In the context, when the delay time introduced by the NAND gate is... f is greater than the delay time introduced by inverter INV2. At time b, the clock signal clkbb_m is delayed relative to the clock signal clkbb, and the gated input circuit 110 is changed to a connected state (in Figure 8C Before the falling edge of the clock signal clkbb_m, transmission gate 130 is turned off (in Figure 8C (The falling edge of the clock signal clkbb in the system). Therefore, during the time interval from the falling edge of the base clock signal CP to the falling edge of the clock signal clkbb, the signal change at the input of the gated input circuit 110 will not propagate to the input node sl_a of the latch 140.

[0079] supply Figure 1A , Figure 3A , Figure 4A and Figure 8A The master-slave flip-flop 100 is provided as a non-limiting example. A sequential circuit 180 is also provided (in...). Figure 1B , Figure 3B and Figure 4B (in) and sequential circuit 880 (in) Figure 8B (The following is a non-limiting example.) Other implementations of master-slave flip-flops and / or sequential circuitry are within the scope of this disclosure. Examples of master-slave flip-flops used with sequential circuitry 180 or 880 include asynchronous reset D flip-flops, asynchronous set D flip-flops, and asynchronous set / reset D flip-flops.

[0080] Figures 9A-9B This is a circuit diagram of a master-slave flip-flop 900A and a timing circuit 180 for providing a clock signal to drive the master-slave flip-flop 900A, according to some embodiments. Figure 9B The circuit diagram of the sequential circuit 180 in the middle and Figure 4B The timing circuit 180 in it is the same. Figure 9A In this configuration, the master-slave flip-flop 900A is an asynchronous reset D flip-flop. Each of the master latch 120A and the slave latch 140A is configured to receive a reset signal CD. During operation, when the reset signal CD is logic low, each p-type transistor having a gate terminal receiving the reset signal CD is in a channel-on state, and each n-type transistor having a gate terminal receiving the reset signal CD is in a channel-off state. Consequently, when the reset signal CD is logic low, Figure 9A The circuit of the main latch 120A is equivalent to Figure 4A The circuit of the main latch 120 in the middle, and Figure 9A The circuit of latch 140A is equivalent to Figure 4A The circuit of latch 140. When the reset signal CD is logic low, Figure 9A The master-slave trigger 900A in the middle is similar to Figure 4A It operates using the master-slave trigger 100 method.

[0081] During operation, when the reset signal CD is logic high, each p-type transistor with a gate terminal receiving the reset signal CD is in a channel-off state, and each n-type transistor with a gate terminal receiving the reset signal CD is in a channel-on state. As a result, when the reset signal CD is logic high, the signal at the output node ml_b of the master latch 120A becomes logic low, and the signal at the output node sl_bx of the slave latch 140A becomes logic high. When the reset signal CD is logic high, the signal at the output of the master-slave flip-flop 900A is reset to logic low.

[0082] Figures 10A-10B This is a circuit diagram of a master-slave flip-flop 900B and a timing circuit 180 for providing a clock signal to drive the master-slave flip-flop 900B, according to some embodiments. Figure 10B The circuit diagram of the sequential circuit 180 in the middle and Figure 4B The timing circuit 180 in it is the same. Figure 10A In this configuration, the master-slave flip-flop 900B is an asynchronous set D flip-flop. Each of the master latch 120B and the slave latch 140B is configured to receive a set signal SDN. During operation, when the set signal SDN is logic high, each p-type transistor having a gate terminal receiving the set signal SDN is in a channel-off state, and each n-type transistor having a gate terminal receiving the set signal SDN is in a channel-on state. As a result, when the set signal SDN is logic high, Figure 10A The circuit of the main latch 120B is equivalent to Figure 4A The circuit of the main latch 120 in the middle, and Figure 10A The circuit of latch 140B is equivalent to Figure 4A The circuit of latch 140. When the set signal SDN is at logic high level, Figure 10A The master-slave trigger 900B in the middle is similar to Figure 4A It operates using the master-slave trigger 100 method.

[0083] During operation, when the set signal SDN is logic low, each p-type transistor with a gate terminal receiving the set signal SDN is in the channel-on state, and each n-type transistor with a gate terminal receiving the set signal SDN is in the channel-off state. As a result, when the set signal SDN is logic low, the signal at the output node ml_b of the master latch 120B becomes logic high, and the signal at the output node sl_bx of the slave latch 140B becomes logic low. When the set signal SDN is logic low, the signal at the output of the master-slave flip-flop 900B is set to logic high.

[0084] Figure 11A-11B This is a circuit diagram of a master-slave flip-flop 900C and a timing circuit 180 for providing a clock signal to drive the master-slave flip-flop 900C, according to some embodiments. Figure 11B The circuit diagram of the sequential circuit 180 in the middle and Figure 4B The timing circuit 180 in it is the same. Figure 11A In this configuration, the master-slave flip-flop 900C is an asynchronous set / reset D flip-flop. Each of the master latch 120C and the slave latch 140C is configured to receive a reset signal CD and a set signal SDN. During operation, when the reset signal CD is logic high, each p-type transistor with a gate terminal receiving the reset signal CD is in a channel-off state, and each n-type transistor with a gate terminal receiving the reset signal CD is in a channel-on state. As a result, when the reset signal CD is logic high, the signal at the output node ml_b of the master latch 120C becomes logic low, and the signal at the output node sl_bx of the slave latch 140C becomes logic high. When the reset signal CD is logic high, regardless of the logic level of the set signal SDN, the signal at the output of the master-slave flip-flop 900C is reset to logic low.

[0085] During operation, when the reset signal CD is logic low, each p-type transistor with a gate terminal receiving the reset signal CD is in the channel-on state, and each n-type transistor with a gate terminal receiving the reset signal CD is in the channel-off state. As a result, when the reset signal CD is logic low, the operation of the master-slave flip-flop 900C depends on the logic level of the set signal SDN.

[0086] During operation, when the set signal SDN is logic low, each p-type transistor with a gate terminal receiving the set signal SDN is in a channel-on state, and each n-type transistor with a gate terminal receiving the set signal SDN is in a channel-off state. As a result, when the set signal SDN is logic low and the reset signal CD is simultaneously logic low, the signal at the output node ml_b of the master latch 120C becomes logic high, and the signal at the output node sl_bx of the slave latch 140C becomes logic low. When the set signal SDN is logic low and the reset signal CD is simultaneously logic low, the signal at the output of the master-slave flip-flop 900C is set to logic high.

[0087] During operation, when the set signal SDN is logic high, each p-type transistor with a gate terminal receiving the set signal SDN is in a channel-off state, and each n-type transistor with a gate terminal receiving the set signal SDN is in a channel-on state. Consequently, when the set signal SDN is logic high and the reset signal CD is logic low, Figure 11A The circuit of the main latch 120C is equivalent to Figure 4A The circuit of the main latch 120 in the middle, and Figure 11A The circuit of latch 140C is equivalent to Figure 4A The circuit of latch 140. When the set signal SDN is logic high and the reset signal CD is logic low, Figure 11A The master-slave trigger 900C in the middle is similar to Figure 4A It operates using the master-slave trigger 100 method.

[0088] Figure 12 This is a flowchart of a method 1200 for operating a master-slave trigger according to some embodiments. It should be understood that... Figure 12 Additional operations are performed before, during, and / or after the method 1200 described herein, and some other processes may only be briefly described herein. In some embodiments, in Figure 4A The circuit diagram of the master-slave flip-flop is shown in the figure. Figure 4A The master-slave flip-flop 100 includes a gated input circuit 110, a master latch 120, a slave latch 140, and a transmission gate 130 coupled between the master latch 120 and the slave latch 140. The master latch 120 is coupled between the gated input circuit 110 and the transmission gate 130.

[0089] In operation 1210 of method 1200, a second clock signal that is delayed relative to the first clock signal is generated. Figure 4BIn the illustrated embodiment, a first clock signal clkb at the output of time delay circuit 182 is coupled to the input of time delay circuit 184, and a second clock signal clkbb is generated at the output of time delay circuit 184. In some embodiments, such as Figure 2 As shown, the second clock signal clkbb is the inverse of the first clock signal clkb, and is delayed by a certain time relative to the first clock signal clkb. b.

[0090] In operation 1220 of method 1200, a third clock signal is generated based on the second clock signal, and the third clock signal is delayed relative to the second clock signal. Figure 4B In the illustrated embodiment, the time delay circuit 185 receives a second clock signal clkbb at one input and a scan enable signal SE at another input, and generates a third clock signal clkb_m at the output of the time delay circuit 185. In some embodiments, such as Figure 2 As shown, the third clock signal clkb_m is the inverse of the second clock signal clkbb, and is delayed by a certain time relative to the second clock signal clkbb. c.

[0091] In operation 1230 of method 1200, a first clock signal and a second clock signal are sent to the transmission gate to change the transmission state of the transmission gate. Figure 4A In the illustrated embodiment, the second clock signal clkbb is coupled to the gate of the n-type transistor in transmission gate 130, and the first clock signal clkb is coupled to the gate of the p-type transistor in transmission gate 130. When the clock signal clkbb is at a logic high level and / or the first clock signal clkb is at a logic low level, the transmission state of transmission gate 130 is connected. When the clock signal clkbb is at a logic low level and the first clock signal clkb is at a logic high level, the transmission state of transmission gate 130 is disconnected.

[0092] In operation 1240 of method 1200, a third clock signal is used to control the input transmission state of the gated input circuit. Figure 4B In the illustrated embodiment, the output signal of time delay circuit 185 is coupled to the input of time delay circuit 187, and a fourth clock signal clkbb_m is generated based on the third clock signal clkb_m. Figure 4AIn this circuit, the input transmission state of the gated input circuit 110 is controlled by clock signals clkb_m and clkbb_m received from the timing circuit 180. When the third clock signal clkb_m is at a logic high level and / or the fourth clock signal clkbb_m is at a logic low level, the input transmission state of the gated input circuit 110 is set to the connected state. When the third clock signal clkb_m is at a logic low level and the fourth clock signal clkbb_m is at a logic high level, the input transmission state of the gated input circuit 110 is set to the disconnected state.

[0093] Figure 13 This is a block diagram of an electronic design automation (EDA) system 1300 according to some embodiments.

[0094] In some embodiments, EDA system 1300 includes an APR system. The design layout method described herein represents a wiring arrangement according to one or more embodiments that can be implemented, for example, using EDA system 1300 according to some embodiments.

[0095] In some embodiments, the EDA system 1300 is a general-purpose computing device including a hardware processor 1302 and a non-transitory computer-readable storage medium 1304. The storage medium 1304 is encoded with (i.e., stores) computer program code 1306 (i.e., a set of executable instructions) and other items. The instructions 1306, executed by the hardware processor 1302, represent (at least partially) an EDA tool that implements part or all of the methods described herein according to one or more embodiments (processes and / or methods described below).

[0096] Processor 1302 is electrically coupled to computer-readable storage medium 1304 via bus 1308. Processor 1302 is also electrically coupled to I / O interface 1310 via bus 1308. Network interface 1312 is also electrically connected to processor 1302 via bus 1308. Network interface 1312 is connected to network 1314, enabling processor 1302 and computer-readable storage medium 1304 to be connected to external components via network 1314. Processor 1302 is configured to execute computer program code 1306 encoded in computer-readable storage medium 1304 so that system 1300 can be used to perform some or all of the described processes and / or methods. In one or more embodiments, processor 1302 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application-specific integrated circuit (ASIC), and / or a suitable processing unit.

[0097] In one or more embodiments, the computer-readable storage medium 1304 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or apparatus or device). For example, the computer-readable storage medium 1304 includes semiconductor or solid-state memory, magnetic tape, removable computer disk, random access memory (RAM), read-only memory (ROM), rigid disk, and / or optical disk. In one or more embodiments using optical disk, the computer-readable storage medium 1304 includes a CD-ROM, a CD-R / W, and / or a digital video optical disc (DVD).

[0098] In one or more embodiments, storage medium 1304 stores computer program code 1306 configured to enable system 1300 (where such execution (at least partially) represents an EDA tool) to perform some or all of the described processes and / or methods. In one or more embodiments, storage medium 1304 also stores information facilitating the execution of some or all of the described processes and / or methods. In one or more embodiments, storage medium 1304 stores a standard cell library 1307 comprising standard cells such as those disclosed herein. In one or more embodiments, storage medium 1304 stores one or more layout diagrams 1309 corresponding to one or more layouts disclosed herein.

[0099] EDA system 1300 includes an I / O interface 1310. The I / O interface 1310 is coupled to an external circuit system. In one or more embodiments, the I / O interface 1310 includes a keyboard, keypad, mouse, trackball, trackpad, touchscreen, and / or cursor arrow keys for transmitting information and commands to processor 1302.

[0100] EDA system 1300 also includes a network interface 1312 coupled to processor 1302. Network interface 1312 allows system 1300 to communicate with a network 1314 to which one or more other computer systems are connected. Network interface 1312 includes: a wireless network interface, such as Bluetooth, WIFI, WIMAX, GPRS, or WCDMA; or a wired network interface, such as Ethernet, USB, or IEEE-1364. In one or more embodiments, some or all of the described processes and / or methods are implemented in two or more systems 1300.

[0101] System 1300 is configured to receive information via I / O interface 1310. The information received via I / O interface 1310 includes one or more of the following: instructions, data, design rules, standard cell libraries, and / or other parameters for processing by processor 1302. The information is transmitted to processor 1302 via bus 1308. EDA system 1300 is configured to receive UI-related information via I / O interface 1310. This information is stored as a user interface (UI) 1342 on computer-readable medium 1304.

[0102] In some embodiments, some or all of the described processes and / or methods are implemented as a standalone software application for processor execution. In some embodiments, some or all of the described processes and / or methods are implemented as a software application as part of an additional software application. In some embodiments, some or all of the described processes and / or methods are implemented as a plug-in to a software application. In some embodiments, at least one of the described processes and / or methods is implemented as a software application as part of an EDA tool. In some embodiments, some or all of the described processes and / or methods are implemented as a software application used by EDA system 1300. In some embodiments, a layout diagram including standard cells is generated using a tool such as VIRTUOSO®, available from CADENCE DESIGN SYSTEMS, or another suitable layout generation tool.

[0103] In some embodiments, these processes are implemented as functions of a program stored in a non-transitory computer-readable recording medium. Examples of non-transitory computer-readable recording media include, but are not limited to, external / removable and / or internal / built-in storage devices or memory units, such as one or more of the following: optical discs (e.g., DVDs), magnetic disks (e.g., hard disks), semiconductor memories (e.g., ROMs), RAMs, memory cards, etc.

[0104] Figure 13 This is a block diagram of an integrated circuit (IC) manufacturing system 1300 and an associated IC manufacturing process according to some embodiments. In some embodiments, based on the layout diagram, the manufacturing system 1300 is used to manufacture at least one of the following: (A) one or more semiconductor masks, or (B) at least one component in a layer of a semiconductor integrated circuit.

[0105] exist Figure 14In this IC manufacturing system 1400, entities such as design room 1420, mask room 1430, and IC fab 1450 interact with each other in the design, development, and manufacturing cycles and / or services related to the manufacture of IC devices 1460. The entities in system 1400 are connected via a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a variety of different networks, such as an intranet and the Internet. The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more other entities and provides services to and / or receives services from one or more other entities. In some embodiments, two or more of design room 1420, mask room 1430, and IC fab 1450 are owned by a single, larger company. In some embodiments, two or more of design room 1420, mask room 1430, and IC fab 1450 coexist in public facilities and use public resources.

[0106] Design studio (or design team) 1420 generates IC design layout 1422. IC design layout 1422 includes various geometric patterns designed for IC device 1460. These geometric patterns correspond to patterns of metal, oxide, or semiconductor layers that constitute the various components of the IC device 1460 to be manufactured. Various layer combinations form various IC features. For example, a portion of IC design layout 1422 includes various IC features, such as active regions, gate electrodes, source and drain electrodes, metal lines or vias for interlayer interconnects, and openings for bonding pads, to be formed in a semiconductor substrate (e.g., a silicon wafer) and in various material layers disposed on the semiconductor substrate. Design studio 1420 implements appropriate design procedures to form IC design layout 1422. Design procedures include one or more logic designs, physical designs, or location and routing. IC design layout 1422 is presented in one or more data files containing information about the geometric patterns. For example, IC design layout 1422 may be represented in GDSII or DFII file format.

[0107] Mask chamber 1430 includes data preparation 1432 and mask fabrication 1444. Mask chamber 1430 uses an IC design layout 1422 to fabricate one or more masks 1445 for fabricating various layers of an IC device 1460 according to the IC design layout 1422. Mask chamber 1430 performs mask data preparation 1432, in which the IC design layout 1422 is converted into a representative data file (“RDF”). Mask data preparation 1432 provides the RDF to mask fabrication 1444. Mask fabrication 1444 includes a mask writer. The mask writer converts the RDF into an image on a substrate, such as a mask (reticle) 1445 or a semiconductor wafer 1453. The design layout 1422 is manipulated by mask data preparation 1432 to conform to the specific characteristics of the mask writer and / or the requirements of the IC fab 1450. Figure 14 In this design, mask data preparation 1432 and mask manufacturing 1444 are shown as separate elements. In some embodiments, mask data preparation 1432 and mask manufacturing 1444 may be collectively referred to as mask data preparation.

[0108] In some embodiments, mask data preparation 1432 includes optical proximity correction (OPC), which uses lithographic enhancement techniques to compensate for image errors, such as those that may be caused by diffraction, interference, other process effects, etc. OPC adjusts the IC design layout diagram 1422. In some embodiments, mask data preparation 1432 also includes resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution auxiliary features, phase-shift masks, other suitable techniques, or combinations thereof. In some embodiments, inverse lithography (ILT) is also used, which treats OPC as an inverse imaging problem.

[0109] In some embodiments, mask data preparation 1432 includes a mask rule checker (MRC) that uses a set of mask creation standard rules to check the IC design layout 1422, which has already been processed in the OPC. This set of mask creation standard rules includes certain geometric and / or connectivity constraints to ensure sufficient margin to account for variability in semiconductor manufacturing processes, etc. In some embodiments, the MRC modifies the IC design layout 1422 to compensate for constraints during mask fabrication 1444, and can undo some modifications performed by the OPC to meet the mask creation standard rules.

[0110] In some embodiments, mask data preparation 1432 includes a lithography process check (LPC) simulating a process that will be implemented by IC fab 1450 to manufacture IC device 1460. The LPC simulates this process based on IC design layout 1422 to create a simulated manufactured device, such as IC device 1460. Process parameters in the LPC simulation may include parameters associated with various processes in the IC manufacturing cycle, parameters associated with the tools used to manufacture the IC, and / or other aspects of the manufacturing process. The LPC considers various factors, such as aerial image contrast, depth of focus (“DOF”), mask error enhancement factor (“MEEF”), other suitable factors, or combinations thereof. In some embodiments, after the simulated manufactured device is created by the LPC, if the shape of the simulated device is insufficient to meet design rules, OPC and / or MRC are repeated to further refine the IC design layout 1422.

[0111] It should be understood that the above description of mask data preparation 1432 has been simplified for clarity. In some embodiments, data preparation 1432 includes additional features such as logic operations (LOPs) to modify the IC design layout 1422 according to manufacturing rules. Furthermore, the processes applied to the IC design layout 1422 during data preparation 1432 can be performed in various different sequences.

[0112] Following mask data preparation 1432 and during mask fabrication 1444, a mask 1445 or a set of masks 1445 is fabricated based on a modified IC design layout 1422. In some embodiments, mask fabrication 1444 includes performing one or more photolithographic exposures based on the IC design layout 1422. In some embodiments, an electron beam (e-beam) or multiple electron beams are used to form a pattern on the mask (photomask or scribe line) 1445 based on the modified IC design layout 1422. The mask 1445 can be formed using various techniques. In some embodiments, a binary technique is used to form the mask 1445. In some embodiments, the mask pattern includes opaque areas and transparent areas. A radiation beam (e.g., an ultraviolet (UV) beam) used to expose an image-sensitive material layer (e.g., photoresist) coated on the wafer is blocked by the opaque areas and passes through the transparent areas. In one example, a binary mask version of mask 1445 includes a transparent substrate (e.g., fused silica) and an opaque material (e.g., chromium) coated on the opaque regions of the binary mask. In another example, mask 1445 is formed using a phase-shifting technique. In a phase-shifting mask (PSM) version of mask 1445, various features in the pattern formed on the phase-shifting mask are configured to have appropriate phase differences to enhance resolution and imaging quality. In various examples, the phase-shifting mask can be a decaying PSM or an alternating PSM. The mask(s) generated by mask fabrication 1444 are used in various processes. For example, such a mask(s) are used in ion implantation processes to form various doped regions in semiconductor wafer 1453, in etching processes to form various etched regions in semiconductor wafer 1453, and / or in other suitable processes.

[0113] IC fab 1450 is an IC manufacturing enterprise that includes one or more manufacturing facilities for manufacturing various different IC products. In some embodiments, IC fab 1450 is a semiconductor foundry. For example, there may be a manufacturing facility (front-end process (FEOL) manufacturing) for the front-end manufacturing of multiple IC products, while a second manufacturing facility may provide back-end manufacturing (back-end process (BEOL) manufacturing) for the interconnection and packaging of IC products, and a third manufacturing facility may provide other services to the foundry enterprise.

[0114] IC fab 1450 includes manufacturing tool 1452, which is configured to perform various manufacturing operations on semiconductor wafer 1453 to manufacture IC device 1460 according to one or more masks (e.g., mask 1445). In various embodiments, manufacturing tool 1452 includes one or more of the following: wafer stepper, ion implanter, photoresist coater, processing chamber (e.g., CVD chamber or LPCVD furnace), CMP system, plasma etching system, wafer cleaning system, or other manufacturing equipment as discussed herein capable of performing one or more suitable manufacturing processes.

[0115] IC fab 1450 uses one or more masks 1445 manufactured by mask chamber 1430 to fabricate IC device 1460. Therefore, IC fab 1450 uses IC design layout 1422 at least indirectly to fabricate IC device 1460. In some embodiments, semiconductor wafer 1453 is fabricated by IC fab 1450 using one or more masks 1445 to form IC device 1460. In some embodiments, IC fabrication includes performing one or more photolithographic exposures based at least indirectly on IC design layout 1422. Semiconductor wafer 1453 includes a silicon substrate or other suitable substrate having a material layer formed thereon. Semiconductor wafer 1453 also includes one or more of various doped regions, dielectric features, multilevel interconnects, etc. (formed in subsequent fabrication steps).

[0116] Regarding integrated circuit (IC) manufacturing systems (e.g., Figure 14 Details of the system 1400 and the associated IC manufacturing process can be found in, for example, the following patent documents: U.S. Patent No. 9,256,709, granted February 9, 2016; U.S. Pre-Publication No. 20150278429, published October 1, 2015; U.S. Pre-Publication No. 20140040838, published February 6, 2014; and U.S. Patent No. 7,260,442, granted August 21, 2007, the entire contents of which are incorporated herein by reference.

[0117] One aspect of this disclosure relates to an integrated circuit. The integrated circuit includes a first time delay circuit, a second time delay circuit, and a master-slave flip-flop. The first time delay circuit has a first input and a first output, the first input being configured to receive a first clock signal, and the first output being configured to generate a second clock signal based on the first clock signal. The second time delay circuit has a second input and a second output, the second input being configured to receive the second clock signal, and the second output being configured to generate a third clock signal based on the second clock signal. The master-slave flip-flop includes a gated input circuit, a master latch, a slave latch, and a transmission gate coupled between the master latch and the slave latch. The master latch is coupled between the gated input circuit and the transmission gate. The transmission gate is configured to receive a first clock signal and a second clock signal for controlling the transmission state of the transmission gate, and the gated input circuit is configured to have an input transmission state controlled by the third clock signal at the second output of the second time delay circuit.

[0118] Another aspect of this disclosure relates to a method of operating a master-slave flip-flop having a master latch coupled between a gated input circuit and a transmission gate. The method includes generating a second clock signal delayed relative to a first clock signal, and generating a third clock signal delayed relative to the second clock signal. The method further includes sending the first and second clock signals to the transmission gate to change the transmission state of the transmission gate, and using the third clock signal to control the input transmission state of the gated input circuit.

[0119] Another aspect of this disclosure relates to an integrated circuit. The integrated circuit includes a first time delay circuit and a second time delay circuit. The first time delay circuit has a first input terminal and a first output terminal, the first input terminal being configured to receive a first clock signal, and the first output terminal being configured to generate a second clock signal based on the first clock signal. The first time delay circuit also includes a first gate conductor intersecting a first type of active region structure and a second type of active region structure in a first region. The second time delay circuit has a second input terminal and a second output terminal, the second input terminal being configured to receive the first clock signal, and the second output terminal being configured to generate a third clock signal based on the first clock signal. The second time delay circuit also includes a second gate conductor intersecting a first type of active region structure and a second type of active region structure in a second region. The first time delay circuit includes a first gate via connection portion that directly contacts the first gate conductor, the first gate conductor being located on top of the first type of active region structure in the first region. The second time delay circuit includes a second gate via connection portion that directly contacts the second gate conductor, the second gate conductor being located on top of the second type of active region structure in the second region.

[0120] Those skilled in the art will readily recognize that one or more of the disclosed embodiments achieve one or more of the advantages described above. After reading the foregoing specification, those skilled in the art will be able to implement various variations, equivalents, and other embodiments as broadly disclosed herein. Therefore, the protection granted herein is limited only by the definitions contained in the appended claims and their equivalents.

[0121] Example 1. An integrated circuit comprising: a first time delay circuit having a first input and a first output, the first input being configured to receive a first clock signal, and the first output being configured to generate a second clock signal based on the first clock signal; a second time delay circuit having a second input and a second output, the second input being configured to receive the second clock signal, and the second output being configured to generate a third clock signal based on the second clock signal; a master-slave flip-flop having a gated input circuit, a master latch, a slave latch, and a transmission gate coupled between the master latch and the slave latch, wherein the master latch is coupled between the gated input circuit and the transmission gate; and wherein the transmission gate is configured to receive the first clock signal and the second clock signal to control the transmission state of the transmission gate, and the gated input circuit is configured to have an input transmission state controlled by the third clock signal at the second output of the second time delay circuit.

[0122] Example 2. The integrated circuit according to Example 1, wherein the second time delay circuit is a NOR gate.

[0123] Example 3. The integrated circuit according to Example 1, wherein the first time delay circuit further includes a first gate conductor and a first gate via connection portion directly contacting the first gate conductor, wherein the first gate conductor intersects with a first type of active region structure and a second type of active region structure in the first region, and wherein at least a portion of the first gate via connection portion is located on top of the first type of active region structure.

[0124] Example 4. The integrated circuit according to Example 1, wherein the second time delay circuit further includes a second gate conductor and a second gate via connection portion in direct contact with the second gate conductor, wherein the second gate conductor intersects with a first type active region structure and a second type active region structure in the second region, and wherein at least a portion of the second gate via connection portion is located on top of the second type active region structure.

[0125] Example 5. The integrated circuit according to Example 1, wherein the first drive strength of the first time delay circuit is greater than the second drive strength of the second time delay circuit.

[0126] Example 6. The integrated circuit according to Example 5, wherein the first time delay circuit further includes two gate conductors, each of the two gate conductors intersecting with a first type of active region structure and a second type of active region structure, and each of the two gate conductors is configured to receive the first clock signal.

[0127] Example 7. A method of operating a master-slave flip-flop having a master latch coupled between a gated input circuit and a transmission gate, the method comprising: generating a second clock signal delayed relative to a first clock signal; generating a third clock signal delayed relative to the second clock signal; sending the first clock signal and the second clock signal to the transmission gate to change the transmission state of the transmission gate; and using the third clock signal to control the input transmission state of the gated input circuit.

[0128] Example 8. According to the method of Example 7, wherein controlling the input transmission state of the gated input circuit includes: inverting the third clock signal to generate a fourth clock signal that is delayed relative to the third clock signal; and sending the third clock signal and the fourth clock signal to the gated input circuit to change the input transmission state of the gated input circuit.

[0129] Example 9. The method according to Example 7 further includes: sending the second clock signal and the scan enable signal to a NOR gate to generate the third clock signal; and sending the first clock signal, the second clock signal and the scan enable signal to a scan input circuit in the gated input circuit.

[0130] Example 10. An integrated circuit includes: a first time delay circuit having a first input terminal and a first output terminal, the first input terminal being configured to receive a first clock signal, and the first output terminal being configured to generate a second clock signal based on the first clock signal; wherein the first time delay circuit further includes a first gate conductor intersecting with a first type active region structure and a second type active region structure in a first region; and a second time delay circuit having a second input terminal and a second output terminal, the second input terminal being configured to receive the first clock signal, and the second output terminal being configured to generate a third clock signal based on the first clock signal; wherein the second time delay circuit further includes a second gate conductor intersecting with a first type active region structure and a second type active region structure in a second region; wherein the first time delay circuit includes a first gate via connection portion directly contacting the first gate conductor, the first gate conductor being located at the top of the first type active region structure in the first region; and wherein the second time delay circuit includes a second gate via connection portion directly contacting the second gate conductor, the second gate conductor being located at the top of the second type active region structure in the second region.

[0131] Example 11. The integrated circuit according to Example 10, wherein the second type of active region structure in the first region and the second type of active region structure in the second region are separated by the first type of active region structure in the first region and the first type of active region structure in the second region.

[0132] Example 12. An integrated circuit according to Example 10, wherein a portion of the first gate conductor in the first time delay circuit is located on top of a first type of active region structure in the first region.

[0133] Example 13. An integrated circuit according to Example 10, wherein the entire first gate conductor in the first time delay circuit is located on top of a first type of active region structure in the first region.

[0134] Example 14. The integrated circuit according to Example 10, wherein a portion of the second gate conductor in the second time delay circuit is located on top of a second type of active region structure in the second region.

[0135] Example 15. The integrated circuit according to Example 10, wherein the entirety of the second gate conductor in the second time delay circuit is located on top of the second type of active region structure in the second region.

[0136] Example 16. The integrated circuit according to Example 10 further includes: a master-slave flip-flop, the master-slave flip-flop including a master latch, a slave latch, and a transmission gate coupled between the master latch and the slave latch; and wherein the transmission gate is configured to receive the first clock signal and the second clock signal to control the transmission state of the transmission gate.

[0137] Example 17. The integrated circuit according to Example 16, wherein the master-slave flip-flop includes a gated input circuit having an input transmission state controlled by the third clock signal at the second output of the second time delay circuit.

[0138] Example 18. The integrated circuit according to Example 16 further includes: a third time delay circuit having a third input and a third output, the third input being configured to receive the third clock signal and the third output being configured to generate a fourth clock signal based on the third clock signal; and a gated input circuit located in the master-slave flip-flop and configured to receive the third clock signal and the fourth clock signal for controlling the input transmission state of the gated input circuit.

[0139] Example 19. The integrated circuit according to Example 10, wherein the first drive strength of the first time delay circuit is greater than the second drive strength of the second delay circuit.

[0140] Example 20. An integrated circuit according to Example 10, wherein the first time delay circuit further includes a third gate conductor intersecting a first type of active region structure and a second type of active region structure in the first region, and wherein each of the first gate conductor and the third gate conductor is configured to receive the first clock signal.

Claims

1. An integrated circuit, comprising: A first time delay circuit has a first input terminal and a first output terminal. The first input terminal is configured to receive a first clock signal, and the first output terminal is configured to generate a second clock signal based on the first clock signal. The second time delay circuit has a second input terminal and a second output terminal. The second input terminal is configured to receive the second clock signal, and the second output terminal is configured to generate a third clock signal based on the second clock signal. A master-slave flip-flop, the master-slave flip-flop having a gated input circuit, a master latch, a slave latch, and a transmission gate coupled between the master latch and the slave latch, wherein the master latch is coupled between the gated input circuit and the transmission gate; The transmission gate is configured to receive the first clock signal and the second clock signal to control its transmission state, and the gated input circuit is configured to have an input transmission state controlled by the third clock signal at the second output of the second time delay circuit. The first time delay circuit further includes a first gate conductor and a first gate via connection portion that is in direct contact with the first gate conductor, wherein the first gate conductor intersects with a first type of active region structure and a second type of active region structure in the first region, and wherein at least a portion of the first gate via connection portion is located on top of the first type of active region structure.

2. The integrated circuit of claim 1, wherein, The second time delay circuit is a NOR gate.

3. The integrated circuit of claim 1, wherein, The second time delay circuit further includes a second gate conductor and a second gate via connection portion that is in direct contact with the second gate conductor, wherein the second gate conductor intersects with a first type active region structure and a second type active region structure in the second region, and wherein at least a portion of the second gate via connection portion is located on top of the second type active region structure.

4. The integrated circuit of claim 1, wherein, The first driving strength of the first time delay circuit is greater than the second driving strength of the second time delay circuit.

5. The integrated circuit of claim 4, wherein, The first time delay circuit further includes two gate conductors, each of which intersects with a first type of active region structure and a second type of active region structure, and each of the two gate conductors is configured to receive the first clock signal.

6. A method of operating a master-slave flip-flop, the master-slave flip-flop having a master latch coupled between a gated input circuit and a transmission gate, the method comprising: A second clock signal that is delayed relative to the first clock signal is generated by the first time delay circuit. A third clock signal that is delayed relative to the second clock signal is generated by the second time delay circuit; The first clock signal and the second clock signal are sent to the transmission gate to change the transmission state of the transmission gate; as well as The third clock signal is used to control the input transmission state of the gated input circuit. The first time delay circuit includes a first gate conductor and a first gate via connection portion that is in direct contact with the first gate conductor. The first gate conductor intersects with a first type of active region structure and a second type of active region structure in the first region. At least a portion of the first gate via connection portion is located on top of the first type of active region structure.

7. The method of claim 6, wherein, Controlling the input transmission state of the gated input circuit includes: Invert the third clock signal to generate a fourth clock signal that is delayed relative to the third clock signal; and The third clock signal and the fourth clock signal are sent to the gated input circuit to change the input transmission state of the gated input circuit.

8. The method according to claim 6, further comprising: The second clock signal and the scan enable signal are sent to the NOR gate to generate the third clock signal; as well as The first clock signal, the second clock signal, and the scan enable signal are sent to the scan input circuit in the gated input circuit.

9. An integrated circuit, comprising: A first time delay circuit has a first input terminal and a first output terminal. The first input terminal is configured to receive a first clock signal, and the first output terminal is configured to generate a second clock signal based on the first clock signal. The first time delay circuit further includes a first gate conductor, which intersects with a first type of active region structure and a second type of active region structure in a first region. The second time delay circuit has a second input terminal and a second output terminal. The second input terminal is configured to receive the first clock signal, and the second output terminal is configured to generate a third clock signal based on the first clock signal. The second time delay circuit further includes a second gate conductor, which intersects with a first type of active region structure and a second type of active region structure in the second region. The first time delay circuit includes a first gate via connection portion, which is in direct contact with a first gate conductor. The first gate conductor is located at the top of a first type of active region structure in the first region. The second time delay circuit includes a second gate via connection portion, which is in direct contact with a second gate conductor, and the second gate conductor is located on top of a second type of active region structure in the second region.

10. The integrated circuit of claim 9, wherein, The second type of active region structure in the first region and the second type of active region structure in the second region are separated by the first type of active region structure in the first region and the first type of active region structure in the second region.

11. The integrated circuit of claim 9, wherein, A portion of the first gate conductor in the first time delay circuit is located on top of the first type of active region structure in the first region.

12. The integrated circuit of claim 9, wherein, The entire first gate conductor in the first time delay circuit is located on top of the first type of active region structure in the first region.

13. The integrated circuit of claim 9, wherein, A portion of the second gate conductor in the second time delay circuit is located on top of the second type of active region structure in the second region.

14. The integrated circuit of claim 9, wherein, The entire second gate conductor in the second time delay circuit is located on top of the second type of active region structure in the second region.

15. The integrated circuit according to claim 9, further comprising: A master-slave trigger, the master-slave trigger including a master latch, a slave latch, and a transmission gate coupled between the master latch and the slave latch; and The transmission gate is configured to receive the first clock signal and the second clock signal to control the transmission state of the transmission gate.

16. The integrated circuit of claim 15, wherein, The master-slave trigger includes a gated input circuit, which has an input transmission state controlled by the third clock signal at the second output of the second time delay circuit.

17. The integrated circuit according to claim 15, further comprising: A third time delay circuit has a third input terminal and a third output terminal. The third input terminal is configured to receive the third clock signal, and the third output terminal is configured to generate a fourth clock signal based on the third clock signal. as well as A gated input circuit, located within the master-slave flip-flop, is configured to receive the third clock signal and the fourth clock signal for controlling the input transmission state of the gated input circuit.

18. The integrated circuit of claim 9, wherein, The first driving strength of the first time delay circuit is greater than the second driving strength of the second time delay circuit.

19. The integrated circuit of claim 9, wherein, The first time delay circuit further includes a third gate conductor that intersects with a first type of active region structure and a second type of active region structure in the first region, and wherein each of the first gate conductor and the third gate conductor is configured to receive the first clock signal.

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