Digital duty cycle correction circuit

Abstract

A digital duty cycle correction circuit is provided. The digital duty cycle correction circuit includes a control circuit having a first transistor and a second transistor connected at a first node and configured to adjust a duty cycle of an input clock received at the first node and provide a duty cycle adjusted output clock at a second node. A single-ended to differential circuit is connected to the control circuit at the second node. The single-ended to differential circuit generates a first output clock and a second output clock from the duty cycle adjusted output clock. A feedback circuit is configured to provide the duty cycle adjusted output clock to respective gates of the first transistor and the second transistor.

Description

Technical Field

[0001] This disclosure relates to a correction circuit, and more particularly to a digital duty cycle correction circuit. Background Technology

[0002] The number of high-speed circuits and systems continues to increase. Generally, the duty cycle of a clock signal in a high-speed circuit should be 50%. However, due to variations in process technology, voltage, and temperature (PVT), the duty cycle of a clock signal is often higher or lower than 50%. In some cases, even if the clock source's duty cycle is 50%, the actual duty cycle can deviate significantly from 50%. Furthermore, determining and applying corrections for duty cycle errors can be challenging. Utility Model Content

[0003] In one embodiment of this disclosure, the digital duty cycle correction circuit includes a control circuit and a single-ended to differential circuit. The control circuit includes a first transistor and a second transistor. The source / drain of the first transistor is connected to a first trimming circuit. The first trimming circuit provides a first voltage at the source / drain of the first transistor. The drain / source of the first transistor is connected to the drain / source of the second transistor at a first node. The source / drain of the second transistor is connected to a second trimming circuit. The second trimming circuit provides a second voltage at the source / drain of the second transistor. The control circuit adjusts the duty cycle of an input clock received at the first node and provides a duty cycle adjustment output clock at a second node. The control circuit also includes a feedback circuit. The feedback circuit connects the second node to the respective gates of the first transistor and the second transistor. A single-ended to differential circuit is connected to the control circuit. The single-ended to differential circuit generates a first output clock and a second output clock from the duty cycle adjustment output clock.

[0004] In one embodiment of this disclosure, the digital duty cycle correction circuit includes a control circuit, a single-ended to differential circuit, and a feedback circuit. The control circuit includes a first transistor and a second transistor connected at a first node. The control circuit adjusts the duty cycle of an input clock received at the first node and provides a duty cycle adjustment output clock at a second node. The single-ended to differential circuit is connected to the control circuit at the second node. The single-ended to differential circuit generates a first output clock and a second output clock from the duty cycle adjustment output clock. The feedback circuit provides the duty cycle adjustment output clock to the respective gates of the first transistor and the second transistor. Attached Figure Description

[0005] The various aspects of this disclosure are best understood from the following detailed description, which includes the accompanying drawings. It should be noted that, in accordance with industry standard practice, the features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion. Furthermore, the illustrations are provided as examples of embodiments of the invention and are not intended to be limiting.

[0006] Figure 1 This is a block diagram of a first example of a digital duty cycle correction (DCC) circuit according to some embodiments.

[0007] Figure 2 According to some embodiments Figure 1 Example circuit diagram of a digital DCC circuit.

[0008] Figure 3 It is used according to some embodiments Figure 1 An example illustration of duty cycle correction using a DCC circuit.

[0009] Figure 4 It is used according to some embodiments Figure 1 Example signal diagram of DCC circuit performing duty cycle correction.

[0010] Figure 5 According to some embodiments Figure 1 Another example circuit diagram of a digital DCC circuit.

[0011] Figure 6 According to some embodiments Figure 1 Another example circuit diagram of a digital DCC circuit.

[0012] Figure 7 This is a flowchart of a method for adjusting the input clock duty cycle according to some embodiments. Detailed Implementation

[0013] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and configurations are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature over or on a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where an additional feature may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be reused in various examples throughout this disclosure. This reuse is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0014] Additionally, for ease of explanation, spatially relative terms such as "beneath," "below," "lower," "above," and "upper" may be used herein to describe the relationship between a component or feature shown in the figures and another component or feature. These spatially relative terms are intended to cover different orientations of the device in use or operation, in addition to those shown in the figures. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used herein will be interpreted accordingly.

[0015] Traditional analog duty cycle correction circuits use analog integrators to detect duty cycle errors. However, analog integrators are only suitable for low-speed applications. Compared to analog duty cycle correctors, digital duty cycle correctors do not use voltage control methods and are therefore less affected by transistor leakage current. Furthermore, digital duty cycle correctors operate over a lower voltage range. However, digital duty cycle correctors suffer from poorer duty cycle linearity.

[0016] The embodiments disclosed herein provide a digital duty cycle correction (DCC) circuit that generates 50% (50%) of the duty cycle for a clock signal. Embodiments of the digital DCC circuit can be used in low-speed and high-speed circuits and systems, including, for example, processing devices, memory input / output interfaces, and high-frequency data converters. Example processing devices include, but are not limited to, central processing units, microprocessors, and digital signal processors. In non-limiting and non-exclusive examples, the digital DCC circuit may be implemented in, but is not limited to, de-offset circuitry, memory input / output interfaces, and / or data converter circuitry.

[0017] The disclosed digital DCC circuit can operate over a wide frequency range of the input signal and / or accommodate a wide range of duty cycle errors. Furthermore, or alternatively, embodiments of the DCC circuit are less complex and use less area on the chip than conventional DCC circuits. For example, example embodiments of the DCC circuit are constructed using fewer transistors than conventional DCC circuits. In some cases, the DCC circuit consumes less power than conventional duty cycle correction circuits.

[0018] Figure 1 This is a block diagram of a digital DCC circuit 100 according to some embodiments. For example... Figure 1As shown, the digital DCC circuit 100 includes a control circuit 102. The control circuit 102 includes a first trimming circuit 104 and a second trimming circuit 106. The digital DCC circuit 100 also includes a single-to-differential circuit 108 connected to the control circuit 102. The control circuit 102 receives an input clock and, in conjunction with the first trimming circuit 104 and the second trimming circuit 106, adjusts the duty cycle of the input clock to be substantially equal to 50%. A duty-adjusted output clock is provided to and received by the single-to-differential circuit 108. The single-to-differential circuit 108 generates a first output clock and a second output clock from the duty-adjusted output clock. The first output clock and the second output clock have a 180-degree phase difference.

[0019] Figure 2 According to some embodiments Figure 1 Example circuit diagram of digital DCC circuit 100. Figure 2 As shown, the digital DCC circuit 100 includes a control circuit 102 and a single-ended to differential circuit 108 connected to the control circuit 102. The control circuit 102 includes a first trimming circuit 104 and a second trimming circuit 106. Furthermore, the control circuit 102 includes a first transistor 122 and a second transistor 124. The source / drain of the first transistor 122 is connected to the first trimming circuit 104 at node 126. The first trimming circuit 104 provides a first voltage to the source / drain of the first transistor 122. The first voltage is variable and varies with the trimming code. The source / drain of the second transistor 124 is connected to the second trimming circuit 106 at node 128. The second trimming circuit 106 provides a second voltage to the source / drain of the second transistor 124. The second voltage is also variable and varies with the trimming code. As discussed in the following sections of this disclosure, the trimming code is determined based on the duty cycle of the input clock. The drain / source of the first transistor 122 is connected to the drain / source of the second transistor 124 at node 130. The term "drain / source" as used here may refer to either the drain or the source, individually or collectively, depending on the context. Node 130 is also referred to as the input node or the first node.

[0020] The input clock (displayed as CK0_input) is received at the first terminal of inverter 132. Inverter 132 inverts the input clock and provides an inverted input clock at its second terminal. The second terminal of inverter 132 is connected to node 130. The first terminal of inverter 134 is connected to node 130. The second terminal of inverter 134 is connected to node 136. Feedback circuit 140 connects node 136 to the respective gates of the first transistor 122 and the second transistor 124. Node 136 is also referred to as the output node or second node of control circuit 102. As discussed in more detail in the following sections of this disclosure, control circuit 102 adjusts the duty cycle of the input clock and provides a duty-adjusted output clock at node 136. Therefore, in some examples, control circuit 102 is also referred to as a duty cycle adjuster (DCA) circuit.

[0021] The first trimming circuit 104 includes a plurality of transistors connected in parallel between the supply voltage node and node 126. In some examples, each of the plurality of transistors is a p-channel metal-oxide-semiconductor (PMOS) transistor. However, other types of transistors may be used to form the first trimming circuit 104. Furthermore, while the first trimming circuit 104 is shown to include 64 first transistors, it may include a different number of first transistors.

[0022] The second trimming circuit 106 includes a second plurality of transistors connected in parallel between node 128 and ground. In some examples, each of the second plurality of transistors is an n-channel metal-oxide-semiconductor (NMOS) transistor. However, other types of transistors may be used to form the second trimming circuit 106. While the second trimming circuit 106 is shown to include 64 second transistors, it may include a different number of second transistors.

[0023] In operation, the first transistor 122 and the second transistor 124 cooperate with the first trimming circuit 104, the second trimming circuit 106 and the feedback circuit 140 to adjust the working period of the input clock to be equal to 50%. Figure 3 Is using Figure 1 Example icon for duty cycle correction of digital DCC circuit 100. Figure 4 Is using Figure 1 Example signal diagram of a digital DCC circuit 100 performing duty cycle correction.

[0024] like Figure 3 As shown, an example input clock with a duty cycle of 45% is received at inverter 132. That is, as Figure 4 As shown in Figure 210, Figure 3 The example input clock is high for 45% of the clock cycle. Inverter 132 includes a PMOS and an NMOS transistor connected together, inverting the input clock and providing an inverted output clock at node 130. Figure 4 As shown in Figure 220, the inverting input clock is high for 55% of the clock cycle. However, current I flows from the first trimming circuit 104 through node 130 to the second trimming circuit 106 and the ground node. Current I alters or drags the duty cycle of the inverting input clock toward 50% (as shown in Figure 220).

[0025] Inverter 134 includes a PMOS and an NMOS transistor connected together, inverting the inverted clock from node 130 and providing a duty cycle adjustment clock at node 136. As shown in diagram 230, the duty cycle adjustment output clock at node 136 is high for 45% of the clock cycle but is changing towards 50%. This duty cycle adjustment output clock at node 136 is provided as feedback to the gates of the first transistor 122 and the second transistor 124. For example, as... Figure 3 As shown, node 136 is connected to the gate of the first transistor 122 and the second transistor 124.

[0026] Providing the duty cycle adjustment output clock to the gates of the first transistor 122 and the second transistor 124 accelerates the duty cycle adjustment toward 50%. For example, the gate voltages of the first transistor 122 and the second transistor 124 vary with the trimming code. Furthermore, according to the current duty cycle of the duty cycle adjustment output clock, one or both of the first transistor 122 and the second transistor 124 are turned on, thereby increasing the current I flowing toward node 130, further accelerating the duty cycle adjustment toward 50%.

[0027] Furthermore, the current I is determined based on the respective configurations of the first trimming circuit 104 and the second trimming circuit 106. A predetermined number of first transistors in the first trimming circuit 104 are turned on based on a trimming code. The trimming code is generated based on the current duty cycle of the input clock. For example, if the duty cycle is less than 50%, a trimming code is generated to increase the duty cycle. To increase the duty cycle, more first transistors in the first trimming circuit 104 are turned on by the generated trimming code. Conversely, if the duty cycle is greater than 50%, a trimming code is generated to decrease the duty cycle. To decrease the duty cycle, more second transistors in the second trimming circuit 106 are turned on by the generated trimming code.

[0028] According to an example embodiment, the first transistor of the first trimming circuit 104 may have different widths and lengths to improve the linearity of the duty cycle correction. For example, the width of one or more first transistors may be increased to increase the current I, while the length may be increased to decrease the current I. Similarly, the second transistor of the second trimming circuit 106 may have different widths and lengths to improve the linearity of the duty cycle correction. Changing the length and width of the first transistor of the first trimming circuit 104 and the second transistor of the second trimming circuit 106 can improve the linearity of the duty cycle correction.

[0029] Back Figure 2 The single-ended to differential circuit 108 includes inverters 142, 146, 150, and 154, transmission gate 162, inverter 166, and inverter 170. Inverters 146, 150, and 154 form a first branch of the single-ended to differential circuit 108. Transmission gate 162, inverter 166, and inverter 170 form a second branch of the single-ended to differential circuit 108. The first branch provides a first output clock (displayed as CK_0), and the second branch provides a second output clock (displayed as CK_180). The second output clock lags the first output clock by 180 degrees.

[0030] like Figure 2 As shown, the first terminal of inverter 142 is connected to node 136, and the second terminal of inverter 142 is connected to the first terminal of inverter 146 at node 144. The second terminal of inverter 146 is connected to the first terminal of inverter 150 at node 148. The second terminal of inverter 150 is connected to the first terminal of inverter 154 at node 152. The second terminal of inverter 154 provides the first output clock at node 156.

[0031] In the second branch, the first terminal of transmission gate 162 is connected to node 144. The second terminal of transmission gate 162 is connected at node 164 to the first terminal of inverter 166. The second terminal of inverter 166 is connected at node 168 to the first terminal of inverter 170. The second terminal of inverter 170 provides a second output clock at node 172.

[0032] Inverters 142, 146, 150, and 154 propagate the duty-adjusted output clock from node 136 to node 156 via nodes 144, 148, and 152 to generate a first output clock. Transmission gate 162 and inverters 142, 166, and 170 propagate the duty-adjusted output clock from node 136 to node 172 via nodes 144, 164, and 168 to generate a second output clock. Nodes 148 and 168 are in phase with or have the same phase as node 136. Those skilled in the art will understand that different configurations of single-ended to differential circuits can be used to generate the first and second output clocks. Furthermore, more than two output clocks with different phase differences can be generated from the duty-adjusted output clock.

[0033] According to an example embodiment, the feedback circuit 140 may be connected between any node in phase with node 136 and the gates of the first transistor 122 and the second transistor 124. Figure 5 This is another circuit diagram of the digital DCC circuit 100, in which the feedback circuit 140 is connected to node 148 of the single-ended to differential circuit 108. As described above, node 148 is in phase with node 136. Figure 5 The digital DCC circuit 100 may be more than Figure 2 The digital DCC circuit 100 has better linearity because the feedback circuit 140 is connected closer to the first output clock position, compared to... Figure 2 The connection position in the text.

[0034] Figure 6 This is another circuit diagram of the digital DCC circuit 100, in which the feedback circuit 140 is connected to node 168 of the single-ended to differential circuit 108. As mentioned above, node 168 is in phase with node 136. Figure 6 The digital DCC circuit 100 may be more than Figure 2 The digital DCC circuit 100 has better linearity because the feedback circuit 140 is connected closer to the second output clock position compared to... Figure 2 The connection position in the text.

[0035] Figure 7 This is a flowchart of a method 400 for adjusting the duty cycle of an input clock according to some embodiments. In block 410 of method 400, the input clock is received at a first node (i.e., node 130) of control circuit 102. As described above, control circuit 102 includes a first transistor 122 and a second transistor 124 connected at the first node (i.e., node 130).

[0036] In block 420 of method 400, the duty cycle of the input clock is adjusted based on a first trimming code and a second trimming code. For example, based on the first trimming code, a predetermined number of first transistors in the first trimming circuit 104 are turned on. Furthermore, based on the second trimming code, a predetermined number of second transistors in the second trimming circuit 106 are turned on. This results in a current I being injected into node 130, thereby altering the duty cycle of the input clock.

[0037] In block 430 of method 400, the duty cycle adjustment output clock is provided at the second node (i.e., node 136) of control circuit 102. In block 440, the duty cycle adjustment output clock is provided as feedback to the respective gates of the first transistor 122 and the second transistor 124 of control circuit 102. This feedback is provided through feedback circuit 140 and accelerates the duty cycle adjustment of the input clock to 50%.

[0038] According to an example embodiment, a digital DCC circuit includes: a control circuit including a first transistor and a second transistor, wherein: the source / drain of the first transistor is connected to a first trimming circuit, wherein the first trimming circuit provides a first voltage at the source / drain of the first transistor; the drain / source of the first transistor is connected to the drain / source of a second transistor at a first node; the source / drain of the second transistor is connected to a second trimming circuit, wherein the second trimming circuit provides a second voltage at the source / drain of the second transistor; the control circuit is configured to adjust the duty cycle of an input clock received at the first node and provide a duty cycle adjusted output clock at the second node; the control circuit also includes a feedback circuit that connects the second node to the respective gates of the first transistor and the second transistor; and a single-ended to differential circuit connected to the control circuit, wherein the single-ended to differential circuit is configured to generate a first output clock and a second output clock from the duty cycle adjusted output clock.

[0039] In one embodiment, the first trimming circuit includes a first plurality of transistors. Each of the first plurality of transistors is connected in parallel with each other between the supply voltage node and the source / drain of the first transistor.

[0040] In one embodiment, the second trimming circuit includes a second plurality of transistors. Each of the second plurality of transistors is connected in parallel with each other between the source / drain of the second transistor and the ground voltage node.

[0041] In one embodiment, the feedback circuit includes a second node.

[0042] In one embodiment, the feedback circuit includes a single-ended circuit to another node in the differential circuit that is in phase with the second node.

[0043] In one embodiment, the inverted clock signal is received at the first node.

[0044] In one embodiment, the single-ended to differential circuit includes another node on a first branch of the single-ended to differential circuit that is in phase with the second node.

[0045] In one embodiment, the single-ended to differential circuit includes another node on the second branch of the single-ended to differential circuit that is in phase with the second node.

[0046] In one embodiment, the control circuit further includes an inverter connected between the first node and the second node.

[0047] In the disclosed example embodiment, the digital DCC circuit includes: a control circuit including a first transistor and a second transistor connected at a first node and configured to adjust the duty cycle of an input clock received at the first node and provide a duty-ratio-adjusted output clock at a second node; a single-ended to differential circuit connected at the second node to the control circuit, wherein the single-ended to differential circuit is configured to generate a first output clock and a second output clock from the duty-ratio-adjusted output clock; and a feedback circuit configured to provide the duty-ratio-adjusted output clock to the respective gates of the first transistor and the second transistor.

[0048] In one embodiment, the control circuit further includes a first trimming circuit and a second trimming circuit. The first trimming circuit is connected to the source / drain of the first transistor. The first trimming circuit provides a first voltage to the source / drain of the first transistor. The second trimming circuit is connected to the source / drain of the second transistor. The second trimming circuit provides a second voltage to the source / drain of the second transistor. The drain / source of the first transistor is connected to the drain / source of the second transistor at a first node.

[0049] In one embodiment, the feedback circuit connects the second node to the respective gates of the first transistor and the second transistor.

[0050] In one embodiment, the feedback circuit connects another node in the single-ended to differential circuit that is in phase with the second node to the respective gates of the first and second transistors.

[0051] In one embodiment, the feedback circuit connects another node on the first branch of the single-ended to differential circuit that is in phase with the second node to the respective gates of the first transistor and the second transistor.

[0052] In one embodiment, the feedback circuit connects another node on the second branch of the single-ended to differential circuit that is in phase with the second node to the respective gates of the first and second transistors.

[0053] In one embodiment, the control circuit further includes an inverter connected between the first node and the second node.

[0054] According to an example embodiment, a method for adjusting the duty cycle of an input clock includes: receiving an input clock at a first node of a control circuit including a first transistor and a second transistor connected at a first node; adjusting the duty cycle of the input clock based on a first trimming code and a second trimming code; providing a duty cycle adjustment output clock at a second node of the control circuit; and providing the duty cycle adjustment output clock as feedback to the respective gates of the first transistor and the second transistor of the control circuit.

[0055] In one embodiment, the method further includes generating a first output clock and a second output clock from an operating ratio adjusted output clock by a single-ended to differential circuit connected to a second node of the control circuit.

[0056] In one embodiment, providing the duty cycle adjusted output clock as feedback to the respective gates of the first and second transistors of the control circuit includes: providing the duty cycle adjusted output clock as feedback to the respective gates of the first and second transistors of the control circuit from a single-ended to another node in the differential circuit.

[0057] In one embodiment, providing the duty cycle adjustment output clock as feedback to the respective gates of the first transistor and the second transistor of the control circuit includes: providing the duty cycle adjustment output clock of the second node as feedback to the respective gates of the first transistor and the second transistor of the control circuit.

[0058] This disclosure outlines several embodiments to enable those skilled in the art to better understand the nature of this disclosure. Those skilled in the art will understand that this disclosure can be readily used as the basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages of the embodiments introduced herein. Those skilled in the art will also recognize that such equivalent constructions should not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made to this document without departing from the spirit and scope of this disclosure.

Claims

1. A digital duty cycle correction circuit, characterized in that, The digital duty cycle correction circuit includes: The control circuit includes a first transistor and a second transistor, wherein: The source / drain of the first transistor is connected to a first trimming circuit, wherein the first trimming circuit provides a first voltage at the source / drain of the first transistor. The drain / source of the first transistor is connected to the drain / source of the second transistor at the first node. The source / drain of the second transistor is connected to a second trimming circuit, wherein the second trimming circuit provides a second voltage at the source / drain of the second transistor. The control circuit is configured to adjust the duty cycle of the input clock received at the first node and to provide a duty cycle-adjusted output clock at the second node. The control circuit further includes a feedback circuit that connects the second node to the respective gates of the first transistor and the second transistor; and A single-ended to differential circuit is connected to the control circuit, wherein the single-ended to differential circuit is configured to adjust the output clock from the duty cycle to generate a first output clock and a second output clock.

2. The digital duty cycle correction circuit according to claim 1, characterized in that, The first trimming circuit includes a first plurality of transistors, wherein each of the first plurality of transistors is connected in parallel with each other between the supply voltage node and the source / drain of the first transistor.

3. The digital duty cycle correction circuit according to claim 1, characterized in that, The second trimming circuit includes a second plurality of transistors, wherein each of the second plurality of transistors is connected in parallel with each other between the source / drain of the second transistor and the ground voltage node.

4. The digital duty cycle correction circuit according to claim 1, characterized in that, The control circuit also includes an inverter connected between the first node and the second node.

5. A digital duty cycle correction circuit, characterized in that, The digital duty cycle correction circuit includes: The control circuit includes a first transistor and a second transistor connected at a first node, and is configured to adjust the duty cycle of the input clock received at the first node and provide a duty cycle adjustment output clock at the second node. A single-ended to differential circuit, connected at the second node to the control circuit, wherein the single-ended to differential circuit is configured to adjust the output clock from the duty cycle to generate a first output clock and a second output clock; and A feedback circuit is configured to provide the duty cycle adjusted output clock to the respective gates of the first transistor and the second transistor.

6. The digital duty cycle correction circuit according to claim 5, characterized in that, The control circuit also includes: A first trimming circuit is connected to the source / drain of the first transistor, wherein the first trimming circuit provides a first voltage at the source / drain of the first transistor; and A second trimming circuit is connected to the source / drain of the second transistor, wherein the second trimming circuit provides a second voltage at the source / drain of the second transistor, and wherein the drain / source of the first transistor is connected to the drain / source of the second transistor at the first node.

7. The digital duty cycle correction circuit according to claim 5, characterized in that, The feedback circuit connects the second node to the respective gates of the first transistor and the second transistor.

8. The digital duty cycle correction circuit according to claim 5, characterized in that, The feedback circuit connects another node in the single-ended to differential circuit that is in phase with the second node to the respective gates of the first transistor and the second transistor.

9. The digital duty cycle correction circuit according to claim 5, characterized in that, The feedback circuit connects another node on the first branch of the single-ended to differential circuit that is in phase with the second node to the respective gates of the first transistor and the second transistor.

10. The digital duty cycle correction circuit according to claim 5, characterized in that, The feedback circuit connects another node on the second branch of the single-ended to differential circuit that is in phase with the second node to the respective gates of the first transistor and the second transistor.

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