Duty cycle correction method and circuit therefor

Abstract

The inventive concept relates to a duty cycle correction method and circuitry thereof. The duty cycle correction method includes the following operations: generating a plurality of intermediate delayed input signals via a delay line driven by an input signal, each intermediate delayed input signal being delayed by at least one unit delay; selecting from the plurality of delayed input signals via a first control signal, wherein the selection is based on the number of unit delays in the input signals; and generating a corrected duty cycle based on a selection of at least one of an increasing duty cycle signal and a decreasing duty cycle signal via a provided second control signal. The inventive concept provides low power consumption and low area for correcting or adjusting the duty cycle of an input signal with high probability or guaranteed monotonicity.

Description

[0001] This application claims priority to Indian Patent Application No. 202041046538, filed on October 26, 2020, with the Intellectual Property Office of India, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] The inventive concept relates to the field of semiconductor circuits, and more specifically, to a duty cycle correction method and circuit thereof. Background Technology

[0003] Duty cycle correction (DCC) is a concept commonly used to adjust the duty cycle of signals and is frequently employed in wired communications, such as serial and parallel links. DCC also finds applications in software-defined radio, cognitive radio, and the like. For many applications, such as systems-on-chips sensitive to the duty cycle of clock signals, a duty cycle correction or adjustment circuit is typically required to correct the signal's duty cycle before it is used in the application. A consistent duty cycle is desirable for signals because precise duty cycle control is beneficial for the proper operation of many digital electronic devices. Research reveals that as the frequency of an external clock signal increases, the duty cycle of the experienced clock signal changes, ultimately leading to duty cycle errors.

[0004] Typically, the ideal duty cycle for clock / data signals is 50%. However, as clock frequency increases, the period of the clock signal decreases. This variation in clock frequency can cause variations in the duty cycle. While lower clock / data frequencies may be negligible, higher frequencies can lead to more significant duty cycle shifts. In such cases, if the clock / data signal duty cycle is not corrected, timing errors can cause device malfunctions and / or ultimately lead to device failure.

[0005] The study also revealed that many duty cycle correction circuits are designed to correct the duty cycle when the clock signal and its inversion have similar duty cycle errors. However, these circuits often suffer from performance defects because they may only correct one duty cycle and not the other.

[0006] Another drawback associated with existing DCC circuits is related to limitations in adjustment resolution (e.g., non-uniform step size, width, etc.). Existing methods aimed at improving adjustment resolution to overcome such limitations typically result in increased power consumption, larger size, and / or a limited range. Due to size and power consumption limitations, the reduced speed of such DCC circuits leads to increased step size and / or increased power consumption, ultimately resulting in impractical applications.

[0007] Another drawback associated with existing DCC circuits is that such circuits cannot maintain the monotonicity of the signal obtained through the delay line. This drawback can arise from device mismatch in the delay elements, which in turn can lead to system-level failures. Summary of the Invention

[0008] This summary is provided to introduce, in a simplified form, the selection of concepts further described in specific embodiments of the inventive concept. This summary is not intended to identify key or essential inventive concepts of the claimed subject matter, nor is it intended to define the scope of the claimed subject matter.

[0009] The present invention eliminates the aforementioned drawbacks that plague the prior art. Furthermore, the present invention provides a method and system that can provide a wider range of duty cycle corrections with a high probability or guaranteed monotonicity.

[0010] The present invention is based on low-power, low-area duty cycle correction with high probability or guarantee of monotonicity.

[0011] In one aspect of this disclosure, a method for duty cycle correction of an input signal is provided, the method comprising: generating a plurality of intermediate delayed input signals via a delay line driven by the input signal, each intermediate delayed input signal being delayed by at least one unit delay. The method further comprises selecting from the plurality of delayed input signals via a first control signal, wherein the selection is based on the number of unit delays in the input signals. The method further comprises generating at least an increased duty cycle signal (path 1) and a decreased duty cycle signal (path 2) based on the selected delayed signal and the input signal. The method further comprises generating a corrected duty cycle based on the selection of at least one of an increased duty cycle or a decreased duty cycle by providing a second control signal.

[0012] In another aspect of this disclosure, a duty cycle correction (DCC) circuit is provided, the duty cycle correction (DCC) circuit comprising: a delay line including a plurality of delay components, the plurality of delay components being driven by an input signal and configured to generate a plurality of delayed input signals, each of the delayed input signals being delayed by at least one unit delay; first logic controlled by a first control signal, configured to receive the plurality of delayed signals, and configured to select at least one of the delayed signals as a first signal; a plurality of duty cycle scaling components, including one or more of an amplification component and a decrementing component, wherein, based on the selected delayed signal and the input signal, the amplification component is configured to generate at least an amplified duty cycle signal (path 1) when the duty cycle of the input signal is less than an ideal duty cycle, and the decrementing component is configured to generate a decremented duty cycle signal (path 2) when the duty cycle of the input signal is greater than the ideal duty cycle; and path correction logic configured to generate a corrected duty cycle based on the selection of at least one of an amplified duty cycle or a decremented duty cycle by providing a second control signal, wherein the amplification or decrementing of the duty cycle is performed until the detected duty cycle of the input signal remains less than or greater than a threshold level.

[0013] In another aspect of this disclosure, a duty cycle correction (DCC) circuit is provided, the duty cycle correction (DCC) circuit including a processing circuit system configured to: generate a plurality of delayed input signals, each of the delayed input signals being delayed by at least one unit delay; receive the plurality of delayed signals to select at least one of the delayed signals as a first signal; based on the first signal and the input signal, generate an increased duty cycle signal (path 1) when the duty cycle of the input signal is less than an ideal duty cycle, and generate a decreased duty cycle signal (path 2) when the duty cycle of the input signal is greater than the ideal duty cycle; and generate a corrected duty cycle based on the selection of at least one of increasing or decreasing the duty cycle by providing a second control signal, wherein the increase or decrease of the duty cycle is performed until the detected duty cycle of the input signal remains less than or greater than a threshold level.

[0014] To further illustrate the advantages and features of the inventive concept, a more specific description of the inventive concept will be presented with reference to exemplary embodiments shown in the accompanying drawings. It should be understood that these drawings depict exemplary embodiments of the inventive concept and should therefore not be considered as limiting the scope of the exemplary embodiments of the inventive concept. The inventive concept will be described and explained with additional features and details in conjunction with the drawings. Attached Figure Description

[0015] These and other features, aspects, and advantages of the invention will be better understood when the following detailed description is read with reference to the accompanying drawings, in which the same characters denote the same parts throughout the drawings, wherein:

[0016] Figure 1A and Figure 1B The control flow for duty cycle correction of input signals for a transceiver is shown according to another example embodiment of this subject matter;

[0017] Figure 2A An implementation of a duty cycle correction control circuit according to another exemplary embodiment of this subject is shown;

[0018] Figure 2B References to another example embodiment of this subject are shown. Figure 2A The arrangement of delay elements;

[0019] Figure 3A Another implementation of a duty cycle correction control circuit according to another example embodiment of this subject matter is shown;

[0020] Figure 3B References to another example embodiment of this subject are shown. Figure 3A The arrangement of delay elements;

[0021] Figure 4 The output waveforms of the corresponding increased duty cycle signal (path 1) and decreased duty cycle signal (path 2) according to another exemplary embodiment of this subject are shown;

[0022] Figure 5 This illustrates the output duty cycle changes corresponding to an increasing duty cycle signal (path 1) and a decreasing duty cycle signal (path 2) according to another example embodiment of this subject matter; and

[0023] Figure 6A , Figure 6B and Figure 6C The duty cycle extended output waveforms corresponding to the OR path (path 1) and the AND path (path 2) according to another example embodiment of this subject are shown.

[0024] Furthermore, those skilled in the art will understand that the elements in the accompanying drawings are shown for simplicity and may not be drawn to scale. For example, flowcharts illustrate methods according to the most prominent operations involved to aid in understanding aspects of the inventive concept. Additionally, regarding the construction of the apparatus, one or more components of the apparatus may already be represented by conventional symbols in the drawings, and the drawings may only show those specific details relevant to exemplary embodiments for understanding the inventive concept, so as not to obscure the drawings due to details that will be readily apparent to those of ordinary skill in the art as described herein. Detailed Implementation

[0025] To facilitate an understanding of the principles of the inventive concept, reference will now be made to the exemplary embodiments shown in the accompanying drawings, and the exemplary embodiments will be described using specific language. However, it should be understood that this is not intended to limit the scope of the inventive concept, and such changes and further modifications in the illustrated system, as well as such further applications of the principles of the inventive concept illustrated therein, are contemplated by those skilled in the art as commonly conceived of the inventive concept.

[0026] Those skilled in the art will understand that the foregoing general description and the following detailed description are illustrative of this disclosure and are not intended to limit it.

[0027] Throughout this specification, references to "one aspect," "another aspect," or similar language mean that a particular feature, structure, or characteristic described in connection with an exemplary embodiment is included in at least one exemplary embodiment of this disclosure. Therefore, the appearance of phrases such as "in an exemplary embodiment," "in another exemplary embodiment," and similar language throughout this specification may, but not necessarily, all refer to the same exemplary embodiment.

[0028] The terms “comprising,” “including,” or any other variations thereof are intended to cover non-exclusive inclusion, such that a process or method that includes a list of operations may include not only those operations but also other operations not expressly listed or inherent to such process or method. Similarly, without further constraints, a list of one or more devices, subsystems, elements, structures, or components beginning with “comprising…” does not exclude the presence of other devices or subsystems or elements or structures or components, or additional devices or subsystems or elements or structures or components.

[0029] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. The systems, methods, and examples provided herein are illustrative only and are not intended to be limiting.

[0030] This invention relates to a method for duty cycle correction of an input signal (IN) from a device such as a transceiver, the method comprising analyzing the duty cycle of the input signal (IN). The analysis of the input signal includes investigating whether the input signal (IN) has a duty cycle greater than or less than a certain level (e.g., 50%). Furthermore, if the duty cycle is greater than this level (e.g., 50%), the duty cycle of the signal is reduced by implementing AND logic on the input signal and the corresponding delay. Similarly, if the duty cycle is less than this level (e.g., 50%), the duty cycle of the signal is increased by implementing OR logic on the input signal and the corresponding delay. The delayed signal can be an input signal with a delay of one or more units, wherein the units of delay are based on the desired duty cycle correction level. An output signal with a corrected duty cycle can be obtained.

[0031] Figure 1A The control flow (1000) of a method for duty cycle correction of an input signal (IN) for a transceiver is shown according to another example embodiment of this subject.

[0032] In the implementation, Figure 1A A method for duty cycle correction of an input signal (IN) is described, the method comprising: detecting (operation 1001) the duty cycle of the input signal (IN) received by a transceiver and the ideal duty cycle of the input signal, and then determining (operation 1002) whether the duty cycle of the input signal is greater than or less than the ideal duty cycle, wherein the ideal duty cycle corresponds to a unit interval (UI).

[0033] The method also includes generating (operation 1004) multiple intermediate delayed input signals (N0 to N) via a delay line driven by the input signal (IN). n Each intermediate input signal is delayed by at least one unit delay.

[0034] The method also includes using a first control signal to control multiple delayed signals (N0 to N). n A selection is made from multiple delayed input signals (N0 to N...) (operation 1006), where the selection is based on the number of unit delays in the input signal (IN). n At least one delayed input signal is selected from the input signals based on a determined difference between the duty cycle of the input signal and the ideal duty cycle. In one implementation, as a non-limiting factor, an 8:1 multiplexer can be implemented to select the delayed signals (N0 to N...). n )one.

[0035] The method further includes: generating (operation 1008) at least one of an increased duty cycle signal (path 1) when the duty cycle of the input signal is less than the ideal duty cycle and a decreased duty cycle signal (path 2) when the duty cycle of the input signal is greater than the ideal duty cycle, based on the selected delayed signal and the input signal (IN). The increased duty cycle signal (path 1) can be obtained using OR logic, and the decreased duty cycle signal (path 2) can be obtained using AND logic. The increase / decrease in the duty cycle of the input signal can be based on the difference between the existing duty cycle of the input signal and the desired level of the duty cycle of the input signal. Therefore, the delayed signal (N0 to N...) n The selection of the duty cycle is based on the desired level of decrease / increase in the duty cycle of the input signal. The method further includes generating (operation 1010) a corrected duty cycle based on the selection of at least one of an increased duty cycle and a decreased duty cycle via a provided second control signal. The corrected duty cycle is output after either an increase or a decrease in the duty cycle, wherein the increase in duty cycle is performed until the detected duty cycle of the input signal reaches less than a threshold, or the decrease in duty cycle is performed until the detected duty cycle of the input signal reaches greater than a threshold. As a non-limiting factor, the threshold can be considered as 50%. As a non-limiting aspect, a 2:1 multiplexer can be used to select either an increased duty cycle path (path 1) or a decreased duty cycle path (path 2). A signal with the corrected duty cycle can be obtained from the output of the multiplexer.

[0036] Figure 1B An example implementation of the method (100) for duty cycle correction of an input signal according to another example embodiment of this subject is shown.

[0037] Following the analysis in operation 102, if the duty cycle of the input signal (IN) is greater than or less than 50%, then operation 104 or operation 106 is followed. This operation 102 corresponds to operation 1004.

[0038] In operation 108, when the duty cycle of the input signal (IN) is greater than 50%, the duty cycle of the signal is reduced. The reduction of the signal's duty cycle is achieved by performing an AND logic (operation 108) on the input signal (IN) and an input signal (INB) with one or more unit delays. This operation 108 corresponds to operations 1006 and 1008.

[0039] Similarly, in operation 110, when the duty cycle of the input signal (IN) is less than 50%, the duty cycle of the signal is increased. This increase in the duty cycle is achieved through an OR logic (operation 110) performed on the input signal (IN) and an input signal (INB) with one or more unit delays. Operations 108 and 110 correspond to operations 1006 and 1008.

[0040] In final operation 112, one of the paths with a corrected duty cycle of the signal is selected, wherein the corrected duty cycle of the signal has a target increase / decrease duty cycle of the signal.

[0041] According to another example embodiment of this subject matter Figure 2A An implementation of the duty cycle correction control circuit is shown. Figure 2B Show reference Figure 2A Arrangement of the delay element (220).

[0042] In embodiments of this disclosure, a method for duty cycle correction of an input signal (IN) is provided, the method comprising generating a plurality of intermediate delayed input signals (N0 to N) via delay lines (221 to 228) driven by the input signal (IN). n The operation is as follows, as shown in the reference. Figure 2B Each intermediate input signal is delayed by at least one unit.

[0043] The method also includes using a first control signal (in) Figure 2A The input signals (N0 to N) are referred to as SEL<2:0>. n The selection is made among the input signals (N0 to N) based on the number of unit delays in the input signal (IN). In one implementation, as a non-limiting factor, an 8:1 multiplexer (202, I0) can be implemented to select the delayed input signals (N0 to N...). n One of them (O1).

[0044] The method further includes generating at least one of an increased duty cycle signal (path 1) and a decreased duty cycle signal (path 2) based on the selected delayed signal and the input signal (IN). The increased duty cycle signal (path 1) can be obtained using OR logic (110), and the decreased duty cycle signal (path 2) can be obtained using AND logic (108), wherein the increase / decrease of the duty cycle of the input signal can be based on the difference between the existing duty cycle of the input signal and the desired level of the duty cycle of the input signal. Therefore, the delayed input signal (N0 to N... n The selection is based on the desired level of decreasing / increasing the duty cycle of the input signal.

[0045] The method further includes: via a provided second control signal (in Figure 2A It is called SEL <3> The corrected duty cycle is generated based on the selection of at least one of an increased duty cycle and a decreased duty cycle. As a non-limiting aspect, a 2:1 multiplexer (208, I1) can be used to select either an increased duty cycle path (path 1) or a decreased duty cycle path (path 2). A signal (OUT) with the corrected duty cycle can be obtained from the output of the multiplexer (208).

[0046] In embodiments of this disclosure, a duty cycle correction (DCC) circuit (200) for a transceiver is provided. The DCC circuit (200) is used to correct or adjust the duty cycle of an input signal (IN). The DCC circuit (200) includes a duty cycle detector for detecting the duty cycle of the input signal received by the transceiver and an ideal duty cycle, and determining whether the duty cycle of the input signal is greater than or less than the ideal duty cycle, wherein the ideal duty cycle corresponds to a unit interval (UI).

[0047] The DCC circuit (200) includes a delay element (220) driven by an input signal (IN). The delay element (220) also includes multiple delay lines (221 to 228) connected in series to generate multiple intermediate delayed input signals (N0 to N). n ), as shown in the reference Figure 2B Each intermediate input signal is delayed by at least one unit.

[0048] The DCC circuit (200) also includes an 8:1 multiplexer (202) (or, referred to as, the first logic), which is implemented as one of the selected delay signals (N0 to N7). This can be achieved via a first control signal (in... Figure 2A The selection is made from multiple delayed signals (N0-N7) using a method called SEL<2:0>. The selection of one of the delayed signals is based on the number of unit delays required in the input signal (IN).

[0049] The DCC circuit (200) also includes an AND gate (206) and an OR gate (204). The AND gate (206) generates a reduced duty cycle signal (path 2) based on a selected delayed signal and the input signal (IN) when the duty cycle of the input signal is greater than the ideal duty cycle. The OR gate (204) generates an increased duty cycle signal (path 1) when the duty cycle of the input signal is less than the ideal duty cycle. The operation of the OR gate (204) and the AND gate (206) is based on one of the selected delayed input signals (N0-N7) and the input signal (IN). The increase or decrease of the duty cycle of the input signal may be based on the difference between the existing duty cycle of the input signal and the desired level of the duty cycle of the input signal. Therefore, the selection of the delayed input signals (N0-N7) is based on the desired level of decrease / increase of the duty cycle of the input signal. In one example, the DCC circuit (200) may include a plurality of duty cycle scaling components, including one or more of an increasing component (204) and a decreasing component (206).

[0050] The DCC circuit (200) also includes a 2:1 multiplexer (208) (or, referred to as, path correction logic), which is used to generate a corrected duty cycle, based on a second control signal provided (in... Figure 2A It is called SEL <3> The 2:1 multiplexer (208) is used to select either an increased duty cycle path (path 1) or a decreased duty cycle path (path 2). A signal (OUT) with the corrected duty cycle can be obtained from the output of the multiplexer (208).

[0051] In another embodiment of this disclosure, a method for duty cycle correction (DCC) of an input signal (IN) is provided, the method comprising generating a plurality of intermediate delayed input signals (N0 to N... n The method involves an operation where each intermediate delayed input signal is delayed by at least one unit delay. The method also includes controlling the input signals (N0 to N) via a first control signal. n The selection is made among the input signals (IN). This selection is based on the required unit delay in the input signal (IN), which is further based on the requirement to increase / decrease the duty cycle of the input signal (IN). The method also includes generating an increased duty cycle signal (path 1) and a decreased duty cycle signal (path 2) based on the selected delay signal and a signal from at least one of the input signal (IN) and its inverted counterpart (INB). OR logic (110) can be implemented to increase the duty cycle of the selected input signal (IN or INB), wherein the increase in the signal's duty cycle is managed by the required unit delay added to the selected input signal (IN or INB). Similarly, AND logic (108) can be implemented to decrease the duty cycle of the selected input signal (IN or INB), wherein the decrease in the signal's duty cycle is managed by the required delay added to the selected input signal (IN or INB).

[0052] The method further includes selecting at least one of a path associated with increasing the duty cycle signal (path 1) or decreasing the duty cycle signal (path 2). The method also includes generating an output signal with a corrected duty cycle based on the selection of at least one of the increasing duty cycle signal (path 1) and decreasing duty cycle signal (path 2) via a provided second control signal.

[0053] According to another example embodiment of this subject matter Figure 3A Another embodiment of the duty cycle correction control circuit shown is as follows: Figure 3B Show reference Figure 3A The arrangement of delay elements.

[0054] In another embodiment of this disclosure, a duty cycle correction (DCC) circuit (300) is provided for correcting / adjusting the duty cycle of an input signal (IN). The DCC circuit (300) includes input signals (N0 to N00) driven by the input signal (IN) to generate a plurality of intermediate delays. n The delay line (320) is a delay line. Each intermediate delayed signal is delayed by at least one unit from the previous signal. The delay line (320) may include a plurality of inverters (321 to 328) connected in series, wherein the intermediate delayed input signals (N0 to N...) are... n One of the following is obtained after each inverter (321 to 328). Each inverter (321 to 328) is adapted to produce a minimum duty step (which may be referred to as an inverter delay), which can be used for very high-speed applications.

[0055] The DCC circuit (300) includes a 2:1 multiplexer (301, I2), as shown in the reference. Figure 3A The control signal SEL is provided <0> To select one from the input signal (IN) and the inverted input signal (INB).

[0056] The selected input signal (IN or INB) (IN_SEL) is used to generate an increased duty cycle signal (path 1) and a decreased duty cycle signal (path 2) based on the selected delay. OR gates (304, 110) can be implemented to increase the duty cycle of the selected input signal (IN or INB), where the increase in the signal's duty cycle is managed by the amount of delay required to add it to the selected input signal (IN or INB). Similarly, AND gates (306, 108) can be implemented to decrease the duty cycle of the selected input signal (IN or INB), where the decrease in the signal's duty cycle is managed by the amount of delay required to add it to the selected input signal (IN or INB).

[0057] The DCC circuit (300) also includes an (n+1):1 multiplexer (302), which can be implemented as a selected delay input signal (N0 to N... n One of (O1), where n is a positive integer. Through the first control signal (in Figure 3A This is also referred to as SEL<2:0> to control multiple delayed input signals (N0 to N). n The choice among (N0 to N) is as follows. As a non-limiting factor, in this embodiment, an 8:1 multiplexer (I0) is used as an example. The 8:1 multiplexer can select delayed input signals (N0 to N). n The selection is also based on the amount of unit delay required in the input signal (IN), which in turn is based on the need to increase / decrease the duty cycle of the input signal (IN).

[0058] The DCC circuit (300) also includes multiple multiplexers (305, 307) (or, path selection logic) that can be used in parallel to select either an increasing duty cycle signal (path 1) or a decreasing duty cycle signal (path 2).

[0059] The DCC circuit (300) also includes a multiplexer (308) for finally selecting the relatively selected signals from the previous multiplexer stages (305, 307) and for generating an output signal with a corrected duty cycle. The second control signal (in...) Figure 3A It is also known as SEL <3> ) is used to control the multiplexer (308).

[0060] In addition, another 2:1 multiplexer stage (310) (or, referred to as, auxiliary logic) is provided to allow based on the first control signal SEL <0> The choice between the output and its complement is taken as the final output OUT, thereby providing an output similar to that of the input stage (301), which allows the choice between the main input IN and its complement INB in ​​the input stage (301). For example, the choice of INB in ​​input 301 results in the output of the complement of the output in the multiplexer stage (310).

[0061] In another implementation, when the LSB bit is 0 (e.g., when the select line S...), <0> When =0 is selected), the inverted input signal (IN) and the inverted signal (INB) from the delay lines (221 to 228, 320) will be compared (as shown in the reference). Figure 2B and Figure 3B The input signal (INB) is provided together with OR logic gates (110, 204, 304) and / or AND logic gates (108, 206, 306). The multiplexer (301) selects the delayed input signal (INB) and passes the selected signal through the AND logic gates and / or logic gates.

[0062] In another implementation, when the LSB bit is 1 (e.g., when the select line S...), <0> When =1 is selected, the buffered input signal (IN) is provided together with the buffered input signal from the delay line (INB) to AND gates (108, 206, 306) and / or OR gates (110, 204, 304). The multiplexer (301) selects the input signal (IN) and passes the selected signal through the AND gates and / or OR gates.

[0063] In another embodiment, when the duty cycle of the input signal is <50%, the selection line SEL is selected from the multiplexer (308). <3> =“0” can be further selected or path (110, 204, 304), or the path continues to increase the SEL<2:0> bits of the multiplexer (302) until the duty cycle reaches close to 50%.

[0064] In another embodiment, when the duty cycle of the input signal is >50%, the selection line SEL is selected from the multiplexer (308). <3> =“1” can be further selected with path (108, 206, 306), with path continuing to reduce the SEL<2:0> bits of multiplexer (302) until the duty cycle reaches close to 50%.

[0065] Any disclosed element may include a processing circuitry system (such as hardware including logic circuitry), a hardware / software combination (such as a processor executing software), or a combination thereof, or implemented in a processing circuitry system (such as hardware including logic circuitry), a hardware / software combination (such as a processor executing software), or a combination thereof. For example, a processing circuitry system may more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field-programmable gate array (FPGA), a system-on-a-chip (SoC), a programmable logic unit, a microprocessor, an application-specific integrated circuit (ASIC), etc.

[0066] Example use cases:

[0067] The following are different scenarios related to methods involving duty cycle correction (DCC):

[0068]

[0069] When the signal has a 40% duty cycle

[0070]

[0071] When the signal has a 60% duty cycle

[0072]

[0073]

[0074] If S <3> =0, regarding the selection bit [s<2:0>], path 1 is selected and the duty cycle is increased.

[0075] If S <3> =1, regarding the selection bit [s<2:0>], path 2 is selected and the duty cycle is reduced.

[0076] If the input duty cycle is 40%:

[0077] The inverter delay is 2% T ON / T OFF [Step size is 2%]

[0078]

[0079] If the input duty cycle is 60%:

[0080] The inverter delay is 2% T ON / T OFF [Step size is 2%]

[0081]

[0082] Figure 4 The output waveforms of the corresponding increasing duty cycle signal (path 1) and decreasing duty cycle signal (path 2) according to another example embodiment of this subject are depicted. The first waveform (from top) depicts the input signal (IN) and the delayed signal (Delay_IN). The intermediate waveform depicts the increasing signal (OR-OUT) obtained after the OR logic gate (path 1), where the input signal (IN) is increased by a specific delay unit. The final waveform depicts the decreasing signal (AND_OUT) obtained after the AND logic gate (path 2), where the input signal (IN) is decreased by a specific delay unit. The increase / decrease of the input signal (IN) is based on the difference between the input signal (IN) and the delayed signal (Delay_IN).

[0083] Figure 5 The changes in output duty cycle (Duty_out) corresponding to an increasing duty cycle signal (path 1) and a decreasing duty cycle signal (path 2) are depicted according to another example embodiment of this subject.

[0084] Figure 6A , Figure 6B and Figure 6C The AND-OR path (path 1) and the duty cycle extended output waveform corresponding to the path (path 2) are shown in another example embodiment of this topic. Figure 6A The waveforms referenced clearly depict a comparative analysis between the input signal (IN) and scaled signals from two different paths (i.e., the increased signal obtained after the OR path (path 1) and the decreased signal obtained after the AND path (path 2)). Furthermore, the waveforms of the scaled signals (increased or decreased) represent changes in the scaling level (A to H), which are based on the selection of the number of unit delays through the delayed signals (N0 to N7). Figure 6B and Figure 6C It is a magnified image, and precisely depicts the scaling levels (A to H) implemented on path 1 and path 2 respectively.

[0085] Experimental results:

[0086] In one example, consider a general scenario where the DCC circuit is used for the analysis of various parameters. Table 1 shows a comparison between conventional techniques and the DDC circuit of this disclosure:

[0087] Table 1

[0088]

[0089] In view of the foregoing, various advantageous features relating to this disclosure are provided:

[0090] Standard cells based on lower power and lower area duty cycle correction.

[0091] A higher probability or guaranteed monotonicity.

[0092] Applications in high-speed electronic devices.

[0093] Using at least one exemplary embodiment, a wider duty cycle correction range with more uniform step size can be achieved.

[0094] Compared to previous designs, at least one example embodiment offers lower power consumption.

[0095] Since at least one example embodiment occupies a smaller area compared to previous designs, this circuit can be used in applications where area is one of the main constraints.

[0096] While specific language has been used to describe the subject matter, it is not intended to limit it in any way. It will be apparent to those skilled in the art that various modifications can be made to the methods to achieve the inventive concept as taught herein. The accompanying drawings and the foregoing description provide examples of exemplary embodiments. Those skilled in the art will understand that one or more of the described elements can be well combined into a single functional element. Optionally, a particular element may be divided into multiple functional elements. Elements from one exemplary embodiment may be added to another exemplary embodiment.

Claims

1. A method for duty cycle correction of an input signal for a transceiver, the method comprising the following operations: Detect the duty cycle of the input signal received by the transceiver and the ideal duty cycle of the input signal; Determine whether the duty cycle of the input signal is greater than or less than the ideal duty cycle, where the ideal duty cycle corresponds to the unit interval; Multiple delayed input signals are generated by delay lines driven by the input signals, each delayed input signal being delayed by at least one unit delay; Based on the difference between the duty cycle of the determined input signal and the ideal duty cycle, at least one delayed input signal is selected from the plurality of delayed input signals; Based on the selected delay signal and the input signal, generate at least one of the following signals: Increasing the duty cycle of the input signal when its duty cycle is less than the ideal duty cycle, and A reduced duty cycle signal when the duty cycle of the input signal is greater than the ideal duty cycle.

2. The method of claim 1, wherein, The corrected duty cycle is output after either increasing or decreasing the duty cycle, wherein increasing the duty cycle is performed until the detected duty cycle of the input signal reaches less than a threshold, or decreasing the duty cycle is performed until the detected duty cycle of the input signal reaches greater than a threshold.

3. The method of claim 1, wherein, When the duty cycle of the input signal is less than the threshold, the duty cycle of the selected delayed signal is increased, and when the duty cycle of the selected input signal is greater than the threshold, the duty cycle of the selected delayed signal is decreased.

4. The method of claim 1, wherein, An increased duty cycle signal is generated by an OR logic operation, and a decreased duty cycle signal is generated by an AND logic operation. The OR and AND logic operations are performed on a selected delayed signal and a signal selected from the input signal and the inverted input signal. The selection of at least one delayed input signal from the plurality of delayed input signals is based on the determination of the duty cycle, using a first control signal.

5. The method of any one of claims 1 to 4, wherein, The signal is executed incrementally by increasing the duty cycle of the OR operation or decreasing the duty cycle of the AND operation until the duty cycle of the signal reaches the desired level.

6. A duty cycle correction circuit for a transceiver, comprising: A delay line includes multiple delay components, which are driven by an input signal and configured to generate multiple delayed input signals, each delayed input signal being delayed by at least one unit delay; A first logic, controlled by a first control signal, is configured to receive the plurality of delayed signals and to select at least one delayed signal from the plurality of delayed signals as a first signal. Multiple duty cycle scaling components, including one or more of an amplification component and a decrementing component, are configured, based on a selected delayed signal and an input signal, such that the amplification component generates an amplified duty cycle signal when the duty cycle of the input signal is less than the ideal duty cycle, and the decrementing component generates a decrementing duty cycle signal when the duty cycle of the input signal is greater than the ideal duty cycle. The path correction logic is configured to generate a corrected duty cycle based on a selection of at least one of increasing and decreasing the duty cycle via a provided second control signal, wherein increasing or decreasing the duty cycle is performed until the detected duty cycle of the input signal remains less than or greater than a threshold level.

7. The duty cycle correction circuit of claim 6, wherein, The plurality of delay components include a plurality of inverters connected in series and / or a plurality of sub-delay lines connected in series, wherein the output after each delay component generates a delayed signal.

8. The duty cycle correction circuit of claim 6, wherein, The first logic consists of (n+1): a 1-multiplexer, where n is a positive integer.

9. The duty cycle correction circuit of claim 6, wherein, The amplification component for generating an amplified duty cycle signal includes an OR logic gate, and the decrementing component for generating a decremented duty cycle signal includes an AND logic gate.

10. The duty cycle correction circuit of claim 6, wherein, The duty cycle correction circuit further includes path selection logic, which is configured to select at least one of path 1 corresponding to the signal that increases the duty cycle and path 2 corresponding to the signal that decreases the duty cycle, so as to increase and / or decrease the duty cycle of the signal.

11. The duty cycle correction circuit according to any one of claims 6 to 10, wherein, The duty cycle correction circuit further includes auxiliary logic configured to select the corrected duty cycle signal.

12. A duty cycle correction circuit for a transceiver, comprising: The processing circuit system is configured as follows: Generate multiple delayed input signals, each delayed by at least one unit delay; Receive the plurality of delayed signals to select at least one delayed signal from the plurality of delayed signals as a first signal; Based on the first signal and the input signal, an increased duty cycle signal is generated when the duty cycle of the input signal is less than the ideal duty cycle, and a decreased duty cycle signal is generated when the duty cycle of the input signal is greater than the ideal duty cycle. A corrected duty cycle is generated based on a selection of at least one of increasing or decreasing the duty cycle using a provided second control signal, wherein increasing or decreasing the duty cycle is performed until the detected duty cycle of the input signal remains less than or greater than a threshold level.

13. The duty cycle correction circuit of claim 12, wherein, The processing circuit system includes multiple delay components, and the multiple delay components include multiple inverters connected in series and / or multiple sub-delay lines connected in series, wherein the output after each delay component generates at least one of the multiple delayed input signals.

14. The duty cycle correction circuit of claim 12, wherein, The processing circuit system includes (n+1): a 1-multiplexer, where n is a positive integer.

15. The duty cycle correction circuit of claim 12, wherein, The processing circuit system includes OR logic gates and AND logic gates, wherein the OR logic gates are configured to generate an increasing duty cycle signal and the AND logic gates are configured to generate a decreasing duty cycle signal.

16. The duty cycle correction circuit of claim 12, wherein, The processing circuit system also includes path selection logic configured to select at least one of path 1 corresponding to the increase duty cycle signal and path 2 corresponding to the decrease duty cycle signal to increase and / or decrease the duty cycle of the input signal.

17. The duty cycle correction circuit according to any one of claims 12 to 16, wherein, The processing circuitry also includes auxiliary logic configured to select the corrected duty cycle signal.

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