Sub-sampling duty cycle corrector and clock generator

Abstract

Proposed are a sub-sampling duty cycle corrector and a clock generator capable of securing high precision low-jitter characteristics by detecting duty cycle information as a voltage through a sub-sampling process and processing the duty cycle information. The sub-sampling duty cycle corrector generates an output signal by correcting the phase of an input signal, and comprises an inverter, a pulse generation unit, a frequency tracking and rising edge alignment unit, and a falling edge alignment unit.

Description

Subsampling duty cycle corrector and clock generator

[0001] The present invention relates to a duty cycle corrector, and more particularly to a subsampling duty cycle corrector capable of securing high precision low jitter characteristics by detecting duty cycle information as voltage through a subsampling process and processing it, and to a clock generator including the same.

[0002] In circuits that operate based on a clock or clock signal, it is important that the duty cycle of the clock signal is accurately controlled. For example, in a memory device where data is input / output at the rising edge and falling edge of a clock signal, if the clock signal duty cycle is not exactly 50%, the timing of the rising and falling edges is misaligned, and data cannot be input / output at the correct moment. Therefore, duty cycle correction circuits are used in various integrated circuits that operate based on clock signals to correct the duty cycle of the clock signal.

[0003] Here, the fact that the clock duty cycle is 50% means that the length of the high-level period and the low-level period of the clock signal are the same.

[0004] Figure 1 is a block diagram of a conventional duty cycle corrector.

[0005] Referring to FIG. 1, a conventional duty cycle adjuster (100) includes a duty cycle adjuster (110, Duty Cycle Adjuster, DCA), a charge pump (120, Charge Pump, CP), a loop filter (130, Loop Filter, LF), and an inverter (140).

[0006] The inverter (140) generates an inverted input signal ( / IN) that inverts the phase of the input signal (IN).

[0007] The duty cycle adjustment device (110) has a first duty control voltage (V OUTP ) and second duty control voltage (V OUTM In response to ), it generates a first output (OUTP) and a second output (OUTM) by adjusting the duty cycle of the input signal (IN) and the inverted input signal ( / IN). The charge pump (120) generates a charge / discharge current corresponding to the duty cycle of the first output (OUTP) and the second output (OUTM). The loop filter (130) generates a first duty control voltage (V) corresponding to the charge / discharge current output from the charge pump (120). OUTP ) and second duty control voltage (V OUTM Creates ).

[0008] Figures 2a and 2b illustrate the operation of a conventional duty cycle corrector.

[0009] FIG. 2a shows the first output (OUTP), second output (OUTM), and first duty control voltage (V) according to the magnitude of the clock duty cycle when the frequency of the clock signal is high (High Speed ​​Clock Signal). OUTP ) and second duty control voltage (V OUTM Displays the waveform of ).

[0010] When the duty cycle of the clock is less than 50% (Duty < 50%), low-pass filtering is performed by the loop filter (130), and the duty cycle information of the first output (OUTP) and the second output (OUTM) is output as DC, and the second duty control voltage (V OUTM The level of ) is the first duty control voltage (V OUTP It has a value greater than ). At this time, the duty cycle adjustment device (110) performs an operation to reduce the duty cycle.

[0011] When the duty cycle is approximately 50% (Duty ≈ 50%), the first duty control voltage (V OUTP ) and second duty control voltage (V OUTMThe level of ) has almost the same value, and at this time the duty cycle becomes 50%, so the duty cycle corrector is said to be locked.

[0012] When the duty cycle is greater than 50% (Duty > 50%), the first duty control voltage (V OUTP ) is the second duty control voltage (V OUTM It has a value greater than ) and performs an operation to reduce the duty cycle in the duty cycle adjustment device (110).

[0013] FIG. 2b shows the first output (OUTP), second output (OUTM), and first duty control voltage (V) according to the magnitude of the clock duty cycle when the clock signal frequency is low (low speed signal). OUTP ) and second duty control voltage (V OUTM Displays the waveform of ).

[0014] Referring to FIG. 2b, since the DC range is relatively wider when the clock signal frequency is low (Fig. 2b) compared to when the clock signal frequency is high (Fig. 2a), the first duty control voltage (V) output from the loop filter (130) OUTP ) and second duty control voltage (V OUTM It can be seen that there is a slight difference in the level of ).

[0015] In particular, when the frequency of the clock signal is low, it can be seen that there is no significant difference between the case where the duty cycle is greater than 50% and the case where the duty cycle is small compared to the case where the duty cycle is 50%.

[0016] That is, the conventional duty cycle corrector (100) has a problem in that it is difficult to achieve high precision in adjusting the duty when the frequency of the clock signal is high.

[0017] The technical problem that the present invention aims to solve is to provide a subsampling duty cycle corrector capable of securing high precision low jitter characteristics by detecting duty cycle information as voltage through a subsampling process and processing it.

[0018] Another technical problem that the present invention aims to solve is to provide a clock generator including a subsampling duty cycle corrector capable of securing high precision low jitter characteristics by detecting duty cycle information as voltage through a subsampling process and processing it.

[0019] A subsampling duty cycle corrector according to the present invention for achieving the above technical problem generates an output signal with the phase corrected of an input signal and includes an inverter, a pulse generation unit, a frequency tracking & rising edge alignment unit and a falling edge alignment unit.

[0020] The inverter generates an inverted output signal by inverting the phase of the output signal. The pulse generation unit generates two pulses having the same phase and inverted phase as the output signal, and two pulses having the same phase and inverted phase as the inverted output signal. The frequency tracking unit and rising edge alignment unit generate a control voltage for a voltage-controlled oscillator using the output signal and two pulses having the same phase and inverted phase as the output signal, and perform the operation of tracking the target frequency and aligning the buffered clock P and buffered clock M to the rising edge of the output signal. The falling edge alignment unit generates the output signal by processing the input signal, the buffered clock P, and the buffered clock M using the inverted output signal and two pulses having the same phase and inverted phase as the inverted output signal.

[0021] A clock generator according to the present invention for achieving the above other technical objectives includes a subsampling duty corrector as described in claim 1.

[0022] The technical solutions to be achieved in the present invention are not limited to those mentioned above, and other technical solutions not mentioned will be clearly understood by those skilled in the art to which the present invention belongs from the description below.

[0023] The subsampling duty cycle corrector and clock generator according to the present invention, as described above, have the advantage of securing high precision low jitter characteristics by detecting duty cycle information as voltage through a subsampling process and processing it.

[0024] Figure 1 is a block diagram of a conventional duty cycle corrector.

[0025] Figures 2a and 2b illustrate the operation of a conventional duty cycle corrector.

[0026] FIG. 3 is a block diagram of a subsampling duty corrector according to the present invention.

[0027] FIG. 4 is a signal diagram illustrating the falling edge alignment operation of a subsampling duty cycle corrector according to the present invention.

[0028] In order to fully understand the present invention, the operational advantages of the present invention, and the objectives achieved by the implementation of the present invention, reference should be made to the accompanying drawings describing embodiments of the present invention and the contents described in the accompanying drawings.

[0029] The present invention will be described in detail below by explaining preferred embodiments of the invention with reference to the attached drawings. Identical reference numerals in each drawing indicate identical components.

[0030] FIG. 3 is a block diagram of a subsampling duty corrector according to the present invention.

[0031] Referring to FIG. 3, the sub-sampling duty cycle corrector (300, SSDCC) according to the present invention generates an output signal (OUT) that corrects the phase of an input signal (IN), and includes an inverter (310) that performs this task, a pulse generation unit (320), a frequency tracking & rising edge alignment unit (330), and a falling edge alignment unit (340).

[0032] The inverter (310) generates an inverted output signal ( / OUT) by inverting the phase of the output signal (OUT).

[0033] The pulse generation unit (320) generates two pulses having the same phase and inverted phase as the output signal (OUT) and two pulses having the same phase and inverted phase as the inverted output signal ( / OUT) output from the inverter (310).

[0034] The frequency tracking & rising edge alignment unit (330) generates a buffered clock P (CLKP_b) and a buffered clock M (CLKM_b) using two pulses having the same phase and inverted phase as the output signal (OUT) and the inverted output signal ( / OUT) generated by the pulse generation unit (320).

[0035] The falling edge alignment unit (340) generates an output signal (OUT) by processing an input signal (IN), a buffered clock P (CLKP_b), and a buffered clock M (CLKM_b) using an inverted output signal ( / OUT) and two pulses having the same phase and an inverted phase as the inverted output signal ( / OUT). Alternatively, the function of the falling edge alignment unit (340) can be described as aligning the falling edges of the output signal (OUT) using the buffered clock P (CLKP_b) and the buffered clock M (CLKM_b).

[0036] The internal configuration and operation of the three units (320, 330, 340) shown in FIG. 3 will be described below.

[0037] The pulse generation unit (320) includes two pulse generators (Pulser).

[0038] The first pulse generator (321) generates two pulses having the same phase and the inverted phase as the inverted output signal ( / OUT) output from the inverter (310). The second pulse generator (322) generates two pulses having the same phase and the inverted phase as the output signal (OUT).

[0039] The frequency tracking & rising edge alignment unit (330) includes a first subsampling phase detector (331), a first charge pump (332), a first loop filter (333), a voltage-controlled oscillator (334), a CMOS buffer (335), an auxiliary circuit (336), and a CML buffer (337).

[0040] The first sub-sampling phase detector (331) samples and outputs a voltage corresponding to the phases of the buffered clock P (CLKP_b) and the buffered clock M (CLKM_b) at the moment when the output signal (OUT) transitions. Here, the moment when the output signal (OUT) transitions is the rising edge of the output signal (OUT), and the rising edge of the output signal (OUT) will be the falling edge of the inverted output signal ( / OUT).

[0041] The first charge pump (332) generates a current corresponding to the sampled voltage output from the first subsampling phase detector (341), and the generated current is output to the outside when two pulses having the same phase and inverted phase as the output signal (OUT) are each activated. Here, the outside may be the first loop filter (343) described later.

[0042] The first loop filter (333) generates an oscillator control voltage by performing charging and discharging of the internal circuit using the current generated by the first charge pump (342) and the current generated by the auxiliary circuit (336). The current generated by the auxiliary circuit (336) has a larger value than the current generated by the first charge pump (342) to reduce the frequency tracking time. When the frequency of the signal (CLKP, CLKM) output from the voltage control oscillator (334) has a value close to the target value, the operation of the auxiliary circuit (336) stops.

[0043] A voltage-controlled oscillator (334, Voltage Controlled Oscillator, VCO) generates clock P (CLKP) and clock M (CLKM), which are differential signals, in response to the oscillator control voltage output from the first loop filter (343).

[0044] The CMOS buffer (335) converts the voltage levels of clock P (CLKP) and clock M (CLKM), which are differential signals, into CMOS voltage levels and outputs them.

[0045] The auxiliary circuit (336) generates a current that charges and discharges the first loop filter (333) until the frequencies of the clock P (CLKP) and clock M (CLKM) converted to CMOS voltage levels approximate the target value. The CML buffer (337, Current Mode Logic) generates buffered clock P (CLKP_b) and buffered clock M (CLKM_b) converted into analog voltages corresponding to the clock P (CLKP) and clock M (CLKM) converted to CMOS voltage levels.

[0046] The polling edge alignment unit (340) includes a second subsampling phase detector (341), a second charge pump (342), a second loop filter (343), and a duty cycle adjuster (344).

[0047] The second subsampling phase detector (341) is a voltage (V) corresponding to the phase of the buffered clock P (CLKP_b) and the buffered clock M (CLKM_b) at the moment the inverted output signal ( / OUT) transitions. CLKP , V CLKM ) is sampled and output. Here, the name of the falling edge alignment unit (340) was selected because alignment is performed using the rising edge of the inverted output signal ( / OUT).

[0048] The second charge pump (342) outputs the sampled voltage (V) from the second subsampling phase detector (341). CLKP , V CLKM It generates a current corresponding to ), and the generated current is output externally when two pulses having the same phase and inverted phase as the inverted output signal ( / OUT) are each activated. Here, the external can be the second loop filter (343) described later.

[0049] The second loop filter (343) generates a duty control voltage that is generated while performing charging and discharging of the internal circuit in response to the current generated by the second charge pump (342).

[0050] The duty cycle adjuster (344, Duty Cycle Adjuster, DCA) generates an output signal (OUT) that adjusts the duty cycle of the input signal (IN) using the duty control voltage output from the second loop filter (343).

[0051] FIG. 4 is a signal diagram illustrating the falling edge alignment operation of a subsampling duty cycle corrector according to the present invention.

[0052] Referring to FIG. 4, in the case of the subsampling duty cycle corrector (300) according to the present invention, the duty cycle information is sampled voltage (V CLKP , V CLKMIt can be seen that it is indicated as ). In conventional duty cycle correctors, the pulse width was used as the criterion for detecting the duty cycle. This means that the subsampling duty cycle corrector (300) according to the present invention can detect the duty cycle more precisely than the conventional duty cycle corrector.

[0053] In FIG. 4, the voltage (V) sampled at the rising edge (refer to the vertical dashed line) of the inverted output signal ( / OUT) indicated by the dashed line is CLKP , V CLKM ...indicated )

[0054] Referring to FIG. 4, when the duty cycle of the input signal (IN) is 50% (Duty ≈ 50%), the sampled voltage (V) when the inverted output signal ( / OUT) is in a logic high state CLKP , V CLKM ) is identical.

[0055] When the duty cycle of the input signal (IN) is less than 50% (Duty < 50%), the voltage (V) sampled from the clock P (CLKP) when the inverted output signal ( / OUT) is in a logic high state CLKP The level of ) is the voltage (V) sampled at clock M (CLKM). CLKM It is greater than the level of ).

[0056] Conversely, when the duty cycle of the input signal (IN) is greater than 50% (Duty > 50%), and the inverted output signal ( / OUT) is in a logic high state, the voltage (V) sampled from the clock P (CLKP) CLKP The level of ) is the voltage (V) sampled at clock M (CLKM). CLKM It is smaller than the level of ).

[0057] The clock P (CLKP) and clock M (CLKM) generated by the voltage-controlled oscillator (344) contain phase noise that is relatively large compared to the input signal, but can be eliminated, for example, by adjusting the bandwidth of the frequency tracking & falling edge alignment unit (330) to be small.

[0058] By operating in this way, the subsampling duty cycle corrector (300) according to the present invention can secure high precision low jitter characteristics.

[0059] The subsampling duty cycle corrector (300) according to the present invention having the above-described features can be said to have very high utility as an interface between high-speed chips and as a clock correction circuit for a clock generator.

[0060] Although the technical concept of the present invention has been described above together with the accompanying drawings, this is merely an illustrative explanation of preferred embodiments of the present invention and is not intended to limit the invention. Furthermore, it is evident that any person skilled in the art to which the present invention pertains can make various modifications and imitations within the scope of the technical concept of the present invention without departing from its scope.

[0061] The present invention relates to a subsampling duty cycle corrector and a clock generator including the same, characterized by detecting duty cycle information as a voltage through a subsampling process and processing it, and has the advantage of securing high precision low jitter characteristics.

Claims

1. In a subsampling duty corrector that generates an output signal with the phase corrected of an input signal, An inverter that generates an inverted output signal by inverting the phase of the above output signal; A pulse generation unit that generates two pulses having the same phase and inverted phase as the output signal and two pulses having the same phase and inverted phase as the inverted output signal; A frequency tracking & rising edge alignment unit that generates an oscillator control voltage using two pulses having phases in the same and inverted phases as the output signal and the inverted output signal, and sets the target frequency tracking and buffered clock P and buffered clock M to the rising edge of the output signal; and A falling edge alignment unit that generates the output signal by processing the input signal, the buffered clock P, and the buffered clock M using the inverted output signal and two pulses having the same phase and the inverted phase as the inverted output signal. Subsampling duty corrector including.

2. In paragraph 1, the pulse generating unit is, A first pulse generator that generates two pulses having phases in phase and inversion phase with the inverted output signal; and A second pulse generator that generates two pulses having in-phase and inverted phases with the above output signal; Subsampling duty corrector including.

3. In paragraph 1, the frequency tracking & rising edge alignment unit is, A first subsampling phase detector that samples and outputs a voltage corresponding to the phases of the buffered clock P and the buffered clock M at the moment the output signal transitions; A first charge pump that generates a current corresponding to the sampled voltage output from the first subsampling phase detector, wherein the generated current is output when two pulses having the same phase and inverted phase as the output signal are each activated; A first loop filter that generates the oscillator control voltage while performing charging and discharging of the internal circuit in response to the current generated by the first charge pump and the current generated by the auxiliary circuit; A voltage-controlled oscillator that generates the clock P and the clock M in response to the oscillator control voltage; A CMOS buffer that converts the voltage levels of the above clock P and the above clock M into CMOS voltage levels and outputs them; The auxiliary circuit that generates current until it is determined that the frequencies of the clock P and the clock M, converted to CMOS voltage levels, approximate a target value; and A CML buffer that generates the buffered clock P and the buffered clock M by converting the clock P and the clock M, which are converted into CMOS voltage levels, into analog voltages corresponding to them. Subsampling duty corrector including.

4. In Paragraph 3, A subsampling duty corrector that outputs the current generated in the first charge pump to the first loop filter when two pulses having the same phase and inverted phase as the output signal are each activated.

5. In Paragraph 3, A subsampling duty corrector in which the moment the output signal transitions is the rising edge of the output signal.

6. In paragraph 1, the falling edge alignment unit is, A second subsampling phase detector that samples and outputs a voltage corresponding to the phases of the buffered clock P and the buffered clock M at the moment the inverted output signal transitions; Here, the moment when the inverted output signal transitions can be the rising edge of the inverted output signal, and for this reason, the name "falling edge alignment unit" was chosen. A second charge pump that generates a current corresponding to the sampled voltage output from the second subsampling phase detector, wherein the generated current is output externally when two pulses having the same phase and inverted phase as the inverted output signal are each activated; A second loop filter that generates a duty control voltage generated while performing charging and discharging of an internal circuit in response to the current generated by the second charge pump; and A duty cycle adjustment device that generates an output signal by adjusting the duty cycle of the input signal using the duty control voltage output from the second loop filter. Subsampling duty corrector including.

7. In Paragraph 6, The current generated by the second charge pump is a subsampling duty corrector that outputs to the second loop filter when two pulses having the same phase and inverted phase as the inverted output signal are each activated.

8. In Paragraph 6, A subsampling duty corrector in which the moment the inverted output signal transitions is the rising edge of the inverted output signal.

9. In Paragraph 3, A subsampling duty corrector that eliminates phase noise generated in the voltage-controlled oscillator by adjusting the bandwidth of the frequency tracking & rising edge alignment unit.

10. A clock generator comprising the subsampling duty corrector described in claim 1

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