A power-on initial state following CLK D-type edge flip-flop
By introducing a POR module, an initial state control module, and a clock control module into a D-type edge-triggered flip-flop, and using the combination of power-on signal and clock signal for control, the problem of inconsistent initial states of the D-type edge-triggered flip-flop upon power-on is solved, and the output signal is in phase with the clock signal, thus simplifying the circuit design.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- XIAMEN YUANSHUN MICROELECTRONICS TECH
- Filing Date
- 2026-02-10
- Publication Date
- 2026-06-16
AI Technical Summary
Existing D-type edge-triggered triggers may have inconsistent initial output states upon power-up under different process conditions and process fluctuations, leading to malfunctions in subsequent circuits. Furthermore, additional SET and RESET pins are required for preset, increasing the complexity of the peripheral circuitry.
The circuit employs a combination of POR module, initial state control module, clock control module, and trigger module. By using control signals such as power-on signal enH, inverted clock signal clka, and non-inverted clock signal clkb, the output signal Q is ensured to be in phase with the clock signal CLK in the initial state. Furthermore, by utilizing NAND gates to control the conduction of the front end and latch unit, the circuit stability is achieved and the control of the initial state is simplified.
It effectively controls the initial state upon power-on, ensuring that the output signal Q is in phase with the clock signal CLK, avoiding circuit malfunctions, simplifying the design of peripheral circuits, and reducing the complexity of pins and control circuits.
Smart Images
Figure CN121690148B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of D-type edge triggers, and more specifically to a D-type edge trigger that follows CLK in its initial power-on state. Background Technology
[0002] D-type edge-triggered flip-flops are core storage elements in digital circuits. Their core function is to capture and latch input data instantaneously at a specific edge of the clock signal, remaining completely "immune" to input changes at other times. This "instantaneous sampling + long-term retention" characteristic makes them the cornerstone of building synchronous sequential circuits. Their working principle can be broken down into three key stages: During the low-level clock, the master latch is in a transparent state, tracking changes in the input data D in real time; when the rising edge of the clock arrives, the master latch instantly turns off, "freezing" the current value of D at an internal node; subsequently, the slave latch turns on during the high-level clock, transferring the value latched by the master latch to the output Q and maintaining this state until the next clock edge. This master-slave structure, with dual latches working in relay, ensures complete temporal isolation between sampling and output through the inverting control of the clock signal, fundamentally avoiding the "flipping" problem caused by input glitches in level-triggered latches.
[0003] Please refer to the appendix. Figure 1 Existing D flip-flops generally do not define the initial state of the output upon power-up. Under different process conditions and objective process fluctuations, different parasitic capacitances may result in different initial output voltages, potentially leading to malfunctions in subsequent circuits. Conventionally, additional SET and RESET pins are required to preset the output state, occupying extra pins and control circuitry, resulting in more complex peripheral circuitry. Summary of the Invention
[0004] The purpose of this invention is to provide a D-type edge-triggered flip-flop that follows CLK in its initial power-on state, aiming to improve the problem that existing D flip-flops may produce different initial output voltages due to different parasitic capacitances under different process conditions and objectively existing process fluctuations, which may lead to subsequent circuit malfunctions.
[0005] To achieve the above objectives, the present invention adopts the following technical solution:
[0006] A D-type edge-triggered flip-flop that follows CLK in its initial power-on state is characterized by comprising a POR module, an initial state control module, a clock control module, and a flip-flop module, wherein the flip-flop module comprises an input unit, a front loop latch unit, a rear loop latch unit, and an output unit.
[0007] The POR module outputs a power-on signal enH to the initial state control module, and a clock signal CLK is input to the clock control module. The clock control module outputs an inverted clock signal clka and a non-inverted clock signal clkb to the initial state control module, as well as the transmission gates of the front loop latch unit and the rear loop latch unit. The initial state control module outputs control signals rst and perst to the NAND gates of the front loop latch unit and the rear loop latch unit.
[0008] The input signal D is input to the input unit, which is electrically connected to the front loop latch unit, which is electrically connected to the rear loop latch unit, which is electrically connected to the output unit, and the output unit outputs the drive control signal Q.
[0009] Furthermore, the POR module includes MOSFETs P21, N21, P20, N20, P19, N19, P18, N18, P29, N29 and capacitor C0;
[0010] External power supply VDD is input to the source of MOSFET P21, the source of MOSFET P20, the source of MOSFET P19, the source of MOSFET P18, and the source of MOSFET P29.
[0011] The gate of MOSFET P21 is electrically connected to the drain and gate of MOSFET N21. The drain of MOSFET P21 is electrically connected to one end of capacitor C0, the gate of MOSFET P20, and the gate of MOSFET N20. The drains of MOSFET P20 and MOSFET N20 are both electrically connected to the gates of MOSFET P19 and MOSFET N18. The drains of MOSFET P19 and MOSFET N18 are both electrically connected to the gates of MOSFET P18 and MOSFET N19. The drains of MOSFET P18 and MOSFET N19 are both electrically connected to the gates of MOSFET P29 and MOSFET N29. The drains of MOSFET P29 and MOSFET N29 serve as output terminals, outputting a power-on signal enH to the initial state control module.
[0012] The source terminals of MOSFET N21, MOSFET N20, MOSFET N18, MOSFET N19, and MOSFET N29, as well as the other end of capacitor C0, are all grounded.
[0013] Furthermore, the clock control module includes MOSFET P13, MOSFET N13, MOSFET P12 and MOSFET N12;
[0014] External power supply VDD is input to the source of MOSFET P13 and the source of MOSFET P12;
[0015] The clock signal CLK is input to the gates of MOSFET P13 and N13. The drains of MOSFET P13 and N13 are electrically connected to the gates of MOSFET P12 and N12, respectively, and output an inverted clock signal clka to the initial state control module, the transmission gates of the front loop latch unit, and the transmission gates of the rear loop latch unit. The drains of MOSFET P12 and N12 output a non-inverted clock signal clkb to the initial state control module, the transmission gates of the front loop latch unit, and the transmission gates of the rear loop latch unit.
[0016] The sources of both MOS transistor N13 and MOS transistor N12 are grounded.
[0017] Furthermore, the initial state control module includes MOSFETs P23, N23, P22, N22, P24, N24, N25, P25, P28, and N28.
[0018] An external power supply VDD is input to the sources of MOSFETs P23, P24, P25, and P28; the POR module outputs a power-on signal enH to the gates of MOSFETs P23, N23, P25, and N25; the clock control module outputs an inverted clock signal clka to the gates of MOSFETs P24 and N24; and the clock control module outputs a non-inverted clock signal clkb to the gates of MOSFETs P22 and N22.
[0019] The source of MOS transistor N23 is electrically connected to the drain of MOS transistor N22. The drains of MOS transistor P23 and N23 are both electrically connected to the drain of MOS transistor P22, and the control signal perst is output to the NAND gate of the front loop latch unit and the NAND gate of the rear loop latch unit.
[0020] The source of MOSFET N24 is electrically connected to the drain of MOSFET N25; the drains of MOSFET P24 and MOSFET N24 are both electrically connected to the drains of MOSFET P25, the gates of MOSFET P28 and MOSFET N28; the drains of MOSFET P28 and MOSFET N28 serve as output terminals to output control signals rst to the NAND gates of the front loop latch unit and the rear loop latch unit.
[0021] The sources of MOS transistors N22, N25, and N28 are all grounded.
[0022] The initial state control module also includes a CLR input unit, which is electrically connected to the stage before the output of the control signal rst.
[0023] Furthermore, the CLR input unit includes MOSFET P27, MOSFET N27, MOSFET P26 and MOSFET N26;
[0024] External power supply VDD is input to the source of MOSFET P27 and the source of MOSFET P26; clear signal CLR is input to the gate of MOSFET N26 and the gate of MOSFET P26.
[0025] The drains of MOSFET P24 and N24 are electrically connected to the drains of MOSFET P25, the gates of MOSFET P27 and N27, respectively. The source of MOSFET N27 is electrically connected to the drain of MOSFET N26. The drains of MOSFET P27 and N27 are electrically connected to the drains of MOSFET P26, the gates of MOSFET P28 and N28, respectively.
[0026] The source of the MOS transistor N26 is grounded.
[0027] Furthermore, the input unit includes MOS transistor P14 and MOS transistor N14;
[0028] An external power supply VDD is input to the source of MOSFET P14; the input signal D is input to the gate of MOSFET P14 and the gate of MOSFET N14; the drain of MOSFET P14 and the drain of MOSFET N14 are electrically connected to the front loop latch unit as output terminals.
[0029] The source of the MOS transistor N14 is grounded.
[0030] Furthermore, the front loop latch unit includes MOS transistors P9, N9, P6, N6, P8, P7, N7, N8, P11, P10, N11, and N10.
[0031] An external power supply VDD is input to the source of MOSFETs P11, P10, P8, and P7; the inverted clock signal clka is input to the gate of MOSFET N9 and P6; the non-inverted clock signal clkb is input to the gate of MOSFET P9 and N6; the control signal rst is input to the gate of MOSFET P8 and N8; and the control signal perst is input to the gate of MOSFET P10 and N10.
[0032] The output terminal of the input unit is electrically connected to the drain of MOSFET P9 and the drain of MOSFET N9. The source of MOSFET P9 and the source of MOSFET N9 are both electrically connected to the gate of MOSFET P11, the gate of MOSFET N11, the drain of MOSFET P6, and the drain of MOSFET N6. The source of MOSFET N11 is electrically connected to the drain of MOSFET N10. The source of MOSFET P6 and the source of MOSFET N6 are both electrically connected to the drain of MOSFET P7, the drain of MOSFET N7, and the drain of MOSFET P8. The source of MOSFET N7 is electrically connected to the drain of MOSFET N8. The gate of MOSFET P7, the gate of MOSFET N7, the drain of MOSFET P11, the drain of MOSFET N11, and the drain of MOSFET P10 are all connected as output terminals to the rear loop latch unit.
[0033] The sources of both MOS transistor N10 and MOS transistor N8 are grounded.
[0034] Furthermore, the rear loop latch unit includes MOS transistors P5, N5, P4, N4, P0, P1, N0, N1, P2, P3, N2, and N3.
[0035] An external power supply VDD is input to the source of MOSFET P0, the source of MOSFET P1, the source of MOSFET P2, and the source of MOSFET P3; the inverted clock signal clka is input to the gate of MOSFET N4 and the gate of MOSFET P5; the non-inverted clock signal clkb is input to the gate of MOSFET P4 and the gate of MOSFET N5; the control signal rst is input to the gate of MOSFET P1 and the gate of MOSFET N1; and the control signal perst is input to the gate of MOSFET P2 and the gate of MOSFET N2.
[0036] The output terminal of the front loop latch unit is electrically connected to the drain of MOSFET P5 and the drain of MOSFET N5. The source of MOSFET P5 and the source of MOSFET N5 are both electrically connected to the gate of MOSFET P0, the gate of MOSFET N0, the drain of MOSFET P4, and the drain of MOSFET N4. The source of MOSFET N0 is electrically connected to the drain of MOSFET N1. The source of MOSFET P4 and the source of MOSFET N4 are both electrically connected to the drain of MOSFET P3, the drain of MOSFET N3, and the drain of MOSFET P2. The source of MOSFET N3 is electrically connected to the drain of MOSFET N2. The gate of MOSFET P3, the gate of MOSFET N3, the drain of MOSFET P0, the drain of MOSFET N0, and the drain of MOSFET P1 are all connected to the output unit as output terminals.
[0037] The sources of both MOS transistor N1 and MOS transistor N2 are grounded.
[0038] Furthermore, the output unit includes MOS transistor P15 and MOS transistor N15;
[0039] An external power supply VDD is input to the source of MOSFET P15; the output terminal of the rear loop latch unit is electrically connected to the gate of MOSFET P15 and the gate of MOSFET N15; the drain of MOSFET P15 and the drain of MOSFET N15 serve as output terminals to output the drive control signal Q; the source of MOSFET N15 is grounded.
[0040] By adopting the above technical solution, the present invention has the following advantages compared with the prior art:
[0041] The POR module controls the power-on signal enH to flip, controls the trigger to power-on reset, and the clock control module outputs the inverted clock signal clka and the in-phase clock signal clkb to the initial state control module. It controls the high and low levels of the control signals rst and perst to ensure that the control signal rst is in phase with the clock signal CLK. It also controls the on / off state of the transmission gates of the front loop latch unit and the rear loop latch unit through the inverted clock signal clka, the in-phase clock signal clkb, the control signal rst, and the control signal perst. The NAND gate is used to ensure that the control signal Q in the initial state is in phase with the clock signal CLK. Attached Figure Description
[0042] Figure 1 The simulation diagram is of an existing D-type edge-triggered flip-flop;
[0043] Figure 2 This is a circuit diagram of the POR module and initial state control module of the D-type edge-triggered flip-flop that follows CLK in the power-on initial state according to the present invention.
[0044] Figure 3 This is a circuit diagram of the clock control module of the D-type edge-triggered flip-flop that follows CLK in the initial power-on state as described in this invention;
[0045] Figure 4 This is a circuit diagram of the trigger module of the D-type edge-triggered trigger that follows CLK in the initial power-on state according to the present invention;
[0046] Figure 5 This is a simulation diagram of the D-type edge-triggered flip-flop with the initial state following CLK as described in this invention, under the condition that the clock signal CLK is high in the initial state and the clear signal CLR is high in the initial state.
[0047] Figure 6 This is a simulation diagram of the D-type edge-triggered flip-flop with the initial state following CLK as described in this invention, under the condition that the initial state of the clock signal CLK is low and the initial state of the clear signal CLR is high.
[0048] Figure 7 This is a simulation diagram of the D-type edge-triggered flip-flop with the initial state following CLK as described in this invention, under the condition that the clock signal CLK is high in the initial state and the clear signal CLR is low in the initial state.
[0049] Figure 8 This is a simulation diagram of the D-type edge-triggered flip-flop described in this invention, whose initial state follows CLK, under the condition that the clock signal CLK is low and the initial state of the clear signal CLR is low.
[0050] Explanation of reference numerals in the attached figures:
[0051] 1. POR module; 2. Initial state control module; 3. Clock control module; 4. Trigger module; 41. Input unit; 42. Front loop latch unit; 43. Rear loop latch unit; 44. Output unit. Detailed Implementation
[0052] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.
[0053] Additionally, it should be noted that the terms "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer" are all based on the orientation or positional relationship shown in the accompanying drawings. They are merely for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element of the present invention must have a specific orientation. Therefore, they should not be construed as limitations on the present invention.
[0054] When an element is referred to as being "fixed to," "set on," or "contained on" another element, it can be directly on or indirectly on that other element. When an element is referred to as being "connected to," it can be directly connected to or indirectly connected to that other element.
[0055] Unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication between two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances. Example
[0056] Please refer to Figure 2-8 As shown, this embodiment provides a D-type edge-triggered flip-flop with an initial state following CLK, including a POR module 1, an initial state control module 2, a clock control module 3, and a flip-flop module 4. The flip-flop module 4 includes an input unit 41, a front-loop latch unit 42, a rear-loop latch unit 43, and an output unit 44. The output of the POR module 1 outputs a power-on signal enH to the initial state control module 2; the clock signal CLK is input to the clock control module 3; the clock control module 3 outputs an inverted clock signal clka and a non-inverted clock signal clkb to the initial state control module 2, as well as the transmission gates of the front-loop latch unit 42 and the rear-loop latch unit 43. The initial state control module 2 outputs control signals rst and perst to the NAND gates of the front-loop latch unit 42 and the rear-loop latch unit 43. The input signal D is input to the input unit 41. The input unit 41 is electrically connected to the front loop latch unit 42. The front loop latch unit 42 is electrically connected to the rear loop latch unit 43. The rear loop latch unit 43 is electrically connected to the output unit 44. The output unit 44 outputs the drive control signal Q.
[0057] POR module 1 controls the power-on signal enH to flip, controls the trigger to power-on reset, and clock control module 3 outputs inverted clock signal clka and non-inverted clock signal clkb to initial state control module 2 to control the high and low levels of control signals rst and perst to ensure that control signal rst is in phase with clock signal CLK; and controls the on / off state of transmission gates of front loop latch unit 42 and rear loop latch unit 43 through inverted clock signal clka, non-inverted clock signal clkb, control signal rst and control signal perst, using NAND gates to ensure that control signal Q in the initial state is in phase with clock signal CLK.
[0058] Please refer to Figure 2 As shown, specifically, POR module 1 includes MOSFETs P21, N21, P20, N20, P19, N19, P18, N18, P29, N29 and capacitor C0.
[0059] External power supply VDD is input to the source of MOSFET P21, the source of MOSFET P20, the source of MOSFET P19, the source of MOSFET P18, and the source of MOSFET P29.
[0060] The gate of MOSFET P21 is electrically connected to the drain and gate of MOSFET N21. The drain of MOSFET P21 is electrically connected to one end of capacitor C0, the gate of MOSFET P20, and the gate of MOSFET N20. The drains of MOSFET P20 and MOSFET N20 are both electrically connected to the gates of MOSFET P19 and MOSFET N18. The drains of MOSFET P19 and MOSFET N18 are both electrically connected to the gates of MOSFET P18 and MOSFET N19. The drains of MOSFET P18 and MOSFET N19 are both electrically connected to the gates of MOSFET P29 and MOSFET N29. The drains of MOSFET P29 and MOSFET N29 serve as output terminals, outputting the power-on signal enH to the initial state control module 2.
[0061] The sources of MOSFET N21, MOSFET N20, MOSFET N18, MOSFET N19, and MOSFET N29, as well as the other end of capacitor C0, are all grounded.
[0062] In this embodiment, MOSFET P21 is a PMOS transistor with a small aspect ratio, a large Ron, and a large gate-source capacitance. The charging circuit formed by MOSFET P21 and the large-capacitance capacitor C0 has a large time constant, resulting in a longer power-on reset time. This ensures effective reset even with a relatively slow VDD power-on speed. The specific aspect ratio of MOSFET P21 can be set according to the required time constant. When the power supply VDD is powered on, the gate of MOSFET P21 rises accordingly. Initially, MOSFET P21 is off, and the voltage across the large-capacitance capacitor C0 is 0. Therefore, the power-on signal enH output by POR module 1 is high. The gate of MOSFET P21 discharges charge through MOSFET N21, the voltage drops, and MOSFET P21 turns on. The power supply VDD charges capacitor C0 through MOSFET P21 until the voltage across capacitor C0 reaches the flip-flop level of the inverter formed by MOSFETs P20 and N20. The flip-flop signal is then shaped by another inverter formed by MOSFETs P19 and N18, and finally, the output power-on signal enH flips to a low level. The time it takes for capacitor C0 to charge to the flip-flop level is the power-on reset time.
[0063] Please refer to Figure 3 As shown, specifically, the clock control module 3 includes MOSFETs P13, N13, P12, and N12. An external power supply VDD is input to the source of MOSFET P13 and the source of MOSFET P12. A clock signal CLK is input to the gate of MOSFET P13 and the gate of MOSFET N13. The drains of MOSFETs P13 and N13 are electrically connected to the gates of MOSFETs P12 and N12, respectively, and output an inverted clock signal clka to the initial state control module 2, the transmission gate of the front loop latch unit 42, and the transmission gate of the rear loop latch unit 43. The drains of MOSFETs P12 and N12 output a non-inverted clock signal clkb to the initial state control module 2, the transmission gate of the front loop latch unit 42, and the transmission gate of the rear loop latch unit 43. The sources of MOSFETs N13 and N12 are both grounded. The in-phase signal does not directly use the clock signal CLK, which effectively reduces the capacitive load of the input CLK bus and reduces signal delay.
[0064] Please refer to Figure 2 As shown, specifically, the initial state control module 2 includes MOSFETs P23, N23, P22, N22, P24, N24, N25, P25, P28, and N28.
[0065] An external power supply VDD is input to the sources of MOSFETs P23, P24, P25, and P28. The output of POR module 1 outputs a power-on signal enH to the gates of MOSFETs P23, N23, P25, and N25. This means the drains of MOSFETs P29 and N29 are electrically connected to the gates of MOSFETs P23, N23, P25, and N24. Clock control module 3 outputs an inverted clock signal clka to the gates of MOSFETs P24 and N24. This means the drains of MOSFETs P13 and N13 are electrically connected to the gates of MOSFETs P24 and N24. The clock control module 3 outputs an in-phase clock signal clkb to the gate of MOSFET P22 and the gate of MOSFET N22. That is, the drain of MOSFET P12 and the drain of MOSFET N12 are electrically connected to the gate of MOSFET P22 and the gate of MOSFET N23.
[0066] The source of MOSFET N23 is electrically connected to the drain of MOSFET N22. The drains of MOSFET P23 and MOSFET N23 are both electrically connected to the drain of MOSFET P22. The control signal perst is output to the NAND gate of the front loop latch unit 42 and the NAND gate of the rear loop latch unit 43.
[0067] The source of MOSFET N24 is electrically connected to the drain of MOSFET N25; the drains of MOSFET P24 and MOSFET N24 are both electrically connected to the drains of MOSFET P25, the gates of MOSFET P28 and MOSFET N28; the drains of MOSFET P28 and MOSFET N28 serve as output terminals to output control signal rst to the NAND gate of the front loop latch unit 42 and the NAND gate of the rear loop latch unit 43.
[0068] The sources of MOSFET N22, MOSFET N25, and MOSFET N28 are all grounded.
[0069] Furthermore, the initial state control module 2 also includes a CLR input unit, which is electrically connected to the stage before the output of the control signal rst. Specifically, the CLR input unit includes MOSFETs P27, N27, P26, and N26.
[0070] External power supply VDD is input to the source of MOSFET P27 and the source of MOSFET P26; the clear signal CLR is input to the gate of MOSFET N26 and the gate of MOSFET P26. The drains of MOSFET P24 and N24 are electrically connected to the drain of MOSFET P25, the gate of MOSFET P27, and the gate of MOSFET N27. The source of MOSFET N27 is electrically connected to the drain of MOSFET N26. The drains of MOSFET P27 and N27 are electrically connected to the drain of MOSFET P26, the gate of MOSFET P28, and the gate of MOSFET N28. The source of MOSFET N26 is grounded.
[0071] MOSFETs P23, P22, N22, and N23 form a NAND gate; MOSFETs P24, P25, N24, and N25 form a NAND gate; MOSFETs P26, P27, N26, and N27 form a NAND gate; and MOSFETs P28 and N28 form an inverter. During the power-on phase when the enH signal is high, when the clock signal CLK is low, the inverted clock signal clka is high, the non-inverted clock signal clkb is low, the control signal rst is low, and the control signal perst is high. When the clock signal CLK is high, the inverted clock signal clka is low, the non-inverted clock signal clkb is high, the control signal rst is high, and the control signal perst is low.
[0072] Please refer to Figure 4 As shown, specifically, input unit 41 includes MOSFET P14 and MOSFET N14. External power supply VDD is input to the source of MOSFET P14. Input signal D is input to the gate of MOSFET P14 and the gate of MOSFET N14; the drain of MOSFET P14 and the drain of MOSFET N14 are electrically connected to the front loop latch unit 42 as output terminals; the source of MOSFET N14 is grounded.
[0073] Furthermore, the front loop latch unit 42 includes MOSFETs P9, N9, P6, N6, P8, P7, N7, N8, P11, P10, N11, and N10. An external power supply VDD is input to the source of MOSFETs P11, P10, P8, and P7.
[0074] The inverting clock signal clka is input to the gates of MOSFET N9 and P6, meaning the drains of MOSFET P13 and N13 are electrically connected to the gates of MOSFET N9 and P6. The non-inverting clock signal clkb is input to the gates of MOSFET P9 and N6, meaning the drains of MOSFET P12 and N12 are electrically connected to the gates of MOSFET P9 and N6. The control signal rst is input to the gates of MOSFET P8 and N8, meaning the drains of MOSFET P28 and N28 are electrically connected to the gates of MOSFET P8 and N8. The control signal perst is input to the gates of MOSFET P10 and N10, meaning the drains of MOSFET P23 and N23 are electrically connected to the gates of MOSFET P10 and N10.
[0075] The output terminal of input unit 41 is electrically connected to the drain of MOSFET P9 and the drain of MOSFET N9, that is, the drains of MOSFET P14 and MOSFET N14 are electrically connected to the drains of MOSFET P9 and MOSFET N9. The source of MOSFET P9 and the source of MOSFET N9 are both electrically connected to the gate of MOSFET P11, the gate of MOSFET N11, the drain of MOSFET P6, and the drain of MOSFET N6. The source of MOSFET N11 is electrically connected to the drain of MOSFET N10. The source of MOSFET P6 and the source of MOSFET N6 are both electrically connected to the drains of MOSFET P7, MOSFET N7, and MOSFET P8. The source of MOSFET N7 is electrically connected to the drain of MOSFET N8. The gates of MOSFET P7 and N7, the drains of MOSFET P11 and N11, and the drain of MOSFET P10 are all connected to the rear loop latch unit 43 as output terminals. The sources of MOSFET N10 and N8 are both grounded.
[0076] Furthermore, the rear loop latch unit 43 includes MOSFETs P5, N5, P4, N4, P0, P1, N0, N1, P2, P3, N2, and N3.
[0077] An external power supply VDD is input to the sources of MOSFETs P0, P1, P2, and P3. An inverting clock signal clka is input to the gates of MOSFETs N4 and P5, meaning the drains of MOSFETs P13 and N13 are electrically connected to the gates of MOSFETs N4 and P5. A non-inverting clock signal clkb is input to the gates of MOSFETs P4 and N5, and the drains of MOSFETs P12 and N12 are electrically connected to the gates of MOSFETs P4 and N5. A control signal rst is input to the gates of MOSFETs P1 and N1, and the drains of MOSFETs P28 and N28 are electrically connected to the gates of MOSFETs P1 and N1. The control signal perst is input to the gate of MOSFET P2 and the gate of MOSFET N2. The drain of MOSFET P23 and the drain of MOSFET N23 are electrically connected to the gate of MOSFET P2 and the gate of MOSFET N2.
[0078] The output of the front loop latch unit 42 is electrically connected to the drain of MOSFET P5 and the drain of MOSFET N5. Specifically, the gates of MOSFET P7, N7, P11, N11, and P10 are all electrically connected to the drains of MOSFET P5 and N5. The sources of MOSFET P5 and N5 are electrically connected to the gates of MOSFET P0, N0, P4, and N4. The source of MOSFET N0 is electrically connected to the drain of MOSFET N1. The sources of MOSFET P4 and N4 are electrically connected to the drains of MOSFET P3, N3, and P2. The source of MOSFET N3 is electrically connected to the drain of MOSFET N2. The gates of MOSFET P3 and N3, the drains of MOSFET P0 and N0, and the drain of MOSFET P1 are all electrically connected to the output unit 44 as output terminals. The sources of MOSFET N1 and N2 are both grounded.
[0079] Furthermore, the output unit 44 includes MOSFETs P15 and N15. An external power supply VDD is input to the source of MOSFET P15. The output terminal of the rear loop latch unit 43 is electrically connected to the gates of MOSFETs P15 and N15; that is, the gates of MOSFETs P3 and N3, the drains of MOSFETs P0 and N0, and the drain of MOSFET P1 are all electrically connected to the gates of MOSFETs P15 and N15. The drains of MOSFETs P15 and N15 serve as output terminals to output the drive control signal Q; the source of MOSFET N15 is grounded.
[0080] The control signals rst and perst are connected to the front and rear loops of the flip-flop module 4 through NAND gates, simultaneously controlling the reset bit position.
[0081] When the clock CLK is low, the transmission gate formed by MOSFETs P5 and N5 is off, and the transmission gate formed by MOSFETs P4 and N4 is on. MOSFETs P0, P1, N0, and N1 form a NAND gate, and MOSFETs P2, P3, N2, and N3 form another NAND gate. When the control signal rst is low and the control signal perst is high, the drive control signal Q outputs a low level.
[0082] When the clock CLK is high, the transmission gate composed of MOSFETs P5 and N5 is turned on, the transmission gate composed of MOSFETs P4 and N4 is turned off, the transmission gate composed of MOSFETs P6 and N6 is turned on, and the transmission gate composed of MOSFETs P9 and N9 is turned off. MOSFETs P7, P8, N7, and N8 form a NAND gate; MOSFETs P10, P11, N10, and N11 form a NAND gate. When the control signal rst is high and the control signal perst is low, the drive control signal Q outputs a high level. In summary, the D-type edge-triggered flip-flop disclosed in this embodiment effectively ensures that, in the initial state, the clock signal CLK can be correctly controlled regardless of its level, so that the high and low levels of the drive control signal Q follow the clock signal CLK.
[0083] Please refer to the appendix. Figure 5-8 , including Figure 5 The simulation diagram is shown below, with the clock signal CLK initially high and the clear signal CLR initially high. Figure 5 As can be seen, the trigger disclosed in this embodiment is triggered on the rising edge of the clock signal CLK, and the control signal Q is cleared to a low level when the clear signal CLR is low. (The attached text is incomplete and requires further context.) Figure 6The simulation diagram is shown below, with the clock signal CLK initially low and the clear signal CLR initially high. Figure 6 As can be seen, the trigger disclosed in this embodiment is triggered on the rising edge of the clock signal CLK, and the control signal Q is cleared to a low level when the clear signal CLR is low. (The attached text is incomplete and requires further context.) Figure 7 The simulation diagram is shown below, with the clock signal CLK initially high and the clear signal CLR initially low. Figure 7 As can be seen, the control signal Q of the trigger disclosed in this embodiment is cleared to a low level and triggered on the rising edge of the clock signal CLK. (The attached text is incomplete and cannot be translated.) Figure 8 The simulation diagram is shown below, with the clock signal CLK initially low and the clear signal CLR initially low. Figure 7 As can be seen, the control signal Q of the trigger disclosed in this embodiment is cleared to a low level and triggered on the rising edge of the clock signal CLK.
[0084] The above description is merely a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.
Claims
1. A D-type edge-triggered flip-flop that follows CLK in its initial power-on state, characterized in that, It includes a POR module, an initial state control module, a clock control module, and a trigger module. The trigger module includes an input unit, a front loop latch unit, a rear loop latch unit, and an output unit. The POR module outputs a power-on signal enH to the initial state control module, and a clock signal CLK is input to the clock control module. The clock control module outputs an inverted clock signal clka and a non-inverted clock signal clkb to the initial state control module, as well as the transmission gates of the front loop latch unit and the rear loop latch unit. The initial state control module outputs control signals rst and perst to the NAND gates of the front loop latch unit and the rear loop latch unit. The input signal D is input to the input unit, which is electrically connected to the front loop latch unit, which is electrically connected to the rear loop latch unit, which is electrically connected to the output unit, and the output unit outputs the drive control signal Q. The initial state control module includes MOSFETs P23, N23, P22, N22, P24, N24, N25, P25, P28, and N28. An external power supply VDD is input to the sources of MOSFETs P22, P23, P24, P25, and P28; the POR module outputs a power-on signal enH to the gates of MOSFETs P23, N23, P25, and N25; the clock control module outputs an inverted clock signal clka to the gates of MOSFETs P24 and N24; and the clock control module outputs a non-inverted clock signal clkb to the gates of MOSFETs P22 and N22. The source of MOS transistor N23 is electrically connected to the drain of MOS transistor N22. The drains of MOS transistor P23 and N23 are both electrically connected to the drain of MOS transistor P22, and the control signal perst is output to the NAND gate of the front loop latch unit and the NAND gate of the rear loop latch unit. The source of MOSFET N24 is electrically connected to the drain of MOSFET N25; the drains of MOSFET P24 and MOSFET N24 are both electrically connected to the drains of MOSFET P25, the gates of MOSFET P28 and MOSFET N28; the drains of MOSFET P28 and MOSFET N28 serve as output terminals to output control signals rst to the NAND gates of the front loop latch unit and the rear loop latch unit. The sources of MOS transistors N22, N25, and N28 are all grounded. The initial state control module also includes a CLR input unit, which is electrically connected to the stage before the output of the control signal rst.
2. The D-type edge-triggered flip-flop that follows CLK in its initial power-on state according to claim 1, characterized in that: The POR module includes MOSFETs P21, N21, P20, N20, P19, N19, P18, N18, P29, N29 and capacitor C0. External power supply VDD is input to the source of MOSFET P21, the source of MOSFET P20, the source of MOSFET P19, the source of MOSFET P18, and the source of MOSFET P29. The gate of MOSFET P21 is electrically connected to the drain and gate of MOSFET N21. The drain of MOSFET P21 is electrically connected to one end of capacitor C0, the gate of MOSFET P20, and the gate of MOSFET N20. The drains of MOSFET P20 and MOSFET N20 are both electrically connected to the gates of MOSFET P19 and MOSFET N18. The drains of MOSFET P19 and MOSFET N18 are both electrically connected to the gates of MOSFET P18 and MOSFET N19. The drains of MOSFET P18 and MOSFET N19 are both electrically connected to the gates of MOSFET P29 and MOSFET N29. The drains of MOSFET P29 and MOSFET N29 serve as output terminals, outputting a power-on signal enH to the initial state control module. The source terminals of MOSFET N21, MOSFET N20, MOSFET N18, MOSFET N19, and MOSFET N29, as well as the other end of capacitor C0, are all grounded.
3. The D-type edge-triggered trigger that follows CLK in its initial power-on state according to claim 1, characterized in that: The clock control module includes MOSFET P13, MOSFET N13, MOSFET P12 and MOSFET N12; External power supply VDD is input to the source of MOSFET P13 and the source of MOSFET P12; The clock signal CLK is input to the gates of MOSFET P13 and N13. The drains of MOSFET P13 and N13 are electrically connected to the gates of MOSFET P12 and N12, respectively, and output an inverted clock signal clka to the initial state control module, the transmission gates of the front loop latch unit, and the transmission gates of the rear loop latch unit. The drains of MOSFET P12 and N12 output a non-inverted clock signal clkb to the initial state control module, the transmission gates of the front loop latch unit, and the transmission gates of the rear loop latch unit. The sources of both MOS transistor N13 and MOS transistor N12 are grounded.
4. The D-type edge-triggered flip-flop that follows CLK in its initial power-on state according to claim 1, characterized in that: The CLR input unit includes MOSFET P27, MOSFET N27, MOSFET P26 and MOSFET N26; External power supply VDD is input to the source of MOSFET P27 and the source of MOSFET P26; clear signal CLR is input to the gate of MOSFET N26 and the gate of MOSFET P26. The drains of MOSFET P24 and N24 are electrically connected to the drains of MOSFET P25, the gates of MOSFET P27 and N27, respectively. The source of MOSFET N27 is electrically connected to the drain of MOSFET N26. The drains of MOSFET P27 and N27 are electrically connected to the drains of MOSFET P26, the gates of MOSFET P28 and N28, respectively. The source of the MOS transistor N26 is grounded.
5. The D-type edge-triggered flip-flop that follows CLK in its initial power-on state according to claim 1, characterized in that: The input unit includes MOS transistor P14 and MOS transistor N14; An external power supply VDD is input to the source of MOSFET P14; the input signal D is input to the gate of MOSFET P14 and the gate of MOSFET N14; the drain of MOSFET P14 and the drain of MOSFET N14 are electrically connected to the front loop latch unit as output terminals. The source of the MOS transistor N14 is grounded.
6. The D-type edge-triggered flip-flop that follows CLK in its initial power-on state according to claim 1, characterized in that: The front loop latch unit includes MOSFETs P9, N9, P6, N6, P8, P7, N7, N8, P11, P10, N11, and N10. External power supply VDD is input to the source of MOSFET P11, the source of MOSFET P10, the source of MOSFET P8, and the source of MOSFET P7. The inverted clock signal clka is input to the gate of MOSFET N9 and the gate of MOSFET P6; the non-inverted clock signal clkb is input to the gate of MOSFET P9 and the gate of MOSFET N6; the control signal rst is input to the gate of MOSFET P8 and the gate of MOSFET N8; the control signal perst is input to the gate of MOSFET P10 and the gate of MOSFET N10. The output terminal of the input unit is electrically connected to the drain of MOSFET P9 and the drain of MOSFET N9. The source of MOSFET P9 and the source of MOSFET N9 are both electrically connected to the gate of MOSFET P11, the gate of MOSFET N11, the drain of MOSFET P6, and the drain of MOSFET N6. The source of MOSFET N11 is electrically connected to the drain of MOSFET N10. The source of MOSFET P6 and the source of MOSFET N6 are both electrically connected to the drain of MOSFET P7, the drain of MOSFET N7, and the drain of MOSFET P8. The source of MOSFET N7 is electrically connected to the drain of MOSFET N8. The gate of MOSFET P7, the gate of MOSFET N7, the drain of MOSFET P11, the drain of MOSFET N11, and the drain of MOSFET P10 are all connected as output terminals to the rear loop latch unit. The sources of both MOS transistor N10 and MOS transistor N8 are grounded.
7. The D-type edge-triggered flip-flop that follows CLK in its initial power-on state according to claim 1, characterized in that: The rear loop latch unit includes MOSFETs P5, N5, P4, N4, P0, P1, N0, N1, P2, P3, N2, and N3. External power supply VDD is input to the source of MOSFET P0, the source of MOSFET P1, the source of MOSFET P2 and the source of MOSFET P3; The inverted clock signal clka is input to the gate of MOSFET N4 and the gate of MOSFET P5; the non-inverted clock signal clkb is input to the gate of MOSFET P4 and the gate of MOSFET N5; the control signal rst is input to the gate of MOSFET P1 and the gate of MOSFET N1; the control signal perst is input to the gate of MOSFET P2 and the gate of MOSFET N2. The output terminal of the front loop latch unit is electrically connected to the drain of MOSFET P5 and the drain of MOSFET N5. The source of MOSFET P5 and the source of MOSFET N5 are both electrically connected to the gate of MOSFET P0, the gate of MOSFET N0, the drain of MOSFET P4, and the drain of MOSFET N4. The source of MOSFET N0 is electrically connected to the drain of MOSFET N1. The source of MOSFET P4 and the source of MOSFET N4 are both electrically connected to the drain of MOSFET P3, the drain of MOSFET N3, and the drain of MOSFET P2. The source of MOSFET N3 is electrically connected to the drain of MOSFET N2. The gate of MOSFET P3, the gate of MOSFET N3, the drain of MOSFET P0, the drain of MOSFET N0, and the drain of MOSFET P1 are all connected to the output unit as output terminals. The sources of both MOS transistor N1 and MOS transistor N2 are grounded.
8. The D-type edge-triggered flip-flop that follows CLK in its initial power-on state according to claim 1, characterized in that: The output unit includes MOS transistor P15 and MOS transistor N15; An external power supply VDD is input to the source of MOSFET P15; the output terminal of the rear loop latch unit is electrically connected to the gate of MOSFET P15 and the gate of MOSFET N15; the drain of MOSFET P15 and the drain of MOSFET N15 serve as output terminals to output the drive control signal Q. The source of the MOS transistor N15 is grounded.