5g resource allocation techniques

Abstract

Apparatuses, systems, and techniques for selecting a set of devices to utilize a frequency band. In at least one embodiment, multiple groups are generated in parallel and one of the selected groups is selected to utilize the frequency band.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to U.S. Patent Application No. 16 / 669,402, filed October 30, 2019, entitled “5G RESOURCEASSIGNMENT TECHNIQUE,” the entire contents of which are incorporated herein by reference and used for all purposes. Technical Field

[0003] At least one embodiment relates to a technique for allocating multiple communication devices to frequency bands used for synchronous data transmission. Background Technology

[0004] Wireless communication devices can transmit data directly to multiple receiving devices. The determination of operating parameters for such transmissions can be improved. Attached Figure Description

[0005] Various techniques will be described with reference to the accompanying drawings, in which:

[0006] Figure 1 An example system for performing frequency resource allocation according to at least one embodiment is shown;

[0007] Figure 2 An example of frequency resource allocation according to at least one embodiment is shown;

[0008] Figure 3 Example techniques for performing frequency resource allocation according to at least one embodiment are shown;

[0009] Figure 4 An example parallel computing system for performing frequency resource allocation according to at least one embodiment is shown;

[0010] Figure 5 An example of a heuristic algorithm for generating candidate groups according to at least one embodiment is shown;

[0011] Figure 6 An example system for performing MU-MIMO transmission according to at least one embodiment is shown;

[0012] Figure 7 An example system for selecting a group of devices to utilize a frequency band, according to at least one embodiment, is shown;

[0013] Figure 8 An example data center system according to at least one embodiment is shown;

[0014] Figure 9A An example of an autonomous vehicle according to at least one embodiment is shown;

[0015] Figure 9B The illustration shows an embodiment according to at least one of the embodiments. Figure 9A Examples of camera positions and field of view for autonomous vehicles;

[0016] Figure 9C This illustrates at least one embodiment. Figure 9A A block diagram of an example system architecture for an autonomous vehicle;

[0017] Figure 9D This illustrates a method for using one or more cloud-based servers according to at least one embodiment. Figure 9A A diagram of a system for communication between autonomous vehicles;

[0018] Figure 10 This is a block diagram illustrating a computer system according to at least one embodiment;

[0019] Figure 11 This is a block diagram illustrating a computer system according to at least one embodiment;

[0020] Figure 12 A computer system according to at least one embodiment is shown;

[0021] Figure 13 A computer system according to at least one embodiment is shown;

[0022] Figure 14A A computer system according to at least one embodiment is shown;

[0023] Figure 14B A computer system according to at least one embodiment is shown;

[0024] Figure 14C A computer system according to at least one embodiment is shown;

[0025] Figure 14D A computer system according to at least one embodiment is shown;

[0026] Figure 14E and Figure 14F A shared programming model according to at least one embodiment is shown;

[0027] Figure 15 An exemplary integrated circuit and a related graphics processor according to at least one embodiment are shown;

[0028] Figure 16A and Figure 16B An exemplary integrated circuit and an associated graphics processor according to at least one embodiment are shown;

[0029] Figure 17A and Figure 17BAdditional exemplary graphics processor logic according to at least one embodiment is shown;

[0030] Figure 18 A computer system according to at least one embodiment is shown;

[0031] Figure 19A A parallel processor according to at least one embodiment is shown;

[0032] Figure 19B A partitioning unit according to at least one embodiment is shown;

[0033] Figure 19C A processing cluster according to at least one embodiment is shown;

[0034] Figure 19D A graphics multiprocessor according to at least one embodiment is shown;

[0035] Figure 20 A multi-graphics processing unit (GPU) system according to at least one embodiment is illustrated;

[0036] Figure 21 A graphics processor according to at least one embodiment is shown;

[0037] Figure 22 It is a block diagram illustrating a processor microarchitecture for a processor according to at least one embodiment;

[0038] Figure 23 At least a portion of a graphics processor according to one or more embodiments is shown;

[0039] Figure 24 At least a portion of a graphics processor according to one or more embodiments is shown;

[0040] Figure 25 At least a portion of a graphics processor according to one or more embodiments is shown;

[0041] Figure 26 It is a block diagram of a graphics processing engine of a graphics processor according to at least one embodiment;

[0042] Figure 27 It is a block diagram of at least a portion of a graphics processor core according to at least one embodiment;

[0043] Figure 28A and Figure 28B The diagram illustrates thread execution logic according to at least one embodiment, which includes an array of processing elements of a graphics processor core;

[0044] Figure 29 A parallel processing unit (“PPU”) according to at least one embodiment is shown.

[0045] Figure 30 A general-purpose processing cluster (“GPC”) according to at least one embodiment is illustrated.

[0046] Figure 31 A memory partitioning unit of a parallel processing unit (“PPU”) according to at least one embodiment is shown;

[0047] Figure 32 A streaming multiprocessor according to at least one embodiment is illustrated;

[0048] Figure 33 A network for communicating data within a 5G wireless communication network, according to at least one embodiment, is shown;

[0049] Figure 34 A network architecture for a 5G LTE wireless network according to at least one embodiment is shown;

[0050] Figure 35 This is a diagram illustrating some basic functions of a mobile telecommunications network / system operating according to LTE and 5G principles according to at least one embodiment;

[0051] Figure 36 A radio access network, which may be part of a 5G network architecture according to at least one embodiment, is shown;

[0052] Figure 37 An example illustration of a 5G mobile communication system using multiple different types of devices according to at least one embodiment is provided;

[0053] Figure 38 An example advanced system according to at least one embodiment is shown;

[0054] Figure 39 The architecture of a network system according to at least one embodiment is shown;

[0055] Figure 40 Example components of a device according to at least one embodiment are shown;

[0056] Figure 41 An example interface of a baseband circuit according to at least one embodiment is shown;

[0057] Figure 42 An example of an uplink channel according to at least one embodiment is shown;

[0058] Figure 43 The architecture of a network system according to at least one embodiment is shown;

[0059] Figure 44 A control plane protocol stack according to at least one embodiment is shown;

[0060] Figure 45 A user plane protocol stack according to at least one embodiment is shown;

[0061] Figure 46 The components of a core network according to at least one embodiment are shown; and

[0062] Figure 47 Components of a system supporting Network Function Virtualization (NFV) according to at least one embodiment are shown. Detailed Implementation

[0063] This disclosure Figure 1 An example system for performing frequency resource allocation according to at least one embodiment is shown.

[0064] In at least one embodiment, base station 100 transmits signals to one or more communication devices 104. In at least one embodiment, the signal transmitted by the base station is a Wi-Fi or 802.11 signal. In at least one embodiment, examples of 802.11 may include one or more of 802.11ac wave 1, 802.11ac wave 2, and 802.11ax.

[0065] In at least one embodiment, base station 100 includes base station antenna 102 that simultaneously transmits signals to multiple communication devices 104. In at least one embodiment, simultaneous transmission includes transmitting multiple signals using the same frequency resources over a period of time. In at least one embodiment, this time period, according to 802.11, may include 802.11ac wave2.

[0066] In at least one embodiment, the signal transmitted by base station 100 is transmitted according to a multi-user, multiple-input, multiple-output (“MU-MIMO”) protocol. In at least one embodiment, the MU-MIMO technology includes 802.11ac wave2 or NextGen AC.

[0067] In at least one embodiment, base station 100 uses beamforming to direct signals to reserved wireless devices.

[0068] In at least one embodiment, the scheduler 108 determines a transmission schedule for sending signals from the base station 100 to the communication device 104. In at least one embodiment, this may include controlling the use of the base station antenna 102. In at least one embodiment, the scheduler 108 identifies a group of communication devices 104 for which signals can be transmitted simultaneously to multiple devices. For example, in at least one embodiment, the scheduler 108 may simultaneously transmit signals to communication devices 106a, b, and c in a first group, and then simultaneously transmit signals to communication devices 106d and e in a second group.

[0069] In at least one embodiment, a group of devices includes a group of devices associated with frequency resources during a time period from t1 to t2, such as a frequency range from f1 to f2. Here, frequencies fl and f2 and times t1 and t2 can be arbitrary or defined by industry standards such as 5G New Radio, MU-MIMO, etc.

[0070] Figure 2 An example of frequency resource allocation according to at least one embodiment is shown. In at least one embodiment, scheduler 202 determines the allocation of resources 200 among a plurality of communication devices 204. In at least one embodiment, the allocation of frequency resources 200 includes assigning devices 204 to groups 206, 208.

[0071] In at least one embodiment, the available frequencies are subdivided into frequency resources 200 by frequency and time. For example, in at least one embodiment, the frequency resources include the use of frequencies f1 to f2 from time t1 to t2, where f1 and f2 define frequency bands and t1 and t2 define time slots.

[0072] In at least one embodiment, scheduler 202 performs frequency resource allocation. In at least one embodiment, scheduler 202 performs frequency resource allocation by at least allocating devices 204 to groups. For example, in at least one embodiment, the scheduler may allocate one group of devices 204b, c, e to a first group 206 and another group of devices 204a, e, f to a second group 208.

[0073] In at least one embodiment, scheduler 202 performs frequency resource allocation by allocating at least groups to frequency resources. For example, in at least one embodiment, scheduler 202 allocates a first group 206 to a first frequency resource 214 and a second group 216 to a second frequency resource.

[0074] Figure 3 An example of execution frequency resource allocation according to at least one embodiment is shown. In at least one embodiment, such as... Figure 8 The scheduler 108 depicted generates a set of devices for using frequency resources based on parallel computing techniques. In at least one embodiment, execution threads perform operations including generating candidate groups 302, computing a precoding matrix 304, and prediction and rate 306. In at least one embodiment, multiple such threads are executed to generate multiple candidate groups. From these, a group can then be selected from candidate groups 308 and allocated to frequency resources 300.

[0075] In at least one embodiment, the sum rate is the sum of communication rates between the base station and the communication devices with which the base station is communicating. In at least one embodiment, the sum rate is the sum of communication rates between the base station and the communication devices in the communication device group. In at least one embodiment, the sum rate is calculated based on a prediction of the communication rate.

[0076] In at least one embodiment, a heuristic algorithm is used to generate candidate groups. In at least one embodiment, the heuristic algorithm includes algorithms for generating solutions that, while not necessarily optimal, complete, or accurate, are generated within a reasonable timeframe or are otherwise reasonably effective. For example, in at least one embodiment, a scheduler calculates the channel gain of each communication device, ranks the communication devices by channel gain, and selects members of a candidate group based on the ranking. This approach may tend to generate reasonable, but not necessarily optimal, suitable candidate groups within a reasonable timeframe.

[0077] In at least one embodiment, a precoding matrix for candidate groups is calculated. In at least one embodiment, the precoding matrix relates to beamforming and describes parameters used to combine data for transmission through multiple antennas. In at least one embodiment, these parameters facilitate multi-stream or multi-layer transmission in a wireless communication system.

[0078] In at least one embodiment, the calculation and rate are used to estimate the throughput of a communication system that can be implemented using candidate packets. In at least one embodiment, the throughput represents the average message passing rate between the base station and the communication devices in the candidate group.

[0079] In at least one embodiment, a group is selected from the generated candidate groups. In at least one embodiment, candidate groups are generated in parallel to facilitate the evaluation of multiple potential groups. In at least one embodiment, a candidate group associated with high sum and rate is selected. In at least one embodiment, the candidate group with the highest sum and rate is selected from among those evaluated. In at least one embodiment, the selected group is used to set parameters for data transmission between the base station and communication devices in the selected group.

[0080] Figure 4 An example of a parallel computing system for performing frequency resource allocation according to at least one embodiment is shown.

[0081] In at least one embodiment, processor thread block 400a generates candidate groups for frequency resource 402b and selects one group from these candidates. Similarly, thread blocks 400b…400n each generate candidate groups for their respective frequency resources 402b…400n and select a group from their respective generated candidates. In at least one embodiment, thread groups 400a…400n operate in parallel to generate candidate groups and select a group from these candidates for their respective frequency resources 402a…400n.

[0082] In at least one embodiment, a thread block comprises a set of threads that execute serially or in parallel. In at least one embodiment, each thread of the thread block executes in parallel on a stream processor shared by all threads of the thread block.

[0083] In at least one embodiment, each execution of thread blocks 400a…400n includes the operations of generating candidate groups 410, evaluating candidate groups 412, and selecting the best group 414 from the candidate groups.

[0084] In at least one embodiment, the operation of generating candidate groups 410 includes further operations, which may include calculating channel gain 420, classifying communication device groups based on their respective channel gains 422, and generating candidate groups 424 using a heuristic algorithm.

[0085] In at least one embodiment, the operation of evaluating candidate group 412 includes further operations, which may include calculating Gram matrix 430, calculating matrix inverse 432, and calculating sum rate 434.

[0086] Figure 5 An example of a heuristic algorithm for generating candidate groups according to at least one embodiment is shown.

[0087] In at least one embodiment, multiple heuristic algorithms for generating candidate groups are executed in parallel. In at least one embodiment, operation 502 is performed to initiate the execution of the heuristic algorithms to generate candidate groups by initiating parallel-executed computational kernels. In at least one embodiment, the computational kernel corresponds to a function or routine executed by a parallel computing architecture. In at least one embodiment, the computational kernel is associated with a CUDA programming model and a CUDA architecture. In at least one embodiment, the computational kernel performs one or more of operations 504-512.

[0088] In at least one embodiment, the heuristic algorithm for generating candidate groups includes operation 504 for calculating the channel gain of the communication device.

[0089] In at least one embodiment, the heuristic algorithm for generating candidate groups includes operation 506 to rank them by their respective channel gains.

[0090] In at least one embodiment, the heuristic algorithm for generating candidate groups includes operation 508 to check the orthogonality with respect to the base station and the communication devices with which the base station is communicating. In at least one embodiment, checking orthogonality includes determining the degree of interference between two or more signals.

[0091] In at least one embodiment, the heuristic algorithm for generating candidate groups includes operation 510 to add the next ranked communication device subject to orthogonal constraints to the candidate group.

[0092] In at least one embodiment, an algorithm for generating candidate groups includes an operation 512 for completing the candidate group. In at least one embodiment, a candidate group is determined to be complete when no more communication can be allocated to frequency resources.

[0093] Figure 6 An example system for performing MU-MIMO transmission according to at least one embodiment is shown.

[0094] In at least one embodiment, operation 602 allocates processor cores to generate a plurality of candidate packets, wherein the candidate packets are used to utilize frequency resources in MU-MIMO transmissions.

[0095] In at least one embodiment, the kernel corresponds to a program, function, or procedure that performs computational operations. In at least one embodiment, these computational operations generate candidate groups by executing algorithms, such as heuristic algorithms for grouping communication devices to use frequency resources simultaneously.

[0096] In at least one embodiment, the kernel executes on a thread associated with a thread group or thread bundle. In at least one embodiment, the processor core executes a thread of a thread group or thread bundle. In at least one embodiment, the operation 602 of allocating a processor core to generate candidate groups includes calling an application programming interface to cause the kernel to be executed by the processor core. In at least one embodiment, the kernel is executed multiple times in parallel by a thread group or thread bundle executing on the processor core.

[0097] In at least one embodiment, operation 604 generates candidate groups in parallel. In at least one embodiment, multiple threads of a thread group or thread bundle execute in parallel on a processor core to generate multiple candidate groups. In at least one embodiment, the threads of the thread group or thread bundle use a heuristic algorithm to generate candidate groups, such as... Figure 5The heuristic algorithm is illustrated. In at least one embodiment, the operations of the heuristic algorithm for generating candidate groups are executed in parallel by threads of a thread group or a thread bundle. In at least one embodiment, the parallel execution of the operations to generate candidate groups includes operations such as calculating channel gain, ranking or sorting communication devices, and selecting communication devices to be included in the candidate groups.

[0098] In at least one embodiment, operation 606 evaluates candidate groups in parallel. In at least one embodiment, operations performed in parallel by threads of a thread group or thread bundle include operations to compute a Gram matrix, operations to compute the matrix inverse, and operations to compute the sum rate.

[0099] In at least one embodiment, operation 608 selects a group from the candidate groups. In at least one embodiment, selecting a group from the candidate groups includes comparing the calculated sum rates of the candidate groups and selecting a group based on the calculated sum rates.

[0100] In at least one embodiment, operation 610 uses selected packets to perform MU-MIMO transmission. In at least one embodiment, performing MU-MIMO transmission includes beamforming the signals of communication devices in the selected packets.

[0101] Figure 7 An example system for selecting a set of devices to use a frequency band, according to at least one embodiment, is shown.

[0102] In at least one embodiment, the operation 702 initiates parallel processing of the group selection algorithm. In at least one embodiment, the parallel processing is initiated by an application programming interface (API) for utilizing a parallel computing architecture. In at least one embodiment, an API for a CUDA architecture is used.

[0103] In at least one embodiment, the thread block is associated with a frequency band, and many individual executions of the group selection algorithm are performed by a processor core that executes the thread associated with the thread block.

[0104] In at least one embodiment, parameters are provided to cause parallel execution of the group selection algorithm to generate multiple potential groups. In at least one embodiment, parameters are provided such that the starting conditions for each execution of the group selection algorithm vary, and multiple executions of the group selection algorithm tend to produce multiple candidate groups.

[0105] In at least one embodiment, multiple operations 704 are performed in parallel to generate multiple packets for a specific frequency band. In at least one embodiment, as described with reference to operation 702, an application programming interface is used to schedule multiple executions of the algorithm in parallel, such that the execution of these algorithms produces various potential packets.

[0106] In at least one embodiment, a set of devices is generated, at least in part, based on a heuristic algorithm. In at least one embodiment, the heuristic algorithm may tend to produce results that are local maxima or local minima, but are not globally optimal. In at least one embodiment, the heuristic algorithm is executed multiple times in parallel with different starting conditions, generating a variety of potential groupings.

[0107] In at least one embodiment, the heuristic algorithm for generating the device group includes iteratively adding devices to the device group based on channel gain. In at least one embodiment, communication devices are sorted according to the gain associated with the respective communication device and added to the group sequentially. In at least one embodiment, adding devices to the group is subject to orthogonal constraints associated with those devices already added to the group.

[0108] In at least one embodiment, operation 706 selects the generated packet and assigns it to frequency resources associated with the frequency band and time period.

[0109] In at least one embodiment, the generated group is selected based at least in part on the sum rate associated with the selected group.

[0110] In at least one embodiment, operation 708 transmits data according to selected packets. In at least one embodiment, transmission according to selected packets includes transmission within a frequency band for a period of time. In at least one embodiment, transmission occurs within a frequency band and time period at least partially based on 5G communication standards. In at least one embodiment, MU-MIMO transmission is at least partially based on selected packets.

[0111] Data Center

[0112] Figure 8 An example data center 800 that can be used with at least one embodiment is shown. In at least one embodiment, the data center 800 includes a data center infrastructure layer 810, a framework layer 820, a software layer 830, and an application layer 840.

[0113] In at least one embodiment, such as Figure 8As shown, the data center infrastructure layer 810 may include a resource coordinator 812, grouped computing resources 814, and node computing resources (“nodes CR”) 816(1)-816(N), where “N” represents any integer, a positive integer. In at least one embodiment, the nodes CR 816(1)-816(N) may include, but are not limited to, any number of central processing units (“CPUs”) or other processors (including accelerators, field-programmable gate arrays (FPGAs), graphics processors, etc.), memory devices (e.g., dynamic read-only memory), storage devices (e.g., solid-state drives or disk drives), network input / output (“NW I / O”) devices, network switches, virtual machines (“VMs”), power modules, and cooling modules, etc. In at least one embodiment, one or more of the nodes CR 816(1)-816(N) may be servers having one or more of the aforementioned computing resources.

[0114] In at least one embodiment, the grouped computing resources 814 may include individual groups (not shown) of node CRs housed in one or more racks, or a plurality of racks (also not shown) housed in data centers in various geographic locations. Individual groups of node CRs within the grouped computing resources 814 may include computing, networking, memory, or storage resources that can be configured or allocated to support groups of one or more workloads. In at least one embodiment, several node CRs, including CPUs or processors, may be grouped within one or more racks to provide computing resources to support one or more workloads. In at least one embodiment, one or more racks may also include any number of power modules, cooling modules, and network switches, in any combination.

[0115] In at least one embodiment, resource coordinator 812 may be configured or otherwise control one or more nodes CR816(1)-816(N) and / or grouped computing resources 814. In at least one embodiment, resource coordinator 812 may include a Software Design Infrastructure (“SDI”) management entity for data center 800. In at least one embodiment, resource coordinator may include hardware, software, or some combination thereof.

[0116] In at least one embodiment, such as Figure 8As shown, framework layer 820 includes a job scheduler 822, a configuration manager 834, a resource manager 836, and a distributed file system 838. In at least one embodiment, framework layer 820 may include a framework of software 832 supporting software layer 830 and / or one or more applications 842 supporting application layer 840. In at least one embodiment, software 832 or application 842 may respectively include web-based service software or applications, such as services or applications provided by Amazon Web Services, Google Cloud, and Microsoft Azure. In at least one embodiment, framework layer 820 may be, but is not limited to, a free and open-source software web application framework, such as Apache Spark, which can utilize distributed file system 838 for large-scale data processing (e.g., "big data"). TM (Hereinafter referred to as "Spark"). In at least one embodiment, the job scheduler 822 may include a Spark driver to facilitate the scheduling of workloads supported by various layers of the data center 800. In at least one embodiment, the configuration manager 834 may be able to configure different layers, such as the software layer 830 and the framework layer 820, which includes Spark and a distributed file system 838 for supporting large-scale data processing. In at least one embodiment, the resource manager 836 is able to manage cluster or group computing resources mapped to or allocated to support the distributed file system 838 and the job scheduler 822. In at least one embodiment, the cluster or group computing resources may include group computing resources 814 on the data center infrastructure layer 810. In at least one embodiment, the resource manager 836 may coordinate with the resource coordinator 812 to manage these mapped or allocated computing resources.

[0117] In at least one embodiment, the software 832 included in the software layer 830 may include software used by at least a portion of the nodes CR 816(1)-816(N), the grouped computing resources 814, and / or the distributed file system 838 of the framework layer 820. One or more types of software may include, but are not limited to, Internet web page search software, email virus scanning software, database software, and streaming video content software.

[0118] In at least one embodiment, one or more applications 842 included in application layer 840 may include one or more types of applications used by at least a portion of nodes CR 816(1)-816(N), grouped computing resources 814, and / or the distributed file system 838 of framework layer 820. One or more types of applications may include, but are not limited to, any number of genomics applications, cognitive computing and machine learning applications, including training or inference software, machine learning framework software (e.g., PyTorch, TensorFlow, Caffe, etc.), or other machine learning applications used in conjunction with one or more embodiments.

[0119] In at least one embodiment, any of the configuration manager 834, resource manager 836, and resource coordinator 812 can perform any number and type of self-modification actions based on any amount and type of data acquired in any technically feasible manner. In at least one embodiment, self-modification actions can mitigate potentially poor configuration decisions by data center operators of data center 800 and can prevent underutilization and / or poor performance of the data center.

[0120] In at least one embodiment, data center 800 may include tools, services, software, or other resources to train one or more machine learning models or to use one or more machine learning models to predict or infer information according to one or more embodiments described herein. For example, in at least one embodiment, a machine learning model can be trained by calculating weight parameters based on a neural network architecture using the software and computing resources described above with respect to data center 800. In at least one embodiment, information can be inferred or predicted using trained machine learning models corresponding to one or more neural networks using the resources described above with respect to data center 800 by using weight parameters calculated through one or more training techniques described herein.

[0121] In at least one embodiment, the data center may use a CPU, application-specific integrated circuit (ASIC), GPU, FPGA, or other hardware to utilize the aforementioned resources to perform training and / or inference. Furthermore, one or more of the aforementioned software and / or hardware resources may be configured as a service to allow a user to train or perform information inference, such as image recognition, speech recognition, or other artificial intelligence services.

[0122] In at least one embodiment, wireless data transmission in data center 800 is performed by a processor, processing core, or circuitry to generate packets for the device in parallel to utilize the frequency band and to select one of the generated packets.

[0123] Autonomous vehicles

[0124] Figure 9A An example of an autonomous vehicle 900 according to at least one embodiment is shown. In at least one embodiment, the autonomous vehicle 900 (which may alternatively be referred to herein as "vehicle 900") may be, but is not limited to, a passenger vehicle, such as a car, truck, bus, and / or another type of vehicle capable of accommodating one or more passengers. In at least one embodiment, vehicle 900 may be a semi-tractor-trailer for hauling goods. In at least one embodiment, vehicle 900 may be an aircraft, a robotic vehicle, or other type of vehicle.

[0125] Autonomous vehicles can be described according to the levels of automation defined by the National Highway Traffic Safety Administration (“NHTSA”) and the Society of Automotive Engineers (“SAE”) of the U.S. Department of Transportation in their “Taxonomy and Definitions for Terms Related to Driving Automation Systems for On-Road Motor Vehicles” (e.g., standard number J3016-201806, published June 15, 2018; standard number J3016-201609, published September 30, 2016; and previous and future versions of this standard). In one or more embodiments, vehicle 900 may be able to function according to one or more of the levels of autonomous driving from Level 1 to Level 5. For example, in at least one embodiment, vehicle 900 may be able to perform conditional automation (Level 3), high automation (Level 4), and / or full automation (Level 5).

[0126] In at least one embodiment, vehicle 900 may include, but is not limited to, components such as chassis, body, wheels (e.g., 2, 4, 6, 8, 18, etc.), tires, axles, and other vehicle components. In at least one embodiment, vehicle 900 may include, but is not limited to, propulsion system 950, such as an internal combustion engine, a hybrid powertrain, an all-electric motor, and / or another type of propulsion system. In at least one embodiment, propulsion system 950 may be connected to the drivetrain of vehicle 900, which may include, but is not limited to, a transmission, to enable propulsion of vehicle 900. In at least one embodiment, propulsion system 950 may be controlled in response to receiving a signal from throttle / accelerator 952.

[0127] In at least one embodiment, when the propulsion system 950 is operating (e.g., when the vehicle is in motion), the steering system 954 (which may include, but is not limited to, a steering wheel) is used to steer the vehicle 900 (e.g., along a desired path or route). In at least one embodiment, the steering system 954 may receive signals from the steering actuator 956. The steering wheel may be optional for fully automated (Level 5) functionality. In at least one embodiment, the brake sensor system 946 may be used to operate the vehicle brakes in response to signals received from the brake actuator 948 and / or brake sensors.

[0128] In at least one embodiment, the controller 936 may include, but is not limited to, one or more system-on-chips (“SoCs”). Figure 9A A controller 936 (not shown) and / or a graphics processing unit (“GPU”) provides signals (e.g., representing commands) to one or more components and / or systems of vehicle 900. For example, in at least one embodiment, controller 936 may send signals to operate vehicle braking via brake actuator 949, to operate steering system 954 via one or more steering actuators 956, and to operate propulsion system 950 via one or more throttles / accelerators 952. One or more controllers 936 may include one or more onboard (e.g., integrated) computing devices (e.g., supercomputers) that process sensor signals and output operating commands (e.g., signals representing commands) to enable autonomous driving and / or assist a driver in driving vehicle 900. In at least one embodiment, one or more controllers 936 may include a first controller 936 for autonomous driving functions, a second controller 936 for functional safety functions, a third controller 936 for artificial intelligence functions (e.g., computer vision), a fourth controller 936 for infotainment functions, a fifth controller 936 for redundancy in emergency situations, and / or other controllers. In at least one embodiment, a single controller 936 may handle two or more of the functions described above, and two or more controllers 936 may handle a single function and / or any combination thereof.

[0129] In at least one embodiment, one or more controllers 936 provide signals for controlling one or more components and / or systems of vehicle 900 in response to sensor data received from one or more sensors (e.g., sensor inputs). In at least one embodiment, sensor data can be received from sensors, including but not limited to one or more Global Navigation Satellite System (“GNSS”) sensors 958 (e.g., one or more Global Positioning System sensors), one or more RADAR sensors 960, one or more ultrasonic sensors 962, one or more LIDAR sensors 964, one or more inertial measurement unit (IMU) sensors 966 (e.g., one or more accelerometers, one or more gyroscopes, one or more magnetic compasses, one or more magnetometers, etc.), one or more microphones 996, one or more stereo cameras 968, one or more wide-angle cameras 970 (e.g., fisheye cameras), one or more infrared cameras 972, one or more surround cameras 974 (e.g., 360-degree cameras), and remote cameras (…). Figure 9A (not shown in the image), medium-range camera ( Figure 9A (Not shown in the diagram) One or more speed sensors 944 (e.g., for measuring the speed of vehicle 900), one or more vibration sensors 942, one or more steering sensors 940, one or more brake sensors (e.g., as part of brake sensor system 946) and / or other sensor types are received.

[0130] In at least one embodiment, one or more controllers 936 may receive input (e.g., represented by input data) from the instrument panel 932 of the vehicle 900 and provide output (e.g., represented by output data, display data, etc.) via a human-machine interface (“HMI”) display 934, a voice signaler, a speaker, and / or other components of the vehicle 900. In at least one embodiment, the output may include information such as vehicle speed, velocity, time, map data (e.g., high-definition map). Figure 9A The HMI display 934 may display information such as (not shown in the image), location data (e.g., the location of vehicle 900, for example, on a map), direction, the location of other vehicles (e.g., occupancy raster), information about objects, and the state of objects sensed by one or more controllers 936. For example, in at least one embodiment, the HMI display 934 may display information about the presence of one or more objects (e.g., road signs, warning signs, traffic light changes, etc.) and / or information about driving operations that the vehicle has made, is making, or will make (e.g., changing lanes now, exiting exit 34B within two miles, etc.).

[0131] In at least one embodiment, vehicle 900 further includes a network interface 924 that can communicate via one or more networks using one or more wireless antennas 926 and / or one or more modems. For example, in at least one embodiment, network interface 924 may be able to communicate via Long Term Evolution (“LTE”), Wideband Code Division Multiple Access (“WCDMA”), Universal Mobile Telecommunications System (“UMTS”), Global System for Mobile Communications (“GSM”), IMT-CDMA Multicarrier (“CDMA2000”) networks, etc. In at least one embodiment, one or more wireless antennas 926 may also enable communication between objects in the environment (e.g., vehicles, mobile devices) using one or more local area networks (e.g., Bluetooth, Bluetooth Low Energy (LE), Z-Wave, ZigBee, etc.) and / or one or more low-power wide area networks (hereinafter “LPWAN”) (e.g., LoRaWAN, SigFox, etc. protocols).

[0132] In at least one embodiment, wireless data transmission in vehicle 900 is performed by a processor, processing core, or circuitry to generate device packets in parallel to utilize the frequency band and to select one of the generated packets.

[0133] Figure 9B The illustration shows an embodiment according to at least one of the embodiments. Figure 9A Examples of camera positions and fields of view for an autonomous vehicle 900. In at least one embodiment, the camera and its respective field of view are an example embodiment and are not intended to be limiting. For example, in at least one embodiment, additional and / or alternative cameras may be included and / or the cameras may be located at different positions on the vehicle 900.

[0134] In at least one embodiment, the camera type used for the camera may include, but is not limited to, a digital camera suitable for use with components and / or systems of vehicle 900. One or more cameras may operate at Automotive Safety Integrity Level (“ASIL”) B and / or other ASILs. In at least one embodiment, the camera type may have any image capture rate, such as 60 frames per second (fps), 120 fps, 240 fps, etc. In at least one embodiment, the camera may be able to use a rolling shutter, a global shutter, another type of shutter, or a combination thereof. In at least one embodiment, the color filter array may include a red transparent (“RCCC”) color filter array, a red transparent blue (“RCCB”) color filter array, a red blue green transparent (“RBGC”) color filter array, a Foveon X3 color filter array, a Bayer sensor (“RGGB”) color filter array, a monochrome sensor color filter array, and / or other types of color filter arrays. In at least one embodiment, a transparent pixel camera, such as a camera with RCCC, RCCB, and / or RBGC color filter arrays, may be used to improve photosensitivity.

[0135] In at least one embodiment, one or more cameras may be used to perform advanced driver assistance system (“ADAS”) functions (e.g., as part of a redundancy or fail-safe design). For example, in at least one embodiment, a multi-function mono camera may be installed to provide functions including lane departure warning, traffic sign assist, and intelligent headlight control. In at least one embodiment, one or more cameras (e.g., all cameras) may simultaneously record and provide image data (e.g., video).

[0136] In at least one embodiment, one or more cameras may be mounted in a mounting assembly, such as a custom-designed (three-dimensional (“3D”-printed) assembly, to cut out stray light and reflections from within the vehicle (e.g., dashboard reflections reflected in the windshield mirror), which may interfere with the camera’s image data capture capabilities. Regarding the rearview mirror mounting assembly, in at least one embodiment, the rearview mirror assembly may be 3D-printed custom-made such that the camera mounting plate matches the shape of the rearview mirror. In at least one embodiment, one or more cameras may be integrated into the rearview mirror. In at least one embodiment, for side-view cameras, one or more cameras may also be integrated within the four pillars at each corner of the vehicle.

[0137] In at least one embodiment, a camera (e.g., a forward-facing camera) having a field of view including a portion of the environment in front of the vehicle 900 can be used for surround view and, with the assistance of one or more controllers 936 and / or control SoCs, to help identify the forward path and obstacles, thereby providing information crucial for generating an occupancy grid and / or determining a preferred vehicle path. In at least one embodiment, the forward-facing camera can be used to perform many of the same ADAS functions as LIDAR, including but not limited to emergency braking, pedestrian detection, and collision avoidance. In at least one embodiment, the forward-facing camera can also be used for ADAS functions and systems, including but not limited to lane departure warning (“LDW”), adaptive cruise control (“ACC”), and / or other functions (e.g., traffic sign recognition).

[0138] In at least one embodiment, various cameras can be used in a forward-facing configuration, including, for example, a monocular camera platform including a CMOS (“complementary metal-oxide-semiconductor”) color imager. In at least one embodiment, a wide-angle camera 970 can be used to sense objects entering from the periphery (e.g., pedestrians, people crossing the street, or bicycles). Although in Figure 9B Only one wide-angle camera 970 is shown; however, in other embodiments, the vehicle 900 may have any number (including zero) of wide-angle cameras. In at least one embodiment, any number of remote cameras 998 (e.g., a pair of remote stereo cameras) can be used for depth-based object detection, especially for objects for which a neural network has not yet been trained. In at least one embodiment, the remote camera 998 can also be used for object detection and classification, as well as basic object tracking.

[0139] In at least one embodiment, any number of stereo cameras 968 may also be included in a forward configuration. In at least one embodiment, one or more stereo cameras 968 may include an integrated control unit comprising a scalable processing unit that may provide programmable logic (“FPGA”) and a multi-core microprocessor with a controller area network (“CAN”) or Ethernet interface integrated on a single chip. In at least one embodiment, such a unit may be used to generate a 3D map of the environment of the vehicle 900, including distance estimates for all points in the image. In at least one embodiment, one or more stereo cameras 968 may include, but are not limited to, a compact stereo vision sensor, which may include, but is not limited to, two camera lenses (one on the left and one on the right) and an image processing chip that can measure the distance from the vehicle 900 to a target object and use the generated information (e.g., metadata) to activate autonomous emergency braking and lane departure warning functions. In at least one embodiment, other types of stereo cameras 968 may also be used in addition to those described herein.

[0140] In at least one embodiment, a camera (e.g., a side-view camera) having a field of view including a portion of the environment on the side of the vehicle 900 can be used for surround viewing, thereby providing information for creating and updating the occupied grid, and generating a side collision warning. For example, in at least one embodiment, a surround camera 974 (e.g., as...) Figure 9B The four surround cameras 974 shown can be positioned on the vehicle 900. One or more surround cameras 974 can include, but are not limited to, any number and combination of wide-angle cameras 970, one or more fisheye lenses, one or more 360-degree cameras, and / or similar cameras. For example, in at least one embodiment, four fisheye lens cameras can be located at the front, rear, and sides of the vehicle 900. In at least one embodiment, the vehicle 900 can use three surround cameras 974 (e.g., left, right, and rear) and can utilize one or more other cameras (e.g., a forward-facing camera) as a fourth surround-view camera.

[0141] In at least one embodiment, a camera (e.g., a rear-view camera) having a field of view including a portion of the environment behind the vehicle 900 can be used for parking assistance, surround view, rear collision warning, and creating and updating occupancy raster. In at least one embodiment, a wide variety of cameras can be used, including but not limited to cameras that are also suitable as one or more forward-facing cameras (e.g., long-range camera 998 and / or one or more mid-range cameras 976, one or more stereo cameras 968, one or more infrared cameras 972, etc.), as described herein.

[0142] In at least one embodiment, wireless data transmission in the autonomous vehicle 900 is performed by a processor, processing core, or circuitry to generate device packets in parallel to utilize the frequency band and select one of the generated packets.

[0143] Figure 9C The illustration shows an embodiment according to at least one of the embodiments. Figure 9A A block diagram of an example system architecture for an autonomous vehicle 900. In at least one embodiment, Figure 9CEach of one or more components, one or more features, and one or more systems of vehicle 900 is shown as connected via bus 902. In at least one embodiment, bus 902 may include, but is not limited to, a CAN data interface (which may alternatively be referred to herein as “CAN bus”). In at least one embodiment, CAN may be a network within vehicle 900 used to help control various features and functions of vehicle 900, such as brake actuation, acceleration, braking, steering, windshield wipers, etc. In one embodiment, bus 902 may be configured to have dozens or even hundreds of nodes, each node having its own unique identifier (e.g., CAN ID). In at least one embodiment, bus 902 can be read to find steering wheel angle, ground speed, engine rotation speed (“RPM”), button position, and / or other vehicle status indicators. In at least one embodiment, bus 902 may be an ASIL B compliant CAN bus.

[0144] In at least one embodiment, FlexRay and / or Ethernet may be used in addition to or from CAN. In at least one embodiment, there may be any number of buses 902, which may include, but are not limited to, zero or more CAN buses, zero or more FlexRay buses, zero or more Ethernet buses, and / or zero or more other types of buses using other protocols. In at least one embodiment, two or more buses 902 may be used to perform different functions and / or may be used for redundancy. For example, a first bus 902 may be used for a collision avoidance function, and a second bus 902 may be used for actuation control. In at least one embodiment, each bus 902 may communicate with any component of the vehicle 900, and two or more buses 902 may communicate with the same component. In at least one embodiment, each of any number of system-on-chip (“SoC”) 904, each of one or more controllers 936, and / or each computer within the vehicle may access the same input data (e.g., input from sensors of the vehicle 900) and may be connected to a common bus, such as a CAN bus.

[0145] In at least one embodiment, vehicle 900 may include one or more controllers 936, such as those described herein. Figure 9A The controller 936 can be used for a variety of functions. In at least one embodiment, the controller 936 can be coupled to any of the various other components and systems of the vehicle 900, and can be used to control the vehicle 900, the artificial intelligence of the vehicle 900, the infotainment and / or other functions of the vehicle 900.

[0146] In at least one embodiment, vehicle 900 may include any number of SoCs 904. Each of the SoCs 904 may include, but is not limited to, a central processing unit (“one or more CPUs”) 906, a graphics processing unit (“one or more GPUs”) 908, one or more processors 910, one or more caches 912, one or more accelerators 914, one or more data storage 916, and / or other components and features not shown. In at least one embodiment, one or more SoCs 904 may be used to control vehicle 900 on various platforms and systems. For example, in at least one embodiment, one or more SoCs 904 may be combined with a high-definition (“HD”) map 922 in a system (e.g., the system of vehicle 900), the HD map 922 being accessible from one or more servers via a network interface 924. Figure 9C (Not shown in the image) Get map refresh and / or update.

[0147] In at least one embodiment, one or more CPU 906s may include CPU clusters or CPU complexes (which may alternatively be referred to herein as “CCPLEX”). In at least one embodiment, one or more CPU 906s may include multiple cores and / or a secondary (“L2”) cache. For example, in at least one embodiment, one or more CPU 906s may include eight cores in an intercoupled multiprocessor configuration. In at least one embodiment, one or more CPU 906s may include four dual-core clusters, each with a dedicated L2 cache (e.g., 2MB L2 cache). In at least one embodiment, one or more CPU 906s (e.g., CCPLEX) may be configured to support simultaneous cluster operation, such that any combination of clusters of one or more CPU 906s can be active at any given time.

[0148] In at least one embodiment, one or more CPUs 906 may implement power management functions, including but not limited to one or more of the following features: automatic clock gating of individual hardware modules to conserve dynamic power when idle; clock gating of each core when the core is not actively executing instructions due to executing Wait for Interrupt (“WFI”) / Event Wait (“WFE”) instructions; independent power supply for each core; independent clock gating for each core cluster when all cores are clock-gated or power-gated; and / or independent power gating for each core cluster when all cores are power-gated. In at least one embodiment, one or more CPUs 906 may further implement an enhanced algorithm for managing power states, wherein allowed power states and expected wake-up times are specified, and the hardware / microcode determines the optimal power state for cores, clusters, and CCPLEX inputs. In at least one embodiment, the processing core may support a simplified power state input sequence in software, wherein the work is offloaded to the microcode.

[0149] In at least one embodiment, one or more GPUs 908 may include an integrated GPU (or “iGPU” herein). In at least one embodiment, one or more GPUs 908 may be programmable and efficient for parallel workloads. In at least one embodiment, one or more GPUs 908 may use an enhanced tensor instruction set. In one embodiment, one or more GPUs 908 may include one or more streaming microprocessors, wherein each streaming microprocessor may include a Level 1 (“L1”) cache (e.g., an L1 cache with at least 96 KB of storage capacity), and two or more streaming microprocessors may share an L2 cache (e.g., an L2 cache with 512 KB of storage capacity). In at least one embodiment, one or more GPUs 908 may include at least eight streaming microprocessors. In at least one embodiment, one or more GPUs 908 may use a computation application programming interface (API). In at least one embodiment, one or more GPUs 908 may use one or more parallel computing platforms and / or programming models (e.g., NVIDIA’s CUDA).

[0150] In at least one embodiment, one or more GPU 908s may be power-optimized for optimal performance in automotive and embedded use cases. For example, in one embodiment, one or more GPU 908s may be fabricated on a FinFET (“FinFET”). In at least one embodiment, each streaming microprocessor may include multiple mixed-precision processing cores divided into multiple blocks. For example, but not limited to, 64 PF32 cores and 32 PF64 cores may be divided into four processing blocks. In at least one embodiment, each processing block may be allocated 16 FP32 cores, 8 FP64 cores, 16 INT32 cores, two mixed-precision NVIDIA Tensor cores for deep learning matrix arithmetic, a level-zero (“L0”) instruction cache, a thread bundle scheduler, a dispatch unit, and / or a 64 KB register file. In at least one embodiment, the streaming microprocessor may include independent parallel integer and floating-point data paths to provide efficient execution of workloads that mix computation and addressing operations. In at least one embodiment, the streaming microprocessor may include independent thread scheduling capabilities to enable finer-grained synchronization and collaboration between parallel threads. In at least one embodiment, the streaming microprocessor may include a combined L1 data cache and shared memory unit to improve performance while simplifying programming.

[0151] In at least one embodiment, one or more GPU 908s may include high-bandwidth memory (“HBM”) and / or a 16 GB HBM2 memory subsystem to provide a peak storage bandwidth of approximately 900 GB / s in some examples. In at least one embodiment, in addition to or instead of HBM memory, synchronous graphics random access memory (“SGRAM”), such as graphics double data rate type five synchronous random access memory (“GDDR5”), may be used.

[0152] In at least one embodiment, one or more GPUs 908 may include unified memory technology. In at least one embodiment, address translation service (“ATS”) support can be used to allow one or more GPUs 908 to directly access the page tables of one or more CPUs 906. In at least one embodiment, when one or more GPUs 908 memory management units (“MMUs”) experience a miss, an address translation request can be sent to one or more CPUs 906. In response, in at least one embodiment, one or more CPUs 906 can look up the virtual-physical mapping of the address in their page tables and transfer the translation back to one or more GPUs 908. In at least one embodiment, unified memory technology can allow a single unified virtual address space to be used for the memory of both one or more CPUs 906 and one or more GPUs 908, thereby simplifying the programming of one or more GPUs 908 and porting applications to one or more GPUs 908.

[0153] In at least one embodiment, one or more GPUs 908 may include any number of access counters that can track the frequency of memory accesses by one or more GPUs 908 to other processors. In at least one embodiment, one or more access counters can help ensure that memory pages are moved to the physical memory of the processor that accesses the pages most frequently, thereby improving the efficiency of shared memory ranges between processors.

[0154] In at least one embodiment, one or more SoCs 904 may include any number of caches 912, including those described herein. For example, in at least one embodiment, one or more caches 912 may include a Level 3 (“L3”) cache available for one or more CPUs 906 and one or more GPUs 908 (e.g., connected to CPUs 906 and GPUs 908). In at least one embodiment, one or more caches 912 may include a write-back cache that can, for example, track the state of a line using a cache coherence protocol (e.g., MEI, MESI, MSI, etc.). In at least one embodiment, although a smaller cache size may be used, according to an embodiment, the L3 cache may include 4 MB or more.

[0155] In at least one embodiment, one or more SoCs 904 may include one or more accelerators 914 (e.g., hardware accelerators, software accelerators, or a combination thereof). In at least one embodiment, one or more SoCs 904 may include a hardware acceleration cluster, which may include optimized hardware accelerators and / or large on-chip memory. In at least one embodiment, large on-chip memory (e.g., 4MB of SRAM) enables the hardware acceleration cluster to accelerate neural networks and other computations. In at least one embodiment, the hardware acceleration cluster may be used to supplement one or more GPUs 908 and offload some tasks from one or more GPUs 908 (e.g., freeing up more cycles from one or more GPUs 908 to perform other tasks). In at least one embodiment, one or more accelerators 914 may be used for a target workload (e.g., perceptual, convolutional neural network (“CNN”), recurrent neural network (“RNN”), etc.) that is sufficiently stable to withstand acceleration testing. In at least one embodiment, the CNN may include region-based or region convolutional neural networks (“RCNN”) and fast RCNN (e.g., for object detection) or other types of CNNs.

[0156] In at least one embodiment, one or more accelerators 914 (e.g., a hardware acceleration cluster) may include one or more deep learning accelerators (“DLAs”). One or more DLAs may include, but are not limited to, one or more Tensor Processing Units (“TPUs”) configured to provide an additional 10 trillion operations per second for deep learning applications and inference. In at least one embodiment, the TPU may be an accelerator configured and optimized for performing image processing functions (e.g., for CNNs, RCNNs, etc.). One or more DLAs may be further optimized for specific sets of neural network types and floating-point operations and inference. In at least one embodiment, one or more DLAs are designed to provide higher performance per millimeter than typical general-purpose GPUs and typically significantly outperform CPUs. In at least one embodiment, one or more TPUs may perform several functions, including single-instance convolution functions supporting, for example, INT8, INT16, and FP16 data types for features and weights, as well as post-processor functions. In at least one embodiment, one or more DLAs can execute neural networks, particularly CNNs, quickly and efficiently on processed or unprocessed data for any of the various functions, including, but not limited to: CNNs for object recognition and detection using data from camera sensors; CNNs for distance estimation using data from camera sensors; CNNs for emergency vehicle detection, recognition, and identification using data from microphone 996; CNNs for face recognition and vehicle owner recognition using data from camera sensors; and / or CNNs for safety and / or safety-related events.

[0157] In at least one embodiment, the DLA can perform any function of one or more GPUs 908, and by using an inference accelerator, for example, the designer can target one or more DLAs or one or more GPUs 908 for any function. For example, in at least one embodiment, the designer can centralize the CNN processing and floating-point operations on one or more DLAs, leaving other functions to one or more GPUs 908 and / or one or more other accelerators 914.

[0158] In at least one embodiment, one or more accelerators 814 (e.g., a hardware acceleration cluster) may include programmable vision accelerators (“PVAs”), which may alternatively be referred to herein as computer vision accelerators. In at least one embodiment, one or more PVAs may be designed and configured to accelerate computer vision algorithms for advanced driver assistance systems (“ADAS”) 838, autonomous driving, augmented reality (“AR”) applications, and / or virtual reality (“VR”) applications. In at least one embodiment, one or more PVAs may strike a balance between performance and flexibility. For example, in at least one embodiment, each of one or more PVAs may include, for example, but not limited to, any number of reduced instruction set computer (“RISC”) cores, direct memory access (“DMA”), and / or any number of vector processors.

[0159] In at least one embodiment, the RISC core can interact with an image sensor (e.g., the image sensor of any camera described herein), an image signal processor, etc. In at least one embodiment, each RISC core may include any number of memories. In at least one embodiment, the RISC core may use any of a variety of protocols, depending on the embodiment. In at least one embodiment, the RISC core may execute a real-time operating system (“RTOS”). In at least one embodiment, the RISC core may be implemented using one or more integrated circuit devices, application-specific integrated circuits (“ASICs”), and / or storage devices. For example, in at least one embodiment, the RISC core may include an instruction cache and / or tightly coupled RAM.

[0160] In at least one embodiment, DMA enables components of the PVA to access system memory independently of one or more CPU 906s. In at least one embodiment, DMA can support any number of features for providing optimization to the PVA, including but not limited to, support for multidimensional addressing and / or circular addressing. In at least one embodiment, DMA can support up to six or more addressing dimensions, which may include, but are not limited to, block width, block height, block depth, horizontal block step, vertical block step, and / or depth step.

[0161] In at least one embodiment, the vector processor may be a programmable processor designed to efficiently and flexibly execute programming for computer vision algorithms and provide signal processing capabilities. In at least one embodiment, the PVA may include a PVA core and two vector processing subsystem partitions. In at least one embodiment, the PVA core may include a processor subsystem, a DMA engine (e.g., two DMA engines), and / or other peripherals. In at least one embodiment, the vector processing subsystem may serve as the main processing engine of the PVA and may include a vector processing unit (“VPU”), an instruction cache, and / or a vector memory (e.g., “VMEM”). In at least one embodiment, the VPU core may include a digital signal processor, such as a Single Instruction Multiple Data (“SIMD”) or Very Long Instruction Word (“VLIW”) digital signal processor. In at least one embodiment, the combination of SIMD and VLIW can improve throughput and speed.

[0162] In at least one embodiment, each vector processor may include an instruction cache and may be coupled to dedicated memory. As a result, in at least one embodiment, each vector processor may be configured to execute independently of other vector processors. In at least one embodiment, vector processors included in a particular PVA may be configured to employ data parallelism. For example, in at least one embodiment, multiple vector processors included in a single PVA may execute the same computer vision algorithm, except on different regions of an image. In at least one embodiment, vector processors included in a particular PVA may execute different computer vision algorithms simultaneously on the same image, or even execute different algorithms on a sequence of images or portions of images. In at least one embodiment, among others, any number of PVAs may be included in the hardware-accelerated cluster, and any number of vector processors may be included in each PVA. In at least one embodiment, the PVA may include additional error-correcting code (“ECC”) memory to enhance overall system security.

[0163] In at least one embodiment, one or more accelerators 914 (e.g., a hardware acceleration cluster) may include an on-chip computer vision network and static random access memory (“SRAM”) for providing high-bandwidth, low-latency SRAM to one or more accelerators 914. In at least one embodiment, the on-chip memory may include at least 4 MB of SRAM, comprising, for example, but not limited to, eight field-configurable memory blocks accessible to both the PVA and DLA. In at least one embodiment, each pair of memory blocks may include an Advanced Peripheral Bus (“APB”) interface, configuration circuitry, a controller, and a multiplexer. In at least one embodiment, any type of memory may be used. In at least one embodiment, the PVA and DLA may access the memory via a backbone providing high-speed access to the memory for both the PVA and DLA. In at least one embodiment, the backbone may include an on-chip computer vision network that interconnects the PVA and DLA to the memory (e.g., using an APB).

[0164] In at least one embodiment, the on-chip computer vision network may include an interface that determines that both the PVA and DLA provide ready and valid signals before transmitting any control signals / addresses / data. In at least one embodiment, the interface may provide separate phases and separate channels for transmitting control signals / addresses / data, as well as bursty communication for continuous data transmission. In at least one embodiment, although other standards and protocols may be used, the interface may conform to the International Organization for Standardization (“ISO”) 26262 or the International Electrotechnical Commission (“IEC”) 61508 standard.

[0165] In at least one embodiment, one or more SoCs 904 may include a real-time eye-tracking hardware accelerator. In at least one embodiment, the real-time eye-tracking hardware accelerator may be used to quickly and efficiently determine the location and extent of an object (e.g., within a world model) to generate real-time visualization simulations for RADAR signal interpretation, for sound propagation synthesis and / or analysis, for simulation of SONAR systems, for general wave propagation simulation, for comparison with LIDAR data for localization and / or other functions, and / or for other purposes.

[0166] In at least one embodiment, one or more accelerators 914 (e.g., a hardware acceleration cluster) have broad applications for autonomous driving. In at least one embodiment, the PVA can be a programmable vision accelerator used in critical processing stages in ADAS and autonomous vehicles. In at least one embodiment, the capabilities of the PVA with low power consumption and low latency are well-matched to algorithmic domains requiring predictable processing. In other words, the PVA performs well in semi-intensive or intensive conventional computations, even on small datasets that may require predictable runtimes with low latency and low power consumption. In at least one embodiment, in an autonomous vehicle, such as vehicle 900, the PVA may be designed to run classical computer vision algorithms, as they are efficient in object detection and integer mathematical operations.

[0167] For example, according to at least one embodiment of the technology, PVA is used to perform computer stereo vision. In at least one embodiment, a semi-global matching-based algorithm may be used in some examples, although this is not intended to be limiting. In at least one embodiment, applications for Level 3-5 autonomous driving use dynamic estimation / stereo matching (e.g., structure recovery from motion, pedestrian recognition, lane detection, etc.) during operation. In at least one embodiment, PVA can perform computer stereo vision functions on input from two monocular cameras.

[0168] In at least one embodiment, the PVA can be used to perform intensive optical flow. For example, in at least one embodiment, the PVA can process raw RADAR data (e.g., using 4D Fast Fourier Transform) to provide processed RADAR data. In at least one embodiment, the PVA is used for time-of-flight depth processing, for example, by processing raw time-of-flight data to provide processed time-of-flight data.

[0169] In at least one embodiment, the DLA can be used to run any type of network to enhance control and driving safety, including, but not limited to, neural networks whose output is used for a confidence score for each object detection. In at least one embodiment, the confidence score can be represented or interpreted as a probability, or as providing a relative “weight” for each detection relative to other detections. In at least one embodiment, the confidence score enables the system to make further decisions about which detections should be considered true positives rather than false positives. For example, in at least one embodiment, the system can set a threshold for the confidence score and only consider detections exceeding the threshold as true positives. In embodiments using an Automatic Emergency Braking (“AEB”) system, false positives would cause the vehicle to automatically perform emergency braking, which is obviously undesirable. In at least one embodiment, a highly confident detection can be considered a trigger for AEB. In at least one embodiment, the DLA can run a neural network for regressing the confidence score value. In at least one embodiment, the neural network may take at least a subset of parameters as its input, such as bounding box size, obtained ground plane estimate (e.g., from another subsystem), and outputs of one or more IMU sensors 966 related to the vehicle 900 orientation, distance, and 3D position estimate of the object obtained from the neural network and / or other sensors (e.g., one or more LiDAR sensors 964 or one or more RADAR sensors 960).

[0170] In at least one embodiment, one or more SoCs 904 (e.g., a hardware acceleration cluster) may include one or more data storage devices 916 (e.g., memory). In at least one embodiment, one or more data storage devices 916 may be on-chip memory of one or more SoCs 904, which may store neural networks to be executed on one or more GPUs 908 and / or DLAs. In at least one embodiment, one or more data storage devices 916 may have a sufficiently large capacity to store multiple instances of the neural network for redundancy and security. In at least one embodiment, one or more data storage devices 912 may include L2 or L3 caches.

[0171] In at least one embodiment, one or more SoCs 904 may include any number of processors 910 (e.g., embedded processors). One or more processors 910 may include a startup and power management processor, which may be a dedicated processor and subsystem to handle startup power and management functions, as well as associated security implementations. In at least one embodiment, the startup and power management processor may be part of a startup sequence of one or more SoCs 904s and may provide runtime power management services. In at least one embodiment, the startup power and management processor may provide clock and voltage programming, assist system low-power state transitions, thermal and temperature sensor management of one or more SoCs 904s, and / or power state management of one or more SoCs 904s. In at least one embodiment, each temperature sensor may be implemented with its output frequency proportional to temperature, and one or more SoCs 904s may use the ring oscillator to detect the temperature of one or more CPUs 906s, one or more GPUs 908s, and / or one or more accelerators 914s. In at least one embodiment, if it is determined that the temperature exceeds a threshold, the startup and power management processor may enter a temperature fault routine and place one or more SoCs 904s into a lower power state and / or place the vehicle 900 into a safe stopping pattern for the driver (e.g., bring the vehicle 900 to a safe stop).

[0172] In at least one embodiment, one or more processors 910 may further include a set of embedded processors that can be used as an audio processing engine. In at least one embodiment, the audio processing engine may be an audio subsystem capable of providing full hardware support for multi-channel audio through multiple interfaces and a wide and flexible range of audio I / O interfaces. In at least one embodiment, the audio processing engine is a dedicated processor core with a digital signal processor with dedicated RAM.

[0173] In at least one embodiment, one or more processors 910 may further include an always-on processor engine. In at least one embodiment, the automatic processing engine may provide the necessary hardware features to support low-power sensor management and wake-up use cases. In at least one embodiment, the processor on the always-on processor engine may include, but is not limited to, a processor core, tightly coupled RAM, support for peripherals (e.g., timers and interrupt controllers), various I / O controller peripherals, and routing logic.

[0174] In at least one embodiment, one or more processors 910 may further include a secure clustering engine, which includes, but is not limited to, a dedicated processor subsystem for handling security management of automotive applications. In at least one embodiment, the secure clustering engine may include, but is not limited to, two or more processor cores, tightly coupled RAM, supporting peripherals (e.g., timers, interrupt controllers, etc.) and / or routing logic. In secure mode, in at least one embodiment, the two or more cores may operate in lockstep mode and may be used as a single core with comparison logic for detecting any differences between their operations. In at least one embodiment, one or more processors 910 may further include a real-time camera engine, which may include, but is not limited to, a dedicated processor subsystem for handling real-time camera management. In at least one embodiment, one or more processors 910 may further include a high dynamic range signal processor, which may include, but is not limited to, an image signal processor, which is a hardware engine as part of the camera processing pipeline.

[0175] In at least one embodiment, one or more processors 910 may include a video image synthesizer, which may be a processing block (e.g., implemented on a microprocessor) that implements video post-processing functions required by the video playback application to produce the final video for the player window. In at least one embodiment, the video image synthesizer may perform lens distortion correction on one or more wide-angle cameras 970, one or more surround cameras 974, and / or one or more cabin monitoring camera sensors. In at least one embodiment, preferably, the cabin monitoring camera sensors are monitored by a neural network running on another instance of the SoC 904, the neural network being configured to recognize cabin events and respond accordingly. In at least one embodiment, the cabin system may perform, but is not limited to, lip reading to activate cellular service and make phone calls, instruct emails, change the vehicle's destination, activate or change the vehicle's infotainment system and settings, or provide voice-activated web browsing. In at least one embodiment, certain functions are available to the driver when the vehicle is operating in autonomous mode, and are otherwise disabled.

[0176] In at least one embodiment, the video image synthesizer may include enhanced temporal denoising for simultaneous spatial and temporal denoising. For example, in at least one embodiment, when motion occurs in the video, denoising appropriately weights spatial information, thereby reducing the weight of information provided by adjacent frames. In at least one embodiment, when the image or a portion of the image does not contain motion, temporal denoising performed by the video image synthesizer may use information from previous images to reduce noise in the current image.

[0177] In at least one embodiment, the video image compositor can also be configured to perform stereoscopic correction on the input stereo lens frames. In at least one embodiment, when using an operating system desktop, the video image compositor can also be used for user interface compositing and does not require one or more GPUs 908 to continuously render new surfaces. In at least one embodiment, when one or more GPUs 908 are powered and actively performing 3D rendering, the video image compositor can be used to offload one or more GPUs 908 to improve performance and responsiveness.

[0178] In at least one embodiment, one or more SoCs of SoC 904 may further include a Mobile Industrial Processor Interface (“MIPI”) camera serial interface, a high-speed interface, and / or a video input block that can be used for receiving video and input from a camera and associated pixel input functions. In at least one embodiment, one or more SoCs of SoC 904 may further include an input / output controller that can be software controlled and can be used to receive I / O signals not assigned to a specific role.

[0179] In at least one embodiment, one or more SoCs 904 may further include extensive peripheral interfaces to enable communication with peripheral devices, audio encoders / decoders (“codecs”), power management and / or other devices. One or more SoCs 904 may be used to process data from (e.g., via gigabit multimedia serial links and Ethernet connections) cameras, sensors (e.g., one or more LiDAR sensors 964, one or more RADAR sensors 960, etc., which may be connected via Ethernet), data from bus 902 (e.g., vehicle 900 speed, steering wheel position, etc.), data from one or more GNSS sensors 958 (e.g., via Ethernet bus or CAN bus connections), etc. In at least one embodiment, one or more SoCs 904 may further include a dedicated high-performance mass storage controller, which may include its own DMA engine and may be used to free one or more CPUs 806 from routine data management tasks.

[0180] In at least one embodiment, one or more SoCs 904 can be an end-to-end platform with a flexible architecture spanning automation levels 3-5, providing a comprehensive functional safety architecture that leverages and effectively utilizes computer vision and ADAS technologies to achieve diversity and redundancy. This provides a platform offering a flexible and reliable driving software stack as well as deep learning tools. In at least one embodiment, one or more SoCs 904 can be faster, more reliable, and even more energy and space efficient than conventional systems. For example, in at least one embodiment, one or more accelerators 914, when combined with one or more CPUs 906, one or more GPUs 908, and one or more data storage devices 916, can provide a fast and efficient platform for Level 3-5 autonomous vehicles.

[0181] In at least one embodiment, the computer vision algorithm can be executed on a CPU, which can be configured using a high-level programming language (such as C) to execute multiple processing algorithms on a variety of visual data. However, in at least one embodiment, the CPU typically cannot meet the performance requirements of many computer vision applications, such as performance requirements related to execution time and power consumption. In at least one embodiment, many CPUs cannot execute complex object detection algorithms in real time, which are used in automotive ADAS applications and practical Level 3-5 autonomous vehicles.

[0182] The embodiments described herein allow multiple neural networks to be executed simultaneously and / or sequentially, and allow the results to be combined to achieve Level 3-5 autonomous driving capabilities. For example, in at least one embodiment, a CNN executed on a DLA or discrete GPU (e.g., one or more GPU 920s) may include text and word recognition, thereby allowing a supercomputer to read and understand traffic signs, including signs for which the neural network has not yet been specifically trained. In at least one embodiment, the DLA may also include a neural network capable of recognizing, interpreting, and providing semantic understanding of symbols, and passing this semantic understanding to a path planning module running on a CPU Complex.

[0183] In at least one embodiment, for drives of levels 3, 4, or 5, multiple neural networks can run simultaneously. For example, in at least one embodiment, a warning sign consisting of a light bulb and the warning sign “Caution: flashing lights indicate icy conditions” can be interpreted independently or jointly by multiple neural networks. In at least one embodiment, the sign itself can be recognized as a traffic sign by a first deployed neural network (e.g., a trained neural network), and the text “flashing lights indicate icy conditions” can be interpreted by a second deployed neural network, which informs the vehicle’s path planning software (preferably executed on a CPU Complex) that icing conditions exist when flashing lights are detected. In at least one embodiment, flashing lights can be identified by operating a third deployed neural network across multiple frames, informing the vehicle’s path planning software of the presence (or absence) of flashing lights. In at least one embodiment, all three neural networks can run simultaneously, for example within a DLA and / or on one or more GPUs 908.

[0184] In at least one embodiment, the CNN for facial recognition and vehicle owner identification can use data from camera sensors to identify the presence of an authorized driver and / or the owner of vehicle 900. In at least one embodiment, a normally open sensor processor engine can be used to unlock the vehicle when the owner approaches the driver's door and turns on the lights, and, in security mode, can be used to disable the vehicle when the owner leaves it. In this way, one or more SoCs 904 provide protection against theft and / or carjacking.

[0185] In at least one embodiment, the CNN for emergency vehicle detection and identification can use data from microphone 996 to detect and identify emergency vehicle sirens. In at least one embodiment, one or more SoCs 904 use the CNN to classify environmental and urban sounds, as well as visual data. In at least one embodiment, the CNN running on DLA is trained to identify the relative approach speed of emergency vehicles (e.g., by using the Doppler effect). In at least one embodiment, the CNN can also be trained to identify emergency vehicles in the area where the vehicle is operating, as identified by one or more GNSS sensors 958. In at least one embodiment, when operating in Europe, the CNN will seek to detect European sirens, while when operating in the United States, the CNN will seek to identify only North American sirens. In at least one embodiment, once an emergency vehicle is detected, a control program can be used, with the assistance of one or more ultrasonic sensors 962, to execute emergency vehicle safety routines, slow the vehicle, pull the vehicle to the side of the road, stop, and / or leave the vehicle idle until the emergency vehicle passes.

[0186] In at least one embodiment, vehicle 900 may include one or more CPUs 918 (e.g., one or more discrete CPUs or one or more dCPUs) that may be coupled to one or more SoCs 904 via high-speed interconnects (e.g., PCIe). In at least one embodiment, one or more CPUs 918 may include x86 processors. For example, one or more CPUs 918 may be used to perform any of the various functions, such as arbitrating the results of potential inconsistencies between ADAS sensors and one or more SoCs 904, and / or monitoring the status and health of one or more monitoring controllers 936 and / or on-chip information systems (“information SoCs”) 930.

[0187] In at least one embodiment, the vehicle 900 may include one or more GPUs 920 (e.g., one or more discrete GPUs or one or more dGPUs) that may be coupled to one or more SoCs 904 via a high-speed interconnect (e.g., NVIDIA's NVLINK). In at least one embodiment, the one or more GPUs 920 may provide additional artificial intelligence capabilities, such as by executing redundant and / or different neural networks, and may be used to train and / or update the neural networks based at least in part on inputs from sensors of the vehicle 900 (e.g., sensor data).

[0188] In at least one embodiment, vehicle 900 may further include a network interface 924, which may include, but is not limited to, one or more wireless antennas 926 (e.g., one or more wireless antennas 926 for different communication protocols, such as cellular antennas, Bluetooth antennas, etc.). In at least one embodiment, network interface 924 may be used to enable wireless connectivity with other vehicles and / or computing devices (e.g., passenger client devices) via the Internet with a cloud (e.g., employing servers and / or other network devices). In at least one embodiment, for communication with other vehicles, a direct link and / or an indirect link (e.g., via a network and the Internet) may be established between vehicle 900 and other vehicles. A vehicle-to-vehicle communication link may be used to provide a direct link. In at least one embodiment, the vehicle-to-vehicle communication link may provide vehicle 900 with information about vehicles near vehicle 900 (e.g., vehicles in front, to the side, and / or behind vehicle 900). In at least one embodiment, the foregoing functionality may be part of a cooperative adaptive cruise control function of vehicle 900.

[0189] In at least one embodiment, network interface 924 may include a System-on-Chip (SoC) that provides modulation and demodulation functions and enables one or more controllers 936 to communicate over a wireless network. In at least one embodiment, network interface 924 may include a radio frequency (RF) front-end for up-conversion from baseband to radio frequency (RF) and down-conversion from RF to baseband. In at least one embodiment, frequency conversion may be performed in any technically feasible manner. For example, frequency conversion may be performed using known processes and / or using a superheterodyne process. In at least one embodiment, the RF front-end functionality may be provided by a separate chip. In at least one embodiment, the network interface may include wireless functions for communication over LTE, WCDMA, UMTS, GSM, CDMA2000, Bluetooth, Bluetooth LE, Wi-Fi, Z-Wave, ZigBee, LoRaWAN, and / or other wireless protocols.

[0190] In at least one embodiment, the vehicle 900 may further include one or more data storage 928, which may include, but is not limited to, off-chip (e.g., one or more SoC 904) storage. In at least one embodiment, the one or more data storage 928 may include, but is not limited to, one or more storage elements, including RAM, SRAM, dynamic random access memory (“DRAM”), video random access memory (“VRAM”), flash memory, hard disk and / or other components and / or devices capable of storing at least one bit of data.

[0191] In at least one embodiment, the vehicle 900 may further include one or more GNSS sensors 958 (e.g., GPS and / or auxiliary GPS sensors) to assist in map creation, perception, occupancy raster generation, and / or path planning functions. In at least one embodiment, any number of GNSS sensors 958 may be used, including, for example, but not limited to, GPS sensors connected to a serial interface (e.g., RS-232) bridge using a USB connector with Ethernet.

[0192] In at least one embodiment, vehicle 900 may further include one or more RADAR sensors 960. One or more RADAR sensors 960 can be used by vehicle 900 for remote vehicle detection, even in dark and / or inclement weather conditions. In at least one embodiment, the RADAR functional safety level may be ASIL B. One or more RADAR sensors 960 may use a CAN bus and / or bus 902 (e.g., to transmit data generated by one or more RADAR sensors 960) for control and access to object tracking data, and in some examples, may have access to an Ethernet channel to access raw data. In at least one embodiment, a wide variety of RADAR sensor types can be used. For example, but not limited to, one or more of the RADAR sensors 960 may be suitable for front, rear, and side RADAR use. In at least one embodiment, one or more RADAR sensors 960 are pulse Doppler RADAR sensors.

[0193] In at least one embodiment, one or more RADAR sensors 960 may include different configurations, such as long-range with a narrow field of view, short-range with a wide field of view, short-range side coverage, etc. In at least one embodiment, the long-range RADAR can be used for adaptive cruise control functions. In at least one embodiment, the long-range RADAR system can provide a wide field of view achieved through two or more independent scans (e.g., within a 250m range). In at least one embodiment, one or more RADAR sensors 960 can help distinguish between stationary and moving objects and can be used by the ADAS system 938 for emergency braking assistance and forward collision warning. One or more sensors 960 included in the long-range RADAR system may include, but are not limited to, a monostatic multimode RADAR with multiple (e.g., six or more) fixed RADAR antennas and high-speed CAN and FlexRay interfaces. In at least one embodiment, having six antennas, with the four central antennas creating a focused beammap designed to record the vehicle 900's surroundings at a high speed while minimizing traffic interference from adjacent lanes. In at least one embodiment, the other two antennas can expand the field of view, thereby enabling rapid detection of lanes entering or leaving the vehicle 900.

[0194] In at least one embodiment, as an example, a mid-range RADAR system may include, for example, a range of up to 160m (front) or 80m (rear), and a field of view of up to 42 degrees (front) or 150 degrees (rear). In at least one embodiment, a short-range RADAR system may include, but is not limited to, any number of RADAR sensors 960 designed to be mounted at both ends of the rear bumper. When mounted at both ends of the rear bumper, in at least one embodiment, the RADAR sensor system may generate two beams that continuously monitor the blind spots at and near the rear of the vehicle. In at least one embodiment, the short-range RADAR system may be used in ADAS system 938 for blind spot detection and / or lane change assistance.

[0195] In at least one embodiment, the vehicle 900 may further include one or more ultrasonic sensors 962. One or more ultrasonic sensors 962, which may be positioned at the front, rear, and / or sides of the vehicle 900, can be used for parking assistance and / or creating and updating occupancy detectors. In at least one embodiment, a wide variety of ultrasonic sensors 962 can be used, and different ultrasonic sensors 962 can be used for different detection ranges (e.g., 2.5m, 4m). In at least one embodiment, the ultrasonic sensors 962 can operate at the ASIL B functional safety level.

[0196] In at least one embodiment, vehicle 900 may include one or more LiDAR sensors 964. The one or more LiDAR sensors 964 may be used for object and pedestrian detection, emergency braking, collision avoidance, and / or other functions. In at least one embodiment, the one or more LiDAR sensors 964 may be of functional safety level ASIL B. In at least one embodiment, vehicle 900 may include multiple (e.g., two, four, six, etc.) LiDAR sensors 964 that can use Ethernet (e.g., providing data to a Gigabit Ethernet switch).

[0197] In at least one embodiment, one or more LiDAR sensors 964 may be able to provide a list of objects and their distances for a 360-degree field of view. In at least one embodiment, one or more commercially available LiDAR sensors 964 may, for example, have an advertising range of approximately 100m, an accuracy of 2cm-3cm, and support a 100Mbps Ethernet connection. In at least one embodiment, one or more non-protruding LiDAR sensors 964 may be used. In such embodiments, one or more LiDAR sensors 964 may be implemented as small devices embedded in the front, rear, sides, and / or corners of a vehicle 900. In at least one embodiment, one or more LiDAR sensors 964, in such embodiments, can provide a horizontal field of view of up to 120 degrees and a vertical field of view of 35 degrees, even for objects with low reflectivity, and have a range of 200m. In at least one embodiment, one or more forward-facing LiDAR sensors 964 may be configured for a horizontal field of view between 45 degrees and 135 degrees.

[0198] In at least one embodiment, LIDAR technology (such as 3D flash LIDAR) may also be used. 3D flash LIDAR uses a laser flash as a transmission source to illuminate approximately 200m around the vehicle 900. In at least one embodiment, the flash LIDAR unit includes, but is not limited to, a receiver that records the laser pulse propagation time and reflected light on each pixel, which in turn corresponds to the range from the vehicle 900 to the object. In at least one embodiment, flash LIDAR can allow the generation of highly accurate and distortion-free images of the surrounding environment using each laser flash. In at least one embodiment, four flash LIDAR sensors may be deployed, one on each side of the vehicle 900. In at least one embodiment, the 3D flash LIDAR system includes, but is not limited to, a solid-state 3D line-of-sight array LIDAR camera with no moving parts other than a fan (e.g., a non-scanning LIDAR device). In at least one embodiment, the flash LIDAR device can use a 5-nanosecond Class I (eye-safe) laser pulse per frame and can capture reflected laser light in the form of a 3D ranging point cloud and co-registered intensity data.

[0199] In at least one embodiment, the vehicle 900 may further include one or more IMU sensors 966. In at least one embodiment, the one or more IMU sensors 966 may be located at the center of the rear axle of the vehicle 900. In at least one embodiment, the one or more IMU sensors 966 may include, for example, but not limited to, one or more accelerometers, one or more magnetometers, one or more gyroscopes, one or more magnetic compasses, and / or other sensor types. In at least one embodiment, for example in a six-axis application, the one or more IMU sensors 966 may include, but are not limited to, accelerometers and gyroscopes. In at least one embodiment, for example in a nine-axis application, the one or more IMU sensors 966 may include, but are not limited to, accelerometers, gyroscopes, and magnetometers.

[0200] In at least one embodiment, one or more IMU sensors 966 may be implemented as a miniature, high-performance GPS-assisted inertial navigation system (“GPS / INS”) combining a microelectromechanical system (“MEMS”) inertial sensor, a high-sensitivity GPS receiver, and an advanced Kalman filtering algorithm to provide position, velocity, and attitude estimations; in at least one embodiment, one or more IMU sensors 966 may enable vehicle 900 to estimate heading without input from a magnetic sensor obtained by directly observing and correlating velocity changes from GPS to one or more IMU sensors 966. In at least one embodiment, one or more IMU sensors 966 and one or more GNSS sensors 958 may be combined in a single integrated unit.

[0201] In at least one embodiment, vehicle 900 may include one or more microphones 996 placed inside and / or around vehicle 900. In at least one embodiment, in addition, one or more microphones 996 may be used for emergency vehicle detection and identification.

[0202] In at least one embodiment, vehicle 900 may further include any number of camera types, including one or more stereo cameras 968, one or more wide-angle cameras 970, one or more infrared cameras 972, one or more surround cameras 974, one or more long-range cameras 998, one or more mid-range cameras 976, and / or other camera types. In at least one embodiment, the cameras can be used to capture image data around the entire perimeter of vehicle 900. In at least one embodiment, the type of camera used depends on vehicle 900. In at least one embodiment, any combination of camera types can be used to provide the necessary coverage around vehicle 900. In at least one embodiment, the number of cameras deployed may vary depending on the embodiment. For example, in at least one embodiment, vehicle 900 may include six cameras, seven cameras, ten cameras, twelve cameras, or other numbers of cameras. The cameras may be examples, but are not limited to, supporting Gigabit Multimedia Serial Link (“GMSL”) and / or Gigabit Ethernet. In at least one embodiment, references previously made herein... Figure 9A and Figure 9B Each camera can be described in more detail.

[0203] In at least one embodiment, the vehicle 900 may further include one or more vibration sensors 942. The one or more vibration sensors 942 can measure vibrations of components of the vehicle 900 (e.g., axles). For example, in at least one embodiment, changes in vibration can indicate changes in road surface conditions. In at least one embodiment, when two or more vibration sensors 942 are used, differences between vibrations can be used to determine road surface friction or slippage (e.g., when there is a vibration difference between a power drive axle and a free-rotating axle).

[0204] In at least one embodiment, vehicle 900 may include ADAS system 938. ADAS system 938 may include, but is not limited to, SoC. In at least one embodiment, ADAS system 938 may include, but is not limited to, any number of autonomous / adaptive / automatic cruise control (“ACC”) systems, cooperative adaptive cruise control (“CACC”) systems, forward collision warning (“FCW”) systems, automatic emergency braking (“AEB”) systems, lane departure warning (“LDW”) systems, lane keeping assist (“LKA”) systems, blind spot warning (“BSW”) systems, rear cross traffic warning (“RCTW”) systems, collision warning (“CW”) systems, lane centering (“LC”) systems, and / or other systems, features, and / or functions, and combinations thereof.

[0205] In at least one embodiment, the ACC system may use one or more RADAR sensors 960, one or more LIDAR sensors 964, and / or any number of cameras. In at least one embodiment, the ACC system may include a longitudinal ACC system and / or a lateral ACC system. In at least one embodiment, the longitudinal ACC system monitors and controls the distance to the vehicle in front of the adjacent vehicle 900 and automatically adjusts the speed of the vehicle 900 to maintain a safe distance from the vehicle in front. In at least one embodiment, the lateral ACC system performs distance holding and suggests that the vehicle 900 change lanes when necessary. In at least one embodiment, the lateral ACC is associated with other ADAS applications, such as LC and CW.

[0206] In at least one embodiment, the CACC system uses information from other vehicles, which may be received from other vehicles via network interface 924 and / or one or more wireless antennas 926 via a wireless link or indirectly via a network connection (e.g., via the Internet). In at least one embodiment, the direct link may be provided by a vehicle-to-vehicle (“V2V”) communication link, while the indirect link may be provided by an infrastructure-to-vehicle (“I2V”) communication link. Typically, the V2V communication concept provides information about the vehicle immediately preceding it (e.g., a vehicle immediately in front of vehicle 900 and in the same lane as it), while the I2V communication concept provides information about traffic further ahead. In at least one embodiment, the CACC system may include one or both of the I2V and V2V information sources. In at least one embodiment, given information about vehicles preceding vehicle 900, the CACC system can be more reliable and has the potential to improve traffic flow smoothness and reduce road congestion.

[0207] In at least one embodiment, the FCW system is designed to warn the driver of danger so that the driver can take corrective action. In at least one embodiment, the FCW system uses a forward-facing camera and / or one or more RADAR sensors 960, coupled to a dedicated processor, DSP, FPGA, and / or ASIC, electrically coupled to driver feedback, such as a display, speaker, and / or vibration components. In at least one embodiment, the FCW system can provide warnings, for example, in the form of audible, visual warnings, vibrations, and / or rapid braking pulses.

[0208] In at least one embodiment, the AEB system detects an impending forward collision with another vehicle or other object and can automatically apply brakes if the driver does not take corrective action within a specified time or distance parameter. In at least one embodiment, the AEB system may use one or more forward-facing cameras and / or one or more RADAR sensors 960 coupled to a dedicated processor, DSP, FPGA, and / or ASIC. In at least one embodiment, when the AEB system detects a hazard, it typically first warns the driver to take corrective action to avoid a collision, and if the driver does not take corrective action, the AEB system may automatically apply brakes to attempt to prevent or at least mitigate the effects of the predicted collision. In at least one embodiment, the AEB system may include techniques such as dynamic braking to support and / or brakes for impending collisions.

[0209] In at least one embodiment, when vehicle 900 crosses lane markings, the LDW system provides visual, auditory, and / or tactile warnings, such as steering wheel or seat vibrations, to alert the driver. In at least one embodiment, the LDW system is inactive when the driver indicates intentional lane departure, such as by activating turn signals. In at least one embodiment, the LDW system may use a front-facing camera coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which is electrically coupled to driver feedback such as a display, speaker, and / or vibration components. In at least one embodiment, the LKA system is a variant of the LDW system. If vehicle 900 begins to leave the lane, the LKA system provides steering input or braking to correct vehicle 900.

[0210] In at least one embodiment, the BSW system detects and warns the driver of a vehicle in the blind spot. In at least one embodiment, the BSW system can provide visual, auditory, and / or tactile alerts to indicate that merging or changing lanes is unsafe. In at least one embodiment, the BSW system can provide additional warnings when the driver uses the turn signal. In at least one embodiment, the BSW system can use one or more rear-facing cameras and / or one or more RADAR sensors 960 coupled to a dedicated processor, DSP, FPGA, and / or ASIC, electrically coupled to driver feedback, such as a display, speaker, and / or vibration assembly.

[0211] In at least one embodiment, the RCTW system can provide visual, auditory, and / or tactile notifications when an object is detected outside the range of the rear camera while the vehicle 900 is reversing. In at least one embodiment, the RCTW system includes an AEB system to ensure the vehicle brakes to avoid a collision. In at least one embodiment, the RCTW system may use one or more rear-facing RADAR sensors 960 coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which are electrically coupled to driver feedback such as a display, speaker, and / or vibration assembly.

[0212] In at least one embodiment, conventional ADAS systems may be prone to generating false alarms, which can be annoying and distracting to the driver, but are generally not catastrophic because conventional ADAS systems alert the driver and allow the driver to determine whether a safe situation truly exists and take appropriate action. In at least one embodiment, in the event of conflicting results, the vehicle 900 itself decides whether to follow the result of the primary computer or the secondary computer (e.g., the first controller 936 or the second controller 936). For example, in at least one embodiment, ADAS system 938 may be a backup and / or auxiliary computer for providing perception information to a backup computer rationality module. In at least one embodiment, the backup computer rationality monitor may run redundant software on hardware components to detect faults in perception and dynamic driving tasks. In at least one embodiment, output from ADAS system 938 may be provided to a monitoring MCU. In at least one embodiment, if there are conflicting outputs from the primary computer and the auxiliary computer, the monitoring MCU decides how to reconcile the conflict to ensure safe operation.

[0213] In at least one embodiment, the master computer may be configured to provide a confidence score to the supervisory MCU to indicate the master computer's confidence in the selected result. In at least one embodiment, if the confidence score exceeds a threshold, the supervisory MCU may follow the master computer's instructions regardless of whether the auxiliary computer provides conflicting or inconsistent results. In at least one embodiment, if the confidence score does not meet the threshold, and if the master computer and the auxiliary computer indicate different results (e.g., conflict), the supervisory MCU may arbitrate between the computers to determine the appropriate result.

[0214] In at least one embodiment, the supervisory MCU may be configured to run a neural network trained and configured to determine, at least in part, the conditions under which the auxiliary computer provides a false alarm based on outputs from both the host computer and the auxiliary computer. In at least one embodiment, the neural network in the supervisory MCU may learn when the output of the auxiliary computer can be trusted and when it cannot. For example, in at least one embodiment, when the auxiliary computer is a RADAR-based FCW system, the neural network in the supervisory MCU may learn when the FCW system identifies a metallic object that is not actually dangerous, such as a drain grat or manhole cover that would trigger an alarm. In at least one embodiment, when the auxiliary computer is a camera-based LDW system, the neural network in the supervisory MCU may learn to override the LDW when a cyclist or pedestrian is present and lane departure is actually the safest operation. In at least one embodiment, the supervisory MCU may include at least one of a DLA or GPU suitable for running a neural network with associated memory. In at least one embodiment, the supervisory MCU may include and / or be included as a component of one or more SoC 904s.

[0215] In at least one embodiment, the ADAS system 938 may include an auxiliary computer that performs ADAS functions using conventional computer vision rules. In at least one embodiment, the auxiliary computer may use classic computer vision rules (if-then), and the presence of a neural network in the supervisory MCU can improve reliability, security, and performance. For example, in at least one embodiment, diverse implementations and intentional non-identity make the entire system more fault-tolerant, especially for failures caused by software (or software-hardware interface) functionality. For example, in at least one embodiment, if a software vulnerability or bug exists in the software running on the host computer, and different software code running on the auxiliary computer provides the same overall result, the supervisory MCU can more confidently assume that the overall result is correct and that the vulnerability in the software or hardware on the host computer will not lead to a significant error.

[0216] In at least one embodiment, the output of the ADAS system 938 can be input to the perception module and / or the dynamic driving task module of the main computer. For example, in at least one embodiment, if the ADAS system 938 indicates a forward collision warning due to an object directly ahead, the perception block can use this information when identifying the object. In at least one embodiment, as described herein, the assistance computer can have its own neural network trained to reduce the risk of false alarms.

[0217] In at least one embodiment, vehicle 900 may further include an infotainment SoC 930 (e.g., an in-vehicle infotainment system (IVI)). Although shown and described as an SoC, in at least one embodiment, infotainment system 930 may not be an SoC and may include, but is not limited to, two or more discrete components. In at least one embodiment, infotainment SoC 930 may include, but is not limited to, a combination of hardware and software that can be used to provide audio (e.g., music, personal digital assistant, navigation instructions, news, radio, etc.), video (e.g., television, movies, streaming media, etc.), telephone (e.g., hands-free calling), network connectivity (e.g., LTE, WiFi, etc.) and / or information services (e.g., navigation system, rear parking assist, radio data system, vehicle-related information such as fuel level, total coverage distance, brake fuel level, fuel level, door opening / closing, air filter information, etc.) to vehicle 900. For example, the infotainment SoC 930 may include a radio, disk player, navigation system, video player, USB and Bluetooth connectivity, automobile, in-vehicle entertainment system, WiFi, steering wheel audio controls, hands-free voice control, head-up display (“HUD”), HMI display 934, telematics device, control panel (e.g., for controlling and / or interacting with various components, features and / or systems) and / or other components. In at least one embodiment, the infotainment SoC 930 may further be used to provide information (e.g., visual and / or auditory) to users of the vehicle, such as information from ADAS system 938, autonomous driving information (such as planned vehicle maneuvers), trajectory, surrounding environment information (e.g., intersection information, vehicle information, road information, etc.) and / or other information.

[0218] In at least one embodiment, the infotainment SoC 930 may include any number and type of GPU functionality. In at least one embodiment, the infotainment SoC 930 may communicate with other devices, systems, and / or components of the vehicle 900 via a bus 902 (e.g., CAN bus, Ethernet, etc.). In at least one embodiment, the infotainment SoC 930 may be coupled to a monitoring MCU, enabling the GPU of the infotainment system to perform some autonomous driving functions in the event of a failure of the main controller 936 (e.g., the main computer and / or backup computer of the vehicle 900). In at least one embodiment, the infotainment SoC 930 may cause the vehicle 900 to enter a driver-to-safe-stop mode, as described herein.

[0219] In at least one embodiment, vehicle 900 may further include instrument panel 932 (e.g., digital instrument panel, electronic instrument panel, digital instrument control panel, etc.). In at least one embodiment, instrument panel 932 may include, but is not limited to, controllers and / or supercomputers (e.g., discrete controllers or supercomputers). Instrument panel 932 may include, but is not limited to, any number and combination of a set of instruments, such as speedometer, fuel level, oil pressure, tachometer, odometer, turn indicator, shift position indicator, one or more seatbelt warning lights, one or more parking brake warning lights, one or more engine malfunction lights, auxiliary restraint system (e.g., airbag) information, lighting controls, safety system controls, navigation information, etc. In some examples, information may be displayed and / or shared between infotainment SoC 930 and instrument panel 932. In at least one embodiment, instrument panel 932 may be included as part of infotainment SoC 930, or vice versa.

[0220] In at least one embodiment, wireless data transmission in the autonomous vehicle 900 is performed by a processor, processing core, or circuitry to generate device packets in parallel to utilize the frequency band and select one of the generated packets.

[0221] Figure 9D It is based on at least one embodiment in a cloud-based server and Figure 9AA diagram of a system 967 for communication between autonomous vehicles 900. In at least one embodiment, system 967 may include, but is not limited to, one or more servers 978, one or more networks 990, and any number and type of vehicles, including vehicle 900. One or more servers 978 may include, but are not limited to, multiple GPUs 984(A)-984(H) (collectively referred to herein as GPU 984), PCIe switches 982(A)-982(D) (collectively referred to herein as PCIe switch 982), and / or CPUs 980(A)-980(B) (collectively referred to herein as CPU 980). GPU 984, CPU 980, and PCIe switch 982 may be interconnected with high-speed interconnects, such as, but not limited to, NVLink interface 988 developed by NVIDIA and / or PCIe connection 986. GPU 984 is connected via NVLink and / or NVSwitchSoC, and GPU 984 and PCIe switch 982 are connected via PCIe interconnect. In at least one embodiment, although eight GPUs 984, two CPUs 980, and four PCIe switches 982 are shown, this is not intended to be limiting. In at least one embodiment, each of one or more servers 978 may include, but is not limited to, any combination of any number of GPUs 984, CPUs 980, and / or PCIe switches 982. For example, in at least one embodiment, one or more servers 978 may each include eight, sixteen, thirty-two, and / or more GPUs 984.

[0222] In at least one embodiment, one or more servers 978 may receive image data representing an image from a vehicle via one or more networks 990, the image showing unexpected or changed road conditions, such as recently commenced roadworks. In at least one embodiment, one or more servers 978 may transmit a neural network 992, an updated neural network 992, and / or map information 994, including but not limited to information about traffic and road conditions, to the vehicle via one or more networks 990. In at least one embodiment, updates to the map information 994 may include, but are not limited to, updates to an HD map 922, such as information about construction sites, potholes, sidewalks, floods, and / or other obstacles. In at least one embodiment, the neural network 992, the updated neural network 992, and / or map information 994 may be generated from new training and / or experience represented by data received from any number of vehicles in the environment, and / or at least based on training performed in a data center (e.g., using one or more servers 978 and / or other servers).

[0223] In at least one embodiment, one or more servers 978 can be used to train a machine learning model (e.g., a neural network) at least in part based on training data. The training data may be generated by the vehicle and / or may be generated in a simulation (e.g., using a game engine). In at least one embodiment, any amount of training data is labeled (e.g., where the associated neural network benefits from supervised learning) and / or undergoes other preprocessing. In at least one embodiment, no amount of training data is labeled and / or preprocessed (e.g., where the associated neural network does not require supervised learning). In at least one embodiment, once the machine learning model is trained, the machine learning model can be used by the vehicle (e.g., transmitted to the vehicle via one or more networks 990), and / or the machine learning model can be used by one or more servers 978 to remotely monitor the vehicle.

[0224] In at least one embodiment, one or more servers 978 may receive data from the vehicle and apply the data to state-of-the-art real-time neural networks for real-time intelligent inference. In at least one embodiment, one or more servers 978 may include a deep learning supercomputer and / or a dedicated AI computer powered by one or more GPUs 984, such as the DGX and DGX Station machines developed by NVIDIA. However, in at least one embodiment, one or more servers 978 may include a deep learning infrastructure in a data center using CPU power.

[0225] In at least one embodiment, the deep learning infrastructure of one or more servers 978 may be capable of fast, real-time inference and can use this capability to assess and verify the health of the processor, software, and / or associated hardware in the vehicle 900. For example, in at least one embodiment, the deep learning infrastructure may receive periodic updates from the vehicle 900, such as image sequences and / or objects located by the vehicle 900 in the image sequence (e.g., via computer vision and / or other machine learning object classification techniques). In at least one embodiment, the deep learning infrastructure may run its own neural network to identify objects and compare them with objects identified by the vehicle 900, and if the results do not match and the deep learning infrastructure determines that the AI ​​in the vehicle 900 is malfunctioning, one or more servers 978 may signal to the vehicle 900 to instruct the fail-safe computer of the vehicle 900 to take control, notify passengers, and complete a safe stopping operation.

[0226] In at least one embodiment, one or more servers 978 may include one or more GPUs 984 and one or more programmable inference accelerators (e.g., NVIDIA's TensorRT 3). In at least one embodiment, the combination of GPU-driven servers and inference acceleration enables real-time response. In at least one embodiment, for example, where performance is less critical, servers driven by CPUs, FPGAs, and other processors may be used for inference. In at least one embodiment, hardware architecture 815 is used to execute one or more embodiments. This document incorporates... Figure 8 A and / or Figure 8 B provides details about the 815 hardware architecture.

[0227] Computer System

[0228] Figure 10 This is a block diagram illustrating an exemplary computer system according to at least one embodiment. The exemplary computer system may be a system of interconnected devices and components, a system-on-a-chip (SoC), or some combination thereof formed with a processor, which may include an execution unit to execute instructions. In at least one embodiment, according to this disclosure, such as the embodiments described herein, computer system 1000 may include, but is not limited to, components such as processor 1002, whose execution unit includes logic to execute algorithms for process data. In at least one embodiment, computer system 1000 may include a processor, such as the PENTIUM® processor family or Xeon processor, available from Intel Corporation of Santa Clara, California. TM Itanium®, XScale TM and / or StrongARM TM The system uses an Intel® Core™ or Intel® Nervana™ microprocessor, although other systems (including PCs, engineering workstations, set-top boxes, etc.) with other microprocessors may also be used. In at least one embodiment, the computer system 1000 may execute a version of the Windows operating system available from Microsoft Corporation of Redmond, Wash., although other operating systems (such as UNIX and Linux), embedded software, and / or graphical user interfaces may also be used.

[0229] The embodiments can be used in other devices, such as handheld devices and embedded applications. Some examples of handheld devices include cellular phones, Internet Protocol (IP) devices, digital cameras, personal digital assistants (“PDAs”), and handheld PCs. In at least one embodiment, the embedded application may include a microcontroller, a digital signal processor (“DSP”), a system-on-a-chip (SoC), a network computer (“NetPC”), a set-top box, a network hub, a wide area network (“WAN”) switch, or any other system that can execute one or more instructions according to at least one embodiment.

[0230] In at least one embodiment, computer system 1000 may include, but is not limited to, processor 1002, which may include, but is not limited to, one or more execution units 1008, to perform machine learning model training and / or inference according to the techniques described herein. In at least one embodiment, system 10 is a single-processor desktop or server system, but in another embodiment, system 10 may be a multiprocessor system. In at least one embodiment, processor 1002 may include, but is not limited to, a Complex Instruction Set Computer (“CISC”) microprocessor, a Reduced Instruction Set Computing (“RISC”) microprocessor, a Very Long Instruction Word (“VLIW”) microprocessor, a processor implementing instruction set combination, or any other processor device, such as a digital signal processor. In at least one embodiment, processor 1002 may be coupled to processor bus 1010, which can transmit data signals between processor 1002 and other components in computer system 1000.

[0231] In at least one embodiment, processor 1002 may include, but is not limited to, a Level 1 (“L1”) internal cache memory (“cache”) 1004. In at least one embodiment, processor 1002 may have a single internal cache or multiple levels of internal cache. In at least one embodiment, the cache memory may reside external to processor 1002. Depending on specific implementation and requirements, other embodiments may also include a combination of internal and external caches. In at least one embodiment, register file 1006 may store different types of data in various registers, including but not limited to integer registers, floating-point registers, status registers, and instruction pointer registers.

[0232] In at least one embodiment, an execution unit 1008, including but not limited to logic performing integer and floating-point operations, is also located within processor 1002. Processor 1002 may also include a microcode (“ucode”) read-only memory (“ROM”) for storing microcode of certain macro instructions. In at least one embodiment, execution unit 1008 may include logic for processing a packaged instruction set 1009. In at least one embodiment, by including the packaged instruction set 1009 in the instruction set of a general-purpose processor, along with the associated circuitry for executing the instructions, packaged data in general-purpose processor 1002 can be used to perform operations used by numerous multimedia applications. In one or more embodiments, many multimedia applications can be executed more quickly and efficiently by using the full width of the processor’s data bus to perform operations on the packaged data, which may eliminate the need to transfer smaller data units on the processor’s data bus to perform one or more operations on one data element at a time.

[0233] In at least one embodiment, execution unit 1008 may also be used in a microcontroller, embedded processor, graphics device, DSP, and other types of logic circuitry. In at least one embodiment, computer system 1000 may include, but is not limited to, memory 1020. In at least one embodiment, memory 1020 may be implemented as a dynamic random access memory (“DRAM”) device, a static random access memory (“SRAM”) device, a flash memory device, or other storage device. Memory 1020 may store instructions 1019 and / or data 1021 represented by data signals that can be executed by processor 1002.

[0234] In at least one embodiment, the system logic chip may be coupled to the processor bus 1010 and the memory 1020. In at least one embodiment, the system logic chip may include, but is not limited to, a memory controller hub (“MCH”) 1016, and the processor 1002 may communicate with the MCH 1016 via the processor bus 1010. In at least one embodiment, the MCH 1016 may provide a high-bandwidth memory path 1018 to the memory 1020 for instruction and data storage, as well as for storage of graphics commands, data, and textures. In at least one embodiment, the MCH 1016 may initiate data signals between the processor 1002, the memory 1020, and other components in the computer system 1000, and bridge data signals between the processor bus 1010, the memory 1020, and the system I / O 1022. In at least one embodiment, the system logic chip may provide a graphics port for coupling to a graphics controller. In at least one embodiment, MCH 1016 can be coupled to memory 1020 via high-bandwidth memory path 1018, and graphics / video card 1012 can be coupled to MCH 1016 via Accelerated Graphics Port (“AGP”) interconnect 1014.

[0235] Computer system 1000 can use system I / O 1022, which is a proprietary hub interface bus, to couple MCH 1016 to I / O controller hub (“ICH”) 1030. In at least one embodiment, ICH 1030 can provide direct connectivity to certain I / O devices via a local I / O bus. In at least one embodiment, the local I / O bus may include, but is not limited to, a high-speed I / O bus for connecting peripheral devices to memory 1020, chipset, and processor 1002. Examples may include, but are not limited to, audio controller 1029, firmware hub (“Flash BIOS”) 1028, wireless transceiver 1026, data storage 1024, a conventional I / O controller 1023 including user input and keyboard interfaces, serial expansion port 1027 (e.g., Universal Serial Bus (USB)), and network controller 1034. Data storage 1024 may include hard disk drives, floppy disk drives, CD-ROM devices, flash memory devices, or other mass storage devices.

[0236] In at least one embodiment, Figure 10 A system including interconnected hardware devices or "chips" is shown, while in other embodiments, Figure 10 A system-on-a-chip (SoC) can be shown. In at least one embodiment, Figure 10The devices shown can be interconnected with proprietary interconnects, standardized interconnects (e.g., PCIe), or some combination thereof. In at least one embodiment, one or more components of system 1000 are interconnected using compute fast link (CXL) interconnects.

[0237] In at least one embodiment, wireless data transmission is performed in the autonomous vehicle 900 by a CPU 980 or a GPU 9984, which generates device packets in parallel to utilize the frequency band and selects one of the generated packets.

[0238] Figure 11 This is a block diagram illustrating a computer system 1100 for utilizing processor 1110 according to at least one embodiment. In at least one embodiment, computer system 1100 may be, for example, but not limited to, a laptop computer, tower server, rack server, blade server, laptop computer, desktop computer, tablet computer, mobile device, telephone, embedded computer, or any other suitable electronic device.

[0239] In at least one embodiment, the computer system 1100 may, but is not limited to, a processor 1110 communicatively coupled to any suitable number or type of components, peripherals, modules, or devices. In at least one embodiment, the processor 1110 uses a bus or interface coupling, such as an I²C bus, a system management bus (“SMBus”), a low pin count (LPC) bus, a serial peripheral interface (“SPI”), a high-definition audio (“HDA”) bus, a serial advanced technology accessory (“SATA”) bus, a universal serial bus (“USB”) (versions 1, 2, 3, etc.), or a universal asynchronous receiver / transmitter (“UART”) bus. In at least one embodiment, Figure 11 The system shown includes interconnected hardware devices or "chips," while in other embodiments, Figure 11 An exemplary system-on-a-chip (SoC) can be illustrated. In at least one embodiment, Figure 11 The device shown can be interconnected with proprietary interconnects, standardized interconnects (e.g., PCIe), or some combination thereof. In at least one embodiment, Figure 11 One or more components are interconnected using Computational Fast Link (CXL) interconnects.

[0240] In at least one embodiment, Figure 11This may include a display 1124, a touchscreen 1125, a touchpad 1130, a near-field communication unit (“NFC”) 1145, a sensor hub 1140, a thermal sensor 1139, a fast chipset (“EC”) 1135, a trusted platform module (“TPM”) 1138, a BIOS / firmware / flash memory (“BIOS, FW Flash”) 1122, a DSP 1160, a drive “SSD or HDD” 1120 (e.g., a solid-state drive (“SSD”) or a hard disk drive (“HDD”)), a wireless local area network unit (“WLAN”) 1150, a Bluetooth unit 1152, a wireless wide area network unit (“WWAN”) 1156, a global positioning system (GPS) 1155, a camera (“USB 3.0 camera”) 1154 (e.g., a USB 3.0 camera), or a low-power double data rate (“LPDDR”) memory unit (“LPDDR3”) 1115 implemented in, for example, the LPDDR3 standard. These components may each be implemented in any suitable manner.

[0241] In at least one embodiment, other components may be communicatively coupled to processor 1110 via the components described above. In at least one embodiment, accelerometer 1141, ambient light sensor (“ALS”) 1142, compass 1143, and gyroscope 1144 may be communicatively coupled to sensor hub 1140. In at least one embodiment, thermal sensor 1139, fan 1137, keyboard 1136, and touchpad 1130 may be communicatively coupled to EC 1135. In at least one embodiment, speaker 1163, earphone 1164, and microphone (“mic”) 1165 may be communicatively coupled to audio unit (“audio codec and Class D amplifier” 1162), which in turn may be communicatively coupled to DSP 1160. In at least one embodiment, audio unit may include, for example, but not limited to, audio encoder / decoder (“codec”) and Class D amplifier. In at least one embodiment, SIM card (“SIM”) 1157 may be communicatively coupled to WWAN unit 1156. In at least one embodiment, components such as WLAN unit 1150, Bluetooth unit 1152, and WWAN unit 1156 can be implemented as next-generation form factor (NGFF).

[0242] In at least one embodiment, the computer system 1100 includes a processor 1110 to generate packets of the device in parallel to utilize the frequency band and to select one of the generated packets.

[0243] Figure 12 A computer system 1200 according to at least one embodiment is shown. In at least one embodiment, the computer system 1200 is configured to implement the various processes and methods described in this disclosure.

[0244] In at least one embodiment, the computer system 1200 includes, but is not limited to, at least one central processing unit (“CPU”) 1202 connected to a communication bus 1210 implemented using any suitable protocol, such as PCI (“Peripheral Device Interconnect”), Peripheral Component Interconnect Express (“PCI-Express”), AGP (“Accelerated Graphics Port”), HyperTransport, or any other bus or point-to-point communication protocol. In at least one embodiment, the computer system 1200 includes, but is not limited to, main memory 1204 and control logic (e.g., implemented in hardware, software, or a combination thereof), and data may be stored in main memory 1204 in the form of random access memory (“RAM”). In at least one embodiment, a network interface subsystem (“Network Interface”) 1222 provides an interface to other computing devices and networks for receiving data from the computer system 1200 and transferring data to other systems.

[0245] In at least one embodiment, the computer system 1200 includes, but is not limited to, an input device 1208, a parallel processing system 1212, and a display device 1206, which may be implemented using conventional cathode ray tube (“CRT”), liquid crystal display (“LCD”), light-emitting diode (“LED”), plasma display, or other suitable display technologies. In at least one embodiment, user input is received from the input device 1208 (such as a keyboard, mouse, touchpad, microphone, etc.). In at least one embodiment, each of the foregoing modules may reside on a single semiconductor platform to form the processing system.

[0246] In at least one embodiment, the computer system 1200 includes a CPU 1202 and a PPU 1214 to generate device packets in parallel to utilize the frequency band and select one of the generated packets.

[0247] Figure 13 A computer system 1300 according to at least one embodiment is illustrated. In at least one embodiment, the computer system 1300 includes, but is not limited to, a computer 1310 and a USB stick 1320. In at least one embodiment, the computer 1310 may include, but is not limited to, any number and type of processors (not shown) and memory (not shown). In at least one embodiment, the computer 1310 includes, but is not limited to, a server, a cloud instance, a laptop computer, and a desktop computer.

[0248] In at least one embodiment, the USB stick 1320 includes, but is not limited to, a processing unit 1330, a USB interface 1340, and USB interface logic 1350. In at least one embodiment, the processing unit 1330 can be any instruction execution system, apparatus, or device capable of executing instructions. In at least one embodiment, the processing unit 1330 can include, but is not limited to, any number and type of processing cores (not shown). In at least one embodiment, the processing core 1330 includes an application-specific integrated circuit (“ASIC”) optimized to perform any number and type of operations associated with machine learning. For example, in at least one embodiment, the processing core 1330 is a tensor processing unit (“TPC”) optimized to perform machine learning inference operations. In at least one embodiment, the processing core 1330 is a vision processing unit (“VPU”) optimized to perform machine vision and machine learning inference operations.

[0249] In at least one embodiment, the USB interface 1340 can be any type of USB connector or USB receptacle. For example, in at least one embodiment, the USB interface 1340 is a USB 3.0 Type-C receptacle for data and power. In at least one embodiment, the USB interface 1340 is a USB 3.0 Type-A connector. In at least one embodiment, the USB interface logic 1350 may include any amount and type of logic enabling the processing unit 1330 to connect to a device (e.g., computer 1310) via the USB interface 1340.

[0250] In at least one embodiment, the computer system 1300 includes a processor to generate packets of the device in parallel to utilize the frequency band, and to select one of the generated packets.

[0251] Figure 14A An exemplary architecture is shown in which multiple GPUs 1410-1413 are communicatively coupled to multiple multi-core processors 1405-1406 via high-speed links 1440-1443 (e.g., bus / point-to-point interconnect, etc.). In one embodiment, the high-speed links 1440-1443 support communication throughput of 4GB / s, 30GB / s, 80GB / s, or higher. Various interconnect protocols can be used, including but not limited to PCIe 4.0 or 5.0 and NVLink 2.0.

[0252] Furthermore, in one embodiment, two or more GPUs 1410-1413 are interconnected via high-speed links 1429-1430, which may use the same or different protocols / links as those used for high-speed links 1440-1443. Similarly, two or more multi-core processors 1405-1406 may be connected via high-speed link 1428, which may be a symmetric multiprocessor (SMP) bus operating at speeds of 20GB / s, 30GB / s, 120GB / s, or higher. Alternatively, the same protocol / link (e.g., via a common interconnect structure) may be used. Figure 14A This shows all communication between the various system components.

[0253] In one embodiment, each multi-core processor 1405-1406 is communicatively coupled to processor memories 1401-1402 via memory interconnects 1426-1427, and each GPU 1410-1413 is communicatively coupled to GPU memories 1420-1423 via GPU memory interconnects 1450-1453. Memory interconnects 1426-1427 and 1450-1453 may utilize the same or different memory access technologies. By way of example and not limitation, processor memories 1401-1402 and GPU memories 1420-1423 may be volatile memories, such as dynamic random access memory (DRAM) (including stacked DRAM), graphics DDR SDRAM (GDDR) (e.g., GDDR5, GDDR6), or high-bandwidth memory (HBM), and / or may be non-volatile memories, such as 3D XPoint or Nano-RAM. In one embodiment, some portions of processor memories 1401-1402 may be volatile memory, while other portions may be non-volatile memory (e.g., using a two-level memory (2LM) hierarchy).

[0254] As described in this article, although the various processors 1405-1406 and GPUs 1410-1413 can be physically coupled to specific memories 1401-1402 and 1420-1423 respectively, a unified memory architecture can be implemented, in which the same virtual system address space (also known as the “effective address” space) is distributed across the various physical memories. For example, processor memories 1401-1402 can each contain 64 GB of system memory address space, and GPU memories 1420-1423 can each contain 32 GB of system memory address space (resulting in a total addressable memory size of 256 GB in this example).

[0255] Figure 14BAdditional details are shown regarding the interconnection between a multi-core processor 1407 and a graphics acceleration module 1446 according to an exemplary embodiment. The graphics acceleration module 1446 may include one or more GPU chips integrated on a line card coupled to the processor 1407 via a high-speed link 1440. Alternatively, the graphics acceleration module 1446 may be integrated on the same package or chip as the processor 1407.

[0256] In at least one embodiment, the processor 1407 shown includes a plurality of cores 1460A-1460D, each core having a translation back buffer 1461A-1461D and one or more caches 1462A-1462D. In at least one embodiment, cores 1460A-1460D may include various other components (not shown) for executing instructions and processing data. In at least one embodiment, caches 1462A-1462D may include level 1 (L1) and level 2 (L2) caches. Furthermore, one or more shared caches 1456 may be included in caches 1462A-1462D and shared by the respective groups of cores 1460A-1460D. For example, one embodiment of the processor 1407 includes 24 cores, each core having its own L1 cache, twelve shared L2 caches, and twelve shared L3 caches. In this embodiment, two adjacent cores share one or more L2 and L3 caches. Processor 1407 and graphics acceleration module 1446 are connected to system memory 1414, which may include Figure 14A The processor memory 1401-1402 in the memory.

[0257] Consistency of data and instructions stored in the various caches 1462A-1462D, 1456 and system memory 1414 is maintained via inter-core communication through the consistency bus 1464. For example, each cache may have associated cache consistency logic / circuit to communicate via the consistency bus 1464 in response to the detection of a read or write to a specific cache line. In one implementation, a cache snooping protocol is implemented via the consistency bus 1464 to snoop on cache accesses.

[0258] In one embodiment, proxy circuitry 1425 communicatively couples graphics acceleration module 1446 to coherence bus 1464, thereby allowing graphics acceleration module 1446 to participate in cache coherence protocols as a peer of cores 1460A-1460D. Specifically, in at least one embodiment, interface 1435 provides connectivity to proxy circuitry 1425 via high-speed link 1440 (e.g., PCIe bus, NVLink, etc.), and interface 1437 connects graphics acceleration module 1446 to link 1440.

[0259] In one implementation, the accelerator integrated circuit 1436 represents multiple graphics processing engines 1431, 1432, N of the graphics acceleration module, providing cache management, memory access, context management, and interrupt management services. The graphics processing engines 1431, 1432, N may each include a separate graphics processing unit (GPU). Optionally, the graphics processing engines 1431, 1432, N may selectively include different types of graphics processing engines within the GPU, such as graphics execution units, media processing engines (e.g., video encoders / decoders), samplers, and blit engines. In at least one embodiment, the graphics acceleration module 1446 may be a GPU having multiple graphics processing engines 1431-1432, N, or the graphics processing engines 1431-1432, N may be individual GPUs integrated on a general-purpose package, line card, or chip.

[0260] In one embodiment, the accelerator integrated circuit 1436 includes a memory management unit (MMU) 1439 for performing various memory management functions, such as virtual-to-physical memory translation (also known as effective-to-real memory translation), and a memory access protocol for accessing system memory 1414. The MMU 1439 may also include a translation back buffer (“TLB”) (not shown) for caching virtual / effective-to-physical / real address translations. In one implementation, cache 1438 may store commands and data for effective access by graphics processing engines 1431-1432,N. In at least one embodiment, data stored in cache 1438 and graphics memories 1433-1434,M is kept consistent with core caches 1462A-1462D, 1456 and system memory 1414. As previously mentioned, this task can be accomplished via proxy circuitry 1425 representing cache 1438 and graphics memory 1433-1434, M (e.g., sending updates related to the modification / access of cache lines on processor caches 1462A-1462D, 1456 to cache 1438 and receiving updates from cache 1438).

[0261] A set of registers 1445 stores context data for threads executed by graphics processing engines 1431, 1432, N, and context management circuitry 1448 manages the thread context. For example, context management circuitry 1448 can perform save and restore operations to save and restore the context of individual threads during context switching (e.g., saving the first thread and storing the second thread so that the second thread can be executed by the graphics processing engine). For example, during context switching, context management circuitry 1448 can store the current register value into a designated area in memory (e.g., identified by the context pointer). The register value can then be restored when returning to the context. In one embodiment, interrupt management circuitry 1447 receives and processes interrupts received from system devices.

[0262] In one implementation, MMU 1439 translates virtual / effective addresses from graphics processing engine 1431 into real / physical addresses in system memory 1414. One embodiment of accelerator integrated circuit 1436 supports multiple (e.g., 4, 8, 16) graphics accelerator modules 1446 and / or other accelerator devices. Graphics accelerator module 1446 may be dedicated to a single application executing on processor 1407, or may be shared among multiple applications. In one embodiment, a virtualized graphics execution environment is presented, where the resources of graphics processing engines 1431-1432, N are shared with multiple applications or virtual machines (VMs). In at least one embodiment, resources may be subdivided into “slices” based on processing requirements and priorities associated with VMs and / or applications, which are allocated to different VMs and / or applications.

[0263] In at least one embodiment, the accelerator integrated circuit 1436 acts as a bridge to the system of the graphics acceleration module 1446, providing address translation and system memory caching services. Additionally, the accelerator integrated circuit 1436 can provide virtualization facilities for the host processor to manage the virtualization, interrupt, and memory management of the graphics processing engines 1431-1432.

[0264] Because of the graphics processing engines 1431-1432, N's hardware resources are explicitly mapped to the real address space seen by the host processor 1407, any host processor can directly address these resources using valid address values. In at least one embodiment, a function of the accelerator integrated circuit 1436 is to physically separate the graphics processing engines 1431-1432, N, so that they appear as independent units to the system.

[0265] In at least one embodiment, one or more graphics memories 1433-1434, M are coupled to each graphics processing engine 1431-1432, N, respectively. The graphics memories 1433-1434, M store instructions and data processed by each graphics processing engine 1431-1432, N. The graphics memories 1433-1434, M can be volatile memory, such as DRAM (including stacked DRAM), GDDR memory (e.g., GDDR5, GDDR6), or HBM, and / or can be non-volatile memory, such as 3D XPoint or Nano-RAM.

[0266] In one embodiment, to reduce data traffic on link 1440, a biasing technique can be used to ensure that the data stored in graphics memories 1433-1434, M is the data most frequently used by graphics processing engines 1431-1432, N, and preferably not used (or at least infrequently used) by cores 1460A-1460D. Similarly, in at least one embodiment, the biasing mechanism attempts to keep the data needed by the cores (and preferably not graphics processing engines 1431-1432, N) in the core caches 1462A-1462D, 1456 and system memory 1414.

[0267] Figure 14C Another exemplary embodiment is shown, in which the accelerator integrated circuit 1436 is integrated within the processor 1407. In this embodiment, graphics processing engines 1431-1432,N communicate directly with the accelerator integrated circuit 1436 via a high-speed link 1440 through interfaces 1437 and 1435 (which can also utilize any form of bus or interface protocol). The accelerator integrated circuit 1436 can perform operations related to... Figure 14B The operations described are the same. However, due to its close proximity to the coherence bus 1464 and caches 1462A-1462D, 1456, it may have higher throughput. One embodiment supports different programming models, including a dedicated process programming model (without graphics acceleration module virtualization) and a shared programming model (with virtualization), which may include a programming model controlled by accelerator integrated circuit 1436 and a programming model controlled by graphics acceleration module 1446.

[0268] In at least one embodiment, graphics processing engines 1431-1432,N are dedicated to a single application or process within a single operating system. In at least one embodiment, a single application can funnel requests from other applications to graphics processing engines 1431-1432,N, thereby providing virtualization within a VM / partition.

[0269] In at least one embodiment, graphics processing engines 1431-1432, N can be shared by multiple VM / application partitions. In at least one embodiment, the shared model can use a hypervisor to virtualize graphics processing engines 1431-1432, N to allow each operating system to access them. For a single-partition system without a hypervisor, the operating system owns graphics processing engines 1431-1432, N. In at least one embodiment, the operating system can virtualize graphics processing engines 1431-1432, N to provide access to each process or application.

[0270] In at least one embodiment, the graphics acceleration module 1446 or the individual graphics processing engines 1431-1432, N uses a process handle to select a process element. In one embodiment, the process element is stored in system memory 1414 and can be addressed using the effective address to physical address translation techniques described herein. In at least one embodiment, the process handle may be an implementation-specific value provided to the host process when registering its context with the graphics processing engines 1431-1432, N (i.e., invoking system software to add the process element to the process element linked list). In at least one embodiment, the lower 16 bits of the process handle may be the offset of the process element in the process element linked list.

[0271] Figure 14D An exemplary accelerator integration slice 1490 is shown. As used herein, a “slice” includes a designated portion of the processing resources of the accelerator integrated circuit 1436. The application is an effective address space 1482 in system memory 1414 that stores process element 1483. In one embodiment, process element 1483 is stored in response to a GPU call 1481 from an application 1480 executing on processor 1407. Process element 1483 contains the process state of the corresponding application 1480. A job descriptor (WD) 1484 contained in process element 1483 may be a single job requested by the application, or it may contain a pointer to a job queue. In at least one embodiment, WD 1484 is a pointer to a job request queue in the application’s address space 1482.

[0272] The graphics acceleration module 1446 and / or the various graphics processing engines 1431-1432, N, can be shared by all processes or a subset of processes in the system. In at least one embodiment, infrastructure may be included for setting process states and sending WD 1484 to the graphics acceleration module 1446 to initiate operations in a virtualized environment.

[0273] In at least one embodiment, the dedicated process programming model is implementation-specific. In this model, a single process owns either the graphics acceleration module 1446 or an individual graphics processing engine 1431. When the graphics acceleration module 1446 is owned by a single process, the hypervisor initializes the accelerator integrated circuit for the owned partition; when the graphics acceleration module 1446 is assigned, the operating system initializes the accelerator integrated circuit 1436 for the owned process.

[0274] In operation, the WD fetch unit 1491 in the accelerator integrated slice 1490 fetches the next WD 1484, which includes instructions for the work to be performed by one or more graphics processing engines of the graphics acceleration module 1446. Data from the WD 1484 can be stored in register 1445 and used by the MMU 1439, interrupt management circuitry 1447, and / or context management circuitry 1448, as shown. For example, one embodiment of the MMU 1439 includes segment / page roaming circuitry for accessing segment / page tables 1486 within the OS virtual address space 1485. The interrupt management circuitry 1447 can handle interrupt events 1492 received from the graphics acceleration module 1446. When performing graphics operations, the effective address 1493 generated by the graphics processing engines 1431-1432,N is translated into a real address by the MMU 1439.

[0275] In one embodiment, for each graphics processing engine 1431-1432, N and / or graphics acceleration module 1446, the same set of registers 1445 is copied, and said registers 1445 can be initialized by a hypervisor or operating system. Each of these copied registers can be included in the accelerator integration slice 1490. Exemplary registers that can be initialized by the hypervisor are shown in Table 1.

[0276]

[0277] Table 2 shows exemplary registers that can be initialized by the operating system.

[0278]

[0279] In one embodiment, each WD 1484 is specific to a particular graphics acceleration module 1446 and / or graphics processing engine 1431-1432,N. It contains all the information required for the graphics processing engine 1431-1432,N to complete its work, or it may be a pointer to a memory location where the application has set up a command queue for the work to be done.

[0280] Figure 14EAdditional details of an exemplary embodiment of the shared model are shown. This embodiment includes a hypervisor real address space 1498, in which a list of process elements 1499 is stored. The hypervisor real address space 1498 can be accessed via a hypervisor 1496, which virtualizes the graphics acceleration module engine for operating system 1495.

[0281] In at least one embodiment, the shared programming model allows all processes or subsets of processes from all partitions or subsets of partitions in the system to use the graphics acceleration module 1446. Two programming models exist where the graphics acceleration module 1446 is shared by multiple processes and partitions: time-slice sharing and graphics-oriented sharing.

[0282] In this model, the hypervisor 1496 owns the graphics acceleration module 1446 and makes its functionality available to all operating systems 1495. For the graphics acceleration module 1446 to support virtualization through the hypervisor 1496, the graphics acceleration module 1446 may comply with the following: (1) the job requests of the application must be autonomous (i.e., no state needs to be maintained between jobs), or the graphics acceleration module 1446 must provide a context saving and restoring mechanism; (2) the graphics acceleration module 1446 guarantees that the job requests of the application are completed within a specified amount of time, including any conversion errors, or the graphics acceleration module 1446 provides the ability to preempt job processing; and (3) when operating in a directed shared programming model, fairness among the processes of the graphics acceleration module 1446 must be ensured.

[0283] In at least one embodiment, application 1480 needs to make a system call to operating system 1495 using graphics acceleration module 1446 type, working descriptor (WD), authority mask register (AMR) value, and context save / restore region pointer (CSRP). In at least one embodiment, the graphics acceleration module 1446 type describes the target acceleration function for the system call. In at least one embodiment, the graphics acceleration module 1446 type can be a system-specific value. In at least one embodiment, the WD is specifically formatted for graphics acceleration module 1446 and can take the form of graphics acceleration module 1446 commands, valid address pointers to user-defined structures, valid address pointers to command queues, or any other data structure describing the work to be performed by graphics acceleration module 1446. In one embodiment, the AMR value is the AMR state for the current process. In at least one embodiment, the value passed to the operating system is similar to that of the application that sets the AMR. If the implementation of accelerator integrated circuit 1436 and graphics acceleration module 1446 does not support the User Authority Mask Overwrite Register (UAMOR), the operating system can apply the current UAMOR value to the AMR value before passing the AMR in the hypervisor call. Hypervisor 1496 may selectively apply the Current Privilege Mask Overwrite Register (AMOR) value before placing the AMR into process element 1483. In at least one embodiment, CSRP is one of registers 1445 containing the effective address of a region in the application's address space 1482 for the graphics acceleration module 1446 to save and restore context state. This pointer is optional if saving state between jobs is not required or when a job is preempted. In at least one embodiment, the context save / restore region may be fixed system memory.

[0284] Upon receiving a system call, the operating system 1495 can verify that the application 1480 has been registered and granted permission to use the graphics acceleration module 1446. Then, the operating system 1495 uses the information shown in Table 3 to invoke the hypervisor 1496.

[0285]

[0286] Upon receiving a hypervisor call, hypervisor 1496 verifies that operating system 1495 has been registered and granted permission to use graphics acceleration module 1446. Then, hypervisor 1496 adds process element 1483 to the linked list of process elements of the corresponding graphics acceleration module 1446 type. The process element may include the information shown in Table 4.

[0287]

[0288] In at least one embodiment, the hypervisor initializes multiple accelerator integration slice 1490 registers 1445.

[0289] like Figure 14F As shown, in at least one embodiment, a unified memory is used, which is addressable via a common virtual memory address space for accessing physical processor memories 1401-1402 and GPU memories 1420-1423. In this implementation, operations performed on GPUs 1410-1413 utilize the same virtual / effective memory address space to access processor memories 1401-1402 and vice versa, thereby simplifying programmability. In at least one embodiment, a first portion of the virtual / effective address space is allocated to processor memory 1401, a second portion to second processor memory 1402, a third portion to GPU memory 1420, and so on. In at least one embodiment, the entire virtual / effective memory space (sometimes referred to as the effective address space) is thus distributed across each of processor memories 1401-1402 and GPU memories 1420-1423, thereby allowing any processor or GPU to access that memory using a virtual address mapped to any physical memory.

[0290] In one embodiment, the bias / coherence management circuitry 1494A-1494E within one or more MMUs 1439A-1439E ensures cache coherence between the caches of one or more host processors (e.g., 1405) and the GPUs 1410-1413, and implements biasing techniques that indicate the physical memory in which certain types of data should be stored. While in Figure 14F Several instances of bias / coherence management circuitry 1494A-1494E are shown, but bias / coherence circuitry can be implemented within the MMU of one or more host processors 1405 and / or within the accelerator integrated circuit 1436.

[0291] One embodiment allows GPU-attached memories 1420-1423 to be mapped as part of system memory and accessed using shared virtual memory (SVM) technology without suffering the performance drawbacks associated with full system cache coherence. In at least one embodiment, the ability to access GPU-attached memories 1420-1423 as system memory without the heavy overhead of cache coherence provides a favorable operating environment for GPU offloading. This arrangement allows the host processor 1405 to software-set operands and access computation results without the overhead of conventional I / O DMA data copying. Such conventional copying includes driver calls, interrupts, and memory-mapped I / O (MMIO) accesses, all of which are less efficient than simple memory accesses. In at least one embodiment, the ability to access GPU-attached memories 1420-1423 without cache coherence overhead can be critical for the execution time of offloaded computations. For example, in cases with high volumes of streaming write memory traffic, cache coherence overhead can significantly reduce the effective write bandwidth seen by GPUs 1410-1413. In at least one embodiment, the efficiency of operand setup, the efficiency of result access, and the efficiency of GPU computation may play a role in determining the effectiveness of GPU offloading.

[0292] In at least one embodiment, the selection of GPU bias and host processor bias is driven by a bias tracker data structure. For example, a bias table can be used, which may be a page-granular structure (e.g., controlled at the granularity of memory pages) comprising 1 or 2 bits of memory pages attached to each GPU. In at least one embodiment, with or without a bias cache (e.g., for caching frequently / recently used entries in the bias table) in GPUs 1410-1413, the bias table can be implemented over one or more stolen memory ranges of GPU-attached memories 1420-1423. Alternatively, the entire bias table can be maintained within the GPU.

[0293] In at least one embodiment, prior to actual access to GPU memory, an access to the bias table entry associated with each access to GPU-attached memory 1420-1423 is performed, causing the following operations: First, a local request from GPUs 1410-1413 to locate its page in the GPU bias is directly forwarded to the corresponding GPU memory 1420-1423. A local request from the GPU to locate its page in the host bias is forwarded to processor 1405 (e.g., via the high-speed link described above). In one embodiment, a request from processor 1405 to locate the requested page in the host processor bias completes a request similar to a normal memory read. Alternatively, requests to GPU bias pages can be forwarded to GPUs 1410-1413. In at least one embodiment, if the GPU is not currently using the page, the GPU may subsequently migrate the page to the host processor bias. In at least one embodiment, the page bias state can be changed through a software-based mechanism, a hardware-assisted software mechanism, or, in limited cases, a purely hardware-based mechanism.

[0294] One mechanism for changing the bias state employs an API call (e.g., OpenCL) that subsequently invokes the GPU's device driver, which then sends a message (or enqueues a command descriptor) to the GPU, instructing the GPU to change the bias state and, in some migrations, performs a cache refresh operation on the host. In at least one embodiment, the cache refresh operation is used for a migration from the host processor 1405 bias to the GPU bias, but not for the reverse migration.

[0295] In one embodiment, cache coherence is maintained by temporarily rendering GPU bias pages that the host processor 1405 cannot cache. To access these pages, the processor 1405 may request access from the GPU 1410, which may or may not grant access immediately. Therefore, to reduce communication between the processor 1405 and the GPU 1410, it is beneficial to ensure that the GPU bias pages are pages needed by the GPU, not those needed by the host processor 1405, and vice versa.

[0296] One or more hardware structures 815 are used to execute one or more embodiments. This document may combine... Figure 8 A and / or Figure 8 B provides details about one or more hardware architectures 815.

[0297] Figure 15Exemplary integrated circuits and associated graphics processors according to various embodiments described herein are illustrated, which may be manufactured using one or more IP cores. In addition to the illustrations, at least one embodiment may include other logic and circuitry, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0298] Figure 15 This is a block diagram illustrating an exemplary system on a chip integrated circuit 1500 that may be fabricated using one or more IP cores according to at least one embodiment. In at least one embodiment, the integrated circuit 1500 includes one or more application processors 1505 (e.g., CPUs), at least one graphics processor 1510, and may additionally include an image processor 1515 and / or a video processor 1520, any of which may be a modular IP core. In at least one embodiment, the integrated circuit 1500 includes peripheral or bus logic including a USB controller 1525, a UART controller 1530, an SPI / SDIO controller 1535, and an I.sup.2S / I.sup.2C controller 1540. In at least one embodiment, the integrated circuit 1500 may include a display device 1545 coupled to one or more of a High Definition Multimedia Interface (HDMI) controller 1550 and a Mobile Industrial Processor Interface (MIPI) display interface 1555. In at least one embodiment, storage may be provided by a flash memory subsystem 1560, including flash memory and a flash memory controller. In at least one embodiment, a memory interface may be provided via a memory controller 1565 for accessing an SDRAM or SRAM memory device. In at least one embodiment, some integrated circuits also include an embedded security engine 1570.

[0299] In at least one embodiment, the SOC integrated circuit 1500 generates device packets in parallel to utilize the frequency band and selects the generated packets.

[0300] Figure 16A and 16B Exemplary integrated circuits and associated graphics processors according to various embodiments described herein are illustrated, which may be manufactured using one or more IP cores. In addition to the illustrations, at least one embodiment may include other logic and circuitry, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0301] Figure 16A and 16B This is a block diagram illustrating an exemplary graphics processor used within a SoC according to embodiments described herein. Figure 16A An exemplary graphics processor 1610, which can be fabricated using one or more IP cores according to at least one embodiment, is shown. Figure 16B Further exemplary graphics processor 1640 of a system-on-a-chip integrated circuit according to at least one embodiment is shown, which can be manufactured using one or more IP cores. In at least one embodiment, Figure 16A The graphics processor 1610 is a low-power graphics processor core. In at least one embodiment, Figure 16B The graphics processor 1640 is a higher-performance graphics processor core. In at least one embodiment, each graphics processor 1610, 1640 may be a variant of the graphics processor 1410 of FIG. 14.

[0302] In at least one embodiment, the graphics processor 1610 includes a vertex processor 1605 and one or more fragment processors 1615A-1615N (e.g., 1615A, 1615B, 1615C, 1615D to 1615N-1 and 1615N). In at least one embodiment, the graphics processor 1610 may execute different shader programs via separate logic, such that the vertex processor 1605 is optimized to perform operations for the vertex shader program, while one or more fragment processors 1615A-1615N perform fragment (e.g., pixel) shading operations for fragments or pixels or shader programs. In at least one embodiment, the vertex processor 1605 performs the vertex processing stage of the 3D graphics pipeline and generates primitive and vertex data. In at least one embodiment, one or more fragment processors 1615A-1615N use the primitive and vertex data generated by the vertex processor 1605 to generate framebuffers for display on a display device. In at least one embodiment, one or more fragment processors 1615A-1615N are optimized to execute fragment shader programs as provided in the OpenGL API, which can be used to perform operations similar to those of pixel shader programs provided in the Direct 3D API.

[0303] In at least one embodiment, the graphics processor 1610 additionally includes one or more memory management units (MMUs) 1620A-1620B, one or more caches 1625A-1625B, and one or more circuit interconnects 1630A-1630B. In at least one embodiment, one or more MMUs 1620A-1620B provide virtual-to-physical address mappings for the graphics processor 1610, including for vertex processors 1605 and / or fragment processors 1615A-1615N, which can reference vertex or image / texture data stored in memory, in addition to vertex or image / texture data stored in one or more caches 1625A-1625B. In at least one embodiment, one or more MMUs 1620A-1620B can be synchronized with other MMUs within the system, including one or more MMUs associated with one or more application processors 1405, graphics processors 1416, and / or video processors 1420 of FIG. 14, such that each processor 1405-1420 can participate in a shared or unified virtual memory system. In at least one embodiment, one or more circuit interconnects 1630A-1630B enable the graphics processor 1610 to connect to other IP cores within the SoC via the SoC's internal bus or via a direct connection.

[0304] In at least one embodiment, the graphics processor 1640 includes Figure 16A The graphics processor 1610 includes one or more MMUs 1620A-1620B, caches 1625A-1625B, and circuit interconnects 1630A-1630B. In at least one embodiment, the graphics processor 1640 includes one or more shader cores 1655A-1655N (e.g., 1655A, 1655B, 1655C, 1655D, 1655E, 1655F to 1655N-1 and 1655N) that provide a unified shader core architecture, wherein a single core or type of core can execute all types of programmable shader code, including shader program code for implementing vertex shaders, fragment shaders, and / or compute shaders. In at least one embodiment, the number of shader cores may vary. In at least one embodiment, the graphics processor 1640 includes an inter-core task manager 1645 that acts as a thread dispatcher to assign execution threads to one or more shader cores 1655A-1655N and a tile unit 1658 to accelerate tile-based rendering operations, wherein rendering operations of a scene are subdivided in image space, for example, to take advantage of local spatial consistency within the scene or to optimize the use of internal caches.

[0305] In at least one embodiment, the graphics processor 1610 generates device packets in parallel to utilize the frequency band and selects one of the generated packets.

[0306] Figure 17A and 17B Additional exemplary graphics processor logic according to embodiments described herein is illustrated. In at least one embodiment, Figure 17A It shows that it can be included in Figure 15 The graphics core 1700 within the graphics processor 1510, and in at least one embodiment, may be as follows: Figure 16B The Unified Shader Core 1655A-1655N is shown. Figure 17B A highly parallel general-purpose graphics processing unit 1730 suitable for deployment on a multi-chip module is shown in at least one embodiment.

[0307] In at least one embodiment, the graphics core 1700 includes a shared instruction cache 1702, texture units 1718, and cache / shared memory 1720, which are common to the execution resources within the graphics core 1700. In at least one embodiment, the graphics core 1700 may include multiple slices 1701A-1701N or partitions of each core, and the graphics processor may include multiple instances of the graphics core 1700. Slices 1701A-1701N may include supporting logic, including local instruction caches 1704A-1704N, thread schedulers 1706A-1706N, thread dispatchers 1708A-1708N, and a set of registers 1710A-1710N. In at least one embodiment, slices 1701A-1701N may include a set of additional functional units (AFU1712A-1712N), floating-point units (FPU 1714A-1714N), integer arithmetic logic units (ALU 1716A-1716N), address calculation units (ACU 1713A-1713N), double-precision floating-point units (DPFPU 1715A-1715N), and matrix processing units (MPU1717A-1717N).

[0308] In at least one embodiment, the FPU 1714A-1714N can perform single-precision (32-bit) and half-precision (16-bit) floating-point operations, while the DPFPU 1715A-1715N performs double-precision (64-bit) floating-point operations. In at least one embodiment, the ALU 1716A-1716N can perform variable-precision integer operations with 8-bit, 16-bit, and 32-bit precision, and can be configured for mixed-precision operations. In at least one embodiment, the MPU 1717A-1717N can also be configured for mixed-precision matrix operations, including half-precision floating-point operations and 8-bit integer operations. In at least one embodiment, the MPU 1717-1717N can perform various matrix operations to accelerate machine learning application frameworks, including enabling support for accelerated generalized matrix-to-matrix multiplication (GEMM). In at least one embodiment, the AFU 1712A-1712N can perform additional logical operations not supported by floating-point or integer units, including trigonometric operations (e.g., sine, cosine, etc.).

[0309] In at least one embodiment, one or more graphics cores 1700 generate device packets in parallel to utilize the frequency band, and select one of the generated packets.

[0310] Figure 17B A general-purpose processing unit (GPGPU) 1730 is illustrated in at least one embodiment, which can be configured to enable highly parallel computational operations to be performed by a set of graphics processing units. In at least one embodiment, the GPGPU 1730 can be directly linked to other instances of the GPGPU 1730 to create a multi-GPU cluster to improve the training speed for deep neural networks. In at least one embodiment, the GPGPU 1730 includes a host interface 1732 for connection to a host processor. In at least one embodiment, the host interface 1732 is a PCI Express interface. In at least one embodiment, the host interface 1732 may be a vendor-specific communication interface or communication structure. In at least one embodiment, the GPGPU 1730 receives commands from the host processor and uses a global scheduler 1734 to allocate execution threads associated with those commands to a set of compute clusters 1736A-1736H. In at least one embodiment, compute clusters 1736A-1736H share a cache memory 1738. In at least one embodiment, cache memory 1738 can be used as a higher-level cache within the cache memory of computing clusters 1736A-1736H.

[0311] In at least one embodiment, the GPGPU 1730 includes memories 1744A-1744B, which are coupled to the computing cluster 1736A-1736H via a set of memory controllers 1742A-1742B. In at least one embodiment, memories 1744A-1744B may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), which includes graphics double data rate (GDDR) memory.

[0312] In at least one embodiment, each of the computing clusters 1736A-1736H includes a set of graphics cores, for example... Figure 17A The graphics core 1700 may include various types of integer and floating-point logic units that can perform computational operations across a range of precisions, including precisions suitable for machine learning computations. For example, in at least one embodiment, at least a subset of the floating-point units in each computing cluster 1736A-1736H may be configured to perform 17-bit or 32-bit floating-point operations, while different subsets of the floating-point units may be configured to perform 64-bit floating-point operations.

[0313] In at least one embodiment, multiple instances of the GPGPU 1730 can be configured as a computing cluster. In at least one embodiment, the communication used for synchronization and data exchange by the computing clusters 1736A-1736H varies between embodiments. In at least one embodiment, the multiple instances of the GPGPU 1730 communicate via a host interface 1732. In at least one embodiment, the GPGPU 1730 includes an I / O hub 1739 that couples the GPGPU 1730 to a GPU link 1740, enabling direct connection to other instances of the GPGPU 1730. In at least one embodiment, the GPU link 1740 is coupled to a dedicated GPU-to-GPU bridge, which enables communication and synchronization between the multiple instances of the GPGPU 1730. In at least one embodiment, the GPU link 1740 is coupled to a high-speed interconnect for sending and receiving data to and from other GPGPUs or parallel processors. In at least one embodiment, the multiple instances of the GPGPU 1730 reside in a separate data processing system and communicate via network devices accessible through the host interface 1732. In at least one embodiment, GPU link 1740 may be configured to connect to a host processor other than or as a replacement for host interface 1732.

[0314] In at least one embodiment, the GPGPU 1730 can be configured to train a neural network. In at least one embodiment, the GPGPU 1730 can be used within an inference platform. In at least one embodiment, when using the GPGPU 1730 for inference, the GPGPU may include fewer compute clusters 1736A-1736H compared to when using the GPGPU to train a neural network. In at least one embodiment, the memory technology associated with the memories 1744A-1744B can differ between inference and training configurations, with higher bandwidth memory technology dedicated to the training configuration. In at least one embodiment, the inference configuration of the GPGPU 1730 can support inference-specific instructions. For example, in at least one embodiment, the inference configuration can provide support for one or more 8-bit integer dot product instructions, which can be used during the inference operation of the deployed neural network.

[0315] In at least one embodiment, one or more GPGPUs 1730 generate device packets in parallel to utilize the frequency band, and select one of the generated packets.

[0316] Figure 18 A block diagram of a computer system 1800 according to at least one embodiment is shown. In at least one embodiment, the computer system 1800 includes a processing subsystem 1801 having one or more processors 1802 and a system memory 1804 communicating via an interconnect path that may include a memory hub 1805. In at least one embodiment, the memory hub 1805 may be a separate component within a chipset component or may be integrated within one or more processors 1802. In at least one embodiment, the memory hub 1805 is coupled to an I / O subsystem 1811 via a communication link 1806. In one embodiment, the I / O subsystem 1811 includes an I / O hub 1807 that enables the computer system 1800 to receive input from one or more input devices 1808. In at least one embodiment, the I / O hub 1807 enables a display controller to provide output to one or more display devices 1810A, the display controller being included in one or more processors 1802. In at least one embodiment, one or more display devices 1810A coupled to the I / O hub 1807 may include local, internal, or embedded display devices.

[0317] In at least one embodiment, the processing subsystem 1801 includes one or more parallel processors 1812 coupled to the memory hub 1805 via a bus or other communication link 1813. In at least one embodiment, the communication link 1813 can be any of many standards-based communication link technologies or protocols, such as, but not limited to, PCI Express, or can be a vendor-specific communication interface or communication architecture. In at least one embodiment, the one or more parallel processors 1812 form a computationally concentrated parallel or vector processing system, which may include a large number of processing cores and / or processing clusters, such as a multi-core integrated (MIC) processor. In at least one embodiment, the one or more parallel processors 1812 form a graphics processing subsystem that can output pixels to one of one or more display devices 1810A coupled via an I / O hub 1807. In at least one embodiment, the one or more parallel processors 1812 may also include a display controller and a display interface (not shown) to enable direct connection to one or more display devices 1810B.

[0318] In at least one embodiment, system storage unit 1814 may be connected to I / O hub 1807 to provide a storage mechanism for computer system 1800. In at least one embodiment, I / O switch 1816 may be used to provide an interface mechanism to enable connectivity between I / O hub 1807 and other components, such as network adapter 1818 and / or wireless network adapter 1817 that may be integrated into the platform, and various other devices that may be added via one or more additional devices 1820. In at least one embodiment, network adapter 1818 may be an Ethernet adapter or another wired network adapter. In at least one embodiment, wireless network adapter 1819 may include one or more of Wi-Fi, Bluetooth, Near Field Communication (NFC), or other network devices including one or more wireless devices.

[0319] In at least one embodiment, the computer system 1800 may include other components not explicitly shown, such as USB or other port connections, optical storage drives, video capture devices, etc., which may also be connected to the I / O hub 1807. In at least one embodiment, the interconnection can be implemented using any suitable protocol, such as PCI (Peripheral Component Interconnect) based protocols (e.g., PCI-Express) or other bus or point-to-point communication interfaces and / or protocols. Figure 18 The communication paths of the various components, such as NV-Link high-speed interconnect or interconnect protocols.

[0320] In at least one embodiment, one or more parallel processors 1812 include circuitry optimized for graphics and video processing, including, for example, video output circuitry, and constituting a graphics processing unit (GPU). In at least one embodiment, one or more parallel processors 1812 include circuitry optimized for general-purpose processing. In at least one embodiment, components of the computer system 1800 may be integrated with one or more other system elements on a single integrated circuit. For example, in at least one embodiment, one or more parallel processors 1812, memory hub 1805, processor 1802, and I / O hub 1807 may be integrated into a system-on-a-chip (SoC) integrated circuit. In at least one embodiment, components of the computer system 1800 may be integrated into a single package to form a system-in-package (SIP) configuration. In at least one embodiment, at least a portion of the components of the computer system 1800 may be integrated into a multi-chip module (MCM) that can interconnect with other MCMs to a modular computer system.

[0321] In at least one embodiment, the computing system 1800 includes a processor and circuitry to generate packets of the device in parallel to utilize a frequency band and to select one of the generated packets.

[0322] processor

[0323] Figure 19A A parallel processor 1900 according to at least one embodiment is illustrated. In at least one embodiment, various components of the parallel processor 1900 may be implemented using one or more integrated circuit devices, such as programmable processors, application-specific integrated circuits (ASICs), or field-programmable gate arrays (FPGAs). In at least one embodiment, the illustrated parallel processor 1900 is according to an exemplary embodiment. Figure 18 The variants of the 1812, which include one or more parallel processors, are shown.

[0324] In at least one embodiment, the parallel processor 1900 includes a parallel processing unit 1902. In at least one embodiment, the parallel processing unit 1902 includes an I / O unit 1904 that enables communication with other devices, including other instances of the parallel processing unit 1902. In at least one embodiment, the I / O unit 1904 can be directly connected to other devices. In at least one embodiment, the I / O unit 1904 is connected to other devices using a hub or switch interface (e.g., a memory hub 1805). In at least one embodiment, the connection between the memory hub 1805 and the I / O unit 1904 forms a communication link 1813. In at least one embodiment, the I / O unit 1904 is connected to a host interface 1906 and a memory crossbar switch 1916, wherein the host interface 1906 receives commands for performing processing operations, and the memory crossbar switch 1916 receives commands for performing memory operations.

[0325] In at least one embodiment, when host interface 1906 receives a command buffer via I / O unit 1904, host interface 1906 can direct work operations to execute those commands to front end 1908. In at least one embodiment, front end 1908 is coupled to scheduler 1910, which is configured to assign commands or other work items to processing cluster array 1912. In at least one embodiment, scheduler 1910 ensures that processing cluster array 1912 is correctly configured and in an active state before assigning tasks to processing cluster array 1912. In at least one embodiment, scheduler 1910 is implemented via firmware logic executed on a microcontroller. In at least one embodiment, the microcontroller-implemented scheduler 1910 can be configured to perform complex scheduling and work assignment operations at both coarse and fine granular levels, thereby enabling fast preemption and context switching of threads executing on processing array 1912. In at least one embodiment, host software can demonstrate workloads scheduled on processing array 1912 via one of multiple graphics processing doorbells. In at least one embodiment, the workload can then be automatically distributed on the processing array 1912 by the scheduler 1910 logic within the microcontroller, which includes the scheduler 1910.

[0326] In at least one embodiment, the processing cluster array 1912 may include up to "N" processing clusters (e.g., clusters 1914A, 1914B to 1914N). In at least one embodiment, each cluster 1914A-1914N of the processing cluster array 1912 may execute a large number of concurrent threads. In at least one embodiment, the scheduler 1910 may use various scheduling and / or work allocation algorithms to allocate work to the clusters 1914A-1914N of the processing cluster array 1912, which may vary depending on the workload generated by each type of program or computation. In at least one embodiment, scheduling may be handled dynamically by the scheduler 1910, or may be partially assisted by compiler logic during the compilation of program logic configured to be executed by the processing cluster array 1912. In at least one embodiment, different clusters 1914A-1914N of the processing cluster array 1912 may be assigned to process different types of programs or to perform different types of computations.

[0327] In at least one embodiment, the processing cluster array 1912 can be configured to perform various types of parallel processing operations. In at least one embodiment, the processing cluster array 1912 is configured to perform general-purpose parallel computing operations. For example, in at least one embodiment, the processing cluster array 1912 may include logic for performing processing tasks, including filtering video and / or audio data, performing modeling operations, including physical operations, and performing data transformations.

[0328] In at least one embodiment, the processing cluster array 1912 is configured to perform parallel graphics processing operations. In at least one embodiment, the processing cluster array 1912 may include additional logic to support the execution of such graphics processing operations, including but not limited to texture sampling logic for performing texture operations, as well as tessellation logic and other vertex processing logic. In at least one embodiment, the processing cluster array 1912 may be configured to execute shader programs related to graphics processing, such as, but not limited to, vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. In at least one embodiment, the parallel processing unit 1902 may transfer data from system memory via I / O unit 1904 for processing. In at least one embodiment, during processing, the transferred data may be stored in on-chip memory (e.g., parallel processor memory 1922) and then written back to system memory.

[0329] In at least one embodiment, when the parallel processing unit 1902 is used to perform graphics processing, the scheduler 1910 may be configured to divide the processing workload into tasks of approximately equal size to better distribute graphics processing operations among the multiple clusters 1914A-1914N of the processing cluster array 1912. In at least one embodiment, portions of the processing cluster array 1912 may be configured to perform different types of processing. For example, in at least one embodiment, a first portion may be configured to perform vertex shading and topology generation, a second portion may be configured to perform tessellation and geometry shading, and a third portion may be configured to perform pixel shading or other screen-space operations to generate a rendered image for display. In at least one embodiment, intermediate data generated by one or more of the clusters 1914A-1914N may be stored in a buffer to allow intermediate data to be transferred between the clusters 1914A-1914N for further processing.

[0330] In at least one embodiment, the processing cluster array 1912 may receive processing tasks to be executed via a scheduler 1910, which receives commands defining the processing tasks from a front end 1908. In at least one embodiment, the processing task may include an index of data to be processed, such as surface (patch) data, raw data, vertex data, and / or pixel data, as well as state parameters and commands defining how the data is processed (e.g., what program to execute). In at least one embodiment, the scheduler 1910 may be configured to acquire an index corresponding to a task, or may receive an index from the front end 1908. In at least one embodiment, the front end 1908 may be configured to ensure that the processing cluster array 1912 is configured to be active before initiating the workload specified by an incoming command buffer (e.g., a batch buffer, push buffer, etc.).

[0331] In at least one embodiment, each of one or more instances of the parallel processing unit 1902 may be coupled to the parallel processor memory 1922. In at least one embodiment, the parallel processor memory 1922 may be accessed via a memory crossbar switch 1916, which may receive memory requests from the processing cluster array 1912 and the I / O unit 1904. In at least one embodiment, the memory crossbar switch 1916 may be accessed via a memory interface 1918. In at least one embodiment, the memory interface 1918 may include a plurality of partition units (e.g., partition units 1920A, 1920B to 1920N), each of which may be coupled to a portion (e.g., a memory cell) of the parallel processor memory 1922. In at least one embodiment, the plurality of partition units 1920A-1920N are configured to be equal to the number of memory units, such that the first partition unit 1920A has a corresponding first memory unit 1924A, the second partition unit 1920B has a corresponding memory unit 1924B, and the Nth partition unit 1920N has a corresponding Nth memory unit 1924N. In at least one embodiment, the number of partition units 1920A-1920N may not be equal to the number of memory devices.

[0332] In at least one embodiment, memory cells 1924A-1924N may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory. In at least one embodiment, memory cells 1924A-1924N may also include 3D stacked memory, including but not limited to high bandwidth memory (HBM). In at least one embodiment, rendering targets such as frame buffers or texture maps may be stored across memory cells 1924A-1924N, allowing partitioning cells 1920A-1920N to write portions of each rendering target in parallel, to efficiently utilize the available bandwidth of the parallel processor memory 1922. In at least one embodiment, local instances of the parallel processor memory 1922 may be excluded to facilitate a unified memory design that combines system memory with local cache memory.

[0333] In at least one embodiment, any of the clusters 1914A-1914N of the processing cluster array 1912 can process data to be written to any memory cell 1924A-1924N within the parallel processor memory 1922. In at least one embodiment, the memory crossbar switch 1916 can be configured to transfer the output of each cluster 1914A-1914N to any partition cell 1920A-1920N or another cluster 1914A-1914N, and the clusters 1914A-1914N can perform further processing operations on the output. In at least one embodiment, each cluster 1914A-1914N can communicate with the memory interface 1918 via the memory crossbar switch 1916 to read from or write to various external storage devices. In at least one embodiment, the memory crossbar switch 1916 has a connection to a memory interface 1918 for communication with I / O unit 1904, and a connection to a local instance of parallel processor memory 1922, thereby enabling processing units within different processing clusters 1914A-1914N to communicate with system memory or other memory not local to parallel processing unit 1902. In at least one embodiment, the memory crossbar switch 1916 may use virtual channels to separate traffic flows between clusters 1914A-1914N and partition units 1920A-1920N.

[0334] In at least one embodiment, multiple instances of the parallel processing unit 1902 may be provided on a single insert card, or multiple insert cards may be interconnected. In at least one embodiment, different instances of the parallel processing unit 1902 may be configured to interoperate, even if the different instances have different numbers of processing cores, different numbers of local parallel processor memories, and / or other configuration differences. For example, in at least one embodiment, some instances of the parallel processing unit 1902 may include higher-precision floating-point units relative to other instances. In at least one embodiment, a system combining one or more instances of the parallel processing unit 1902 or the parallel processor 1900 may be implemented in various configurations and form factors, including but not limited to desktop, laptop, or handheld personal computers, servers, workstations, game consoles, and / or embedded systems.

[0335] Figure 19B This is a block diagram of a partitioning unit 1920 according to at least one embodiment. In at least one embodiment, the partitioning unit 1920 is... Figure 19AThis is an example of one of the partitioning units 1920A-1920N. In at least one embodiment, the partitioning unit 1920 includes an L2 cache 1921, a frame buffer interface 1925, and a ROP 1926 (raster operation unit). The L2 cache 1921 is a read / write cache configured to perform load and store operations received from the memory crossbar switch 1916 and the ROP 1926. In at least one embodiment, the L2 cache 1921 outputs read misses and urgent write-back requests to the frame buffer interface 1925 for processing. In at least one embodiment, updates can also be sent to the frame buffer for processing via the frame buffer interface 1925. In at least one embodiment, the frame buffer interface 1925 communicates with memory cells in the parallel processor memory (such as...). Figure 19A It interacts with one of the memory cells 1924A-1924N (e.g., within the parallel processor memory 1922).

[0336] In at least one embodiment, ROP 1926 is a processing unit that performs raster operations such as stenciling, z-testing, blending, etc. In at least one embodiment, ROP 1926 then outputs processed graphics data stored in graphics memory. In at least one embodiment, ROP 1926 includes compression logic to compress depth or color data written to memory and decompress depth or color data read from memory. In at least one embodiment, the compression logic may be lossless compression logic utilizing one or more of a variety of compression algorithms. In at least one embodiment, the type of compression performed by ROP 1926 may vary based on the statistical characteristics of the data to be compressed. For example, in at least one embodiment, incremental color compression is performed based on depth and color data on a per-tile basis.

[0337] In at least one embodiment, ROP 1926 is included within each processing cluster (e.g., Figure 19A Clusters 1914A-1914N are used instead of partition units 1920. In at least one embodiment, read and write requests for pixel data are made via memory crossbar switch 1916 instead of pixel fragment data transfer. In at least one embodiment, the processed graphics data can be displayed on a display device (such as...). Figure 18 One or more display devices 1810) display, routed by processor 1702 for further processing, or by Figure 19A One of the processing entities within the parallel processor 1900 is routed for further processing.

[0338] Figure 19C This is a block diagram of a processing cluster 1914 within a parallel processing unit according to at least one embodiment. In at least one embodiment, the processing cluster is... Figure 19AAn example of one of the processing clusters 1914A-1914N. In at least one embodiment, the processing cluster 1914 can be configured to execute a number of threads in parallel, wherein the term "thread" refers to an instance of a specific program executing on a particular set of input data. In at least one embodiment, a Single Instruction Multiple Data (SIMD) instruction issuing technique is used to support the parallel execution of a large number of threads without providing multiple independent instruction units. In at least one embodiment, a Single Instruction Multiple Threading (SIMT) technique is used to support the parallel execution of a large number of generally synchronous threads, which uses a common instruction unit configured to issue instructions to a set of processing engines within each processing cluster.

[0339] In at least one embodiment, the operation of the processing cluster 1914 can be controlled by a pipeline manager 1932 that assigns processing tasks to the SIMT parallel processors. In at least one embodiment, the pipeline manager 1932... Figure 19A The scheduler 1910 receives instructions and manages the execution of these instructions via the graphics multiprocessor 1934 and / or texture unit 1936. In at least one embodiment, the graphics multiprocessor 1934 is an exemplary instance of a SIMT parallel processor. However, in at least one embodiment, the processing cluster 1914 may include various types of SIMT parallel processors with different architectures. In at least one embodiment, the processing cluster 1914 may include one or more instances of the graphics multiprocessor 1934. In at least one embodiment, the graphics multiprocessor 1934 can process data, and the data cross switch 1940 can be used to distribute the processed data to one of a number of possible destinations, including other shader units. In at least one embodiment, the pipeline manager 1932 can facilitate the distribution of processed data by specifying the destination of the processed data to be distributed via the data cross switch 1940.

[0340] In at least one embodiment, each graphics multiprocessor 1934 within the processing cluster 1914 may include the same set of functional execution logic (e.g., arithmetic logic units, load-memory units, etc.). In at least one embodiment, the functional execution logic may be configured in a pipelined manner, wherein new instructions may be issued before previous instructions complete. In at least one embodiment, the functional execution logic supports a variety of operations, including integer and floating-point arithmetic, comparison operations, Boolean operations, shift operations, and computation of various algebraic functions. In at least one embodiment, the same functional unit hardware may be used to perform different operations, and any combination of functional units may exist.

[0341] In at least one embodiment, instructions sent to the processing cluster 1914 constitute threads. In at least one embodiment, a group of threads executed across a set of parallel processing engines is a thread group. In at least one embodiment, the thread group executes programs on different input data. In at least one embodiment, each thread within the thread group may be assigned to a different processing engine within the graphics multiprocessor 1934. In at least one embodiment, the thread group may include fewer threads than the number of processing engines within the graphics multiprocessor 1934. In at least one embodiment, when the number of threads included in the thread group is less than the number of processing engines, one or more processing engines may be idle during a loop that is processing the thread group. In at least one embodiment, the thread group may also include more threads than the number of processing engines within the graphics multiprocessor 1934. In at least one embodiment, when the thread group includes more threads than the number of processing engines within the graphics multiprocessor 1934, processing can be performed in consecutive clock cycles. In at least one embodiment, multiple thread groups can be executed simultaneously on the graphics multiprocessor 1934.

[0342] In at least one embodiment, the graphics multiprocessor 1934 includes an internal cache memory for performing load and store operations. In at least one embodiment, the graphics multiprocessor 1934 may forgo the internal cache and use a cache memory within the processing cluster 1914 (e.g., L1 cache 1948). In at least one embodiment, each graphics multiprocessor 1934 may also access partition units (e.g., Figure 19A The L2 cache is located within partition units 1920A-1920N, which are shared among all processing clusters 1914 and can be used to transfer data between threads. In at least one embodiment, the graphics multiprocessor 1934 can also access off-chip global memory, which may include one or more of local parallel processor memory and / or system memory. In at least one embodiment, any memory outside of the parallel processing unit 1902 can be used as global memory. In at least one embodiment, the processing cluster 1914 includes multiple instances of the graphics multiprocessor 1934, which can share common instructions and data that can be stored in the L1 cache 1948.

[0343] In at least one embodiment, each processing cluster 1914 may include a memory management unit (“MMU”) 1945 configured to map virtual addresses to physical addresses. In at least one embodiment, one or more instances of the MMU 1945 may reside in Figure 19AThe memory interface 1918 is located within the MMU 1945. In at least one embodiment, the MMU 1945 includes a set of page table entries (PTEs) for mapping virtual addresses to physical addresses of tiles (more accurately, tiling) and optionally to cache line indices. In at least one embodiment, the MMU 1945 may include an address translation lookahead buffer (TLB) or a cache that may reside within the graphics multiprocessor 1934 or the L1 cache or processing cluster 1914. In at least one embodiment, physical addresses are processed to allocate surface data access locality for efficient request interleaving between partition units. In at least one embodiment, cache line indices may be used to determine whether a request for a cache line is a hit or a miss.

[0344] In at least one embodiment, the processing cluster 1914 can be configured such that each graphics multiprocessor 1934 is coupled to a texture unit 1936 to perform texture mapping operations that determine texture sample locations, read texture data, and filter texture data. In at least one embodiment, texture data is read as needed from an internal texture L1 cache (not shown) or from an L1 cache within the graphics multiprocessor 1934, and texture data is also retrieved from an L2 cache, local parallel processor memory, or system memory. In at least one embodiment, each graphics multiprocessor 1934 outputs a processed task to a data crossbar switch 1940 to provide the processed task to another processing cluster 1914 for further processing or to store the processed task in an L2 cache, local parallel processor memory, or system memory via a memory crossbar switch 1916. In at least one embodiment, a PreROP 1942 (pre-raster operation unit) is configured to receive data from the graphics multiprocessor 1934 and direct the data to a ROP unit, which can be coupled with the partitioning unit described herein (e.g., Figure 19A The PreROP 1942 unit is located together with the partition units 1920A-1920N. In at least one embodiment, the PreROP 1942 unit can perform optimizations for color blending, organize pixel color data, and perform address translation.

[0345] In at least one embodiment, the parallel processor 1900 generates packets of the device in parallel to utilize the frequency band and selects one of the generated packets.

[0346] Figure 19DA graphics multiprocessor 1934 according to at least one embodiment is illustrated. In at least one embodiment, the graphics multiprocessor 1934 is coupled to a pipeline manager 1932 of a processing cluster 1914. In at least one embodiment, the graphics multiprocessor 1934 has an execution pipeline including, but not limited to, an instruction cache 1952, an instruction unit 1954, an address mapping unit 1956, a register file 1958, one or more general-purpose graphics processing unit (GPGPU) cores 1962, and one or more load / store units 1966. The GPGPU cores 1962 and the load / store units 1966 are coupled to a cache memory 1972 and a shared memory 1970 via a memory and cache interconnect 1968.

[0347] In at least one embodiment, instruction cache 1952 receives a stream of instructions to be executed from pipeline manager 1932. In at least one embodiment, instructions are cached in instruction cache 1952 and dispatched to instruction unit 1954 for execution. In one embodiment, instruction unit 1954 may dispatch instructions as thread groups (e.g., thread bundles), assigning each thread of the thread group to a different execution unit within GPGPU core 1962. In at least one embodiment, instructions can access any local, shared, or global address space by specifying an address within a unified address space. In at least one embodiment, address mapping unit 1956 may be used to translate addresses in the unified address space into different memory addresses that can be accessed by load / store unit 1966.

[0348] In at least one embodiment, register file 1958 provides a set of registers for the functional units of graphics multiprocessor 1934. In at least one embodiment, register file 1958 provides temporary storage for operands on data paths connected to functional units of graphics multiprocessor 1934 (e.g., GPGPU core 1962, load / store unit 1966). In at least one embodiment, register file 1958 is partitioned among each functional unit, such that a dedicated portion of register file 1958 is allocated to each functional unit. In at least one embodiment, register file 1958 is partitioned among different thread bundles being executed by graphics multiprocessor 1934.

[0349] In at least one embodiment, the GPGPU core 1962 may each include a floating-point unit (FPU) and / or an integer arithmetic logic unit (ALU) for executing instructions of the graphics multiprocessor 1934. The GPGPU core 1962 may be architecturally similar or may differ in architecture. In at least one embodiment, a first portion of the GPGPU core 1962 includes a single-precision FPU and an integer ALU, while a second portion of the GPGPU core includes a double-precision FPU. In at least one embodiment, the FPU may implement the IEEE 754-2008 standard for floating-point algorithms or enable variable-precision floating-point algorithms. In at least one embodiment, the graphics multiprocessor 1934 may additionally include one or more fixed-function or special-function units to perform specific functions, such as copying rectangles or pixel blending operations. In at least one embodiment, one or more of the GPGPU cores may also include fixed-function or special-function logic.

[0350] In at least one embodiment, the GPGPU core 1962 includes SIMD logic capable of executing a single instruction on multiple sets of data. In one embodiment, the GPGPU core 1962 can physically execute SIMD4, SIMD8, and SIMD16 instructions, and logically execute SIMD1, SIMD2, and SIMD32 instructions. In at least one embodiment, the SIMD instructions for the GPGPU core can be generated by a shader compiler at compile time, or automatically generated when executing a program written and compiled for a Single Program Multiple Data (SPMD) or SIMT architecture. In at least one embodiment, multiple threads of a program configured for a SIMT execution model can be executed using a single SIMD instruction. For example, in at least one embodiment, eight SIMD threads performing the same or similar operations can be executed in parallel using a single SIMD8 logic unit.

[0351] In at least one embodiment, the memory and cache interconnect 1968 is an interconnect network connecting each functional unit of the graphics multiprocessor 1934 to the register file 1958 and the shared memory 1970. In at least one embodiment, the memory and cache interconnect 1968 is a cross-switch interconnect that allows the load / store unit 1966 to perform load and store operations between the shared memory 1970 and the register file 1958. In at least one embodiment, the register file 1958 can operate at the same frequency as the GPGPU core 1962, resulting in very low latency for data transfer between the GPGPU core 1962 and the register file 1958. In at least one embodiment, the shared memory 1970 can be used to enable communication between threads executing on functional units within the graphics multiprocessor 1934. In at least one embodiment, the cache memory 1972 can be used, for example, as a data cache to cache texture data communicated between functional units and texture units 1936. In at least one embodiment, the shared memory 1970 can also be used as a program-managed cache. In at least one embodiment, in addition to the data automatically cached in cache memory 1972, the thread executing on GPGPU core 1962 can also programmatically store data in shared memory.

[0352] In at least one embodiment, a parallel processor or GPGPU, as described herein, is communicatively coupled to a host / processor core to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general-purpose GPU (GPGPU) functions. In at least one embodiment, the GPU may be communicatively coupled to the host processor / core via a bus or other interconnect (e.g., high-speed interconnects such as PCIe or NVLink). In at least one embodiment, the GPU may be integrated with the core on the same package or chip and communicatively coupled to the core via an internal processor bus / interconnect (i.e., within the package or chip). In at least one embodiment, regardless of how the GPU is connected, the processor core may assign work to the GPU in the form of a sequence of commands / instructions contained in a job descriptor. In at least one embodiment, the GPU then uses dedicated circuitry / logic to efficiently process these commands / instructions.

[0353] Figure 20A multi-GPU computing system 2000 according to at least one embodiment is illustrated. In at least one embodiment, the multi-GPU computing system 2000 may include a processor 2002 coupled to a plurality of general-purpose graphics processing units (GPGPUs) 2006A-D via a host interface switch 2004. In at least one embodiment, the host interface switch 2004 is a PCI Express switch device that couples the processor 2002 to a PCI Express bus, through which the processor 2002 can communicate with the GPGPUs 2006A-D. The GPGPUs 2006A-D may be interconnected via a set of high-speed P2P GPU-to-GPU links 2016. In at least one embodiment, the GPU-to-GPU links 2016 are connected to each of the GPGPUs 2006A-D via dedicated GPU links. In at least one embodiment, the P2P GPU links 2016 enable direct communication between each of the GPGPUs 2006A-D without communication via the host interface bus to which the processor 2002 is connected. In at least one embodiment, when GPU-to-GPU traffic is directed to the P2P GPU link 2016, the host interface bus remains available for system memory access or, for example, communication with other instances of the multi-GPU computing system 2000 via one or more network devices. While in at least one embodiment, the GPGPUs 2006A-D are connected to the processor 2002 via the host interface switch 2004, in at least one embodiment, the processor 2002 includes direct support for the P2P GPU link 2016 and can be directly connected to the GPGPUs 2006A-D.

[0354] In at least one embodiment, the multi-GPU computing system 2000 generates device packets in parallel to utilize the frequency band and selects one of the generated packets.

[0355] Figure 21 This is a block diagram of a graphics processor 2100 according to at least one embodiment. In at least one embodiment, the graphics processor 2100 includes a ring interconnect 2102, a pipeline front end 2104, a media engine 2137, and graphics cores 2180A-2180N. In at least one embodiment, the ring interconnect 2102 couples the graphics processor 2100 to other processing units, said processing units including other graphics processors or one or more general-purpose processor cores. In at least one embodiment, the graphics processor 2100 is one of many processors integrated within a multi-core processing system.

[0356] In at least one embodiment, graphics processor 2100 receives multiple batches of commands via ring interconnect 2102. In at least one embodiment, the input commands are interpreted by command streamer 2103 in pipeline front-end 2104. In at least one embodiment, graphics processor 2100 includes scalable execution logic for performing 3D geometry processing and media processing via graphics cores 2180A-2180N. In at least one embodiment, for 3D geometry processing commands, command streamer 2103 provides commands to geometry pipeline 2136. In at least one embodiment, for at least some media processing commands, command streamer 2103 provides commands to video front-end 2134, which is coupled to media engine 2137. In at least one embodiment, media engine 2137 includes a video quality engine (VQE) 2130 for video and image post-processing, and a multi-format encoding / decoding (MFX) engine 2133 for providing hardware-accelerated media data encoding and decoding. In at least one embodiment, the geometry pipeline 2136 and the media engine 2137 each generate an execution thread for the thread execution resources provided by at least one graphics core 2180A.

[0357] In at least one embodiment, the graphics processor 2100 includes scalable thread execution resources featuring modular cores 2180A-2180N (sometimes referred to as core slices), each graphics core having multiple sub-cores 2150A-2150N, 2160A-2160N (sometimes referred to as core sub-slices). In at least one embodiment, the graphics processor 2100 may have any number of graphics cores 2180A to 2180N. In at least one embodiment, the graphics processor 2100 includes a graphics core 2180A having at least a first sub-core 2150A and a second sub-core 2160A. In at least one embodiment, the graphics processor 2100 is a low-power processor with a single sub-core (e.g., 2150A). In at least one embodiment, the graphics processor 2100 includes multiple graphics cores 2180A-2180N, each graphics core including a set of first sub-cores 2150A-2150N and a set of second sub-cores 2160A-2160N. In at least one embodiment, each of the first sub-cores 2150A-2150N includes at least a first set of execution units 2152A-2152N and media / texture samplers 2154A-2154N. In at least one embodiment, each of the second sub-cores 2160A-2160N includes at least a second set of execution units 2162A-2162N and samplers 2164A-2164N. In at least one embodiment, each sub-core 2150A-2150N, 2160A-2160N shares a set of shared resources 2170A-2170N. In at least one embodiment, the shared resources include shared cache memory and pixel operation logic.

[0358] In at least one embodiment, the graphics processor 2100 generates device packets in parallel to utilize the frequency band and selects one of the generated packets.

[0359] Figure 22 This is a block diagram illustrating a microarchitecture for a processor 2200 according to at least one embodiment, the processor 2200 including logic circuitry for executing instructions. In at least one embodiment, the processor 2200 can execute instructions, including x86 instructions, ARM instructions, and special-purpose instructions for application-specific integrated circuits (ASICs). In at least one embodiment, the processor 2200 may include registers for storing packaged data, such as the 64-bit wide MMX registers used in Intel Corporation's Santa Clara, California-enabled MMX technology microprocessors. TMRegisters. In at least one embodiment, MMX registers available in integer and floating-point forms can operate alongside packaged data elements accompanied by Single Instruction Multiple Data (“SIMD”) and Streaming SIMD Extensions (“SSE”) instructions. In at least one embodiment, a 128-bit wide XMM register associated with SSE2, SSE3, SSE4, AVX, or later (generally referred to as “SSEx”) technologies can hold such packaged data operands. In at least one embodiment, processor 2200 can execute instructions to accelerate machine learning or deep learning algorithms, training, or inference.

[0360] In at least one embodiment, processor 2200 includes an ordered front end (“front end”) 2201 to fetch instructions to be executed and prepare instructions for later use in the processor pipeline. In at least one embodiment, front end 2201 may include several units. In at least one embodiment, instruction prefetcher 2226 fetches instructions from memory and provides the instructions to instruction decoder 2228, which in turn decodes or interprets the instructions. For example, in at least one embodiment, instruction decoder 2228 decodes the received instructions into one or more machine-executable so-called “micro-instructions” or “micro-operations” (also referred to as “micro-operations” or “micro-instructions”). In at least one embodiment, instruction decoder 2228 parses the instructions into opcodes and corresponding data and control fields, which can be used by the microarchitecture to perform operations according to at least one embodiment. In at least one embodiment, trace cache 2230 may assemble the decoded micro-instructions into a program-ordered sequence or trace in micro-instruction queue 2234 for execution. In at least one embodiment, when trace cache 2230 encounters complex instructions, microcode ROM 2232 provides the micro-instructions required to complete the operation.

[0361] In at least one embodiment, some instructions may be converted into a single micro-operation, while others require several micro-operations to complete the entire operation. In at least one embodiment, if more than four micro-instructions are required to complete an instruction, the instruction decoder 2228 may access the microcode ROM 2232 to execute the instruction. In at least one embodiment, an instruction may be decoded into a small number of micro-instructions for processing at the instruction decoder 2228. In at least one embodiment, if multiple micro-instructions are required to complete the operation, the instructions may be stored in the microcode ROM 2232. In at least one embodiment, the tracking cache 2230 references an entry point programmable logic array (“PLA”) to determine the correct micro-instruction pointer for reading a microcode sequence from the microcode ROM 2232 to complete one or more instructions, according to at least one embodiment. In at least one embodiment, after the microcode ROM 2232 has completed the micro-operation ordering of the instructions, the machine front end 2201 may resume fetching micro-operations from the tracking cache 2230.

[0362] In at least one embodiment, the out-of-order execution engine (“out-of-order engine”) 2203 can prepare instructions for execution. In at least one embodiment, the out-of-order execution logic has multiple buffers to smooth and reorder the instruction flow to optimize performance as instructions descend the pipeline and are scheduled for execution. The out-of-order execution engine 2203 includes, but is not limited to, an allocator / register renamer 2240, a memory microinstruction queue 2242, an integer / floating-point microinstruction queue 2244, a memory scheduler 2246, a fast scheduler 2202, a slow / general-purpose floating-point scheduler (“slow / general-purpose FP scheduler”) 2204, and a simple floating-point scheduler (“simple FP scheduler”) 2206. In at least one embodiment, the fast scheduler 2202, the slow / general-purpose floating-point scheduler 2204, and the simple floating-point scheduler 2206 are also collectively referred to as “microinstruction schedulers 2202, 2204, 2206”. The allocator / register renamer 2240 allocates the machine buffers and resources required for each microinstruction to be executed sequentially. In at least one embodiment, allocator / register renaming unit 2240 renames logical registers to entries in a register file. In at least one embodiment, allocator / register renaming unit 2240 also assigns entries for each microinstruction in one of two microinstruction queues, memory microinstruction queue 2242 for memory operations and integer / floating-point microinstruction queue 2244 for non-memory operations, preceding memory scheduler 2246 and microinstruction schedulers 2202, 2204, 2206. In at least one embodiment, microinstruction schedulers 2202, 2204, 2206 determine when they are ready to execute a microinstruction based on the readiness of their dependent input register operand sources and the availability of the execution resource microinstructions that need to be completed. In at least one embodiment, fast scheduler 2202 can schedule on each half of the master clock cycle, while slow / general-purpose floating-point scheduler 2204 and simple floating-point scheduler 2206 can schedule once per master processor clock cycle. In at least one embodiment, microinstruction schedulers 2202, 2204, and 2206 arbitrate the scheduling port to schedule microinstructions for execution.

[0363] In at least one embodiment, execution block 2211 includes, but is not limited to, integer register file / tribute network 2208, floating-point register file / tribute network (“FP register file / tribute network”) 2210, address generation units (“AGU”) 2212 and 2214, fast arithmetic logic units (“fast ALU”) 2216 and 2218, slow arithmetic logic unit (“slow ALU”) 2220, floating-point ALU (“FP”) 2222, and floating-point movement unit (“FP movement”) 2224. In at least one embodiment, integer register file / tribute network 2208 and floating-point register file / tribute network 2210 are also referred to herein as “register files 2208, 2210”. In at least one embodiment, AGUs 2212 and 2214, fast ALUs 2216 and 2218, slow ALU 2220, floating-point ALU 2222, and floating-point movement unit 2224 are also referred to herein as "execution units 2212, 2214, 2216, 2218, 2220, 2222, and 2224". In at least one embodiment, execution block 2211 may include, but is not limited to, any number (including zero) and type of register files, branch networks, address generation units, and execution units (in any combination).

[0364] In at least one embodiment, register files 2208, 2210 may be arranged between microinstruction schedulers 2202, 2204, 2206 and execution units 2212, 2214, 2216, 2218, 2220, 2222, and 2224. In at least one embodiment, integer register file / tribute network 2208 performs integer operations. In at least one embodiment, floating-point register file / tribute network 2210 performs floating-point operations. In at least one embodiment, each of register files 2208, 2210 may include, but is not limited to, a tribute network that can bypass or forward recently completed results not yet written to the register file to a new dependent object. In at least one embodiment, register files 2208, 2210 may communicate data with each other. In at least one embodiment, integer register file / tribute network 2208 may include, but is not limited to, two separate register files, one register file for low-order 32-bit data and a second register file for high-order 32-bit data. In at least one embodiment, the floating-point register file / branch network 2210 may include, but is not limited to, entries with a width of 128 bits, since floating-point instructions typically have operands with a width of 64 to 128 bits.

[0365] In at least one embodiment, execution units 2212, 2214, 2216, 2218, 2220, 2222, and 2224 can execute instructions. In at least one embodiment, register files 2208 and 2210 store integer and floating-point data operation values ​​that the microinstructions need to execute. In at least one embodiment, processor 2200 can include, but is not limited to, any number of execution units 2212, 2214, 2216, 2218, 2220, 2222, and 2224, and combinations thereof. In at least one embodiment, floating-point ALU 2222 and floating-point move unit 2224 can perform floating-point, MMX, SIMD, AVX, and SSE or other operations, including specialized machine learning instructions. In at least one embodiment, floating-point ALU 2222 can include, but is not limited to, a 64-bit multiplication-64-bit floating-point divider to perform division, square root, and remainder micro-operations. In at least one embodiment, floating-point hardware can be used to process instructions involving floating-point values. In at least one embodiment, ALU operations can be passed to fast ALUs 2216 and 2218. In at least one embodiment, fast ALUs 2216 and 2218 can perform fast operations with an effective delay of half a clock cycle. In at least one embodiment, most complex integer operations are routed to slow ALU 2220, because slow ALU 2220 can include, but is not limited to, integer execution hardware for long-latency type operations, such as multipliers, shifters, flag logic, and branching. In at least one embodiment, memory load / store operations can be performed by AGUS 2212 and 2214. In at least one embodiment, fast ALU 2216, fast ALU 2218, and slow ALU 2220 can perform integer operations on 64-bit data operands. In at least one embodiment, fast ALU 2216, fast ALU 2218, and slow ALU 2220 can be implemented to support various data bit sizes, including sixteen, thirty-two, 128, 256, etc. In at least one embodiment, the floating-point ALU 2222 and the floating-point movement unit 2224 can be implemented to support a range of operands with various bit widths. In at least one embodiment, the floating-point ALU 2222 and the floating-point movement unit 2224 can operate on 128-bit wide packaged data operands in conjunction with SIMD and multimedia instructions.

[0366] In at least one embodiment, microinstruction schedulers 2202, 2204, and 2206 schedule dependent operations before the parent load completes execution. In at least one embodiment, since microinstructions can be speculatively scheduled and executed within processor 2200, processor 2200 may also include logic for handling memory misses. In at least one embodiment, if a data load miss occurs in the data cache, there may be a dependent operation running in the pipeline that temporarily deprives the scheduler of the correct data. In at least one embodiment, a replay mechanism tracks and re-executes instructions that use incorrect data. In at least one embodiment, it may be necessary to replay dependent operations and may allow independent operations to be completed. In at least one embodiment, the scheduler and replay mechanism of at least one embodiment of the processor may also be designed to capture instruction sequences for text string comparison operations.

[0367] In at least one embodiment, the term "register" may refer to an onboard processor storage location that can be used as part of an instruction that identifies an operand. In at least one embodiment, a register may be one that can be used from outside the processor (from a programmer's perspective). In at least one embodiment, a register may not be limited to a particular type of circuitry. Rather, in at least one embodiment, a register may store data, provide data, and perform the functions described herein. In at least one embodiment, the registers described herein may be implemented using a variety of different techniques via circuitry within the processor, such as dedicated physical registers, dynamically allocated physical registers renamed using register renaming, a combination of dedicated and dynamically allocated physical registers, etc. In at least one embodiment, an integer register stores 32-bit integer data. The register file of at least one embodiment also includes eight multimedia SIMD registers for encapsulating data.

[0368] In at least one embodiment, the processor 2200 generates device packets in parallel to utilize the frequency band and selects one of the generated packets.

[0369] Figure 23 A block diagram of a processing system according to at least one embodiment is shown. In at least one embodiment, system 2300 includes one or more processors 2302 and one or more graphics processors 2308, and may be a single-processor desktop system, a multi-processor workstation system, or a server system having a large number of processors 2302 or processor cores 2307. In at least one embodiment, system 2300 is a processing platform incorporated within a system-on-a-chip (SoC) integrated circuit for use in mobile, handheld, or embedded devices.

[0370] In at least one embodiment, system 2300 may include or be integrated into a server-based gaming platform, including a game console, mobile game console, handheld game console, or online game console, which are game and media consoles. In at least one embodiment, system 2300 is a mobile phone, smartphone, tablet computing device, or mobile internet device. In at least one embodiment, processing system 2300 may also include components coupled to or integrated into a wearable device, such as a smartwatch, smart glasses, augmented reality, or virtual reality device. In at least one embodiment, processing system 2300 is a television or set-top box device having one or more processors 2302 and a graphical interface generated by one or more graphics processors 2308.

[0371] In at least one embodiment, each of the one or more processors 2302 includes one or more processor cores 2307 for processing instructions that, when executed, perform operations against the system and user software. In at least one embodiment, each of the one or more processor cores 2307 is configured to process a particular instruction set 2309. In at least one embodiment, the instruction set 2309 may facilitate Complex Instruction Set Computing (CISC), Reduced Instruction Set Computing (RISC), or computation via Very Long Instruction Word (VLIW). In at least one embodiment, each processor core 2307 may process a different instruction set 2309, which may include instructions that facilitate the emulation of other instruction sets. In at least one embodiment, the processor core 2307 may also include other processing devices, such as a digital signal processor (DSP).

[0372] In at least one embodiment, processor 2302 includes cache memory 2304. In at least one embodiment, processor 2302 may have a single internal cache or more levels of internal caches. In at least one embodiment, the cache memory is shared among various components of processor 2302. In at least one embodiment, processor 2302 also uses an external cache (e.g., a Level 3 (L3) cache or a last-level cache (LLC)) (not shown), which can be shared among processor cores 2307 using known cache coherence techniques. In at least one embodiment, processor 2302 further includes a register file 2306, which may include different types of registers (e.g., integer registers, floating-point registers, status registers, and instruction pointer registers) for storing different types of data. In at least one embodiment, register file 2306 may include general-purpose registers or other registers.

[0373] In at least one embodiment, one or more processors 2302 are coupled to one or more interface buses 2310 to transmit communication signals, such as address, data, or control signals, between the processors 2302 and other components in the system 2300. In at least one embodiment, the one or more interface buses 2310 may be a processor bus, such as a version of the Direct Media Interface (DMI) bus. In at least one embodiment, the one or more interface buses 2310 are not limited to the DMI bus and may include one or more peripheral component interconnect buses (e.g., PCI, PCI Express), memory buses, or other types of interface buses. In at least one embodiment, the processor 2302 includes an integrated memory controller 2316 and a platform controller hub 2330. In at least one embodiment, the memory controller 2316 facilitates communication between memory devices and other components of the processing system 2300, while the platform controller hub (PCH) 2330 provides connectivity to input / output (I / O) devices via a local I / O bus.

[0374] In at least one embodiment, memory device 2320 may be a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a flash memory device, a phase-change memory device, or a device with suitable performance for use as processor memory. In at least one embodiment, memory device 2320 may be used as system memory of processing system 2300 to store data 2322 and instructions 2321 for use when one or more processors 2302 execute an application or process. In at least one embodiment, memory controller 2316 is also coupled to an optional external graphics processor 2312, which may communicate with one or more graphics processors 2308 of processor 2302 to perform graphics and media operations. In at least one embodiment, display device 2311 may be connected to processor 2302. In at least one embodiment, display device 2311 may include one or more internal display devices, such as in mobile electronic devices or laptop devices, or external display devices connected via a display interface (e.g., DisplayPort). In at least one embodiment, the display device 2311 may include a head-mounted display (HMD), such as a stereoscopic display device for virtual reality (VR) or augmented reality (AR) applications.

[0375] In at least one embodiment, the platform controller hub 2330 enables peripheral devices to connect to the storage device 2320 and the processor 2302 via a high-speed I / O bus. In at least one embodiment, the I / O peripheral devices include, but are not limited to, an audio controller 2346, a network controller 2334, a firmware interface 2328, a wireless transceiver 2326, a touch sensor 2325, and a data storage device 2324 (e.g., a hard disk drive, flash memory, etc.). In at least one embodiment, the data storage device 2324 may be connected via a storage interface (e.g., SATA) or via a peripheral bus, such as a peripheral component interconnect bus (e.g., PCI, PCIe). In at least one embodiment, the touch sensor 2325 may include a touchscreen sensor, a pressure sensor, or a fingerprint sensor. In at least one embodiment, the wireless transceiver 2326 may be a Wi-Fi transceiver, a Bluetooth transceiver, or a mobile network transceiver, such as a 3G, 4G, or LTE transceiver. In at least one embodiment, the firmware interface 2328 enables communication with the system firmware and may be, for example, a Unified Extensible Firmware Interface (UEFI). In at least one embodiment, network controller 2334 may enable network connectivity to a wired network. In at least one embodiment, a high-performance network controller (not shown) is coupled to one or more interface buses 2310. In at least one embodiment, audio controller 2346 is a multi-channel high-definition audio controller. In at least one embodiment, processing system 2300 includes an optional legacy I / O controller 2340 for coupling legacy (e.g., Personal System 2 (PS / 2)) devices to system 2300. In at least one embodiment, platform controller hub 2330 may also be connected to one or more Universal Serial Bus (USB) controllers 2342 that connect input devices, such as a keyboard and mouse combination 2343, a camera 2344, or other USB input devices.

[0376] In at least one embodiment, instances of the memory controller 2316 and platform controller hub 2330 may be integrated into a discrete external graphics processor, such as external graphics processor 2312. In at least one embodiment, the platform controller hub 2330 and / or the memory controller 2316 may be external to one or more processors 2302. For example, in at least one embodiment, system 2300 may include external memory controller 2316 and platform controller hub 2330, which may be configured as a memory controller hub and peripheral controller hub in a system chipset communicating with processor 2302.

[0377] In at least one embodiment, the processing system 2300 generates packets for the device in parallel to utilize the frequency band and selects one of the generated packets.

[0378] Figure 24 This is a block diagram of a processor 2400 having one or more processor cores 2402A-2402N, an integrated memory controller 2414, and an integrated graphics processor 2408 according to at least one embodiment. In at least one embodiment, the processor 2400 may include additional cores, up to and including additional cores 2402N, indicated by dashed boxes. In at least one embodiment, each processor core 2402A-2402N includes one or more internal cache units 2404A-2404N. In at least one embodiment, each processor core may also access one or more shared cache units 2406.

[0379] In at least one embodiment, internal cache units 2404A-2404N and shared cache unit 2406 represent a cache memory hierarchy within processor 2400. In at least one embodiment, cache memory units 2404A-2404N may include at least one level of instruction and data cache within each processor core and one or more levels of cache in a shared intermediate cache, such as Level 2 (L2), Level 3 (L3), Level 4 (L4), or other levels of cache, wherein the highest level of cache preceding external memory is classified as LLC. In at least one embodiment, cache coherence logic maintains coherence between the various cache units 2406 and 2404A-2404N.

[0380] In at least one embodiment, the processor 2400 may further include a set of one or more bus controller units 2416 and a system agent core 2410. In at least one embodiment, the one or more bus controller units 2416 manage a set of peripheral buses, such as one or more PCI or PCIe buses. In at least one embodiment, the system agent core 2410 provides management functions for various processor components. In at least one embodiment, the system agent core 2410 includes one or more integrated memory controllers 2414 to manage access to various external memory devices (not shown).

[0381] In at least one embodiment, one or more processor cores 2402A-2402N include support for multi-threaded concurrent processing. In at least one embodiment, system agent core 2410 includes components for coordinating and operating cores 2402A-2402N during multi-threaded processing. In at least one embodiment, system agent core 2410 may additionally include a power control unit (PCU) including logic and components for regulating one or more power states of processor cores 2402A-2402N and graphics processor 2408.

[0382] In at least one embodiment, processor 2400 further includes a graphics processor 2408 for performing graph processing operations. In at least one embodiment, graphics processor 2408 is coupled to a shared cache unit 2406 and a system proxy core 2410 including one or more integrated memory controllers 2414. In at least one embodiment, system proxy core 2410 further includes a display controller 2411 for driving graphics processor outputs to one or more coupled displays. In at least one embodiment, display controller 2411 may also be a separate module coupled to graphics processor 2408 via at least one interconnect, or it may be integrated within graphics processor 2408.

[0383] In at least one embodiment, ring-based interconnect unit 2412 is used to couple internal components of processor 2400. In at least one embodiment, alternative interconnect units, such as point-to-point interconnects, switched interconnects, or other technologies, may be used. In at least one embodiment, graphics processor 2408 is coupled to ring interconnect 2412 via I / O link 2413.

[0384] In at least one embodiment, I / O link 2413 represents at least one of a variety of I / O interconnects, including packaged I / O interconnects that facilitate communication between various processor components and high-performance embedded memory module 2418 (e.g., eDRAM module). In at least one embodiment, each of processor cores 2402A-2402N and graphics processor 2408 uses embedded memory module 2418 as a shared last-level cache.

[0385] In at least one embodiment, processor cores 2402A-2402N are homogeneous cores executing a common instruction set architecture. In at least one embodiment, processor cores 2402A-2402N are heterogeneous in terms of instruction set architecture (ISA), with one or more processor cores 2402A-2402N executing a common instruction set, while one or more other processor cores 2402A-2402N execute a subset of the common instruction set or a different instruction set. In at least one embodiment, processor cores 2402A-2402N are heterogeneous in terms of microarchitecture, with one or more cores having relatively high power consumption coupled to one or more power cores having lower power consumption. In at least one embodiment, processor 2400 may be implemented on one or more chips or implemented as a SoC integrated circuit.

[0386] In at least one embodiment, the processor 2400 generates packets for the device in parallel to utilize the frequency band and selects one of the generated packets.

[0387] Figure 25This is a block diagram of a graphics processor 2500, which may be a discrete graphics processing unit or a graphics processor integrated with multiple processing cores. In at least one embodiment, the graphics processor 2500 communicates with registers on the graphics processor 2500 and commands placed in memory via a memory-mapped I / O interface. In at least one embodiment, the graphics processor 2500 includes a memory interface 2514 for accessing memory. In at least one embodiment, the memory interface 2514 is an interface to local memory, one or more internal caches, one or more shared external caches, and / or to system memory.

[0388] In at least one embodiment, the graphics processor 2500 further includes a display controller 2502 for driving display output data to the display device 2520. In at least one embodiment, the display controller 2502 includes a combination of hardware for one or more overlay planes of the display device 2520 and multi-layer video or user interface elements. In at least one embodiment, the display device 2520 may be an internal or external display device. In at least one embodiment, the display device 2520 is a head-mounted display device, such as a virtual reality (VR) display device or an augmented reality (AR) display device. In at least one embodiment, the graphics processor 2500 includes a video codec engine 2506 for encoding, decoding, or transcoding media into one or more media encoding formats, encoding, decoding, or transcoding from one or more media encoding formats, or encoding, decoding, or transcoding between one or more media encoding formats, including but not limited to Moving Picture Experts Group (MPEG) formats (e.g., MPEG-2), Advanced Video Coding (AVC) formats (e.g., H.264 / MPEG-4 AVC, and SMPTE 421M / VC-1), and Joint Picture Experts Group (JPEG) formats (e.g., JPEG) and MotionJPEG (MJPEG) formats.

[0389] In at least one embodiment, the graphics processor 2500 includes a block image transfer (BLIT) engine 2504 to perform two-dimensional (2D) rasterizer operations, including, for example, bit boundary block transfer. However, in at least one embodiment, one or more components of a graphics processing engine (GPE) 2510 are used to perform 2D graphics operations. In at least one embodiment, the GPE 2510 is a computational engine for performing graphics operations, including three-dimensional (3D) graphics operations and media operations.

[0390] In at least one embodiment, GPE 2510 includes a 3D pipeline 2512 for performing 3D operations, such as rendering 3D images and scenes using processing functions that manipulate 3D primitive shapes (e.g., rectangles, triangles, etc.). The 3D pipeline 2512 includes programmable and fixed function elements that perform various tasks and / or generate execution threads to the 3D / media subsystem 2515. While the 3D pipeline 2512 can be used to perform media operations, in at least one embodiment, GPE 2510 also includes a media pipeline 2516 for performing media operations such as video post-processing and image enhancement.

[0391] In at least one embodiment, the media pipeline 2516 includes fixed-function or programmable logic units for performing one or more specialized media operations, such as video decoding acceleration, video deinterlacing, and video encoding acceleration, replacing or representing the video codec engine 2506. In at least one embodiment, the media pipeline 2516 also includes a thread generation unit for generating threads to execute on the 3D / media subsystem 2515. In at least one embodiment, the generated threads perform computations of media operations on one or more graphics execution units included in the 3D / media subsystem 2515.

[0392] In at least one embodiment, the 3D / media subsystem 2515 includes logic for executing threads generated by the 3D pipeline 2512 and the media pipeline 2516. In at least one embodiment, the 3D pipeline 2512 and the media pipeline 2516 send thread execution requests to the 3D / media subsystem 2515, which includes thread dispatch logic for arbitrating various requests and dispatching them to available thread execution resources. In at least one embodiment, the execution resources include an array of graphics execution units for processing 3D and media threads. In at least one embodiment, the 3D / media subsystem 2515 includes one or more internal caches for thread instructions and data. In at least one embodiment, the subsystem 2515 also includes shared memory, which includes registers and addressable memory, for sharing data between threads and storing output data.

[0393] In at least one embodiment, the graphics processor 2500 generates device packets in parallel to utilize the frequency band and selects one of the generated packets.

[0394] Figure 26 This is a block diagram of a graphics processing engine 2610 of a graphics processor according to at least one embodiment. In at least one embodiment, the graphics processing engine (GPE) 2610 is... Figure 25The version of GPE 2510 shown is illustrated. In at least one embodiment, the media pipeline 2616 is optional and may not be explicitly included in the GPE 2610. In at least one embodiment, a separate media and / or image processor is coupled to the GPE 2610.

[0395] In at least one embodiment, GPE 2610 is coupled to or includes command stream converter 2603, which provides command streams to 3D pipeline 2612 and / or media pipeline 2616. In at least one embodiment, command stream converter 2603 is coupled to memory, which may be system memory, or one or more of internal cache memory and shared cache memory. In at least one embodiment, command stream converter 2603 receives commands from memory and sends the commands to 3D pipeline 2612 and / or media pipeline 2616. In at least one embodiment, the commands are instructions, primitives, or micro-operations retrieved from a circular buffer that stores commands for 3D pipeline 2612 and media pipeline 2616. In at least one embodiment, the circular buffer may further include a batch command buffer storing multiple commands in batches. In at least one embodiment, commands for 3D pipeline 2612 may further include references to data stored in memory, such as, but not limited to, vertex and geometry data for 3D pipeline 2612 and / or image data and memory objects for media pipeline 2616. In at least one embodiment, the 3D pipeline 2612 and the media pipeline 2616 process commands and data by performing operations or by dispatching one or more execution threads to the graphics core array 2614. In at least one embodiment, the graphics core array 2614 includes one or more graphics core blocks (e.g., one or more graphics cores 2615A, one or more graphics cores 2615B), each block including one or more graphics cores. In at least one embodiment, each graphics core includes a set of graphics execution resources, which include general and graphics-specific execution logic for performing graphics and computation operations, as well as fixed-function texture processing and / or machine learning and artificial intelligence acceleration logic.

[0396] In at least one embodiment, the 3D pipeline 2612 includes fixed functions and programmable logic for processing one or more shader programs, such as vertex shaders, geometry shaders, pixel shaders, fragment shaders, compute shaders, or other shader programs, by processing instructions and dispatching execution threads to the graphics core array 2614. In at least one embodiment, the graphics core array 2614 provides a unified execution resource block for processing shader programs. In at least one embodiment, the multipurpose execution logic (e.g., execution units) within the graphics cores 2615A-2615B of the graphics core array 2614 includes support for various 3D API shader languages ​​and can execute multiple concurrently running threads associated with multiple shaders.

[0397] In at least one embodiment, the graphics core array 2614 further includes execution logic for performing media functions, such as video and / or image processing. In at least one embodiment, in addition to graphics processing operations, the execution unit also includes general-purpose logic programmable to perform parallel general-purpose computing operations.

[0398] In at least one embodiment, output data can be output to memory in a unified return buffer (URB) 2618, the output data being generated by a thread executing on the graphics core array 2614. In at least one embodiment, the URB 2618 can store data from multiple threads. In at least one embodiment, the URB 2618 can be used to send data between different threads executing on the graphics core array 2614. In at least one embodiment, the URB 2618 can also be used for synchronization between threads on the graphics core array 2614 and fixed-function logic within shared-function logic 2620.

[0399] In at least one embodiment, the graphics core array 2614 is scalable, such that it includes a variable number of graphics cores, each having a variable number of execution units based on the target power and performance level of the GPE 2610. In at least one embodiment, the execution resources are dynamically scalable, such that they can be enabled or disabled as needed.

[0400] In at least one embodiment, the graphics core array 2614 is coupled to shared function logic 2620, which includes multiple resources shared among the graphics cores in the graphics core array 2614. In at least one embodiment, the shared functions performed by the shared function logic 2620 are embodied in hardware logic units that provide dedicated supplementary functions to the graphics core array 2614. In at least one embodiment, the shared function logic 2620 includes, but is not limited to, a sampler 2621, math 2622, and inter-thread communication (ITC) logic 2623. In at least one embodiment, one or more caches 2625 are included in or coupled to the shared function logic 2620.

[0401] In at least one embodiment, shared functionality is used if the demand for dedicated functionality is insufficient to be contained within the graphics core array 2614. In at least one embodiment, a single instance of the dedicated functionality is used within shared functionality logic 2620 and shared among other execution resources within the graphics core array 2614. In at least one embodiment, a specific shared functionality may be included within shared functionality logic 2620 within the graphics core array 2614, said specific shared functionality being within shared functionality logic 2616, which is widely used within the graphics core array 2614. In at least one embodiment, shared functionality logic 2616 within the graphics core array 2614 may include some or all of the logic within shared functionality logic 2620. In at least one embodiment, all logic elements within shared functionality logic 2620 may be replicated within shared functionality logic 2616 of the graphics core array 2614. In at least one embodiment, shared functionality logic 2620 is excluded to support shared functionality logic 2616 within the graphics core array 2614.

[0402] In at least one embodiment, the graphics core 2615 generates device packets in parallel to utilize the frequency band, and another circuit of the graphics processing engine 2610 selects one of the generated packets.

[0403] Figure 27This is a block diagram of the hardware logic of a graphics processor core 2700 according to at least one embodiment described herein. In at least one embodiment, the graphics processor core 2700 is included within a graphics core array. In at least one embodiment, the graphics processor core 2700 (sometimes referred to as a core slice) may be one or more graphics cores within a modular graphics processor. In at least one embodiment, the graphics processor core 2700 is an example of a graphics core slice, and the graphics processor described herein may include multiple graphics core slices based on target power and performance envelopes. In at least one embodiment, each graphics core 2700 may include a fixed-function block 2730, also referred to as a sub-slice, coupled to a plurality of sub-cores 2701A-2701F, which includes modular blocks of general-purpose and fixed-function logic.

[0404] In at least one embodiment, the fixed-function block 2730 includes a geometry and fixed-function pipeline 2736, which, for example, may be shared by all sub-cores of the graphics processor 2700 in a lower-performance and / or lower-power graphics processor implementation. In at least one embodiment, the geometry and fixed-function pipeline 2736 includes a 3D fixed-function pipeline, a video front-end unit, a thread generator and a thread dispatcher, and a unified return buffer manager that manages a unified return buffer.

[0405] In at least one fixed embodiment, fixed functional block 2730 also includes a graphics SoC interface 2737, a graphics microcontroller 2738, and a media pipeline 2739. The graphics SoC interface 2737 provides an interface between the graphics core 2700 and other processor cores in the on-chip integrated circuit system. In at least one embodiment, the graphics microcontroller 2738 is a programmable subprocessor configurable to manage various functions of the graphics processor 2700, including thread dispatch, scheduling, and preemption. In at least one embodiment, the media pipeline 2739 includes logic that facilitates decoding, encoding, preprocessing, and / or post-processing of multimedia data, including image and video data. In at least one embodiment, the media pipeline 2739 implements media operations via requests for computation or sampling logic within subcores 2701-2701F.

[0406] In at least one embodiment, the SoC interface 2737 enables the graphics core 2700 to communicate with a general-purpose application processor core (e.g., a CPU) and / or other components within the SoC, including memory hierarchy elements such as shared last-level cache, system RAM, and / or embedded on-chip or packaged DRAM. In at least one embodiment, the SoC interface 2737 also enables communication with fixed-function devices within the SoC (e.g., a camera imaging pipeline) and enables the use and / or implementation of global memory atoms that can be shared between the graphics core 2700 and the CPU within the SoC. In at least one embodiment, the SoC interface 2737 also implements power management control for the graphics core 2700 and enables interfacing between the clock domain of the graphics core 2700 and other clock domains within the SoC. In at least one embodiment, the SoC interface 2737 enables the receipt of command buffers from a command stream converter and a global thread dispatcher, configured to provide commands and instructions to each of one or more graphics cores within the graphics processor. In at least one embodiment, when a media operation is to be performed, commands and instructions may be dispatched to the media pipeline 2739, or when a graphics processing operation is to be performed, they may be assigned to the geometry and fixed-function pipeline (e.g., geometry and fixed-function pipeline 2736, and / or geometry and fixed-function pipeline 2714).

[0407] In at least one embodiment, the graphics microcontroller 2738 can be configured to perform various scheduling and management tasks on the graphics core 2700. In at least one embodiment, the graphics microcontroller 2738 can perform graphics and / or compute workload scheduling on various graphics parallel engines within the execution unit (EU) arrays 2702A-2702F, 2704A-2704F in subcores 2701A-2701F. In at least one embodiment, host software executing on the CPU core of the SoC including the graphics core 2700 can submit a workload of one of a plurality of graphics processor doorbells, which invokes scheduling operations on the appropriate graphics engine. In at least one embodiment, the scheduling operation includes determining which workload should be run next, submitting the workload to a command stream converter, preempting existing workloads running on the engine, monitoring the progress of the workload, and notifying the host software when the workload is completed. In at least one embodiment, the graphics microcontroller 2738 may also facilitate a low-power or idle state of the graphics core 2700, thereby providing the graphics core 2700 with the ability to save and restore registers across low-power state transitions within the graphics core 2700, independent of the operating system and / or the graphics driver software on the system.

[0408] In at least one embodiment, the graphics core 2700 may have up to N more or fewer modular sub-cores than the illustrated sub-cores 2701A-2701F. For each group of N sub-cores, in at least one embodiment, the graphics core 2700 may further include shared functional logic 2710, shared and / or cache memory 2712, geometry / fixed-function pipeline 2714, and additional fixed-function logic 2716 to accelerate various graphics and computational processing operations. In at least one embodiment, the shared functional logic 2710 may include logic units (e.g., samplers, mathematical and / or inter-thread communication logic) that can be shared by each of the N sub-cores within the graphics core 2700. In at least one embodiment, the shared and / or cache memory 2712 may be the last-level cache of the N sub-cores 2701A-2701F within the graphics core 2700, and may also be used as shared memory accessible by multiple sub-cores. In at least one embodiment, a geometry / fixed function pipeline 2714 may be included to replace the geometry / fixed function pipeline 2736 within the fixed function block 2730, and may include the same or similar logic units.

[0409] In at least one embodiment, the graphics core 2700 includes additional fixed-function logic 2716, which may include various fixed-function acceleration logics for use by the graphics core 2700. In at least one embodiment, the additional fixed-function logic 2716 includes additional geometry pipelines for use in position-only shading. In position-only shading, there are at least two geometry pipelines, and in the full geometry pipeline and culling pipeline within the geometry and fixed-function pipelines 2714, 2736, it is an additional geometry pipeline that can be included in the additional fixed-function logic 2716. In at least one embodiment, the culling pipeline is a trimmed version of the full geometry pipeline. In at least one embodiment, the full pipeline and the culling pipeline can execute different instances of the application, each with a separate environment. In at least one embodiment, position-only shading can hide long culling runs of discarded triangles, thereby allowing shading to be completed earlier in some cases. For example, in at least one embodiment, the culling pipeline logic in the additional fixed-function logic 2716 can execute the position shader in parallel with the main application and typically generates critical results faster than the full pipeline because the culling pipeline acquires and occludes the positional attributes of vertices without performing rasterization and rendering pixels to the framebuffer. In at least one embodiment, the culling pipeline can use the generated critical results to compute visibility information for all triangles, regardless of whether those triangles were culled. In at least one embodiment, the full pipeline (which may be referred to as the replay pipeline in this case) can consume visibility information to skip culled triangles and only occlude the visible triangles that are ultimately passed to the rasterization stage.

[0410] In at least one embodiment, the additional fixed-function logic 2716 may also include machine learning acceleration logic, such as fixed-function matrix multiplication logic, for implementing optimizations for machine learning training or inference.

[0411] In at least one embodiment, each graphics subcore 2701A-2701F includes a set of execution resources that can be used to perform graphics, media, and computational operations in response to requests from the graphics pipeline, media pipeline, or shader program. In at least one embodiment, the graphics subcore 2701A-2701F includes multiple EU arrays 2702A-2702F, 2704A-2704F, thread dispatch and inter-thread communication (TD / IC) logic 2703A-2703F, 3D (e.g., texture) samplers 2705A-2705F, media samplers 2706A-2706F, shader processors 2707A-2707F, and shared local memory (SLM) 2708A-2708F. In at least one embodiment, each of the EU arrays 2702A-2702F and 2704A-2704F includes multiple execution units, which are general-purpose graphics processing units capable of servicing graphics, media, or computational operations, performing floating-point and integer / fixed-point logic operations, including graphics, media, or computational shader programs. In at least one embodiment, the TD / IC logic 2703A-2703F performs local thread dispatch and thread control operations for the execution units within the subcore and facilitates communication between threads executing on the execution units of the subcore. In at least one embodiment, the 3D samplers 2705A-2705F can read data associated with textures or other 3D graphics into memory. In at least one embodiment, the 3D samplers can read texture data differently based on the sampling state and texture format configured and associated with a given texture. In at least one embodiment, the media samplers 2706A-2706F can perform similar read operations based on the type and format associated with the media data. In at least one embodiment, each graphics subcore 2701A-2701F may alternatively include a unified 3D and media sampler. In at least one embodiment, threads executing on execution units within each subcore 2701A-2701F may utilize shared local memory 2708A-2708F within each subcore, enabling threads executing within a thread group to utilize a common pool of on-chip memory for execution.

[0412] In at least one embodiment, subcores 2701A-2701F generate device packets in parallel to utilize the frequency band, and processing core 2700 selects one of the generated packets.

[0413] Figure 28A and 28BThe diagram illustrates thread execution logic 2800 of an array of processing elements including a graphics processor core, according to at least one embodiment. Figure 28A At least one embodiment is shown in which thread execution logic 2800 is used. Figure 28B Exemplary internal details of an execution unit according to at least one embodiment are shown.

[0414] like Figure 28A As shown, in at least one embodiment, thread execution logic 2800 includes a shader processor 2802, a thread dispatcher 2804, an instruction cache 2806, a scalable execution unit array including multiple execution units 2808A-2808N, a sampler 2810, a data cache 2812, and a data port 2814. In at least one embodiment, the scalable execution unit array can be dynamically scaled, for example, based on the computational requirements of the workload, by enabling or disabling one or more execution units (e.g., any one of execution units 2808A, 2808B, 2808C, 2808D, through 2808N-1 and 2808N). In at least one embodiment, the scalable execution units are interconnected via an interconnect structure linking to each execution unit. In at least one embodiment, the thread execution logic 2800 includes one or more connections to memory (such as system memory or cache memory) via one or more of the instruction cache 2806, data port 2814, sampler 2810, and execution units 2808A-2808N. In at least one embodiment, each execution unit (e.g., 2808A) is an independent programmable general-purpose computing unit capable of executing multiple concurrent hardware threads, processing multiple data elements in parallel for each thread. In at least one embodiment, the array of execution units 2808A-2808N is scalable to include any number of individual execution units.

[0415] In at least one embodiment, execution units 2808A-2808N are primarily used to execute shader programs. In at least one embodiment, shader processor 2802 can process various shader programs and dispatch execution threads associated with the shader programs via thread dispatcher 2804. In at least one embodiment, thread dispatcher 2804 includes logic for arbitrating thread initialization celebrations from the graphics and media pipeline and for instantiating requested threads on one or more execution units 2808A-2808N. For example, in at least one embodiment, the geometry pipeline can dispatch vertex, tessellation, or geometry shaders to thread execution logic for processing. In at least one embodiment, thread dispatcher 2804 can also handle runtime thread generation requests from executing shader programs.

[0416] In at least one embodiment, the execution units 2808A-2808N support an instruction set that includes native support for many standard 3D graphics shader instructions, enabling shader programs in graphics libraries (e.g., Direct3D and OpenGL) to execute with minimal conversion. In at least one embodiment, the execution units support vertex and geometry processing (e.g., vertex programs, geometry programs, vertex shaders), pixel processing (e.g., pixel shaders, fragment shaders), and general processing (e.g., computation and media shaders). In at least one embodiment, each execution unit 2808A-2808N includes one or more arithmetic logic units (ALUs) capable of performing multiple-issue single-instruction multiple-data (SIMD) operations, and multithreaded operation enables an efficient execution environment despite higher latency memory access. In at least one embodiment, each hardware thread within each execution unit has a dedicated high-bandwidth register file and associated independent thread states. In at least one embodiment, execution is multiple issues per clock cycle to a pipeline capable of integer, single-precision, and double-precision floating-point operations, SIMD branching functions, logical operations, a priori operations, and other operations. In at least one embodiment, while waiting for data from one of the memory or shared functions, dependency logic within execution units 2808A-2808N causes the waiting thread to sleep until the requested data is returned. In at least one embodiment, while the waiting thread is sleeping, hardware resources can be dedicated to processing other threads. For example, in at least one embodiment, during the latency associated with vertex shader operations, the execution unit can perform operations on the pixel shader, fragment shader, or another type of shader program (including different vertex shaders).

[0417] In at least one embodiment, each execution unit in the execution units 2808A-2808N operates on an array of data elements. In at least one embodiment, the plurality of data elements is an "execution size" or the number of instruction channels. In at least one embodiment, an execution channel is a logical unit for execution of data element access, masking, and flow control within an instruction. In at least one embodiment, the plurality of channels may be independent of the plurality of physical arithmetic logic units (ALUs) or floating-point units (FPUs) for a particular graphics processor. In at least one embodiment, the execution units 2808A-2808N support integer and floating-point data types.

[0418] In at least one embodiment, the execution unit instruction set includes SIMD instructions. In at least one embodiment, various data elements can be stored in registers as encapsulated data types, and the execution unit will process various elements based on the data size of those elements. For example, in at least one embodiment, when operating on a 256-bit wide vector, 256 bits of the vector are stored in registers, and the execution unit operates on the vector as four separate 64-bit encapsulated data elements (quad-word (QW) size data elements), eight separate 32-bit encapsulated data elements (double-word (DW) size data elements), sixteen separate 16-bit encapsulated data elements (word (W) size data elements), or thirty-two separate 8-bit data elements (byte (B) size data elements). However, in at least one embodiment, different vector widths and register sizes are possible.

[0419] In at least one embodiment, one or more execution units may be combined into a fused execution unit 2809A-2809N having thread control logic (2807A-2807N) that typically fuses EUs. In at least one embodiment, multiple EUs may be fused into an EU group. In at least one embodiment, the number of EUs in the fused EU group may be configured to execute separate SIMD hardware threads. The number of EUs in the fused EU group may vary depending on the embodiment. In at least one embodiment, each EU may execute various SIMD widths, including but not limited to SIMD8, SIMD16, and SIMD32. In at least one embodiment, each fused graphics execution unit 2809A-2809N includes at least two execution units. For example, in at least one embodiment, the fused execution unit 2809A includes a first EU 2808A, a second EU 2808B, and thread control logic 2807A shared by the first EU 2808A and the second EU 2808B. In at least one embodiment, thread control logic 2807A controls the threads executing on the fused graphics execution unit 2809A, thereby allowing each EU within the fused execution units 2809A-2809N to execute using a common instruction pointer register.

[0420] In at least one embodiment, one or more internal instruction caches (e.g., 2806) are included in the thread execution logic 2800 to cache thread instructions for the execution unit. In at least one embodiment, one or more data caches (e.g., 2812) are included to cache thread data during thread execution. In at least one embodiment, a sampler 2810 is included to provide texture sampling for 3D operations and media sampling for media operations. In at least one embodiment, the sampler 2810 includes dedicated texture or media sampling functions to process texture or media data during the sampling process before providing sampled data to the execution unit.

[0421] During execution, in at least one embodiment, the graphics and media pipeline sends thread initiation requests to thread execution logic 2800 via thread creation and dispatch logic. In at least one embodiment, once a set of geometric objects has been processed and rasterized into pixel data, pixel processor logic (e.g., pixel shader logic, fragment shader logic, etc.) within shader processor 2802 is invoked to further compute output information and cause the results to be written to output surfaces (e.g., color buffer, depth buffer, stencil buffer, etc.). In at least one embodiment, the pixel shader or fragment shader computes values ​​of various vertex attributes to be interpolated on the rasterized objects. In at least one embodiment, the pixel processor logic within shader processor 2802 then executes a pixel or fragment shader program provided by an application programming interface (API). In at least one embodiment, to execute the shader program, shader processor 2802 dispatches threads to execution units (e.g., 2808A) via thread dispatcher 2804. In at least one embodiment, shader processor 2802 uses texture sampling logic in sampler 2810 to access texture data in a texture map stored in memory. In at least one embodiment, arithmetic operations on the texture data and the input geometry data are performed to calculate pixel color data for each geometric segment, or one or more pixels are discarded for further processing.

[0422] In at least one embodiment, data port 2814 provides a memory access mechanism for thread execution logic 2800 to output processed data to memory for further processing on the graphics processor output pipeline. In at least one embodiment, data port 2814 includes or is coupled to one or more cache memories (e.g., data cache 2812) to cache data for memory access via the data port.

[0423] like Figure 28BAs shown, in at least one embodiment, the graphics execution unit 2808 may include an instruction fetch unit 2837, a general-purpose register file array (GRF) 2824, an architecture register file array (ARF) 2826, a thread arbiter 2822, a send unit 2830, a branch unit 2832, a set of SIMD floating-point units (FPUs) 2834, and a set of dedicated integer SIMD ALUs 2835. In at least one embodiment, the GRF 2824 and ARF 2826 include a set of general-purpose register files and architecture register files associated with each concurrent hardware thread that may be active in the graphics execution unit 2808. In at least one embodiment, the architecture state of each thread is maintained in the ARF 2826, while data used during thread execution is stored in the GRF 2824. In at least one embodiment, the execution state of each thread, including the instruction pointer of each thread, may be stored in thread-specific registers in the ARF 2826.

[0424] In at least one embodiment, the graphics execution unit 2808 has an architecture that is a combination of simultaneous multithreading (SMT) and fine-grained interleaved multithreading (IMT). In at least one embodiment, the architecture has a modular configuration that can be fine-tuned at design time based on a target number of simultaneous threads and the number of registers per execution unit, wherein execution unit resources are logically allocated for executing multiple simultaneous threads.

[0425] In at least one embodiment, the graphics execution unit 2808 can jointly issue multiple instructions, each of which can be a different instruction. In at least one embodiment, the thread arbiter 2822 of the graphics execution unit thread 2808 can dispatch instructions to one of the sending unit 2830, the branching unit 2842, or the SIMD FPU 2834 for execution. In at least one embodiment, each execution thread can access 128 general-purpose registers in the GRF 2824, where each register can store 32 bytes and can be accessed as a SIMD 8-element vector of 32-bit data elements. In at least one embodiment, each execution unit thread can access 4 KB in the GRF 2824, although the embodiments are not limited thereto, and more or fewer register resources may be provided in other embodiments. In at least one embodiment, although the number of threads per execution unit may also vary depending on the embodiment, a maximum of seven threads can be executed simultaneously. In at least one embodiment where seven threads can access 4 KB, the GRF 2824 can store a total of 28 KB. In at least one embodiment, the flexible addressing mode can allow registers to be addressed together to efficiently build wider registers or rectangular block data structures representing strides.

[0426] In at least one embodiment, memory operations, sampler operations, and other longer-latency system communications are scheduled via a "send" instruction executed by message sending unit 2830. In at least one embodiment, branch instructions are dispatched to a dedicated branching unit 2832 to facilitate SIMD divergence and eventual convergence.

[0427] In at least one embodiment, the graphics execution unit 2808 includes one or more SIMD floating-point units (FPUs) 2834 to perform floating-point operations. In at least one embodiment, the one or more FPUs 2834 also support integer computation. In at least one embodiment, the one or more FPUs 2834 can perform up to M 32-bit floating-point (or integer) operations in SIMD, or up to 2M 16-bit integer or 16-bit floating-point operations in SIMD. In at least one embodiment, at least one FPU provides extended mathematical capabilities to support high-throughput a priori mathematical functions and double-precision 64-bit floating-point operations. In at least one embodiment, a set of 8-bit integer SIMD ALUs 2835 is also present and can be specifically optimized to perform operations related to machine learning computations.

[0428] In at least one embodiment, an array of multiple instances of the graphics execution unit 2808 may be instantiated in a graphics sub-core group (e.g., a sub-slice). In at least one embodiment, the execution unit 2808 may execute instructions across multiple execution channels. In at least one embodiment, each thread executed on the graphics execution unit 2808 executes on a different channel.

[0429] In at least one embodiment, an array of multiple instances of the graphics execution unit 2808 generates device groups in parallel to utilize the frequency band.

[0430] Figure 29A parallel processing unit (“PPU”) 2900 according to at least one embodiment is illustrated. In at least one embodiment, the PPU 2900 is configured with machine-readable code that, if executed by the PPU 2900, causes the PPU 2900 to perform some or all of the processes and techniques described herein. In at least one embodiment, the PPU 2900 is a multi-threaded processor implemented on one or more integrated circuit devices and utilizes multi-threading as a latency-hiding technique designed to process computer-readable instructions (also referred to as machine-readable instructions or simple instructions) executed in parallel on multiple threads. In at least one embodiment, a thread refers to an execution thread and is an instance of a set of instructions configured to be executed by the PPU 2900. In at least one embodiment, the PPU 2900 is a graphics processing unit (“GPU”) configured to implement a graphics rendering pipeline for processing three-dimensional (“3D”) graphics data to generate two-dimensional (“2D”) image data for display on a display device, such as a liquid crystal display (“LCD”) device. In at least one embodiment, the PPU 2900 is used to perform computations, such as linear algebra operations and machine learning operations. Figure 29 An example parallel processor is shown for illustrative purposes only and should be interpreted as a non-limiting example of a processor architecture contemplated within the scope of this disclosure, which may be supplemented and / or replaced by any suitable processor.

[0431] In at least one embodiment, one or more PPU 2900s are configured to accelerate high-performance computing (“HPC”), data center, and machine learning applications. In at least one embodiment, the PPU 2900 is configured to accelerate deep learning systems and applications, including, but not limited to, the following non-limiting examples: autonomous vehicle platforms, deep learning, high-precision speech, image, and text recognition systems, intelligent video analytics, molecular simulation, drug discovery, disease diagnosis, weather forecasting, big data analytics, astronomy, molecular dynamics simulation, financial modeling, robotics, factory automation, real-time language conversion, online search optimization, and personalized user recommendations, etc.

[0432] In at least one embodiment, the PPU 2900 includes, but is not limited to, an input / output (“I / O”) unit 2906, a front-end unit 2910, a scheduler unit 2912, a job allocation unit 2914, a hub 2916, a crossbar (“Xbar”) 2920, one or more general-purpose processing clusters (“GPCs”) 2918, and one or more partitioning units (“memory partitioning units”) 2922. In at least one embodiment, the PPU 2900 is connected to a host processor or other PPU 2900 via one or more high-speed GPU interconnects (“GPU interconnects”) 2908. In at least one embodiment, the PPU 2900 is connected to a host processor or other peripheral device via an interconnect 2902. In one embodiment, the PPU 2900 is connected to local memory including one or more memory devices (“memory”) 2904. In at least one embodiment, the memory device 2904 includes, but is not limited to, one or more dynamic random access memory (“DRAM”) devices. In at least one embodiment, one or more DRAM devices are configured and / or configurable as high-bandwidth memory (“HBM”) subsystems, and multiple DRAM dies are stacked within each device.

[0433] In at least one embodiment, the high-speed GPU interconnect 2908 may refer to a wire-based multi-channel communication link used by the system for scaling, and includes one or more PPUs 2900s (“CPUs”) combined with one or more central processing units, supporting cache coherency between the PPUs 2900s and the CPUs, as well as CPU master control. In at least one embodiment, the high-speed GPU interconnect 2908 transmits data and / or commands to other units of the PPU 2900, such as one or more copy engines, video encoders, video decoders, power management units, and / or other components, via a hub 2916. Figure 29 Other components that may not be explicitly shown.

[0434] In at least one embodiment, the I / O unit 2906 is configured to access the host processor via the system bus. Figure 29 (Not shown) Sending and receiving communications (e.g., commands, data). In at least one embodiment, I / O unit 2906 communicates directly with the host processor via the system bus or via one or more intermediate devices (e.g., memory bridges). In at least one embodiment, I / O unit 2906 may communicate with one or more other processors (e.g., one or more PPUs 2900) via the system bus. In at least one embodiment, I / O unit 2906 implements a Peripheral Component Interconnect Express (“PCIe”) interface for communication via the PCIe bus. In at least one embodiment, I / O unit 2906 implements an interface for communicating with external devices.

[0435] In at least one embodiment, I / O unit 2906 decodes packets received via the system bus. In at least one embodiment, at least some packets represent commands configured to cause PPU 2900 to perform various operations. In at least one embodiment, I / O unit 2906 sends the decoded commands to various other units of PPU 2900 as specified by the commands. In at least one embodiment, the commands are sent to front-end unit 2910 and / or to hub 2916 or other units of PPU 2900, such as one or more copy engines, video encoders, video decoders, power management units, etc. Figure 29 (Not explicitly shown). In at least one embodiment, I / O unit 2906 is configured to route communication between various logical units of PPU 2900.

[0436] In at least one embodiment, a program executed by the host processor encodes a command stream in a buffer that provides a workload to the PPU 2900 for processing. In at least one embodiment, the workload includes instructions and data to be processed by those instructions. In at least one embodiment, the buffer is a region in memory accessible (e.g., read / write) by both the host processor and the PPU 2900—the host interface unit can be configured to access the buffer in system memory connected to the system bus via memory requests transmitted through the system bus via I / O unit 2906. In at least one embodiment, the host processor writes a command stream to the buffer and then sends a pointer indicating the start of the command stream to the PPU 2900, causing the front-end unit 2910 to receive pointers to one or more command streams and manage one or more command streams, read commands from the command streams, and forward the commands to the respective units of the PPU 2900.

[0437] In at least one embodiment, front-end unit 2910 is coupled to scheduler unit 2912, which configures various GPCs 2918 to process tasks defined by one or more command streams. In at least one embodiment, scheduler unit 2912 is configured to track status information related to the various tasks managed by scheduler unit 2912, wherein the status information may indicate which GPC 2918 a task is assigned to, whether the task is active or inactive, the priority associated with the task, etc. In at least one embodiment, scheduler unit 2912 manages multiple tasks executed on one or more GPCs 2918.

[0438] In at least one embodiment, scheduler unit 2912 is coupled to job allocation unit 2914, which is configured to dispatch tasks for execution on GPC 2918. In at least one embodiment, job allocation unit 2914 tracks multiple scheduled tasks received from scheduler unit 2912 and manages a pool of pending tasks and an active task pool for each GPC 2918. In at least one embodiment, the pool of pending tasks includes multiple time slots (e.g., 32 time slots) containing tasks assigned to a particular GPC 2918 for processing; the active task pool may include multiple time slots (e.g., 4 time slots) for tasks actively processed by GPC 2918, such that as one of the GPCs 2918 completes its execution, that task is evicted from the active task pool of the GPC 2918, and another task is selected from the pool of pending tasks and scheduled for execution on the GPC 2918. In at least one embodiment, if the active task is idle on GPC 2918, for example while waiting for data dependency resolution, the active task is evicted from GPC 2918 and returned to the task pool, while another task in the task pool is selected and scheduled to be executed on GPC 2918.

[0439] In at least one embodiment, the work allocation unit 2914 communicates with one or more GPCs 2918 via XBar 2920. In at least one embodiment, XBar 2920 is an interconnect network that couples a plurality of units of PPU 2900 to other units of PPU 2900, and can be configured to couple the work allocation unit 2914 to a specific GPC 2918. In at least one embodiment, other units of one or more PPUs 2900 can also be connected to XBar 2920 via hub 2916.

[0440] In at least one embodiment, tasks are managed by scheduler unit 2912 and assigned to one of GPCs 2918 by job allocation unit 2914. In at least one embodiment, GPC 2918 is configured to process tasks and produce results. In at least one embodiment, results may be consumed by other tasks in GPC 2918, routed to different GPCs 2918 via XBar 2920, or stored in memory 2904. In at least one embodiment, results may be written to memory 2904 via partitioning unit 2922, which implements a memory interface for writing data to or reading data from memory 2904. In at least one embodiment, results may be transferred to another PPU 2904 or CPU via high-speed GPU interconnect 2908. In at least one embodiment, PPU 2900 includes, but is not limited to, U partitioning units 2922, which is equal to the number of separate and different memory devices 2904 coupled to PPU 2900. In at least one embodiment, partitioning units 2922 will combine Figure 31 To describe in more detail.

[0441] In at least one embodiment, the host processor executes a driver core that implements an application programming interface (API) that enables one or more applications executing on the host processor to schedule operations for execution on the PPU 2900. In one embodiment, multiple computing applications are executed concurrently by the PPU 2900, and the PPU 2900 provides isolation, Quality of Service (“QoS”), and independent address spaces for the multiple computing applications. In at least one embodiment, application-generating instructions (e.g., in the form of API calls) cause the driver core to generate one or more tasks for execution by the PPU 2900, and the driver core outputs the tasks to one or more streams processed by the PPU 2900. In at least one embodiment, each task includes one or more associated thread groups, which may be referred to as a warp. In at least one embodiment, a warp includes multiple associated threads (e.g., 32 threads) that can be executed in parallel. In at least one embodiment, a cooperating thread may refer to multiple threads, including instructions for performing tasks and exchanging data via shared memory, in combination with... Figure 31 Threads and cooperative threads are described in more detail according to at least one embodiment.

[0442] Figure 30 A general-purpose processing cluster (“GPC”) 3000 is illustrated according to at least one embodiment. In at least one embodiment, the GPC 3000 is Figure 29The GPC 2918. In at least one embodiment, each GPC 3000 includes, but is not limited to, a plurality of hardware units for processing tasks, and each GPC 3000 includes, but is not limited to, a pipeline manager 3002, a pre-raster operation unit (“PROP”) 3004, a raster engine 3008, a work assignment crossbar switch (“WDX”) 3016, a memory management unit (“MMU”) 3018, one or more data processing clusters (“DPC”) 3006, and any suitable combination of components.

[0443] In at least one embodiment, the operation of GPC 3000 is controlled by pipeline manager 3002. In at least one embodiment, pipeline manager 3002 manages the configuration of one or more DPCs 3006 to handle tasks assigned to GPC 3000. In at least one embodiment, pipeline manager 3002 configures at least one of one or more DPCs 3006 to implement at least a portion of the graphics rendering pipeline. In at least one embodiment, DPC 3006 is configured to execute vertex shader programs on a programmable streaming multiprocessor (“SM”) 3014. In at least one embodiment, pipeline manager 3002 is configured to route data packets received from the work allocation unit to appropriate logic units within GPC 3000, and in at least one embodiment, some data packets may be routed to fixed-function hardware units in PROP 3004 and / or raster engine 3008, while other data packets may be routed to DPC 3006 for processing by raw engine 3012 or SM 3014. In at least one embodiment, pipeline manager 3002 configures at least one of DPCs 3006 to implement a neural network model and / or computation pipeline.

[0444] In at least one embodiment, the PROP unit 3004 is configured to route data generated by the raster engine 3008 and DPC 3006 to the raster operation (“ROP”) unit in the partition unit 2922, in conjunction with the above. Figure 29More detailed description. In at least one embodiment, the PROP unit 3004 is configured to perform optimizations for color blending, organize pixel data, perform address translation, etc. In at least one embodiment, the raster engine 3008 includes, but is not limited to, multiple fixed-function hardware units configured to perform various raster operations, and in at least one embodiment, the raster engine 3008 includes, but is not limited to, a setup engine, a coarse raster engine, a culling engine, a clipping engine, a fine raster engine, a tile aggregation engine, and any suitable combination thereof. In at least one embodiment, the setup engine receives transformed vertices and generates plane equations associated with the geometric primitives defined by the vertices; the plane equations are passed to the coarse raster engine to generate coverage information of basic primitives (e.g., x, y coverage masks of tiles); the output of the coarse raster engine is passed to the culling engine, in which fragments associated with primitives that fail the z-test are culled, and passed to the clipping engine, in which fragments located outside the view frustum are clipped. In at least one embodiment, the clipped and culled fragments are passed to the fine raster engine to generate properties of pixel fragments based on the plane equations generated by the setup engine. In at least one embodiment, the output of the raster engine 3008 includes fragments that will be processed by any appropriate entity (e.g., by the fragment shader implemented within the DPC 3006).

[0445] In at least one embodiment, each DPC 3006 included in the GPC 3000 includes, but is not limited to, an M-pipeline controller (“MPC”) 3010; a primitive engine 3012; one or more SMs 3014; and any suitable combination thereof. In at least one embodiment, the MPC 3010 controls the operation of the DPC 3006, routing packets received from the pipeline manager 3002 to the appropriate units within the DPC 3006. In at least one embodiment, packets associated with vertices are routed to the primitive engine 3012, which is configured to retrieve vertex attributes associated with vertices from memory; conversely, data packets associated with shader programs may be sent to the SMs 3014.

[0446] In at least one embodiment, the SM 3014 includes, but is not limited to, a programmable streaming processor configured to process tasks represented by multiple threads. In at least one embodiment, the SM 3014 is multithreaded and configured to execute multiple threads (e.g., 32 threads) from a specific thread group concurrently, and implements a Single Instruction, Multiple Data (“SIMD”) architecture, wherein each thread in a group of threads (e.g., a thread bundle) is configured to process a different dataset based on the same instruction set. In at least one embodiment, all threads in the thread group execute the same instructions. In at least one embodiment, the SM 3014 implements a Single Instruction, Multiple Thread (“SIMT”) architecture, wherein each thread in a group of threads is configured to process a different dataset based on the same instruction set, but wherein individual threads in the thread group are allowed to diverge during execution. In at least one embodiment, a program counter, call stack, and execution state are maintained for each thread bundle, thereby achieving concurrency between the thread bundle and serial execution within the thread bundle when threads in the thread bundle diverge. In another embodiment, a program counter, call stack, and execution state are maintained for each individual thread, thereby ensuring equal concurrency among all threads within and between thread bundles. In at least one embodiment, an execution state is maintained for each individual thread, and threads executing the same instructions can be converged and executed in parallel to improve efficiency. At least one embodiment of the SM 3014 is described in more detail herein.

[0447] In at least one embodiment, the MMU 3018 is integrated with the GPC 3000 and memory partitioning unit (e.g., Figure 29 The MMU 3018 provides an interface between the partition units 2922 and the physical address translation, memory protection, and memory request arbitration. In at least one embodiment, the MMU 3018 provides one or more translation back buffers (“TLBs”) for performing virtual address to physical address translation in memory.

[0448] In at least one embodiment, the GPC 3000 generates device packets in parallel to utilize the frequency band and selects one of the generated packets.

[0449] Figure 31A memory partitioning unit 3100 of a parallel processing unit (“PPU”) according to at least one embodiment is illustrated. In at least one embodiment, the memory partitioning unit 3100 includes, but is not limited to, a raster operation (“ROP”) unit 3102; a secondary (“L2”) cache 3104; a memory interface 3106; and any suitable combination thereof. The memory interface 3106 is coupled to memory. The memory interface 3106 may implement a 31, 64, 128, or 1024-bit data bus, or a similar implementation for high-speed data transfer. In at least one embodiment, the PPU includes U memory interfaces 3106, one memory interface 3106 per pair of partitioning units 3100, wherein each pair of partitioning units 3100 is connected to a corresponding memory device. For example, in at least one embodiment, the PPU may be connected to up to Y memory devices, such as a high-bandwidth memory stack or a graphics dual data rate version 5 synchronous dynamic random access memory (“GDDR5 SDRAM”).

[0450] In at least one embodiment, memory interface 3106 implements a high-bandwidth memory second-generation (“HBM2”) memory interface, and Y is equal to half of U. In at least one embodiment, the HBM2 memory stack resides on the same physical package as a PPU, providing significant power savings and area savings compared to conventional GDDR5 SDRAM systems. In at least one embodiment, each HBM2 stack includes, but is not limited to, four memory dies, with Y=4, and each HBM2 stack includes two 128-bit channels per die for a total of eight channels and a 1024-bit data bus width. In at least one embodiment, the memory supports Single Error Corrected Double Error Detection (“SECDED”) error correction code (“ECC”) to protect data. ECC can provide higher reliability for data corruption-sensitive computing applications.

[0451] In at least one embodiment, the PPU implements a multi-level memory hierarchy. In at least one embodiment, memory partitioning unit 3100 supports unified memory to provide a single unified virtual address space for the central processing unit (“CPU”) and PPU memory, thereby enabling data sharing between virtual memory systems. In at least one embodiment, the frequency of PPU accesses to memory located on other processors is tracked to ensure that memory pages are moved to the physical memory of the PPU that accesses pages more frequently. In at least one embodiment, high-speed GPU interconnect 2908 supports address translation services, which allow the PPU to directly access the CPU's page tables and provide full access to the CPU's memory through the PPU.

[0452] In at least one embodiment, the replication engine transfers data between multiple PPUs or between a PPU and a CPU. In at least one embodiment, the replication engine can generate page faults for addresses not mapped to page tables, and memory partitioning unit 3100 then servicees the page faults, mapping the addresses t...

Claims

1. A processor, comprising: One or more processing cores are used to execute multiple thread blocks in parallel, where each thread block is used to generate multiple candidate packets for multiple devices for a frequency band and select one packet to utilize that frequency band. Specifically, for each of the plurality of thread blocks, the thread block is used to evaluate a plurality of candidate groups generated by the thread block, and select the candidate group with the highest sum and rate from the plurality of candidate groups as the optimal group based on the evaluation results. Each thread block generates candidate groups by: calculating the channel gain of the plurality of devices, sorting the plurality of devices based on the calculated channel gain, and selecting the plurality of devices based on the sorting to include them in the candidate groups.

2. The processor of claim 1, wherein candidate groups for the device are generated at least in part based on a heuristic algorithm.

3. The processor of claim 2, wherein the heuristic algorithm includes iteratively adding the device to the candidate group of the device, at least in part based on channel gain.

4. The processor of claim 2, wherein the heuristic algorithm is executed by a thread block associated with at least one of the one or more processing cores.

5. The processor of claim 1, wherein the selected packet is allocated to frequency resources associated with the frequency band and time period.

6. The processor of claim 1, wherein the frequency band is at least partially based on the 5G communication standard.

7. The processor of claim 1, wherein the MU-MIMO transmission is at least partially based on the selected packet.

8. A system comprising: One or more processors are configured to execute multiple thread blocks in parallel, wherein each thread block is configured to generate multiple candidate groups of multiple devices for a frequency band and select one group to utilize the frequency band, and for each of the multiple thread blocks, the thread block is configured to evaluate the multiple candidate groups generated by the thread block and select the candidate group with the highest sum and rate as the best group based on the evaluation results, wherein each thread block generates candidate groups by: calculating the channel gain of the multiple devices, sorting the multiple devices based on the calculated channel gain, and selecting the multiple devices to be included in the candidate group based on the sorting.

9. The system of claim 8, wherein candidate groups of the device are generated at least in part based on a heuristic algorithm.

10. The system of claim 9, wherein the heuristic algorithm includes iteratively adding devices to the candidate groups of the devices, at least in part based on channel gain.

11. The system of claim 9, wherein the heuristic algorithm is executed by a thread block associated with at least one of the one or more processing cores.

12. The system of claim 8, wherein the selected packet is allocated to frequency resources associated with the frequency band and time period.

13. The system of claim 8, wherein the frequency band is at least partially based on the 5G communication standard.

14. The system of claim 8, wherein the MU-MIMO transmission is at least partially based on the selected packet.

15. A machine-readable medium having a set of instructions stored thereon, which, when executed by one or more processors, causes the one or more processors to at least: Multiple thread blocks are executed in parallel, where each thread block is used to generate multiple candidate packets for multiple devices for a frequency band and select one packet to utilize that frequency band. in, For each of the plurality of thread blocks, the thread block is used to evaluate a plurality of candidate groups generated by the thread block, and select the candidate group with the highest sum and rate from the plurality of candidate groups as the optimal group based on the evaluation results. Each thread block generates candidate groups by: calculating the channel gain of the plurality of devices, sorting the plurality of devices based on the calculated channel gain, and selecting the plurality of devices based on the sorting to include them in the candidate groups.

16. The machine-readable medium of claim 15, wherein candidate groups of the device are generated at least in part based on a heuristic algorithm.

17. The machine-readable medium of claim 16, wherein the heuristic algorithm includes iteratively adding the device to the candidate group of the device, at least in part based on channel gain.

18. The machine-readable medium of claim 16, wherein the heuristic algorithm is executed by a thread block associated with at least one of the one or more processing cores.

19. The machine-readable medium of claim 15, wherein the selected packet is allocated to frequency resources associated with the frequency band and time period.

20. The machine-readable medium of claim 15, wherein the frequency band is at least partially based on the 5G communication standard.

21. The machine-readable medium of claim 15, wherein the MU-MIMO transmission is at least partially based on the selected packet.

22. A communication device, comprising: Multiple processing cores are used to execute multiple thread blocks in parallel, where each thread block is used to generate multiple candidate packets for multiple devices for a frequency band and select one packet to utilize that frequency band. Specifically, for each of the plurality of thread blocks, the thread block is used to evaluate a plurality of candidate groups generated by the thread block, and select the candidate group with the highest sum and rate from the plurality of candidate groups as the optimal group based on the evaluation results. Each thread block generates candidate groups by: calculating the channel gain of the plurality of devices, sorting the plurality of devices based on the calculated channel gain, and selecting the plurality of devices based on the sorting to include them in the candidate groups.

23. The communication device of claim 22, wherein candidate packets of the device are generated based at least in part on a heuristic algorithm.

24. The communication device of claim 23, wherein the heuristic algorithm includes iteratively adding the device to the candidate packets of the device, at least in part based on channel gain.

25. The communication device of claim 23, wherein the heuristic algorithm is executed by a thread block associated with at least one of one or more processing cores.

26. The communication device of claim 22, wherein the selected packet is allocated to frequency resources associated with the frequency band and time period.

27. The communication device of claim 22, wherein the frequency band is at least partially based on the 5G communication standard.

28. The communication device of claim 22, wherein the MU-MIMO transmission is at least partially based on the selected packet.

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