Transistor source / drain contacts and methods of forming the same

Abstract

The present disclosure relates generally to transistor source / drain contacts and methods of forming the same. In one embodiment, a device includes a gate structure over a channel region of a substrate, a gate mask over the gate structure, the gate mask including a first dielectric material and an impurity, a concentration of the impurity in the gate mask decreasing along a direction extending from an upper region of the gate mask to a lower region of the gate mask, a gate spacer on sidewalls of the gate mask and sidewalls of the gate structure, the gate spacer including the first dielectric material and the impurity, a concentration of the impurity in the gate spacer decreasing along a direction extending from an upper region of the gate spacer to a lower region of the gate spacer, and a source / drain region adjacent to the gate spacer and the channel region.

Description

Technical Field

[0001] This disclosure generally relates to transistor source / drain contacts and methods for forming them. Background Technology

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers of material on a semiconductor substrate, and using photolithography to pattern the various material layers to form circuit components and elements thereon.

[0003] The semiconductor industry continues to increase the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by constantly reducing the minimum feature size, which allows more components to be integrated into a given area. However, as the minimum feature size decreases, other problems arise that need to be addressed. Summary of the Invention

[0004] According to one embodiment of this disclosure, a semiconductor device is provided, comprising: a gate structure located on a channel region of a substrate; a gate mask located on the gate structure, the gate mask including a first dielectric material and an impurity, the concentration of the impurity in the gate mask decreasing along a direction extending from an upper region of the gate mask to a lower region of the gate mask; a gate spacer located on a sidewall of the gate mask and a sidewall of the gate structure, the gate spacer including the first dielectric material and the impurity, the concentration of the impurity in the gate spacer decreasing along a direction extending from an upper region of the gate spacer to a lower region of the gate spacer; and a source / drain region adjacent to the gate spacer and the channel region.

[0005] According to another embodiment of this disclosure, a semiconductor device is provided, comprising: a source / drain region adjacent to a channel region of a substrate; an etch stop layer located on the source / drain region; an interlayer dielectric located on the etch stop layer, the interlayer dielectric comprising a first dielectric material and impurities, wherein the concentration of the impurities in an upper region of the interlayer dielectric is greater than that in a lower region of the interlayer dielectric; and a source / drain contact extending through the interlayer dielectric and the etch stop layer to contact the source / drain region, the source / drain contact having a straight sidewall in the lower region of the interlayer dielectric and an arcuate sidewall in the upper region of the interlayer dielectric.

[0006] According to another embodiment of this disclosure, a method of manufacturing a semiconductor device is provided, comprising: depositing an interlayer dielectric on a source / drain region; forming a gate mask on a gate structure disposed on a channel region of a substrate, the channel region being adjacent to the source / drain region; implanting impurities in the gate mask to increase etch selectivity between the gate mask and the interlayer dielectric for a contact etching process; and performing the contact etching process to pattern contact openings in the interlayer dielectric, the contact openings exposing the source / drain region, the gate mask covering the gate structure during the contact etching process. Attached Figure Description

[0007] The various aspects of this disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It is worth noting that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily enlarged or reduced.

[0008] Figure 1 An example of a fin field-effect transistor (FinFET) according to some embodiments is shown in a three-dimensional view.

[0009] Figures 2 to 20C This is a view of an intermediate stage in the fabrication of a FinFET according to some embodiments.

[0010] Figure 21 This is a view of a FinFET according to some other embodiments.

[0011] Figure 22 This is a view of a FinFET according to some other embodiments.

[0012] Figure 23 This is a view of a FinFET according to some other embodiments.

[0013] Figure 24 This is a graph of experimental data obtained from the implantation process in the fabrication of FinFETs.

[0014] Figure 25 The reaction during contact opening etching in the fabrication of a FinFET is shown. Detailed Implementation

[0015] The following disclosure provides numerous different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the following description of forming a first feature on or over a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features do not need to be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. Such repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0016] Furthermore, this document may use spatially relevant terms (e.g., "below," "below," "lower than," "higher than," "upper," etc.) to readily describe the relationship of one element or feature shown in the figure relative to another element(s) or feature(s). These spatially relevant terms are intended to cover different orientations of the device in use or operation other than those shown in the figure. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relevant descriptors used herein may be interpreted accordingly.

[0017] According to various embodiments, an implantation process is performed to modify the upper region of the gate mask and the upper region of the interlayer dielectric. Then, a self-aligned contact (SAC) etching process is performed to form contact openings for source / drain contacts through the interlayer dielectric. The modified upper region of the gate mask exhibits high etch selectivity for the interlayer dielectric, thereby reducing gate mask losses during the etching process. Reducing these losses can decrease leakage in the device, thereby improving device performance.

[0018] Figure 1 An example of a FinFET (Fin Field-Effect Transistor) according to some embodiments is shown. Figure 1This is a three-dimensional view, in which some features of the FinFET are omitted for clarity. The FinFET includes fins 52 extending from a substrate 50 (e.g., a semiconductor substrate), wherein the fins 52 serve as channel regions 58 of the FinFET. Isolation regions 56, such as shallow trench isolation (STI) regions, are disposed between adjacent fins 52, which may protrude above the adjacent isolation regions 56. Although the isolation regions 56 are described / shown as separate from the substrate 50, as used herein, the term "substrate" may refer only to the semiconductor substrate or a combination of the semiconductor substrate and the isolation regions. Furthermore, although the bottom portion of the fin 52 is shown as being a single continuous material with the substrate 50, the bottom portion of the fin 52 and / or the substrate 50 may comprise a single material or multiple materials. In this context, fin 52 refers to the portion extending between adjacent isolation regions 56.

[0019] Gate dielectric 112 runs along the sidewall of fin 52 and is located above the top surface of fin 52. Gate electrode 114 is located above gate dielectric 112. Epitaxial source / drain regions 88 are disposed on the opposite side of fin 52 relative to gate dielectric 112 and gate electrode 114. Epitaxial source / drain regions 88 may be shared between the various fins 52. For example, adjacent epitaxial source / drain regions 88 may be electrically connected, for example by joining epitaxial source / drain regions 88 by epitaxial growth, or by coupling epitaxial source / drain regions 88 to the same source / drain contact.

[0020] Figure 1 Reference cross sections used in the following figures are also shown. Cross section A-A' is along the longitudinal axis of fin 52 and in the direction of current flow between, for example, the epitaxial source / drain regions 88 of the FinFET. Cross section B-B' is perpendicular to cross section A-A' and along the longitudinal axis of gate electrode 114. Cross section C-C' is parallel to cross section B-B' and extends through the epitaxial source / drain regions 88 of the FinFET. These reference cross sections are referenced in subsequent figures for clarity.

[0021] Some embodiments discussed herein are described in the context of FinFETs formed using a gate-last process. In other embodiments, a gate-first process may be used. Furthermore, some embodiments consider aspects used in planar devices, such as planar FETs.

[0022] Figures 2 to 20C This is a view of an intermediate stage in the fabrication of a FinFET according to some embodiments. Figure 2 , Figure 3 and Figure 4These are three-dimensional views, showing the relationship with... Figure 1 A similar 3D view. Figure 5A , Figure 6A , Figure 7A , Figure 8A , Figure 9A , Figure 10A , Figure 11A , Figure 12A , Figure 13A , Figure 14A , Figure 15A , Figure 16A , Figure 17A , Figure 18A , Figure 19A and Figure 20A Is along with Figure 1 The cross-sectional view is shown in the reference section A-A'. Figure 5B , Figure 6B , Figure 7B , Figure 8B , Figure 9B , Figure 10B , Figure 11B , Figure 12B , Figure 13B , Figure 14B , Figure 15B , Figure 16B , Figure 17B , Figure 18B , Figure 19B and Figure 20B Is along with Figure 1 The cross-sectional view is shown in the reference section B-B'. Figure 5C , Figure 6C , Figure 7C , Figure 8C , Figure 9C , Figure 10C , Figure 11C , Figure 12C , Figure 13C , Figure 14C , Figure 15C , Figure 16C , Figure 17C , Figure 18C , Figure 19C and Figure 20C Is along with Figure 1 The cross-sectional view is shown in the reference section C-C'.

[0023] exist Figure 2A substrate 50 is provided. The substrate 50 can be a semiconductor substrate, such as a bulk semiconductor or semiconductor-on-insulator (SOI) substrate, which can be doped (e.g., doped with p-type or n-type impurities) or undoped. The substrate 50 can be a wafer, such as a silicon wafer. Typically, an SOI substrate is a layer of semiconductor material formed on an insulating layer. The insulating layer can be, for example, a buried oxide (BOX) layer or a silicon oxide layer. The insulating layer is disposed on a substrate that is typically a silicon substrate or a glass substrate. Other substrates can also be used, such as multilayer substrates or gradient substrates. In some embodiments, the semiconductor material of the substrate 50 may include: silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium indium arsenide phosphide; combinations of the foregoing; or similar materials.

[0024] Substrate 50 has an n-type region 50N and a p-type region 50P. The n-type region 50N can be used to form an n-type device, such as an NMOS transistor, like an n-type FinFET, and the p-type region 50P can be used to form a p-type device, such as a PMOS transistor, like a p-type FinFET. The n-type region 50N can be physically separated from the p-type region 50P (not shown separately), and any number of device features (e.g., other active devices, doped regions, isolation structures, etc.) can be provided between the n-type region 50N and the p-type region 50P. Although one n-type region 50N and one p-type region 50P are shown, any number of n-type regions 50N and p-type regions 50P can be provided.

[0025] Fins 52 are formed in substrate 50. Fins 52 are semiconductor strips. Fins 52 can be formed in substrate 50 by etching trenches in substrate 50. The etching can be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), or a combination thereof. The etching process can be anisotropic.

[0026] The fin 52 can be patterned using any suitable method. For example, one or more photolithography processes, including dual-patterning or multi-patterning processes, can be used to pattern the fin 52. Typically, dual-patterning or multi-patterning processes combine photolithography and self-alignment processes, allowing the created patterns to have smaller spacing, for example, than that achievable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed on a substrate and patterned using a photolithography process. A spacer is formed along the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacer can subsequently be used as a mask to pattern the fin 52. In some embodiments, the mask (or other layer) may remain on the fin 52.

[0027] An STI region 56 is formed on the substrate 50 and between adjacent fins 52. The STI region 56 is configured to surround the lower portion of the fin 52 such that the upper portion of the fin 52 protrudes between adjacent STI regions 56. In other words, the upper portion of the fin 52 extends above the top surface of the STI region 56. The STI region 56 separates the features of adjacent devices.

[0028] The STI regions 56 can be formed by any suitable method. For example, an insulating material can be formed on the substrate 50 and between adjacent fins 52. The insulating material can be an oxide (e.g., silicon oxide), a nitride (e.g., silicon nitride), or a combination thereof, and can be formed by a chemical vapor deposition (CVD) process (e.g., high-density plasma CVD (HDP-CVD), flowable chemical vapor deposition (FCVD), or a combination thereof). Other insulating materials formed by any acceptable process can be used. In some embodiments, the insulating material is silicon oxide formed by FCVD. Once the insulating material is formed, an annealing process can be performed. Although each of the STI regions 56 is shown as a single layer, some embodiments may employ multiple layers. For example, in some embodiments, a liner (not shown separately) can be formed first along the surfaces of the substrate 50 and the fins 52. Subsequently, an insulating material such as described above can be formed on the liner. In one embodiment, the insulating material is formed such that excess insulating material covers the fins 52. A removal process is then applied to the insulating material to remove excess insulating material on the fins 52. In some embodiments, planarization processes such as chemical mechanical polishing (CMP), etching back, or combinations thereof may be employed. In embodiments where the mask remains on the fin 52, the planarization process can expose or remove the mask. After the planarization process, the top surface of the insulating material and the top surface of the mask (if present) or the top surface of the fin 52 are coplanar (within process variations). Therefore, the top surface of the mask (if present) or the top surface of the fin 52 is exposed through the insulating material. In the illustrated embodiment, no mask is retained on the fin 52. The insulating material is then recessed to form the STI region 56. The insulating material is recessed such that the upper portion of the fin 52 protrudes between adjacent portions of the insulating material. Furthermore, the top surface of the STI region 56 may have a flat surface (as shown), a convex surface, a concave surface (e.g., dish-shaped), or a combination thereof. The top surface of the STI region 56 may be formed as flat, convex, and / or concave by appropriate etching. Any acceptable etching process can be used to recess the insulating material, such as a material-selective etching process (e.g., selectively etching the insulating material of the STI region 56 at a faster rate than etching the material of fin 52). For example, dilute hydrofluoric acid (dHF) can be used to perform oxide removal.

[0029] The previously described process is merely one example of how the fin 52 and STI region 56 can be formed. In some embodiments, a mask and epitaxial growth process can be used to form the fin 52. For example, a dielectric layer can be formed over the top surface of the substrate 50, and trenches can be etched through the dielectric layer to expose the underlying substrate 50. An epitaxial structure can be epitaxially grown in the trench, and the dielectric layer can be recessed such that the epitaxial structure protrudes relative to the dielectric layer to form the fin 52. In some embodiments of epitaxial growth of the epitaxial structure, the material to be epitaxially grown can be in-situ doped during growth, which can avoid prior and / or subsequent implantation; however, in-situ doping and implantation doping can also be used together.

[0030] Furthermore, it may be advantageous to epitaxially grow a material different from that in the p-type region 50P in the n-type region 50N. In various embodiments, the upper part of the fin 52 may be made of silicon-germanium (Si). x Ge 1-x The semiconductor can be formed from materials such as silicon carbide, pure or substantially pure germanium, III-V compound semiconductors, or II-VI compound semiconductors, where x can be in the range of 0 to 1. For example, materials that can be used to form III-V compound semiconductors include, but are not limited to, indium arsenide, aluminum arsenide, gallium arsenide, indium phosphide, gallium nitride, indium gallium arsenide, indium aluminum arsenide, gallium antimonide, aluminum antimonide, aluminum phosphide, or gallium phosphide.

[0031] Furthermore, suitable wells (not shown separately) may be formed in the fin 52 and / or the substrate 50. The conductivity type of the well may be opposite to the conductivity type of the source / drain regions subsequently formed in each of the n-type region 50N and the p-type region 50P. In some embodiments, a p-type well is formed in the n-type region 50N and an n-type well is formed in the p-type region 50P. In some embodiments, either a p-type well or an n-type well is formed in both the n-type region 50N and the p-type region 50P.

[0032] In embodiments with different well types, different implantation steps for n-type region 50N and p-type region 50P can be implemented using a mask such as a photoresist (not shown separately). For example, a photoresist can be formed over fin 52 and STI region 56 in n-type region 50N. The photoresist is patterned to expose p-type region 50P. The photoresist can be formed using a spin coating technique and can be patterned using an acceptable photolithography technique. Once the photoresist is patterned, n-type impurity implantation is performed in p-type region 50P, and the photoresist can be used as a mask to substantially prevent n-type impurities from being implanted into n-type region 50N. The n-type impurity can be phosphorus, arsenic, antimony, etc., implanted into the region at a concentration of 10. 13 cm-3 Up to 10 14 cm -3 Within the range. After injection, the photoresist is removed, for example, by any acceptable ashing process.

[0033] After or before implantation into the p-type region 50P, a mask, such as a photoresist (not shown separately), is formed over the fins 52 and STI region 56 in the p-type region 50P. The photoresist is patterned to expose the n-type region 50N. The photoresist can be formed using a spin coating technique and can be patterned using an acceptable photolithography technique. Once the photoresist is patterned, p-type impurity implantation can be performed in the n-type region 50N, and the photoresist can be used as a mask to substantially prevent p-type impurities from being implanted into the p-type region 50P. The p-type impurities can be boron, boron fluoride, indium, etc., implanted into the region at a concentration of 10. 13 cm -3 Up to 10 14 cm -3 Within the range. After injection, the photoresist is removed, for example, by any acceptable ashing process.

[0034] Following implantation into the n-type region 50N and the p-type region 50P, annealing can be performed to repair implantation damage and activate the implanted p-type and / or n-type impurities. In some embodiments for epitaxial growth of epitaxial structures for fin 52, the grown material can be in-situ doped during growth, which avoids implantation, but in-situ doping and implantation doping can be used together.

[0035] exist Figure 3In this process, a dummy dielectric layer 62 is formed on fin 52. The dummy dielectric layer 62 can be formed of a dielectric material such as silicon oxide, silicon nitride, or combinations thereof, and can be deposited or thermally grown according to acceptable techniques. A dummy gate layer 64 is formed on the dummy dielectric layer 62, and a mask layer 66 is formed on the dummy gate layer 64. The dummy gate layer 64 can be deposited on the dummy dielectric layer 62 and then planarized, for example, by CMP. The mask layer 66 can be deposited on the dummy gate layer 64. The dummy gate layer 64 can be formed of a conductive or non-conductive material, such as amorphous silicon, polysilicon, poly-SiGe, metal, metal nitride, metal silicide, metal oxide, etc., and can be deposited by physical vapor deposition (PVD) or CVD, etc. The dummy gate layer 64 can be formed of one or more materials with high etch selectivity relative to the etching of the isolation material (e.g., STI region 56 and / or dummy dielectric layer 62). The mask layer 66 can be formed of a dielectric material such as silicon nitride, silicon oxynitride, etc. In this example, a single dummy gate layer 64 and a single mask layer 66 are formed across the n-type region 50N and the p-type region 50P. In the illustrated embodiment, the dummy dielectric layer 62 covers the fin 52 and the STI region 56 such that the dummy dielectric layer 62 is over the STI region 56 and extends between the dummy gate layer 64 and the STI region 56. In another embodiment, the dummy dielectric layer 62 covers only the fin 52.

[0036] exist Figure 4 In this process, mask layer 66 is patterned using acceptable photolithography and etching techniques to form mask 76. The pattern of mask 76 is then transferred to dummy gate layer 64 by any acceptable etching technique to form dummy gate 74. Optionally, the pattern of mask 76 can be further transferred to dummy dielectric layer 62 by any acceptable etching technique to form dummy dielectric 72. Dummy gate 74 covers the corresponding channel region 58 of fin 52. The pattern of mask 76 can be used to physically separate adjacent dummy gates 74. Dummy gate 74 may also have a length direction substantially perpendicular to the length direction of fin 52 (within process variations). Mask 76 may be removed during the patterning of dummy gate 74, or it may be removed during subsequent processing.

[0037] Figures 5A to 20C Various additional steps in the manufacture of the embodiment device are shown. Figures 5A to 20C Features of either n-type region 50N or p-type region 50P are shown. For example, the structure shown can be applied to both n-type region 50N and p-type region 50P. Differences in the structure of n-type region 50N and p-type region 50P (if any) are described in the text corresponding to each figure.

[0038] exist Figures 5A to 5C In this configuration, a gate spacer 82 is formed on the fin 52, on the mask 76 (if present), on the exposed sidewalls of the dummy gate 74, and on the dummy dielectric 72. The gate spacer 82 can be formed by conformally depositing one or more dielectric materials and subsequently etching the dielectric material(s). Acceptable dielectric materials may include silicon nitride, silicon carbide nitride, silicon oxynitride, or silicon carbonitride, which can be formed by conformal deposition processes such as chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), or plasma-enhanced atomic layer deposition (PEALD). Other insulating materials formed by any acceptable process can be used. Any acceptable etching process (e.g., dry etching, wet etching, or combinations thereof) can be performed to pattern the dielectric material(s). The etching can be anisotropic. After etching, some portions of the dielectric material(s) remain on the sidewalls of the dummy gate 74 (thus forming the gate spacer 82, see [link]). Figure 5A As will be described in more detail later, in some embodiments, the etching used to form the gate spacer 82 is adjusted such that the dielectric material(s)(s) remaining on the sidewalls of the fin 52 after etching (thus forming the fin spacer 84, see below) Figure 5C After etching, the fin spacer 84 (if present) and the gate spacer 82 may have straight sidewalls (as shown) or may have arcuate sidewalls (not shown separately).

[0039] Additionally, implantation can be performed to form lightly doped source / drain (LDD) regions (not shown separately). In embodiments with different device types, similar to the implantation previously described for a well, a mask such as a photoresist (not shown separately) can be formed over the n-type region 50N while exposing the p-type region 50P, and an impurity of an appropriate type (e.g., p-type) can be implanted into the fin 52 exposed in the p-type region 50P. The mask can then be removed. Subsequently, a mask such as a photoresist (not shown separately) can be formed over the p-type region 50P while exposing the n-type region 50N, and an impurity of an appropriate type (e.g., n-type) can be implanted into the fin 52 exposed in the n-type region 50N. The mask can then be removed. The n-type impurity can be any of the previously described n-type impurities, and the p-type impurity can be any of the previously described p-type impurities. During implantation, the channel region 58 remains covered by the dummy gate 74 such that the channel region 58 remains substantially free of impurities implanted to form the LDD region. The LDD region can have 10 15 cm -3 Up to 10 19 cm-3 The impurity concentration is within a certain range. Annealing can be used to repair implantation damage and reactivate the implanted impurities.

[0040] Note that the previous disclosures generally describe a process for forming spacers and LDD regions. Other processes and sequences can be used. For example, fewer or additional spacers can be used, different step sequences can be employed, additional spacers can be formed and removed, etc. Furthermore, different structures and steps can be used to form n-type and p-type devices.

[0041] exist Figures 6A to 6C In the illustrated embodiment, source / drain recesses 86 are formed in fin 52. In this embodiment, the source / drain recesses 86 extend into fin 52. Source / drain recesses 86 may also extend into substrate 50. In various embodiments, source / drain recesses 86 may extend to the top surface of substrate 50 without etching substrate 50; fin 52 may be etched such that the bottom surface of the source / drain recesses 86 is set below the top surface of STI region 56; and so on. Source / drain recesses 86 can be formed by etching fin 52 using an anisotropic etching process (e.g., RIE or NBE). During the etching process used to form the source / drain recesses 86, gate spacers 82 and dummy gates 74 jointly mask portions of fin 52. A timing etching process can be used to stop etching the source / drain recesses 86 after they reach a desired depth. In some embodiments, fin spacers 84 are also recessed until they reach a desired height. The height of the fin spacer 84 allows for control over the size of the subsequently grown source / drain regions.

[0042] exist Figures 7A to 7C In the process, an epitaxial source / drain region 88 is formed in the source / drain recess 86. This provides an epitaxial source / drain region 88 within the fin 52 such that each dummy gate 74 (and corresponding channel region 58) is located between adjacent pairs of the corresponding epitaxial source / drain regions 88. Thus, the epitaxial source / drain regions 88 are adjacent to the channel region 58 and the gate spacer 82. In some embodiments, the gate spacer 82 is used to separate the epitaxial source / drain regions 88 from the dummy gates 74 by an appropriate lateral distance, such that the epitaxial source / drain regions 88 do not short-circuit with the subsequently formed gate of the resulting FinFET. The material of the epitaxial source / drain regions 88 can be selected to apply stress in the corresponding channel region 58, thereby improving performance.

[0043] The epitaxial source / drain region 88 in the n-type region 50N can be formed by masking the p-type region 50P. Then, the epitaxial source / drain region 88 in the n-type region 50N is epitaxially grown in the source / drain recess 86 in the n-type region 50N. The epitaxial source / drain region 88 may include any acceptable material suitable for an n-type device. For example, if the fin 52 is silicon, the epitaxial source / drain region 88 in the n-type region 50N may include a material on which tensile strain is applied to the channel region 58, such as silicon, silicon carbide, phosphorus-doped silicon carbide, silicon phosphide, etc. The epitaxial source / drain region 88 in the n-type region 50N may be referred to as the "n-type source / drain region". The epitaxial source / drain region 88 in the n-type region 50N may have a surface protruding from the corresponding surface of the fin 52 and may have a facet.

[0044] The epitaxial source / drain region 88 in the p-type region 50P can be formed by masking the n-type region 50N. Then, the epitaxial source / drain region 88 in the p-type region 50P is epitaxially grown in the source / drain recess 86 in the p-type region 50P. The epitaxial source / drain region 88 may include any acceptable material suitable for a p-type device. For example, if the fin 52 is silicon, the epitaxial source / drain region 88 in the p-type region 50P may include a material that applies compressive stress to the channel region 58, such as silicon-germanium, boron-doped silicon-germanium, germanium, germanium-tin, etc. The epitaxial source / drain region 88 in the p-type region 50P may be referred to as the "p-type source / drain region". The epitaxial source / drain region 88 in the p-type region 50P may have a surface protruding from the corresponding surface of the fin 52 and may have a small facet.

[0045] The epitaxial source / drain 88 and / or fin 52 may be implanted with impurities to form source / drain regions, similar to the previously described process for forming LDD regions, followed by annealing. The impurity concentration in the source / drain regions can be up to 10. 19 cm -3 Up to 10 21 cm -3 Within the range. The n-type and / or p-type impurities used for the source / drain regions can be any of the previously described impurities. In some embodiments, the epitaxial source / drain regions 88 can be doped in situ during growth.

[0046] As a result of the epitaxial process used to form the epitaxial source / drain regions 88, the upper surface of the epitaxial source / drain regions has facets that extend laterally outward beyond the sidewalls of the fin 52. In some embodiments, these facets cause adjacent epitaxial source / drain regions 88 to merge, such as... Figure 7CAs shown. In some embodiments, adjacent epitaxial source / drain regions 88 remain separated after the epitaxial process is completed. In the illustrated embodiment, fin spacers 84 are formed to cover portions of the sidewalls of fin 52 extending above STI region 56, thereby blocking epitaxial growth. In another embodiment, the spacer etching used to form gate spacers 82 is adjusted to not form fin spacers 84, thereby allowing epitaxial source / drain regions 88 to extend to the surface of STI region 56.

[0047] The epitaxial source / drain region 88 may include one or more semiconductor material layers. For example, the epitaxial source / drain region 88 may each include a liner layer 88A, a main layer 88B, and a trimming layer 88C (or more generally, a first semiconductor material layer, a second semiconductor material layer, and a third semiconductor material layer). Any number of semiconductor material layers may be used for the epitaxial source / drain region 88. The liner layer 88A, the main layer 88B, and the trimming layer 88C may be formed of different semiconductor materials and / or may be doped with different impurity concentrations. In some embodiments, the main layer 88B has a higher impurity concentration than the trimming layer 88C, and the trimming layer 88C has a higher impurity concentration than the liner layer 88A. In embodiments where the epitaxial source / drain region 88 includes three semiconductor material layers, the liner layer 88A may be grown in the source / drain recess 86, the main layer 88B may be grown on the liner layer 88A, and the trimming layer 88C may be grown on the main layer 88B. Forming a liner layer 88A with a lower impurity concentration than the main layer 88B can increase the adhesion in the source / drain recess 86, and forming a trimming layer 88C with a lower impurity concentration than the main layer 88B can reduce the diffusion of dopants from the main layer 88B outward during subsequent processes.

[0048] exist Figures 8A to 8C In this process, a first interlayer dielectric (ILD) 94 is deposited over the epitaxial source / drain region 88, the gate spacer 82, and the mask 76 (if present) or dummy gate 74. The first ILD 94 can be formed of a dielectric material, which can be deposited by any suitable method, such as CVD, plasma-enhanced CVD (PECVD), or FCVD. Acceptable dielectric materials may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), or undoped silicate glass (USG). Other insulating materials formed by any acceptable process may be used.

[0049] In some embodiments, a contact etch stop layer (CESL) 92 is formed between the first ILD 94 and the epitaxial source / drain region 88, the gate spacer 82, and the mask 76 (if present) or the dummy gate 74. The CESL 92 may be formed of a dielectric material having high etch selectivity relative to the etching of the first ILD 94. Acceptable dielectric materials may include silicon nitride, silicon carbide nitride, silicon oxynitride, or silicon carbonitride, which can be formed by conformal deposition processes such as chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), or plasma-enhanced atomic layer deposition (PEALD).

[0050] exist Figures 9A to 9C In this process, a planarization process is performed to make the top surface of the first ILD 94 flush with the top surface of the mask 76 (if present) or the dummy gate 74. In some embodiments, planarization processes such as chemical mechanical polishing (CMP), etch-back processes, or combinations thereof may be employed. This planarization process may also remove the mask 76 on the dummy gate 74, as well as portions of the gate spacer 82 along the sidewalls of the mask 76. After the planarization process, the top surfaces of the first ILD 94, CESL 92, gate spacer 82, and mask 76 (if present) or the dummy gate 74 are coplanar (within process variations). Therefore, the top surface of the mask 76 (if present) or the dummy gate 74 is exposed through the first ILD 94. In the illustrated embodiment, the mask 76 is retained, and the planarization process makes the top surface of the first ILD 94 flush with the top surface of the mask 76.

[0051] exist Figures 10A to 10C In the etching process, the mask 76 (if present) and the dummy gate 74 are removed to form a recess 96. A portion of the dummy dielectric 72 located within the recess 96 may also be removed. In some embodiments, only the dummy gate 74 is removed, and the dummy dielectric 72 remains and is exposed by the recess 96. In some embodiments, the dummy dielectric 72 is removed from the recess 96 in a first region of the die (e.g., a core logic region) and remains in the recess 96 in a second region of the die (e.g., an input / output region). In some embodiments, the dummy gate 74 is removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using one or more reactive gases that selectively etch the dummy gate 74 at a rate faster than etching the first ILD 94 or the gate spacer 82. During removal, the dummy dielectric 72 may be used as an etch stop layer while the dummy gate 74 is being etched. The dummy dielectric 72 may then be optionally removed after the removal of the dummy gate 74. Each recess 96 exposes and / or covers the channel area 58 of the corresponding fin 52.

[0052] exist Figures 11A to 11C In the recess 96, a gate dielectric layer 102 is formed. A gate electrode layer 104 is formed on the gate dielectric layer 102. The gate dielectric layer 102 and the gate electrode layer 104 are layers for replacing the gate, and each extends along the sidewall of the channel region 58 and extends above the top surface of the channel region 58.

[0053] A gate dielectric layer 102 is disposed on the sidewalls and / or top surface of the fin 52 and on the sidewalls of the gate spacer 82. The gate dielectric layer 102 may also be formed on the top surface of the first ILD 94 and the top surface of the gate spacer 82. The gate dielectric layer 102 may include oxides (e.g., silicon oxide or metal oxides), silicates (e.g., metal silicates), combinations of the foregoing, multilayers of the foregoing, etc. The gate dielectric layer 102 may include high-k dielectric materials (e.g., dielectric materials with a k value greater than 7.0), such as metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. Methods for forming the gate dielectric layer 102 may include molecular beam deposition (MBD), ALD, and PECVD, etc. In embodiments where some portions of the dummy dielectric 72 remain in the recess 96, the gate dielectric layer 102 includes the material of the dummy dielectric 72 (e.g., silicon oxide). Although a single-layer gate dielectric layer 102 is shown, the gate dielectric layer 102 may include any number of interface layers and any number of main layers. For example, the gate dielectric layer 102 may include an interface layer and an overlying high-k dielectric layer.

[0054] The gate electrode layer 104 may include a metallic material, such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, tungsten, cobalt, ruthenium, aluminum, combinations thereof, or multiple layers thereof. In some embodiments, the gate electrode layer 104 includes tantalum nitride rich in tantalum and tungsten. Although a single-layer gate electrode layer 104 is shown, the gate electrode layer 104 may include any number of work function adjustment layers, any number of barrier layers, any number of adhesive layers, and filler materials.

[0055] The formation of the gate dielectric layer 102 in the n-type region 50N and the p-type region 50P can occur simultaneously, such that the gate dielectric layer 102 in each region is formed of the same (one or more) materials, and the formation of the gate electrode layer 104 can occur simultaneously, such that the gate electrode layer 104 in each region is formed of the same (one or more) materials. In some embodiments, the gate dielectric layer 102 in each region can be formed by different processes, such that the gate dielectric layer 102 can be made of different materials and / or have different numbers of layers, and / or the gate electrode layer 104 in each region can be formed by different processes, such that the gate electrode layer 104 can be made of different materials and / or have different numbers of layers. When using different processes, various masking steps can be used to mask and expose appropriate regions.

[0056] exist Figures 12A to 12C In this process, a removal process is performed to remove excess material from the gate dielectric layer 102 and the gate electrode layer 104, which lies above the top surfaces of the first ILD 94, CESL 92, and gate spacer 82, thereby forming the gate dielectric 112 and the gate electrode 114. In some embodiments, planarization processes such as chemical mechanical polishing (CMP), etch-back processes, or combinations thereof may be employed. After planarization, the gate dielectric layer 102 has a portion remaining in the recess 96 (thus forming the gate dielectric 112). After planarization, the gate electrode layer 104 has a portion remaining in the recess 96 (thus forming the gate electrode 114). After the planarization process, the top surfaces of the gate spacer 82, CESL 92, first ILD 94, gate dielectric 112, and gate electrode 114 are coplanar (within process variations). The gate dielectric 112 and gate electrode 114 form the replacement gate of the resulting FinFET. Each corresponding pair of gate dielectric 112 and gate electrode 114 may be collectively referred to as a “gate structure”. Each gate structure extends along the top surface, sidewalls and bottom surface of the channel region 58 of fin 52.

[0057] exist Figures 13A to 13C In this process, a gate mask 116 is formed over the gate structure (including the gate dielectric 112 and the gate electrode 114). In some embodiments, the gate mask 116 may also be formed over the gate spacer 82 (hereinafter referred to as...). Figure 21(Description in more detail). The gate mask 116 is formed of one or more dielectric materials that have high etch selectivity relative to the etching of the first ILD 94. Acceptable dielectric materials may include silicon nitride, silicon carbide nitride, silicon oxynitride, or silicon carbonitride, which can be formed by conformal deposition processes such as chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), or plasma-enhanced atomic layer deposition (PEALD). Other insulating materials formed by any acceptable process may be used. Gate contacts will then be formed to penetrate the gate mask 116 and contact the top surface of the gate electrode 114.

[0058] As an example of forming the gate mask 116, the gate structure (including the gate dielectric 112 and the gate electrode 114) can be recessed using any acceptable etching process. In some embodiments, the gate spacers 82 are also recessed. When the gate spacers 82 are recessed, they can be recessed by the same amount as the gate structure, or they can be recessed by a different amount. A dielectric material (one or more) is then conformally deposited in the recess. A removal process is performed to remove excess portions of the dielectric material (located above the top surface of the first ILD 94), thereby forming the gate mask 116. In some embodiments, planarization processes such as chemical mechanical polishing (CMP), etch-back processes, or combinations thereof can be employed. After planarization, the dielectric material (one or more) has portions retained in the recesses (thus forming the gate mask 116). After the planarization process, the gate spacers 82, CESL 92, the first ILD 94, and the top surface of the gate mask 116 are coplanar (within process variations).

[0059] exist Figures 14A to 14C In this embodiment, impurities are implanted into the upper regions 120U of gate spacer 82, CESL 92, and gate mask 116 to modify the etch rate of these upper regions 120U. Impurities can also be implanted into the upper region 120U of the first ILD 94. Impurities can be boron, phosphorus, arsenic, germanium, carbon, silicon, argon, or xenon, etc. In embodiments where gate spacer 82, CESL 92, and gate mask 116 are each formed of nitrides (e.g., silicon nitride, silicon carbonitride, silicon oxynitride, silicon carbonitride, etc.), the impurities can be boron or phosphorus, and implantation can be performed by implantation process 118. Therefore, gate spacer 82, CESL 92, and gate mask 116 can each include the same dielectric material and impurities.

[0060] The upper regions 120U of various features are enriched with impurities. For example, the upper regions 120U of gate spacer 82, CESL 92, and gate mask 116 may each include boron or phosphorus nitrides with a higher concentration (atomic percentage) than the lower regions 120L of gate spacer 82, CESL 92, and gate mask 116. As will be described in more detail later, contact openings will be etched in the first ILD 94 to expose the epitaxial source / drain regions 88. The modified (e.g., impurity-rich) upper regions 120U of gate spacer 82, CESL 92, and gate mask 116 have high etch selectivity relative to the etching of the first ILD 94, thereby helping to reduce losses during the etching of contact openings in the first ILD 94 of gate spacer 82, CESL 92, and gate mask 116.

[0061] Compared to the upper region 120U, during / after impurity implantation, the lower region 120L of the gate spacer 82, the lower region 120L of the CESL 92, the lower region 120L of the first ILD 94, and the lower region 120L of the gate mask 116 remain unmodified or minimally modified. In some embodiments, the lower region 120L retains its initial composition such that the final composition of the lower region 120L is the same as its initial composition. Therefore, the lower region 120L may be substantially free of impurities. In some embodiments, the lower region 120L is modified, but less so than the upper region 120U, such that the final composition of the lower region 120L is closer to its initial composition than the final composition of the upper region 120U. Therefore, the lower region 120L may include impurities. As will be described in more detail later, the average concentration of implanted impurities in the upper region 120U may be several orders of magnitude larger than the average concentration of implanted impurities in the lower region 120L. For example, the impurity concentration in the upper region 120U can be 10 times the impurity concentration in the lower region 120L. 3 Up to 10 4 The change in average impurity concentration between the upper region 120U and the lower region 120L can be abrupt or gradual. More generally, the impurity concentrations in the various features form a gradient, wherein the concentration decreases in the direction extending from the upper region 120U to the lower region 120L of the various features.

[0062] As described above, the gate spacer 82, CESL 92, and gate mask 116 can each be formed of a nitride (e.g., silicon nitride, silicon carbonitride, silicon oxynitride, silicon carbonitride, etc.), and the first ILD 94 can be formed of an oxide (e.g., silicon oxide). The implantation process 118 can implant more impurities into the oxide than into the nitride, such that the upper region 120U of the first ILD 94 has a greater depth and impurity concentration than the upper regions 120U of the gate spacer 82, CESL 92, and gate mask 116. For example, the upper region 120U of the first ILD 94 can have a depth D1 in the range of 0 nm to 6 nm (see...). Figure 14C ), and can have 10 18 cm -3 Up to 10 22 cm -3 The impurity concentration is within a certain range, while the upper region 120U of the gate mask 116 can have a depth D2 in the range of 0 nm to 4 nm (see [reference]). Figure 14B ), and can have 10 15 cm -3 Up to 10 16 cm -3 The impurity concentration within this range. Implanting the upper region 120U of the gate mask 116 into this range of impurity concentration provides sufficient etch selectivity relative to the etching of the first ILD 94 without degrading device performance. Implanting the upper region 120U of the gate mask 116 into impurity concentrations outside this range may not provide sufficient etch selectivity relative to the etching of the first ILD 94 without degrading device performance.

[0063] In some embodiments, implantation process 118 includes a thermal implantation process. Specifically, the thermal implantation process can be performed by the following steps: placing substrate 50 on an implanter platen; and implanting impurities into gate spacer 82, CESL 92, first ILD 94, and gate mask 116 while controlling the temperature of the implanter platen. Impurities can be implanted at high energies, such as implantation energies in the range of 0.5 keV to 10 keV. The temperature of the implanter platen can be controlled in the range of 100 °C to 500 °C. Implanting impurities using a thermal implantation process helps reduce surface oxidation of gate spacer 82, CESL 92, and gate mask 116 during implantation process 118, thereby further increasing their etch selectivity with the first ILD 94. Performing the hot implantation process with parameters within these ranges allows the upper regions 120U of gate spacer 82, CESL 92, and gate mask 116 to be implanted to the desired impurity concentrations (previously described) while avoiding implantation damage. Performing the hot implantation process with parameters outside these ranges may not allow the upper regions 120U of gate spacer 82, CESL 92, and gate mask 116 to be implanted to the desired impurity concentrations while avoiding implantation damage.

[0064] In some embodiments, the implantation process 118 further includes an annealing process following the thermal implantation process. The annealing process may be molten laser annealing (MLA) or dynamic surface annealing (DSA), etc. In some embodiments, the annealing process is molten laser annealing performed at a temperature ranging from 800 °C to 1000 °C for a duration ranging from 1 μs to 10 μs. In some embodiments, the annealing process is dynamic surface annealing performed at a temperature ranging from 850 °C to 900 °C for a duration ranging from 0.1 ms to 1 ms. Performing the annealing process repairs implantation damage and activates the implanted impurities. Specifically, the annealing process promotes the bonding of impurities (e.g., boron or phosphorus) with nitrides (e.g., gate spacer 82, CESL 92, and gate mask 116). Increasing the bonding of impurities in gate spacer 82, CESL 92, and gate mask 116 helps to increase their etch selectivity with the first ILD94.

[0065] Figure 24 This is a graph of experimental data obtained from implantation process 118. The concentration of the implanted impurities is plotted as a function of the depth from the top surface of the first ILD 94. As shown, the impurity concentration in the upper region 120U is several orders of magnitude higher than the impurity concentration in the lower region 120L.

[0066] exist Figures 15A to 15CIn this configuration, a dielectric layer 122 is optionally formed over the gate spacer 82, CESL 92, first ILD 94, and gate mask 116. The dielectric layer 122 may be referred to as a pad layer. The dielectric layer 122 may be formed of an oxide such as silicon oxide or aluminum oxide, and it may be deposited by CVD or ALD.

[0067] Mask 124 is formed on dielectric layer 122 (if present) and over gate spacer 82, CESL 92, first ILD 94, and gate mask 116. Mask 124 can be formed by depositing one or more masking layers on dielectric layer 122 and patterning the mask(s) using slit opening 126. The mask(s) can be formed of materials comprising metals (e.g., titanium nitride, titanium, tantalum nitride, tantalum, metal-doped carbides (e.g., tungsten carbide)) and / or quasi-metals (e.g., silicon nitride, boron nitride, silicon carbide, etc.) and can be formed by deposition processes such as CVD or ALD. In some embodiments, the mask(s) includes a lower masking layer and an upper masking layer, wherein the lower masking layer is formed of metal and the upper masking layer is formed of an oxide such as tetraethyl orthosilicate (TEOS) oxide or nitrogen-free antireflective coating (NFARC). An acceptable photolithography technique can be used to pattern one or more masking layers (one or more) using slit opening 126 to form mask 124. Slit opening 126 is a strip extending parallel to the length direction of fin 52 and overlaps with CESL 92, first ILD 94, and gate mask 116. Specifically, slit opening 126 extends over multiple gate structures (including gate dielectric 112 and gate electrode 114) and multiple epitaxial source / drain regions 88.

[0068] exist Figures 16A to 16CIn this process, mask 124 is used as an etching mask and CESL 92 is used as an etch stop layer to etch the first ILD 94 to form contact openings 128 for source / drain contacts. This etching can be any acceptable etching process, such as an etching process selective for the material of the first ILD 94 (e.g., selectively etching the material of the first ILD 94 at a faster rate than the materials of gate spacer 82, CESL 92, and gate mask 116). The etching process can be anisotropic. Thus, slit opening 126 extends through dielectric layer 122 (if present), and portions of the first ILD 94 not covered by mask 124 (e.g., exposed by slit opening 126) are etched to form contact openings 128. Contact openings 128 are then extended through CESL 92 by any acceptable etching process to expose epitaxial source / drain regions 88. After the etching process, the mask can be removed, for example, by any acceptable ashing process. Gate mask 116 covers the gate structure (including gate dielectric 112 and gate electrode 114) during etching, thereby protecting the gate structure during etching of contact opening 128.

[0069] The etching process used to form the contact opening 128 is a self-aligned contact (SAC) etching process, in which the gate spacer 82, CESL 92, and gate mask 116 are exposed to the etchant during the etching of the contact opening 128. Depending on the selectivity of the etching process used to form the contact opening 128, some loss occurs in the gate spacer 82, CESL 92, and / or gate mask 116, such that the sidewalls and top surfaces of the gate spacer 82, CESL 92, and / or gate mask 116 are curved after etching. However, as described above, the upper regions 120U of the gate spacer 82, CESL 92, and gate mask 116 include impurities implanted by the implantation process 118 (see...). Figures 14A to 14CIn embodiments where gate spacer 82, CESL 92, and gate mask 116 are each formed from nitrides (e.g., silicon nitride, silicon carbonitride, silicon oxynitride, silicon carbonitride, etc.), the impurity may be boron or phosphorus, and implantation may be performed via implantation process 118. The upper regions 120U of gate spacer 82, CESL 92, and gate mask 116, having impurities, have high etch selectivity relative to the etching of the first ILD 94. Therefore, losses of gate spacer 82, CESL 92, and gate mask 116 during the etching process for forming contact opening 128 can be reduced. Although gate spacer 82, CESL 92, and / or gate mask 116 may have some curvature, the amount of curvature is small. In some embodiments, gate spacer 82, CESL 92, and gate mask 116 collectively have arcuate sidewalls connecting the straight sidewalls of CESL 92 to the top surface of gate mask 116, and the arc length of these arcuate sidewalls is in the range of 5 nm to 15 nm. Reducing the losses of gate spacer 82, CESL 92, and gate mask 116 during the etching of contact opening 128 helps reduce leakage between the subsequently formed source / drain contacts and gate electrode 114. This can thus improve device performance.

[0070] In some embodiments, by using fluorocarbon-based compounds (C x F y The first ILD 94 is etched using a dry etching process with an etchant. In one example, the gate spacer 82, CESL 92, and gate mask 116 can each be formed from a nitride (e.g., silicon nitride, silicon carbonitride, silicon oxynitride, silicon carbonitride, etc.), the first ILD 94 can be formed from an oxide (e.g., silicon oxide), the impurity is boron, and the first ILD 94 is etched using C4F6 while plasma is being generated. During plasma generation, fluorine is separated from C4F6 to form C4F5. * Free radicals and F * Free radicals, as shown in Equation 1. F * Free radicals attack both the Si-N and Si-B bonds in one or more of the materials of gate spacer 82, CESL 92, and gate mask 116 to break these bonds, causing F * Free radicals bond to open N-terminal atoms. - Atoms and B - Atoms, as shown in equations 2 and 3. F * Free radicals also bond to open Si atoms. The products of these reactions can be expelled (e.g., using a vacuum). F *The reaction of free radicals with boron is faster than with nitrogen. Including boron in one or more materials of gate spacer 82, CESL 92, and gate mask 116 accelerates the reaction of free radicals with nitrogen. * The consumption of free radicals results in less F * Free radicals can react with C4F5 * Free radicals recombine. C4F5 * Free radicals react on the surfaces of gate spacer 82, CESL 92, and gate mask 116 to form polymer byproducts (e.g., (C4F5)6) on these surfaces, as shown in Equation 4. Therefore, the polymer byproducts are byproducts of the SAC etching process. Examples of reactions describing the formation of polymer byproducts as described in Equations 1-4 are as follows: Figure 25 As shown. The polymeric byproducts are substantially inert to etching and act as a protective layer over the surfaces of gate spacer 82, CESL 92, and gate mask 116 during the etching of contact opening 128. Impurities in one or more of the materials of gate spacer 82, CESL 92, and gate mask 116 promote the formation of polymeric byproducts during the SAC etching process, resulting in a thicker protective layer. For example, the protective layer can have a thickness of up to 200 Å, such as a thickness in the range of 0 Å to 200 Å. Forming a thicker protective layer provides greater protection against etching, thereby reducing the loss of gate spacer 82, CESL 92, and / or gate mask 116 during the etching of contact opening 128.

[0071] (1)

[0072] (2)

[0073] (3)

[0074] (4)

[0075] exist Figures 17A to 17CIn this embodiment, contact spacers 132 are formed in contact openings 128. Contact spacers 132 can be formed by conformally depositing one or more dielectric materials in the contact openings 128 and subsequently etching the dielectric material(s). Acceptable dielectric materials may include silicon nitride, silicon carbonitride, silicon oxynitride, or silicon carbonitride, which can be formed by conformal deposition processes such as chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), or plasma-enhanced atomic layer deposition (PEALD). Other insulating materials formed by any acceptable process may be used. Any acceptable etching process (e.g., dry etching, wet etching, or combinations thereof) can be performed to pattern the dielectric material(s). The etching may be anisotropic. After etching, some portions of the dielectric material(s) remain on the sidewalls of the CESL 92 (thus forming contact spacers 132). After etching, some excess portion of (one or more) dielectric material may remain on the top surface of the gate mask 116.

[0076] One or more conductive layers 134 for source / drain contacts are formed in the contact opening 128. For example, the conductive layers 134 can be formed by forming a liner (not shown separately) and a conductive material, such as a diffusion barrier layer or an adhesion layer, in the contact opening 128. The liner may include titanium, titanium nitride, tantalum, or tantalum nitride. The conductive material may be a metal, such as cobalt, tungsten, copper, copper alloys, silver, gold, aluminum, or nickel, which can be formed by a deposition process such as PVD, ALD, or CVD. One or more conductive layers 134 are formed on the sidewalls and / or top surface of the contact spacer 132 and the dielectric layer 122.

[0077] exist Figures 18A to 18C In the process, a removal process is performed to remove excess portions of conductive layer(s) 134 and contact spacer(s) 132 located above the top surface of gate mask(s) 116. The removal process may also remove dielectric layer(s) 122. In some embodiments, planarization processes such as chemical mechanical polishing (CMP), etch-back processes, or combinations thereof may be employed. The remaining conductive layer(s) 134 in contact opening(s) 128 forms source / drain contacts 136 within contact opening(s) 128. The source / drain contacts 136 extend through the first ILD(s) 94 and CESL(s) 92 to contact the epitaxial source / drain region(s) 88. After the planarization process, the top surfaces of the source / drain contacts 136, the contact spacer(s) 132, the gate mask(s) 116, the first ILD(s) 94, and the gate spacer(s) 82 are coplanar (within the range of process variations).

[0078] The removal process performed to remove excess portions of conductive layer(s) 134 and contact spacer 132 may also remove portions of gate spacer 82, first ILD 94, and gate mask 116, depending on the selectivity of the removal process. Specifically, gate mask 116 may experience some loss, resulting in a reduction in the height of gate mask 116 and gate spacer 82. In the illustrated embodiment, contact spacer 132 extends along the arcuate sidewalls of the remaining portions of gate spacer 82, CESL 92, and gate mask 116 and makes solid contact with these arcuate sidewalls. In another embodiment (subsequently addressed)... Figure 22-23 (To be described in more detail), reduce the height of gate mask 116 and gate spacer 82 until the top surfaces of gate mask 116 and CESL 92 are coplanar (within the range of process variations), such that contact spacer 132 is separated from the sidewall solid of gate mask 116 by CESL 92.

[0079] In some embodiments, after the removal process, portions of the upper region 120U of the gate spacer 82, the upper region 120U of the CESL 92, the upper region 120U of the first ILD 94, and the upper region 120U of the gate mask 116 are retained. For example, the removal process may thin but not remove the upper regions 120U of various features. Although the gate spacer 82, CESL 92, first ILD 94, and gate mask 116 contain impurities implanted through the implantation process 118 (see...). Figures 14A to 14C However, the concentration of impurities can be low enough that it does not degrade device performance. Furthermore, as previously mentioned, impurities present in gate spacer 82, CESL 92, first ILD 94, and gate mask 116 reduce the etched contact opening 128 (see [link to documentation]). Figures 16A to 16C This helps improve device performance by reducing losses during operation, thereby reducing leakage between the source / drain contact 136 and the gate electrode 114. In another embodiment (hereinafter referred to as...) Figures 22 to 23 (To be described in more detail), reduce the height of gate spacer 82, CESL 92, first ILD 94 and gate mask 116 until the upper regions 120U of gate spacer 82, CESL 92, first ILD 94 and gate mask 116 are removed.

[0080] When some portions of the upper region 120U remain after the removal process, the source / drain contact 136 extends through the various features of the upper region 120U and the lower region 120L. The source / drain contact 136 has straight sidewalls in at least a portion of the lower region 120L. The source / drain contact 136 has arcuate sidewalls in the upper region 120U (and may also have arcuate sidewalls in a portion of the lower region 120L). A contact spacer 132 extends along the arcuate sidewalls of the source / drain contact 136 and along the remaining arcuate sidewalls of the gate spacer 82, CESL 92, and the gate mask 116.

[0081] exist Figures 19A to 19C In this configuration, a second ILD 144 is deposited over the first ILD 94, gate mask 116, source / drain contacts 136, and contact spacers 132. In some embodiments, the second ILD 144 is a flowable film formed by a flowable CVD method. In some embodiments, the second ILD 144 is formed of a dielectric material such as PSG, BSG, BPSG, USG, etc., which can be deposited by any suitable method such as CVD, PECVD, etc.

[0082] In some embodiments, an etch stop layer (ESL) 142 is formed between the second ILD 144 and the first ILD 94, the gate mask 116, the source / drain contact 136, and the contact spacer 132. The ESL 142 may include a dielectric material having high etch selectivity relative to the etching of the second ILD 144, such as silicon nitride, silicon oxide, or silicon oxynitride.

[0083] exist Figures 20A to 20C In this configuration, source / drain contacts 146 and gate contacts 148 are formed to contact source / drain contacts 136 and gate electrode 114, respectively. Source / drain contacts 146 are physically coupled and electrically coupled to source / drain contacts 136. Gate contacts 148 are physically coupled and electrically coupled to gate electrode 114.

[0084] As an example of forming the source / drain contact 146 and the gate contact 148, an opening for the source / drain contact 146 is formed through the second ILD 144 and ESL 142, and an opening for the gate contact 148 is formed through the second ILD 144, ESL 142, and gate mask 116. These openings can be formed using acceptable photolithography and etching techniques. A liner (not shown separately), such as a diffusion barrier layer or adhesion layer, and a conductive material are formed in the openings. The liner may include titanium, titanium nitride, tantalum, or tantalum nitride. The conductive material may be cobalt, tungsten, copper, copper alloys, silver, gold, aluminum, or nickel. A planarization process, such as CMP, can be performed to remove excess material from the top surface of the second ILD 144. The remaining liner and conductive material form the source / drain contact 146 and the gate contact 148 in the openings. The source / drain contact 146 and the gate contact 148 can be formed using different processes or using the same process. Although each source / drain contact 146 and gate contact 148 is shown to have the same cross-section, it should be understood that each source / drain contact 112 and gate contact 110 may be formed with different cross-sections, which can prevent short circuits of the contacts.

[0085] Figure 21 This is a view of a FinFET according to some other embodiments. Figure 21 The embodiments are similar to Figure 20A In one embodiment, the gate mask 116 is also formed over the gate spacer 82. This embodiment can be formed by recessing the gate spacer 82 before depositing one or more dielectric materials of the gate mask 116. As a result, the gate mask 116 covers the gate spacer 82. In some embodiments, since the gate spacer 82 is covered by the gate mask 116, no impurities are implanted into the gate spacer 82.

[0086] Figures 22 to 23 This is a view of a FinFET according to some other embodiments. Figure 22 and Figure 23 The embodiments are respectively similar to Figure 20A and Figure 21 In one embodiment, the difference is that the contact spacer 132 is physically separated from the sidewall of the gate mask 116 via the CESL 92. Furthermore, the upper region 120U of the gate spacer 82, the upper region 120U of the CESL 92, the upper region 120U of the first ILD 94, and the upper region 120U of the gate mask 116 are removed. These embodiments can be formed by performing an action targeting... Figures 18A to 18C The described removal process continues until the top surface of gate mask 116 and the top surface of CESL 92 are coplanar (within process variations) and until the upper region 120U is removed.

[0087] The embodiment can achieve several advantages. Performing implantation process 118 modifies the upper region 120U of the gate spacer 82 (where applicable) and the upper region 120U of the gate mask 116 to be impurity-rich. Therefore, the upper regions 120U of the gate spacer 82 and the gate mask 116 can have high etch selectivity relative to the etching of the first ILD 94. Therefore, losses in the gate spacer 82 and the gate mask 116 during the self-aligned contact (SAC) etching process for forming the contact opening 128 can be reduced. Reducing this loss can reduce leakage between the source / drain contact 136 and the gate electrode 114, thereby improving device performance.

[0088] The disclosed FinFET embodiments can also be applied to nanostructured devices, such as nanostructured (e.g., nanosheets, nanowires, gate-all-around, etc.) field-effect transistors (NSFETs). In NSFET embodiments, the fins are replaced by nanostructures formed by patterning alternating layers of channel and sacrificial layers. The dummy gate structure and source / drain regions are formed in a manner similar to the embodiments described above. After the dummy gate structure is removed, the sacrificial layer may be partially or completely removed in the channel region. The replacement gate structure is formed in a manner similar to the embodiments described above, and the replacement gate structure may partially or completely fill the opening left by removing the sacrificial layer, and the replacement gate structure may partially or completely surround the channel layer in the channel region of the NSFET device. The ILD and contacts with the replacement gate structure and source / drain regions can be formed in a manner similar to the embodiments described above. Nanostructured devices can be formed as disclosed in U.S. Patent Application Publication No. 2016 / 0365414, which is incorporated herein by reference in its entirety.

[0089] Furthermore, FinFET / NSFET devices can be interconnected via the metallization layer in the interconnect structure above to form an integrated circuit. The interconnect structure above can be formed in a back-end process (BEOL) process, where the metallization layer connects to the source / drain contacts 146 and the gate contact 148. Additional features such as passive devices, memories (e.g., magnetoresistive random access memory (MRAM), resistive random access memory (RRAM), phase-change random access memory (PCRAM), etc.) can be integrated with the interconnect structure during the BEOL process.

[0090] In one embodiment, a device includes: a gate structure located on a channel region of a substrate; a gate mask located on the gate structure, the gate mask including a first dielectric material and impurities, the concentration of the impurities in the gate mask decreasing along a direction extending from an upper region of the gate mask to a lower region of the gate mask; a gate spacer located on a sidewall of the gate mask and a sidewall of the gate structure, the gate spacer including a first dielectric material and impurities, the concentration of the impurities in the gate spacer decreasing along a direction extending from an upper region of the gate spacer to a lower region of the gate spacer; and a source / drain region adjacent to the gate spacer and the channel region. In some embodiments of the device, the first dielectric material is a nitride. In some embodiments of the device, the impurity is boron. In some embodiments of the device, the impurity is phosphorus. In some embodiments of the device, the lower region of the gate mask is free of impurities. In some embodiments of the device, the lower region of the gate mask includes impurities.

[0091] In one embodiment, a device includes: a source / drain region adjacent to a channel region of a substrate; an etch stop layer located on the source / drain region; an interlayer dielectric located on the etch stop layer, the interlayer dielectric including a first dielectric material and impurities, wherein the concentration of impurities in an upper region of the interlayer dielectric is greater than that in a lower region of the interlayer dielectric; and a source / drain contact extending through the interlayer dielectric and the etch stop layer to contact the source / drain region, the source / drain contact having a straight sidewall in the lower region of the interlayer dielectric and an arcuate sidewall in the upper region of the interlayer dielectric. In some embodiments, the device further includes: a gate structure located on the channel region; and a gate mask located on the gate structure, the gate mask including a second dielectric material and impurities, the second dielectric material being different from the first dielectric material, and the top surface of the gate mask being coplanar with the top surface of the interlayer dielectric. In some embodiments, the device further includes a gate spacer located between the source / drain region and the gate structure, the gate spacer comprising a second dielectric material and impurities, and the top surface of the gate spacer being coplanar with the top surface of the interlayer dielectric. In some embodiments of the device, the gate spacer has arcuate sidewalls, and the device further includes a contact spacer surrounding the source / drain contact, the contact spacer extending along the arcuate sidewalls of the gate spacer and the source / drain contact.

[0092] In one embodiment, a method includes: depositing an interlayer dielectric on a source / drain region; forming a gate mask on a gate structure disposed on a channel region of a substrate, the channel region being adjacent to the source / drain region; implanting impurities into the gate mask to increase etch selectivity between the gate mask and the interlayer dielectric for a contact etching process; and performing a contact etching process to pattern contact openings in the interlayer dielectric that expose the source / drain region, the gate mask covering the gate structure during the contact etching process. In some embodiments of the method, the gate mask comprises a nitride, the interlayer dielectric comprises an oxide, and the impurity is boron or phosphorus. In some embodiments of the method, implanting impurities into the gate mask includes: placing a substrate on an implantation stage; implanting impurities into the gate mask while controlling the temperature of the implantation stage; and annealing the gate mask. In some embodiments of the method, the impurities are implanted at an implantation energy in the range of 0.5 keV to 10 keV while the implantation stage is heated to a temperature in the range of 100 °C to 500 °C. In some embodiments of the method, the gate mask is annealed using melt laser annealing (MLA) performed at a temperature in the range of 800 °C to 1000 °C, and the annealing duration is in the range of 1 µs to 10 µs. In some embodiments of the method, performing a contact etching process includes: etching an interlayer dielectric using C4F6 while generating plasma; forming a protective layer on the gate mask during the contact etching process, the protective layer comprising polymer byproducts of the contact etching process. In some embodiments of the method, the thickness of the protective layer is in the range of 0 Å to 200 Å. In some embodiments, the method further includes: forming a gate spacer between the gate structure and the source / drain regions; and implanting impurities in the gate spacer while implanting impurities in the gate mask. In some embodiments, the method further includes: implanting impurities in the interlayer dielectric while implanting impurities in the gate mask, the depth of impurity implantation in the interlayer dielectric being greater than the depth of implantation in the gate mask. In some embodiments of the method, after impurities are implanted into the gate mask, the concentration of impurities in the gate mask decreases along a direction extending from the upper region of the gate mask to the lower region of the gate mask.

[0093] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments introduced herein. Those skilled in the art should also recognize that these equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure.

[0094] Example 1 is a semiconductor device comprising: a gate structure located on a channel region of a substrate; a gate mask located on the gate structure, the gate mask comprising a first dielectric material and an impurity, the concentration of the impurity in the gate mask decreasing along a direction extending from an upper region of the gate mask to a lower region of the gate mask; a gate spacer located on a sidewall of the gate mask and a sidewall of the gate structure, the gate spacer comprising the first dielectric material and the impurity, the concentration of the impurity in the gate spacer decreasing along a direction extending from an upper region of the gate spacer to a lower region of the gate spacer; and a source / drain region adjacent to the gate spacer and the channel region.

[0095] Example 2 is the device described in Example 1, wherein the first dielectric material is a nitride.

[0096] Example 3 is the device described in Example 1, wherein the impurity is boron.

[0097] Example 4 is the device described in Example 1, wherein the impurity is phosphorus.

[0098] Example 5 is the device described in Example 1, wherein the lower region of the gate mask is free of the impurities.

[0099] Example 6 is the device described in Example 1, wherein the lower region of the gate mask includes the impurity.

[0100] Example 7 is a semiconductor device comprising: a source / drain region adjacent to a channel region of a substrate; an etch stop layer located on the source / drain region; an interlayer dielectric located on the etch stop layer, the interlayer dielectric comprising a first dielectric material and impurities, wherein the concentration of the impurities in an upper region of the interlayer dielectric is greater than that in a lower region of the interlayer dielectric; and a source / drain contact extending through the interlayer dielectric and the etch stop layer to contact the source / drain region, the source / drain contact having a straight sidewall in the lower region of the interlayer dielectric and an arcuate sidewall in the upper region of the interlayer dielectric.

[0101] Example 8 is the device described in Example 7, further comprising: a gate structure located on the channel region; and a gate mask located on the gate structure, the gate mask comprising a second dielectric material and the impurity, the second dielectric material being different from the first dielectric material, and the top surface of the gate mask being coplanar with the top surface of the interlayer dielectric.

[0102] Example 9 is the device described in Example 8, further comprising: a gate spacer located between the source / drain region and the gate structure, the gate spacer comprising the second dielectric material and the impurity, the top surface of the gate spacer being coplanar with the top surface of the interlayer dielectric.

[0103] Example 10 is the device described in Example 9, wherein the gate spacer has arcuate sidewalls, and the device further includes: a contact spacer surrounding the source / drain contact and extending along the arcuate sidewalls of the gate spacer and the source / drain contact.

[0104] Example 11 is a method of manufacturing a semiconductor device, comprising: depositing an interlayer dielectric on a source / drain region; forming a gate mask on a gate structure disposed on a channel region of a substrate, the channel region being adjacent to the source / drain region; implanting impurities in the gate mask to increase etch selectivity between the gate mask and the interlayer dielectric for a contact etch process; and performing the contact etch process to pattern contact openings in the interlayer dielectric, the contact openings exposing the source / drain region, the gate mask covering the gate structure during the contact etch process.

[0105] Example 12 is the method of Example 11, wherein the gate mask comprises a nitride, the interlayer dielectric comprises an oxide, and the impurity is boron or phosphorus.

[0106] Example 13 is the method of Example 11, wherein implanting the impurity into the gate mask includes: placing the substrate on an implantation stage; implanting the impurity into the gate mask while controlling the temperature of the implantation stage; and annealing the gate mask.

[0107] Example 14 is the method described in Example 13, wherein the impurity is injected with an injection energy in the range of 0.5 keV to 10 keV while the injection machine platform is heated to a temperature in the range of 100°C to 500°C.

[0108] Example 15 is the method of Example 13, wherein the gate mask is annealed using melt laser annealing (MLA) performed at a temperature in the range of 800 °C to 1000 °C, and the duration of the annealing is in the range of 1 µs to 10 µs.

[0109] Example 16 is the method of Example 11, wherein performing the contact etching process includes: etching the interlayer dielectric using C4F6 while generating plasma, and forming a protective layer on the gate mask during the contact etching process, the protective layer comprising polymer byproducts of the contact etching process.

[0110] Example 17 is the method described in Example 16, wherein the thickness of the protective layer is in the range of 0 Å to 200 Å.

[0111] Example 18 is the method of Example 11, further comprising: forming a gate spacer between the gate structure and the source / drain regions; and implanting the impurity in the gate spacer while implanting the impurity in the gate mask.

[0112] Example 19 is the method of Example 11, further comprising: simultaneously implanting the impurity in the gate mask and implanting the impurity in the interlayer dielectric, wherein the depth of the impurity implanted in the interlayer dielectric is greater than the depth of the impurity implanted in the gate mask.

[0113] Example 20 is the method of Example 11, wherein, after the impurity is implanted in the gate mask, the concentration of the impurity in the gate mask decreases along a direction extending from the upper region of the gate mask to the lower region of the gate mask.

Claims

1. A semiconductor device, comprising: A gate structure located on a channel region of a substrate; A gate mask located on the gate structure, the gate mask including a first dielectric material and impurities, the concentration of the impurities in the gate mask decreasing along a direction extending from the upper region of the gate mask to the lower region of the gate mask; A gate spacer is located on the sidewall of the gate mask and the sidewall of the gate structure. The gate spacer includes the first dielectric material and the impurity. The concentration of the impurity in the gate spacer decreases along a direction extending from the upper region of the gate spacer to the lower region of the gate spacer. as well as The source / drain region is adjacent to the gate spacer and the channel region. The gate mask and the gate spacer include a protective layer, which includes polymer byproducts from the contact etching process.

2. The device according to claim 1, wherein, The first dielectric material is a nitride.

3. The device according to claim 1, wherein, The impurity is boron.

4. The device according to claim 1, wherein, The impurity is phosphorus.

5. The device according to claim 1, wherein, The lower region of the gate mask is free of the impurities.

6. The device according to claim 1, wherein, The lower region of the gate mask includes the impurities.

7. A semiconductor device, comprising: Source / drain regions, which are adjacent to the channel regions of the substrate; An etch stop layer is located on the source / drain region; An interlayer dielectric, located on the etch stop layer, the interlayer dielectric comprising a first dielectric material and impurities, wherein the concentration of the impurities in the upper region of the interlayer dielectric is greater than that in the lower region of the interlayer dielectric; as well as Source / drain contacts extending through the interlayer dielectric and the etch stop layer to contact the source / drain regions, the source / drain contacts having straight sidewalls in the lower region of the interlayer dielectric and arcuate sidewalls in the upper region of the interlayer dielectric. The etching stop layer includes a protective layer, which comprises polymer byproducts from the contact etching process.

8. The device according to claim 7, further comprising: A gate structure located on the channel region; as well as A gate mask located on the gate structure, the gate mask comprising a second dielectric material and the impurity, the second dielectric material being different from the first dielectric material, and the top surface of the gate mask being coplanar with the top surface of the interlayer dielectric.

9. The device according to claim 8, further comprising: A gate spacer is located between the source / drain region and the gate structure. The gate spacer includes the second dielectric material and the impurity. The top surface of the gate spacer is coplanar with the top surface of the interlayer dielectric.

10. The device according to claim 9, wherein, The gate spacer has arcuate sidewalls, and the device further includes: A contact spacer surrounding the source / drain contact and extending along the arcuate sidewalls of the gate spacer and the source / drain contact.

11. A method for manufacturing a semiconductor device, comprising: Deposit interlayer dielectric in the source / drain regions; A gate mask is formed on a gate structure, the gate structure being disposed on a channel region of a substrate, the channel region being adjacent to the source / drain region; Impurities are injected into the gate mask to increase the etch selectivity between the gate mask and the interlayer dielectric for the contact etching process; as well as The contact etching process is performed to pattern contact openings in the interlayer dielectric, the contact openings exposing the source / drain regions, and the gate mask covers the gate structure during the contact etching process, wherein a protective layer is formed on the gate mask during the contact etching process, the protective layer comprising polymer byproducts of the contact etching process.

12. The method according to claim 11, wherein, The gate mask comprises a nitride, the interlayer dielectric comprises an oxide, and the impurity is boron or phosphorus.

13. The method according to claim 11, wherein, Implanting the impurity in the gate mask includes: The substrate is placed on the injection machine platform; While controlling the temperature of the injection machine stage, the impurity is injected into the gate mask; and The gate mask is annealed.

14. The method according to claim 13, wherein, The impurities are injected with an injection energy ranging from 0.5 keV to 10 keV while the injection machine platform is heated to a temperature ranging from 100 ℃ to 500 ℃.

15. The method according to claim 13, wherein, The gate mask is annealed using melt laser annealing (MLA) performed at a temperature in the range of 800 °C to 1000 °C, and the duration of the annealing is in the range of 1 µs to 10 µs.

16. The method according to claim 11, wherein, Performing the contact etching process includes: While generating plasma, C4F6 is used to etch the interlayer dielectric.

17. The method according to claim 11, wherein, The thickness of the protective layer is in the range of 0 Å to 200 Å.

18. The method of claim 11, further comprising: A gate spacer is formed between the gate structure and the source / drain region; as well as The impurity is implanted in the gate mask and simultaneously implanted in the gate spacer.

19. The method of claim 11, further comprising: Simultaneously with implanting the impurity in the gate mask, the impurity is also implanted in the interlayer dielectric, wherein the depth of the impurity implanted in the interlayer dielectric is greater than the depth of the impurity implanted in the gate mask.

20. The method according to claim 11, wherein, After the impurity is implanted into the gate mask, the concentration of the impurity in the gate mask decreases along a direction extending from the upper region of the gate mask to the lower region of the gate mask.

Images