Method of manufacturing a semiconductor device

Abstract

A method of manufacturing a semiconductor device includes forming a first conductor structure on a substrate, forming a first spacer on sidewalls of the first conductor structure, forming a sacrificial layer on sidewalls of the first spacer, forming a second spacer on sidewalls of the sacrificial layer, forming a second conductor structure adjacent to the second spacer, and removing the sacrificial layer to form an air gap. The method of removing the sacrificial layer to form the air gap includes providing a first gas to form at a first pressure in a first stage, providing a second gas and the first gas to form at the first pressure in a second stage, providing a third gas, the second gas, and the first gas to form at the first pressure in a third stage, and providing the first gas to form at a second pressure in a fourth stage, wherein the second pressure is lower than the first pressure. The sacrificial layer is removed in the third stage. The stability of the vapor etching process is improved to improve the etching selectivity, thereby reducing the loss of the spacer to improve the yield of the semiconductor device.

Description

Technical Field

[0001] This invention relates to a method for manufacturing a semiconductor, and more particularly to a method for manufacturing a semiconductor having an air gap. Background Technology

[0002] As technology advances, semiconductor devices are becoming increasingly integrated, with conductors within these devices getting closer together. This leads to significant parasitic capacitance and RC delay between conductors. Because air has a low dielectric constant (approximately 1), using air gaps in semiconductor devices can effectively reduce parasitic capacitance and RC delay. Therefore, optimizing air gap processes can contribute to the manufacturing quality of semiconductor devices. Summary of the Invention

[0003] According to some embodiments of the present invention, a method of manufacturing a semiconductor device includes forming a first conductor structure on a substrate, forming a first spacer on a sidewall of the first conductor structure, forming a sacrificial layer on a sidewall of the first spacer, forming a second spacer on a sidewall of the sacrificial layer such that the sacrificial layer is located between the first spacer and the second spacer, forming a second conductor structure adjacent to the second spacer, and removing the sacrificial layer by a vapor phase etching process to form an air gap. The method of removing the sacrificial layer to form the air gap includes providing a first gas to form a first stage at a first gas pressure, providing a second gas and a first gas to form a second stage maintaining the first gas pressure, providing a third gas, a second gas, and a first gas to form a third stage maintaining the first gas pressure, and providing a first gas to form a fourth stage at a second gas pressure, wherein the second gas pressure is lower than the first gas pressure. In the third stage, the sacrificial layer is removed to form the air gap.

[0004] In some embodiments, the method of manufacturing a semiconductor device further includes venting a second gas and a third gas after forming an air gap.

[0005] In some embodiments, the third gas includes a fluorine-containing gas.

[0006] In some embodiments, the second gas includes a nitrogen-containing gas.

[0007] In some embodiments, the first gas includes an inert gas, a nitrogen-containing gas, or a combination thereof.

[0008] In some embodiments, the second stage is maintained at the first gas pressure by adjusting the pressure of the first gas.

[0009] In some embodiments, the third stage is maintained at the first gas pressure by adjusting the pressure of the first gas.

[0010] In some embodiments, the second, third, and fourth stages are repeated after the fourth stage.

[0011] According to some embodiments of the present invention, a method of manufacturing a semiconductor device includes forming a bit line structure on a substrate, forming a first spacer on a sidewall of the bit line structure, forming a sacrificial layer on a sidewall of the first spacer, forming a second spacer on a sidewall of the sacrificial layer, forming a contact plug adjacent to and contacting the second spacer, forming a landing pad adjacent to and contacting the second spacer, providing a first gas to form a first stage at a first pressure, providing a second gas and the first gas to form a second stage maintained at the first pressure, providing a third gas, the second gas, and the first gas to form a third stage maintained at the first pressure, and providing a first gas to form a fourth stage at a second pressure, wherein the second pressure is lower than the first pressure. In the third stage, the sacrificial layer is removed to form an air gap.

[0012] In some embodiments, the first gas has low reactivity with the sacrificial layer.

[0013] In some embodiments, the pressure of the first gas is adjusted so that the second and third stages are maintained at the first gas pressure.

[0014] According to some embodiments of the present invention, a method for manufacturing semiconductors is provided that improves etch selectivity by enhancing the stability of the vapor phase etching process. This reduces spacer loss and thereby improves semiconductor device yield. Attached Figure Description

[0015] The following embodiments are read in conjunction with the accompanying drawings for a clear understanding of the invention. It should be noted that, according to industry standard practice, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily enlarged or reduced.

[0016] Figures 1 to 6 Cross-sectional schematic diagrams of the manufacturing of semiconductor devices at different process stages are illustrated according to some embodiments of the present invention.

[0017] Figure 7 A flowchart illustrating a method for manufacturing a semiconductor device is provided for some embodiments of the present invention.

[0018] Figure 8 A total pressure-time diagram is drawn for manufacturing a semiconductor device in a vapor phase etching process according to some embodiments of the present invention.

[0019] Figure 9 A pressure-time diagram of the first gas in a vapor phase etching process for manufacturing a semiconductor device is illustrated according to some embodiments of the present invention.

[0020] Figure 10Cross-sectional schematic diagrams of the manufacturing of semiconductor devices at different process stages are illustrated according to some embodiments of the present invention. Detailed Implementation

[0021] When an element is referred to as “on”, it can mean that the element is directly on another element, or that another element exists between the two. Conversely, when an element is referred to as “directly on” another element, it cannot mean that another element exists between the two. As used herein, the term “and / or” includes any combination of one or more of the listed related items.

[0022] In this invention, the use of terms such as first, second, and third, etc., to describe various elements, components, regions, layers, and / or blocks is understandable. However, these elements, components, regions, layers, and / or blocks should not be limited by these terms. These terms are limited to identifying individual elements, components, regions, layers, and / or blocks only. Therefore, the first element, component, region, layer, and / or block mentioned below may also be referred to as the second element, component, region, layer, and / or block without departing from the spirit of this invention.

[0023] The term "about" as used in this invention generally refers to an error or range of about 20 percent, preferably about 10 percent, and more preferably about 5 percent. Unless otherwise specified, all values ​​mentioned herein are considered approximate, i.e., the error or range indicated by "about".

[0024] This invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming air gaps in a semiconductor device. In semiconductor devices with decreasing dimensions, air gaps with narrow channel widths can be formed by vapor phase etching (VPE). Although there is an etch selectivity in the VPE process for forming air gaps, the actual etch selectivity is unstable due to the insufficient stability of the VPE process. This can lead to unexpected losses in the spacer layer adjacent to the air gap, potentially causing leakage. To improve the etch selectivity in the VPE process, embodiments of this invention provide a method for improving the stability of the VPE process.

[0025] Figures 1 to 6 and Figure 10 Cross-sectional schematic diagrams of methods for manufacturing semiconductor devices at various process stages are illustrated for some embodiments of the present invention. It should be noted that when... Figures 1 to 6 and Figure 10 When illustrating or describing a series of operations or events, the order in which these operations or events are described should not be limited. For example, some operations or events may be performed in a different order than in this invention, some operations or events may occur simultaneously, some operations or events may be unnecessary, and / or some operations or events may be repeated. Furthermore, the actual process may require… Figures 1 to 6 and Figure 10 Additional operational steps are performed before, during, or after the illustrated process flow to fully form the semiconductor device with an air gap. Therefore, some of these additional operational steps may be briefly described in this invention. Furthermore, unless otherwise stated, Figures 1 to 6 and Figure 10 Descriptions of the same components can be directly applied to other images.

[0026] See Figure 1 A first conductive structure 110 is formed on the substrate 100. The first conductive structure 110 is substantially perpendicular to the substrate 100 and extends in a direction away from the substrate 100 (e.g., upward along the Z-axis).

[0027] The substrate 100 further includes an isolation region 102 and an active region 104, wherein the isolation region 102 electrically isolates adjacent active regions 104. The substrate 100 may include silicon, such as crystalline silicon, polycrystalline silicon, or amorphous silicon. The substrate 100 may include alloy semiconductors, such as silicon germanide (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), indium gallium arsenide (InGaAs), gallium indium phosphide (GaInP), and / or gallium arsenide indium phosphide (GaInAsP), or other suitable materials. The substrate 100 may include compound semiconductors, such as silicon carbide (SiC), germanium arsenide (GeAs), gallium phosphide, indium phosphide, indium arsenide (InAs), indium antimonide, or the like. Furthermore, the substrate 100 may include a silicon-on-insulator (SOI) structure.

[0028] In some embodiments, the isolation region 102 is formed using shallow trench isolation (STI) technology to define and separate the active region 104. In some embodiments, the isolation region 102 is an STI region. The isolation region 102 may include silicon oxide, silicon nitride, silicon oxynitride, fluoride-doped silicate glass (FSG), low dielectric constant materials, other suitable materials, or combinations thereof.

[0029] The substrate 100 may be subjected to an ion implantation process to dope N-type or P-type dopants. In some embodiments, source and drain regions (not shown) may be formed in the active region 104 of the substrate 100 by doping with N-type or P-type dopants.

[0030] exist Figure 1In this example, the insulating layer 106 on the substrate 100 covers the upper surface of the isolation region 102 and the upper surface of the active region 104, thereby isolating them from other subsequently formed components. Figure 1 In this example, the insulating layer 106 has an opening 108H. The opening 108H extends into the interior of the substrate 100 and exposes a portion of the active region 104. In a subsequent process, the opening 108H is filled with a conductive material to form a direct contact 108. The direct contact 108 is electrically connected to the active region 104.

[0031] See also Figure 1 A first conductive structure 110 is formed on the substrate 100. Adjacent first conductive structures 110 are spaced apart from each other, and the first conductive structures 110 may be formed on the insulating layer 106 or on the direct contact 108. Figure 1 In the illustrated embodiment, the first conductive structure 110 is essentially a bit line structure. Therefore, the first conductive structure 110 can be divided into two parts along a direction perpendicular to the substrate 100 (e.g., the Z-axis direction): one part is a conductive layer 112 located at the bottom, and the other part is an insulating capping layer 114 located at the top. Furthermore, when the first conductive structure 110 is formed on the direct contact 108, the conductive layer 112 located at the bottom can be electrically connected to the direct contact 108.

[0032] The first conductive structure 110 may include a semiconductor material, a doped semiconductor material, a metal, a metal nitride, a metal silicide, other suitable conductive materials, or a combination thereof. In an embodiment of the bitline structure, the conductive layer 112 of the first conductive structure 110 may include tungsten, tungsten nitride, and / or titanium nitride. The insulating capping layer 114 of the first conductive structure 110 is an insulating material, such as, but not limited to, silicon nitride.

[0033] See Figure 2 A first spacer 200 is formed on the horizontal sidewall of the first conductive structure 110, a sacrificial layer 202 is formed on the horizontal sidewall of the first spacer 200, and a second spacer 204 is formed on the horizontal sidewall of the sacrificial layer 202, wherein the sacrificial layer 202 is located between the first spacer 200 and the second spacer 204. It should be understood that the term "horizontal" as used above refers to a direction parallel to the extension direction of the substrate 100 (e.g., parallel to the X-axis).

[0034] One or more deposition processes can be used to form the first spacer 200, the sacrificial layer 202, and the second spacer 204. For example, a conformal deposition process can be used to sequentially deposit the first spacer 200, the sacrificial layer 202, and the second spacer 204 on the first conductive structure 110 and the substrate 100, such that the first spacer 200, the sacrificial layer 202, and the second spacer 204 have a similar profile to the first conductive structure 110 and the substrate 100. The deposition process may include chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), other suitable deposition processes, or combinations thereof.

[0035] Furthermore, depending on the device design or process conditions, deposition and etching processes can be performed alternately. In cases such as... Figure 2 In the illustrated embodiments, the deposition process may be combined with one or more etching processes to remove the first spacer 200, the sacrificial layer 202, or the second spacer 204, or a combination thereof, located in a horizontal position (e.g., parallel to the X-axis). In some embodiments, the second spacer 204 located on the top surface 110T of the first conductive structure 110 may be retained and cover the first spacer 200 and the sacrificial layer 202.

[0036] The thickness of the first spacer 200, the sacrificial layer 202, or the second spacer 204 may be between about 1 nanometer and about 10 nanometers. In some embodiments, the thickness of the sacrificial layer 202 is less than about 5 nanometers.

[0037] In some embodiments, any two adjacent layers of the first spacer 200, sacrificial layer 202, or second spacer 204 may be made of different materials, and the materials of any two adjacent layers may have different etching selectivity for the same etchant. In some embodiments, the first spacer 200 and the second spacer 204 may be formed of the same material. When the first spacer 200 and the second spacer 204 are oxides (e.g., silicon oxide), the sacrificial layer 202 may be a nitride (e.g., silicon nitride). When the first spacer 200 and the second spacer 204 are nitrides (e.g., silicon nitride), the sacrificial layer 202 may be an oxide (e.g., silicon oxide).

[0038] See Figure 3A second conductive structure 300 is formed adjacent to the second spacer 204. Further, a contact opening 300H is formed in the space separated by the adjacent first conductive structure 110, and in a subsequent process, the conductive material of the second conductive structure 300 is formed between the contact opening 300H and the adjacent first conductive structure 110, thereby forming the second conductive structure 300. The contact opening 300H allows the second conductive structure 300 to protrude into the substrate 100. When the first conductive structure 110 is a bitline structure, the second conductive structure 300 essentially acts as a contact plug and contacts the active region 104 of the substrate 100.

[0039] The second conductive structure 300 may include a semiconductor material, a doped semiconductor material, a metal, a metal nitride, a metal silicide, other suitable conductive materials, or a combination thereof. In some embodiments, the second conductive structure 300 may include a silicon-containing material, such as doped polycrystalline silicon, but the invention is not limited to this example.

[0040] Please see Figure 4 A conductive material layer 400 is formed on the second conductive structure 300, covering the first conductive structure 110 and the second conductive structure 300. In some embodiments, the conductive material layer 400 may contain a metal, such as tungsten, copper, or other suitable metal. In some embodiments, the conductive material layer 400 may be formed by blanket deposition.

[0041] Please see Figure 5 A portion of the conductive material layer 400 is removed to form several third conductive structures 500. In some embodiments, a portion of the conductive material layer 400 is removed by an etching process.

[0042] The formed third conductive structure 500 covers a portion of the top surface 110T of the first conductive structure 110 and the horizontal sidewall of the second spacer 204. The third conductive structure 500 has a top surface 500T that is generally parallel to the plane of the substrate 100 (e.g., a plane parallel to the XY plane) and may be coplanar with each other. The third conductive structure 500 is electrically connected to the second conductive structure 300. In some embodiments, the third conductive structure 500 is substantially a landing pad.

[0043] exist Figure 5In the illustrated embodiment, in addition to removing a portion of the conductive material layer 400, portions of the first conductive structure 110, the first spacer 200, the sacrificial layer 202, the second spacer 204, or combinations thereof, may also be removed. The space formed after removing a portion of the conductive material layer 400 is an opening 502, located between adjacent third conductive structures 500. One end of the sacrificial layer 202 is exposed in the opening 502.

[0044] Please see Figure 6 The sacrificial layer 202 is removed to form the air gap 600. Since the thickness of the sacrificial layer 202 is less than approximately 5 nanometers, a vapor phase etching process can be used to form the air gap 600 with narrow channels. During the formation of the third conductive structure 500, because one end of the sacrificial layer 202 is exposed in the opening 502, the gas etchant can contact the sacrificial layer 202 and gradually remove it. The space left after the removal of the sacrificial layer 202 forms the air gap 600.

[0045] In some embodiments of the present invention Figure 6 The vapor phase etching process used in this process can be performed using method 700, in which... Figure 7 Flowchart for method 700 Figure 8 To plot the total gas pressure-time diagram in the vapor phase etching process according to method 700, and Figure 9 To illustrate the pressure-time diagram of the first gas in the vapor phase etching process according to method 700, i.e., the partial pressure of the first gas in the vapor phase etching process. The total pressure is the sum of the pressures (partial pressures) of the various component gases. In some embodiments, the steps of method 700 are performed at a substantially constant operating temperature.

[0046] Please see Figure 7 First, step 702 is performed, where a first gas is provided to form a first stage S1 at a first gas pressure P1. The first gas is used in the first stage S1 for cleaning. Figure 6 The semiconductor device and its chamber (not shown). Since the first stage S1 is for cleaning purposes, the selected constituent gases of the first gas in the first stage S1 will not react with... Figure 6 The first gas reacts with the materials within the semiconductor device to avoid damaging them. In other words, the selected component gas of the first gas has low reactivity with the materials of the semiconductor device. For example, the first gas may include low-reactivity gas molecules, such as nitrogen, inert gases (helium, neon, argon, krypton, xenon), other suitable low-reactivity gases, or combinations thereof. In some embodiments, the first gas may include one of the inert gases and nitrogen. In some embodiments, the first gas may include argon and nitrogen.

[0047] Please see Figure 8 and Figure 9In the first stage S1, only the first gas is composed, therefore Figure 8 Total air pressure and Figure 9 The pressure of the first gas is essentially the same. The pressure of the first gas can be adjusted by controlling the flow rate of the first gas, thereby bringing the total pressure to the desired value. For example... Figure 8 The total gas pressure in the process is a first gas pressure P1. In some embodiments, the first gas pressure P1 may be substantially the same as the total gas pressure of the subsequent vapor phase etchant reaction stage (e.g., the subsequent third stage S3).

[0048] Step 702 will continue for a first time length T1, during which the first gas is continuously supplied to form a total gas pressure in the first stage S1 of the first gas pressure P1. The first time length T1 depends on the size of the chamber (not shown) where the semiconductor device is located, and the first time length T1 is lengthened as the chamber size increases to ensure... Figure 6 The cleaning of the semiconductor device and its chamber (not shown).

[0049] Please see next. Figure 7 Step 704 is performed, providing a second gas and a first gas to form a second stage S2 at a first gas pressure P1. The composition of the second gas may vary depending on the material of the sacrificial layer 202. In embodiments where the sacrificial layer 202 is an oxide (e.g., silicon oxide), the second gas may include a nitrogen-containing gas. In some embodiments, the second gas may be ammonia. Furthermore, the composition of the second gas is not combined with... Figure 6 The materials inside the semiconductor device react.

[0050] Please see Figure 8 In the second stage S2, the total pressure remains stably maintained at the first pressure P1, meaning the total pressure of the second stage S2 is substantially the same as the total pressure of the first stage S1 at the first pressure P1. The second stage S2 consists of a first gas and a second gas, so the total pressure is contributed by both gases. Compared to the first stage S1, the second stage S2 is as if an additional second gas has been added to the first stage S1. To maintain the total pressure at the first pressure P1, the pressure of the first gas can be adjusted so that the second stage S2 has the same total pressure as the first stage S1. For example, as... Figure 9As shown, when the pressure of the added second gas is the second pressure P2, the pressure of the first gas can be correspondingly reduced by the second pressure P2, causing the pressure of the first gas to drop from the first pressure P1 to the third pressure P3. Therefore, the total pressure maintained at the first pressure P1 in the second stage S2 is the sum of the partial pressure of the second gas at the second pressure P2 and the partial pressure of the first gas at the third pressure P3, i.e., P1 = P2 + P3. Similarly, as mentioned before, the pressure of the first or second gas can be affected by adjusting the gas flow rate.

[0051] Step 704 will continue for a second time length T2, during which the second gas and the first gas are continuously supplied to form a second stage S2 with a total gas pressure of the first gas pressure P1. The second time length T2 varies depending on the machine capability and process conditions. In some embodiments, the second time length T2 should be longer than the time required to reach a steady state in the second stage S2. If the second stage S2 is not fully stable before termination, it may affect the stability of the total gas pressure in subsequent stages (e.g., the third stage S3).

[0052] Please see next. Figure 7 Step 706 is performed, providing a third gas, a second gas, and a first gas to form a third stage S3 at a first gas pressure P1. The third stage S3 serves as the reaction stage of the vapor phase etching process, during which the sacrificial layer 202 is removed to form the gas gap 600 (e.g., ...). Figure 6 (As shown). The constituent gas selected in the third stage S3 may vary depending on the material of the sacrificial layer 202. In embodiments where the sacrificial layer 202 is an oxide (e.g., silicon oxide), the third gas may include a fluorine-containing gas. In embodiments where the second gas includes ammonia, the third gas, as a vapor-phase etchant, reacts with the second gas after mixing with it, removing the sacrificial layer 202 and thus forming the air gap 600.

[0053] Please see Figure 8 In the third stage S3, the total pressure remains stably at the first pressure P1. That is, the total pressure of the third stage S3 is substantially the same as the total pressure of the first stage S1 and the total pressure of the second stage S2, both at the first pressure P1. The third stage S3 consists of a third gas, a second gas, and a first gas; therefore, the total pressure is contributed by all three gases. Compared to the second stage S2, the third stage S3 is as if a third gas has been added to the second stage S2. To maintain the total pressure at the first pressure P1, the pressure of the first gas can be adjusted to keep the total pressure of the third stage S3 at the first pressure P1. For example, if... Figure 9As shown, when the gas pressure of the third gas added is the fourth gas pressure P4, the fourth gas pressure P4 value can be correspondingly reduced again for the first gas, so that the gas pressure of the first gas is reduced from the third gas pressure P3 to the fifth gas pressure P5. Therefore, the total gas pressure maintained at the first gas pressure P1 in the third stage S3 is the sum of the gas pressure (partial pressure) of the second gas at the second gas pressure P2, the gas pressure (partial pressure) of the third gas at the fourth gas pressure P4, and the gas pressure (partial pressure) of the first gas at the fifth gas pressure P5, that is, P1 = P2 + P4 + P5. Similarly, as described above, the gas pressure values of the first gas, the second gas, or the third gas can be affected by adjusting the gas flow rates of the first gas, the second gas, or the third gas.

[0054] It should be noted that in some other embodiments of the third stage S3, the amount of gas pressure consumed in the gas-phase etching reaction may not be consistent with the amount of gas pressure formed by the reaction. Therefore, the gas pressure value reduced for the first gas may be different from the aforementioned fourth gas pressure P4 (that is, the gas pressure of the third gas added is the fourth gas pressure P4) in order to maintain the total gas pressure at the first gas pressure P1.

[0055] Step 706 will continue for the third time length T3, that is, in the third time length T3, the third gas, the second gas, and the first gas are continuously provided to form the third stage S3 with the total gas pressure at the first gas pressure P1. The third time length T3 can be adjusted according to process conditions and semiconductor device design, such as the reaction conditions between the third gas and the second gas, both of which are used as gas-phase etchants, and the sacrificial layer 202, or the structure of the sacrificial layer 202 (such as the aspect ratio). The present invention is not limited to the above enumeration.

[0056] Next, please refer to Figure 7 , perform step 708 to provide the first gas to form the fourth stage S4 with the sixth gas pressure P6, where the sixth gas pressure P6 is lower than the first gas pressure P1. The fourth stage S4 is similar to the first stage S1. The fourth stage S4 also serves the purpose of cleaning. The first gas is used to remove the third gas and the second gas from the semiconductor device and the chamber (not shown) where it is located to avoid the continuous progress of unexpected etching reactions. Generally, by exhausting all the gases in the chamber (for example, the first gas, the second gas, and the third gas), the total gas pressure is reduced from the first gas pressure P1 to the sixth gas pressure P6, that is, P6 < P1, and the third gas and the second gas can be quickly removed and the chamber (not shown) can be cleaned.

[0057] Step 708 will continue for the fourth time length T4, that is, in the fourth time length T4, the first gas is continuously provided to form the fourth stage S4 with the total gas pressure at the sixth gas pressure P6. The fourth time length T2 depends on the size of the chamber (not shown) where the semiconductor device is located. As the chamber size increases, the fourth time length T4 is lengthened to ensure Figure 6The cleaning of the semiconductor device and its chamber (not shown).

[0058] After step 708 is completed, steps 704, 706, and 708 may be repeated depending on process requirements, such as... Figure 7 As shown.

[0059] Please see Figure 8 In an embodiment repeating step 704, a second gas and a first gas are provided to form a fifth stage S5 at a first gas pressure P1. The fifth stage S5 is similar to the second stage S2, i.e., the total gas pressure is stably maintained at the first gas pressure P1 in the fifth stage S5. However, since the total gas pressure in the preceding step of the fifth stage S5 (i.e., the sixth gas pressure P6 of the fourth stage S4) is lower than the first gas pressure P1, there is a pressure ramp-up section after entering the fifth stage S5 to raise the total gas pressure from the sixth gas pressure P6 to the first gas pressure P1, and maintain it at the first gas pressure P1 for a fifth time length T5.

[0060] In some embodiments, during the pressure ramp-up phase, the total pressure can be significantly increased to between approximately 95% and approximately 97% of the first pressure P1, and then precisely adjusted to approximately 100% of the first pressure P1.

[0061] Once the total pressure reaches the first pressure P1, it is maintained at the first pressure P1 for a fifth time length T5. The fifth time length T5 varies depending on the machine's capabilities and process conditions. In some embodiments, the fifth time length T5 should be greater than the time required to reach a stable state in the fifth stage S5. If the fifth stage S5 is not in a stable state before termination, it may affect the stability of the total pressure in subsequent stages (e.g., the sixth stage S6). Furthermore, in some embodiments, the fifth time length T5 may be extended in the fifth stage S5 to ensure the cleanliness of the semiconductor device and its surrounding chamber (not shown).

[0062] Since the fifth stage S5 is similar to the second stage S2, and is also composed of a second gas and a first gas, the first gas is adjusted accordingly based on the pressure of the second gas to maintain the total pressure at the first pressure P1. In some embodiments, after the total pressure of the fifth stage S5 rises to the first pressure P1, in order to maintain the total pressure at the first pressure P1, as mentioned above, the pressure of the first gas can be adjusted to the third pressure P3 based on the pressure of the second gas added being the second pressure P2. Therefore, the total pressure maintained at the first pressure P1 in the fifth stage S5 is the sum of the partial pressure of the second gas at the second pressure P2 and the partial pressure of the first gas at the third pressure P3, i.e., P1 = P2 + P3. Figure 9 Show.

[0063] Please see Figure 8 and Figure 9 In an embodiment of repeated step 706, a third gas, a second gas, and a first gas are provided to form a sixth stage S6 at a first gas pressure P1. Since the total gas pressure entering the sixth stage S6 is substantially equal to the first gas pressure P1, the total gas pressure-time diagram of the sixth stage S6 is substantially equivalent to the total gas pressure-time diagram of the aforementioned third stage S3, and will not be repeated here.

[0064] Please see Figure 8 and Figure 9 In an embodiment of repeated step 708, a first gas is provided to form a seventh stage S7 at a sixth pressure P6, wherein the sixth pressure P6 is lower than the first pressure P1. Since the total pressure-time diagram of the aforementioned sixth stage S6 is substantially equivalent to the total pressure-time diagram of the aforementioned third stage S3, the total pressure-time diagram of the subsequent seventh stage S7 is substantially equivalent to the total pressure-time diagram of the aforementioned fourth stage S4, and therefore will not be described again here.

[0065] After step 708 is completed, steps 704, 706, and 708 may be repeated a second time depending on process requirements, such as... Figure 7 As shown. In the embodiments of the second repetition of steps 704, 706, and 708, an eighth stage S8, a ninth stage S9, and a tenth stage S10 are formed, as follows. Figure 8 and Figure 9 As shown. Among them, the total pressure-time diagram of stage 8 S8 is essentially equivalent to the total pressure-time diagram of stage 5 S5 mentioned above, the total pressure-time diagram of stage 9 S9 is essentially equivalent to the total pressure-time diagram of stage 3 / 6 S3 / S6 mentioned above, and the total pressure-time diagram of stage 10 S10 is essentially equivalent to the total pressure-time diagram of stage 4 / 7 S4 / S7 mentioned above, so it will not be described again here.

[0066] In the vapor phase etching process method 700, the total gas pressure before entering the reaction stage of the vapor phase etching process is maintained at a target gas pressure value by adjusting the first gas, thereby improving the stability of the total gas pressure during the switching process between stages. In other words, in the vapor phase etching process method 700, the total gas pressure in the first stage S1 to the third stage S3 is maintained at a first gas pressure P1 by adjusting the first gas, where the first gas pressure P1 is the total gas pressure of the reaction stage of the vapor phase etching process (e.g., the third stage S3). When entering the reaction stage of the vapor phase etching process while maintaining the total gas pressure at the target gas pressure value, the concentration of the etchant can be effectively controlled, thereby improving the etch selectivity between the sacrificial layer 202 and the spacers (e.g., the first spacer 200, the second spacer 204), and allowing the spacers to maintain an appropriate thickness.

[0067] Please see Figure 10A capping layer 1000 is formed on the substrate 100 to cover the channel opening of the air gap 600. The capping layer 1000 protects the air gap 600 from damage caused by other materials filling the air gap 600, which has low dielectric constant characteristics. The capping layer 1000 is an insulating material, such as, but not limited to, silicon nitride. The first conductive structure 110 and the second conductive structure 300 are electrically isolated by the air gap 600, the first spacer 200, and the second spacer 204.

[0068] This invention relates to a method for manufacturing a semiconductor device. In a vapor phase etching process that removes a sacrificial layer to form a gap, the total gas pressure in each stage is maintained at the same pressure as in the reaction stage to improve the stability of the vapor phase etching process. This allows for effective control of the etchant concentration, thereby improving the etch selectivity. Improved etch selectivity reduces spacer loss, ensuring reliable electrical isolation of adjacent conductive structures, thus reducing the possibility of semiconductor device leakage and improving semiconductor device yield.

[0069] The above-described structure, besides being applied to the formation of air gaps in semiconductor devices, can also be applied to any device that removes a sacrificial layer to form a fine channel. In some embodiments, the narrowest side length of the channel may be less than about 5 nanometers. Based on this invention, any device or system using the same implementation concept as method 700 but with different operating methods is within the spirit and scope of this invention.

[0070] The foregoing outlines the features of several embodiments of the present invention, enabling those skilled in the art to more readily understand the invention. It should be understood by anyone skilled in the art that this specification can easily serve as a basis for changes or designs to other structures or processes to achieve the same objectives and / or obtain the same advantages as the embodiments of the present invention. It will also be understood by anyone skilled in the art that equivalent structures described above do not depart from the spirit and scope of the present invention, and that modifications, substitutions, and alterations can be made without departing from the spirit and scope of the present invention.

[0071] [Symbol Explanation]

[0072] 100: Substrate

[0073] 102: Isolation Area

[0074] 104: Active Area

[0075] 106: Insulation layer

[0076] 108: Direct contact parts

[0077] 108H: Opening

[0078] 110: First conductive structure

[0079] 110T: Top surface

[0080] 112: Conductive layer

[0081] 114: Insulation Covering

[0082] 200: First spacer

[0083] 202: Sacrifice Layer

[0084] 204: Second spacer

[0085] 300: Second conductive structure

[0086] 300H: Opening

[0087] 400: Conductive material layer

[0088] 500: Third conductive structure

[0089] 500T: Top Surface

[0090] 502: Opening

[0091] 600: Air gap

[0092] 700: Method

[0093] 702: Steps

[0094] 704: Steps

[0095] 706: Steps

[0096] 708: Steps

[0097] P1, P2, P3, P4, P5, P6: Air pressure

[0098] S1, S2, S3, S4, S5, S6, S7, S8, S9, S10: Stages

[0099] T1, T2, T3, T4, T5: Time length

[0100] X, Y, Z: Axes.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, include: The first conductor structure is formed on the substrate; A first spacer is formed on the sidewall of the first conductor structure; A sacrificial layer is formed on the sidewall of the first spacer; A second spacer is formed on the sidewall of the sacrificial layer, wherein the sacrificial layer is located between the first spacer and the second spacer; A second conductor structure is formed adjacent to the second spacer; as well as The sacrificial layer is removed by a vapor phase etching process to form an air gap, including: A first gas is provided to form a first stage, wherein the first stage is at a first gas pressure; A second gas and the first gas are provided to form a second stage, wherein the second stage is maintained at the first gas pressure; A third gas, the second gas, and the first gas are provided to form a third stage, wherein the third stage is maintained at the first gas pressure, and the sacrificial layer is removed in the third stage to form the air gap; and The first gas is provided to form a fourth stage, wherein the gas environment of the fourth stage is at a second pressure, which is lower than the first pressure.

2. The method of manufacturing a semiconductor device according to claim 1, further comprising, after forming the air gap, discharging the second gas and the third gas.

3. The method of manufacturing a semiconductor device according to claim 1, wherein the third gas comprises a fluorine-containing gas.

4. The method of manufacturing a semiconductor device according to claim 1, wherein the second gas comprises a nitrogen-containing gas.

5. The method of manufacturing a semiconductor device according to claim 1, wherein the first gas comprises an inert gas, a nitrogen-containing gas, or a combination thereof.

6. The method of manufacturing a semiconductor device according to claim 1, wherein the second stage is maintained at the first gas pressure by adjusting the pressure of the first gas.

7. The method of manufacturing a semiconductor device according to claim 1, wherein the third stage is maintained at the first gas pressure by adjusting the pressure of the first gas.

8. The method of manufacturing a semiconductor device according to claim 1, wherein the second stage, the third stage, and the fourth stage are repeated after the fourth stage.

9. A method for manufacturing a semiconductor device, characterized in that, include: Forming bitline structures on the substrate; The first spacer is formed on the sidewall of the bit line structure; A sacrificial layer is formed on the sidewall of the first spacer; A second spacer is formed on the sidewall of the sacrificial layer; A contact plug is formed on the substrate, adjacent to and in contact with the second spacer; A landing pad is formed on the contact plug, adjacent to and in contact with the second spacer; A first gas is provided to form a first stage, wherein the first stage is at a first gas pressure; A second gas and the first gas are provided to form a second stage, wherein the second stage is maintained at the first gas pressure; A third gas, the second gas, and the first gas are provided to form a third stage, wherein the third stage is maintained at the first gas pressure, and the sacrificial layer is removed in the third stage to form an air gap; as well as The first gas is provided to form a fourth stage, wherein the gas environment of the fourth stage is at a second pressure, which is lower than the first pressure.

10. The method of manufacturing a semiconductor device according to claim 9, wherein the first gas has low reactivity toward the sacrificial layer.

11. The method of manufacturing a semiconductor device according to claim 9, wherein the pressure of the first gas is adjusted so that the second stage and the third stage are maintained at the first gas pressure.

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