Electronic device and display device

Abstract

The present invention relates to an electronic device and a display device. The electronic device includes: a frame including a first connection portion; a strap connected to the frame; a display device mounted on the frame and including a second connection portion connected to the first connection portion; and a lens. The display device includes: a substrate having a first pixel area, a second pixel area, and a third pixel area, and including a first longer side and a shorter side adjacent to the first longer side; pixels on the substrate, the pixels including a first pixel in the first pixel area, a second pixel in the second pixel area, and a third pixel in the third pixel area; a first scan driver configured to supply a first scan signal to a first scan line connected to the first pixel; a second scan driver configured to supply a second scan signal to a second scan line connected to the second pixel; and a third scan driver configured to supply a third scan signal to a third scan line connected to the third pixel.

Description

[0001] This application is a divisional application of patent application with application number 201711286984.4 and title “Display Device” filed on December 7, 2017.

[0002] CROSS-REFERENCE TO RELATED APPLICATIONS

[0003] This application claims priority to and the benefit of Korean Patent Application No. 10-2016-0166201 filed on December 7, 2016, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference in their entirety. Technical Field

[0004] An aspect of some example embodiments of the present invention relates to a display device. Background Art

[0005] Recently, various types of electronic devices that can be worn on the body have been developed. These devices are generally referred to as wearable electronic devices.

[0006] Head-mounted display (hereinafter 'HMD') devices, which are one example of such wearable electronic devices, have been used for various purposes such as watching movies because they provide a deep sense of immersion by displaying vivid images.

[0007] The above information discussed in this Background section is only for enhancement of understanding of the background of the technology and therefore it may contain information that does not form the prior art that is already known to a person having ordinary skill in the art. Summary of the invention

[0008] An aspect of some example embodiments of the present invention is directed to a display device having improved display quality.

[0009] According to some example embodiments of the present invention, a display device may include: a pixel unit including a first pixel in a first pixel area, a second pixel in a second pixel area, and a third pixel in a third pixel area; a first scan driver including a first multiplexer, the first scan driver being configured to operate in response to a first mode and a second mode different from the first mode, and being configured to supply a first scan signal to a first scan line connected to the first pixel; a second scan driver being configured to supply a second scan signal to a second scan line connected to the second pixel; and a third scan driver including a second multiplexer, the third scan driver being configured to operate in response to the first mode and the second mode, and being configured to supply a third scan signal to a third scan line connected to the third pixel.

[0010] According to some example embodiments, the first scan driver further includes first scan stages respectively connected to the first scan lines, and the first scan stages receive the output signal from the first multiplexer.

[0011] According to some example embodiments, the third scan driver further includes third scan stages respectively connected to the third scan lines, and the third scan stages receive the output signal from the second multiplexer.

[0012] According to some example embodiments, each of the first multiplexers includes a first switch configured to be turned on in the first mode and a second switch configured to be turned on in the second mode.

[0013] According to some example embodiments, a second switch of a first one of the first multiplexers is configured to receive a first start signal, and second switches of the remaining first multiplexers are configured to receive an output signal from a first scan stage located in a previous horizontal line.

[0014] According to some example embodiments, the first switch of a last one of the first multiplexers is configured to receive the second start signal, and the first switches of the remaining first multiplexers are configured to receive the first sub start signal.

[0015] According to some example embodiments, the first sub start signal is simultaneously supplied to the first scan stage in the first mode.

[0016] According to some example embodiments, the first scan signals are simultaneously supplied to the first scan lines located among the odd-numbered horizontal lines, and the first scan signals are simultaneously supplied to the first scan lines located among the even-numbered horizontal lines.

[0017] According to some example embodiments, each of the second multiplexers includes a first switch configured to be turned on in the first mode and a second switch configured to be turned on in the second mode.

[0018] According to some example embodiments, the first switch of the second multiplexer is configured to receive the second sub start signal, and the second switch of the second multiplexer is configured to receive the output signal from the scan stage located in a previous horizontal line.

[0019] According to some example embodiments, the second sub start signal is simultaneously supplied to the third scan stage in the first mode.

[0020] According to some example embodiments, the third scan signals are simultaneously supplied to the third scan lines located among the odd-numbered horizontal lines, and the third scan signals are simultaneously supplied to the third scan lines located among the even-numbered horizontal lines.

[0021] According to some example embodiments, the first scan driver, the second scan driver, and the third scan driver are configured to sequentially output the first scan signal, the second scan signal, and the third scan signal, respectively, during a single frame in the second mode.

[0022] According to some example embodiments, the second scan driver is configured to sequentially output the second scan signal after the first scanner and the second scanner output the first scan signal and the third scan signal in the first mode.

[0023] According to some example embodiments, in the first mode, a pulse width of each of the first scan signal and the third scan signal is greater than a pulse width of each of the second scan signals.

[0024] According to some example embodiments, the first pixel region is adjacent to a first horizontal line of the second pixel region, and the third pixel region is adjacent to a last horizontal line of the second pixel region.

[0025] According to some example embodiments, the display device further includes a data driver configured to supply data signals to data lines connected to the first pixel, the second pixel, and the third pixel.

[0026] According to some example embodiments, the display device further includes a memory configured to store a first dummy data signal corresponding to an image displayed on a first horizontal line of the second pixel area during a previous frame in the first mode, and a second dummy data signal corresponding to an image displayed on a last horizontal line of the second pixel area.

[0027] According to some example embodiments, the data driver is configured to supply a first dummy data signal to the first pixel and a second dummy data signal to the third pixel in a first mode.

[0028] According to some example embodiments, the display device further includes: a first emission driver including a third multiplexer, the first emission driver configured to operate in response to the first mode and the second mode, and configured to supply the first emission signal to the first emission line connected to the first pixel; a second emission driver configured to supply the second emission signal to the second emission line connected to the second pixel; and a third emission driver including a fourth multiplexer, the third emission driver configured to operate in response to the first mode and the second mode, and configured to supply the third emission signal to the third emission line connected to the third pixel.

[0029] According to some example embodiments, the first transmit driver further includes first transmit stages respectively connected to the first transmit lines, and the first transmit stages are configured to receive the output signal from the third multiplexer.

[0030] According to some example embodiments, the third emission driver further includes third emission stages respectively connected to the third emission lines, and the third emission stages are configured to receive the output signal from the fourth multiplexer.

[0031] According to some example embodiments, each of the third multiplexer and the fourth multiplexer includes a first switch configured to be turned on in the first mode and a second switch configured to be turned on in the second mode.

[0032] According to some example embodiments, a second switch of a first one of the third multiplexers is configured to receive a third enable signal, and second switches of the remaining third multiplexers are configured to receive an output signal from a first transmitting stage located in a previous horizontal line.

[0033] According to some example embodiments, a first switch of a last one of the third multiplexers is configured to receive the fourth start signal, and first switches of the remaining third multiplexers are configured to receive the third sub start signal.

[0034] According to some example embodiments, the third sub start signal is simultaneously supplied to the first emission stage in the first mode.

[0035] According to some example embodiments, in the first mode, the first transmission signals are simultaneously supplied to the first transmission lines located in odd-numbered horizontal lines, and the first transmission signals are simultaneously supplied to the first transmission lines located in even-numbered horizontal lines.

[0036] According to some example embodiments, the first switch of the fourth multiplexer is configured to receive the fourth sub start signal, and the second switch of the fourth multiplexer is configured to receive the output signal from the emission stage located in the previous horizontal line.

[0037] According to some example embodiments, the fourth sub start signal is simultaneously supplied to the third emission stage in the first mode.

[0038] According to some example embodiments, in the first mode, the third emission signals are simultaneously supplied to the third emission lines located in odd-numbered horizontal lines, and the third emission signals are simultaneously supplied to the third emission lines located in even-numbered horizontal lines.

[0039] According to some example embodiments, the first emission driver, the second emission driver, and the third scan driver are configured to cause the first pixel region, the second pixel region, and the third pixel region to sequentially emit light during a single frame period in the second mode.

[0040] According to some example embodiments, the first emission driver, the second emission driver, and the third emission driver are configured to cause the second pixel region to emit light after the first pixel region and the third pixel region emit light during a single frame period in a first mode.

[0041] According to some example embodiments, in a first mode, during a current frame, each horizontal line of a first pixel region is configured to display the same image as an image displayed on a first horizontal line of a second pixel region during a previous frame.

[0042] According to some example embodiments, in the first mode, during a current frame, each horizontal line of the third pixel region is configured to display the same image as an image displayed on a last horizontal line of the second pixel region during a previous frame.

[0043] According to some example embodiments, when the display device is mounted on the wearable device, the display device is set to the first mode, and when the display device is not mounted on the wearable device, the display device is set to the second mode. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Aspects of some example embodiments are described below with reference to the accompanying drawings. However, the present system and method should not be understood as being limited to these embodiments. Instead, these embodiments are provided to facilitate understanding by those of ordinary skill in the art.

[0045] In the accompanying drawings, the dimensions of the drawings may be exaggerated for clarity. It should be understood that when an element is referred to as being "between" two elements, it may be the only element between the two elements, or one or more intermediate elements may also be present, unless otherwise indicated. Throughout the text, the same reference numerals refer to the same elements.

[0046] Figures 1A to 1C is a schematic diagram illustrating example embodiments of a display device connected to a wearable device according to some example embodiments of the present invention.

[0047] Figure 2 is a schematic diagram illustrating a substrate provided in the display device shown in FIG. 1 according to some example embodiments of the present invention.

[0048] Figure 3 is a schematic diagram illustrating an example configuration of a display device according to some example embodiments of the present invention.

[0049] Figure 4 is a diagram illustrating some example embodiments according to the present invention Figure 3 Schematic diagram of an embodiment of a pixel is shown in FIG.

[0050] Figure 5 is a diagram illustrating some example embodiments according to the present invention Figure 3 Schematic diagram of the configuration of the scan driver shown in .

[0051] Figure 6 is a diagram illustrating a driving operation when a display device is driven in a second mode according to some example embodiments of the present invention. Figure 5 The waveform diagram of the scanning level method is shown in FIG.

[0052] Figure 7 are schematic diagrams illustrating image display methods according to some example embodiments of the present invention.

[0053] Figure 8 is a diagram illustrating a method of driving a display device in a first mode according to some example embodiments of the present invention. Figure 5 The waveform diagram of the scanning level method is shown in FIG.

[0054] Fig. 9 2 is a detailed view illustrating a configuration of a display device according to some example embodiments of the present invention.

[0055] Fig.10 is a diagram illustrating some example embodiments according to the present invention Fig. 9 Schematic diagram of an embodiment of a first pixel is shown in FIG.

[0056] Fig.11 is a diagram illustrating some example embodiments according to the present invention Fig.10 A schematic diagram of an embodiment of a method for driving a pixel is shown in FIG.

[0057] Fig.12 is a diagram illustrating some example embodiments according to the present invention Fig. 9 A schematic diagram of the configuration of the transmit driver is shown in FIG.

[0058] Fig.13 and Fig.14 is a diagram illustrating a method of driving a display device in a first mode according to some example embodiments of the present invention. Fig. 9 and Fig.11 The waveform diagram of the transmit driver is shown in .

[0059] Fig.15 are schematic diagrams illustrating display devices according to some example embodiments of the present invention. DETAILED DESCRIPTION

[0060] Although some aspects of some exemplary embodiments of the present invention are described with reference to the accompanying drawings, it should be understood that various changes and modifications can be made in the present invention without departing from its spirit and scope. Further, it should be understood that the present invention is not limited to its specific embodiments, and various changes, equivalents and substitutions can be made without departing from the scope and spirit of the present invention.

[0061] Throughout the accompanying drawings, the same reference numerals designate the same elements. In the accompanying drawings, the size of the elements may be exaggerated for clarity of the present invention. Although the terms "first", "second", etc. are used to describe various elements in this article, these elements should not be limited to these terms. These terms are only used to distinguish one element from another element. For example, the first element may be designated as the second element without departing from the scope of the present invention. Similarly, the second element may be designated as the first element. Further, the singular form "one" includes multiple indicators unless the context clearly indicates otherwise.

[0062] Hereinafter, a display device according to some example embodiments will be described in more detail with reference to the accompanying drawings.

[0063] Figures 1A to 1C is a schematic diagram illustrating a display device 10 mounted on a wearable device 30 according to some example embodiments of the present invention.

[0064] Reference Figures 1A to 1C , the wearable device 30 may be a head-mounted device and include a frame 31. A strap 32 may be connected to the frame 31. The user may wear the frame 31 using the strap 32. The display device 10 may be detachable from the frame 31. The display device 10 mounted on the wearable device 30 may be, for example, a smart phone. However, the display device 10 according to an example embodiment of the present invention is not limited to a smart phone. For example, the display device 10 may include any suitable electronic device having a display unit, such as a tablet PC, an e-book reader, a computer, a workstation, a personal digital assistant (PDA), a portable multimedia player (PMP), a camera, and the like.

[0065] According to some example embodiments, when the display device 10 is mounted on the frame 31 , the connection portion 41 of the display device 10 and the connection portion 33 of the frame 31 may be electrically connected to each other so that communication may be established between the frame 31 and the display device 10 .

[0066] In order to control the display device 10 mounted on the frame 31, the wearable device 30 may include at least one of a touch sensor, a button, and a wheel key.

[0067] When the display device 10 is mounted on the wearable device 30, the display device 10 may be operated as a head mounted display (HMD) device. In other words, when the display device 10 is mounted on the wearable device 30, the display device 10 may be driven in a first mode (e.g., virtual reality (VR) or augmented reality (AR) mode). When the display device 10 is separated from the wearable device 30, the display device 10 may be driven in a second mode (e.g., normal mode).

[0068] When the display device 10 is mounted on the wearable device 30, the driving mode of the display device 10 can be switched to the first mode automatically or in response to user input or setting adjustment. In addition, when the display device 10 is separated from the wearable device 30, the driving mode of the display device 10 can be switched to the second mode automatically or in response to user input or setting adjustment.

[0069] The wearable device 30 may include a lens 20 corresponding to the user's eyes. The lens 20 may be configured as a fisheye lens or a wide-angle lens to expand the user's field of view (FOV).

[0070] When the display device 10 is fixed to the frame 31, the user can see the display unit of the display device 10 through the lens 20. Therefore, the user can perceive that they are viewing an image on a large-sized screen at a predetermined distance.

[0071] Reference Figure 1C , when the wearable device 30 is mounted on the display device 10, a portion of the display area may be blocked by the frame 31 in order to provide a more vivid image to the user.

[0072] A portion of the entire display area of ​​the display device 10 corresponding to the first mode viewed by the user is called a viewing area VDA. The other portion of the entire display area of ​​the display device 10 driven in the first mode that the user cannot view is called a non-viewing area VNDA.

[0073] A central portion of the display area corresponding to the position of the lens 20 may be a viewing area VDA, and the remaining portion may be a non-viewing area VNDA.

[0074] When the display device 10 is driven in the first mode, a valid image may be displayed on the viewing area VDA, no image may be displayed on the non-viewing area VNDA, or a dummy image may be displayed on the non-viewing area VNDA.

[0075] On the other hand, when the display device 10 is driven in the second mode, the user can view the entire display area. Therefore, an effective image can be displayed over the entire display area.

[0076] According to an embodiment, various forms of images may be displayed when the display device 10 is used in combination with the wearable device 30. However, as described above, since effective images are displayed on different areas depending on the first mode and the second mode, when the driving mode of the display device 10 is switched, the boundary between the viewing area and the non-viewing area may be visible to the user.

[0077] Therefore, when an image is displayed on a display device 10 mounted on the wearable device 30, the boundary between the viewing area and the non-viewing area may not be visible or perceptible to the user.

[0078] Figure 2 is a schematic diagram illustrating a pixel area of ​​a display device 10 according to some example embodiments.

[0079] Reference Figure 2 According to some example embodiments, the substrate 110 may include pixel areas AA1, AA2, and AA3. The substrate may further include a peripheral area NA outside the occupied spaces of the pixel areas AA1, AA2, and AA3 or surrounding the pixel areas AA1, AA2, and AA3.

[0080] A plurality of pixels PXL1, PXL2, and PXL3 may be located in pixel areas AA1, AA2, and AA3, respectively. A predetermined image may be displayed on the pixel areas AA1, AA2, and AA3. Therefore, the pixel areas AA1, AA2, and AA3 may be collectively referred to as a display area.

[0081] Components (eg, wires) for driving the pixels PXL1, PXL2, and PXL3 may be located in the peripheral area NA. Since the pixels PXL1, PXL2, and PXL3 do not exist in the peripheral area NA, the peripheral area NA may be referred to as a non-display area.

[0082] For example, the peripheral area NA may be provided outside the pixel areas AA1 , AA2 , and AA3 , and surround at least a portion of the pixel areas AA1 , AA2 , and AA3 .

[0083] The pixel areas AA1 , AA2 , and AA3 may include a first pixel area AA1 , a second pixel area AA2 located at one side of the first pixel area AA1 , and a third pixel area AA3 located at one side of the second pixel area AA2 .

[0084] The second pixel area AA2 may be located between the first pixel area AA1 and the third pixel area AA3 , and may have a larger area than the first pixel area AA1 and the third pixel area AA3 .

[0085] The second pixel area AA2 may be Figure 1C The first pixel area AA1 and the third pixel area AA3 may correspond to the viewing area VDA shown in FIG.

[0086] In other words, when the display device 10 is driven in the first mode, the user may not be able to see the images displayed on the first pixel area AA1 and the third pixel area AA3 , and can only see the image displayed on the second pixel area AA2 .

[0087] On the other hand, when the display device 10 is driven in the second mode, the user may view images displayed on the first pixel area AA1 , the second pixel area AA2 , and the third pixel area AA3 .

[0088] The pixels PXL1 , PXL2 , and PXL3 may include a first pixel PXL1 , a second pixel PXL2 , and a third pixel PXL3 .

[0089] For example, the first pixel PXL1 may be located in the first pixel area AA1, the second pixel PXL2 may be located in the second pixel area AA2, and the third pixel PXL3 may be located in the third pixel area AA3.

[0090] Each of the pixels PXL1, PXL2, and PXL3 may emit light at a brightness (eg, a predetermined brightness) in response to control of each driver. Each of the pixels PXL1, PXL2, and PXL3 may include an emission device (eg, an organic light emitting diode).

[0091] Figure 2 The first pixel area AA1, the second pixel area AA2, and the third pixel area AA3 are shown to have the same width. However, example embodiments of the present invention are not limited thereto. For example, according to some example embodiments, the first pixel area AA1 and / or the third pixel area AA3 may gradually decrease in width away from the second pixel area AA2. Accordingly, the first pixel area AA1 and / or the third pixel area AA3 may have a smaller width than the second pixel area AA2. The first pixel area AA1 and / or the third pixel area AA3 may include a plurality of first pixel areas and / or third pixel areas arranged in a vertical direction or a horizontal direction.

[0092] The substrate 110 may have various forms so that the above-mentioned pixel areas AA1, AA2, and AA3 may be provided thereon. The substrate 110 may include an insulating material such as glass or resin. In addition, the substrate 110 may include a material having flexibility so that the substrate 110 may be bendable or foldable. The substrate 110 may have a single-layer structure or a multi-layer structure.

[0093] Figure 3 1 is a schematic diagram illustrating a configuration of a display device 10 according to some example embodiments of the present invention. Figure 3The display device 10 may include pixels PXL1 , PXL2 , and PXL3 and a display driver. The display driver may include a first scan driver 211 , a second scan driver 212 , a third scan driver 213 , a data driver 230 , a memory 240 , and a timing controller 250 .

[0094] The first pixel PXL1 may be located in a first pixel area AA1 divided by the first scan lines S11 to S1j and the data lines D1 to Dm. When a scan signal is supplied from the first scan lines S11 to S1j, the first pixel PXL1 may receive a data signal from the data lines D1 to Dm. Each of the first pixels PXL1 receiving the data signal may control the amount of current flowing from the first power source ELVDD to the second voltage source ELVSS via the organic light emitting diode. The organic light emitting diode of each of the first pixels PXL1 may generate light of a brightness corresponding to the amount of current.

[0095] The second pixel PXL2 may be located in a second pixel area AA2 divided by the second scan lines S21 to S2n and the data lines D1 to Dm. When a scan signal is provided from the second scan lines S21 to S2n, the second pixel PXL2 may receive a data signal from the data lines D1 to Dm. Each of the second pixels PXL2 receiving the data signal may control the amount of current flowing from the first power source ELVDD to the second voltage source ELVSS via the organic light emitting diode. The organic light emitting diode of each of the second pixels PXL2 may generate light having a brightness level corresponding to the amount of current.

[0096] The third pixel PXL3 may be located in a third pixel area AA3 divided by the third scan lines S31 to S3k and the data lines D1 to Dm. When the scan signal is supplied from the third scan lines S31 to S3k, the third pixel PXL3 may receive a data signal from the data lines D1 to Dm. Each of the third pixels PXL3 receiving the data signal may control the amount of current flowing from the first power source ELVDD to the second power source ELVSS through the organic light emitting diode. The organic light emitting diode of each of the third pixels PXL3 may generate light of brightness corresponding to the amount of current.

[0097] When the display device 10 is driven in the second mode, a valid image can be displayed on the first pixel area AA1, the second pixel area AA2, and the third pixel area AA3. In other words, the user can see the image displayed on the first pixel area AA1, the second pixel area AA2, and the third pixel area AA3.

[0098] When the display device 10 is driven in the first mode, a valid image can be displayed on the second pixel area AA2, and the first pixel area AA1 and the third pixel area AA3 can be covered by the frame 31 of the wearable device 30.

[0099] When the display device 10 is driven in the first mode, the first pixel area AA1 and the third pixel area AA3 may be blocked from displaying an image because the first pixel area AA1 and the third pixel area AA3 are not visible to a user.

[0100] The scan signals may not be provided to the first and third scan lines S11 to S1j and S31 to S3k respectively connected to the first and third pixels PXL1 and PXL3, and the separated data signals may not be supplied to the first and third pixels PXL1 and PXL3.

[0101] However, when the second pixel PXL2 is driven, if the first and third pixels PXL1 and PXL3 are not driven, characteristics of driving transistors included in the first and third pixels PXL1 and PXL3 may be different from characteristics of driving transistors included in the second pixel PXL2 .

[0102] As a result, when the driving mode is switched from the first mode to the second mode, a brightness deviation may occur between the second pixel area AA2 and the first and third pixel areas AA1 and AA3 due to characteristic deviations between the driving transistors included in the pixel areas AA1, AA2, and AA3. In addition, a boundary between the first pixel area AA1 and the second pixel area AA2 and a boundary between the second pixel area AA2 and the third pixel area AA3 may be visible to a user.

[0103] However, according to some example embodiments of the present invention, when the display device 10 is driven in the first mode, the first pixel PXL1 and the third pixel PXL3 can be driven by supplying a scan signal and a data signal (e.g., a dummy data signal) to the first pixel PXL1 and the third pixel PXL3, so that the visible boundary due to the characteristic deviation of the driving transistor can be prevented.

[0104] The first scan driver 211 may supply a scan signal to the first scan lines S11 to S1j in response to the first scan control signals (CLK1, CLK2, MCS1, MCS2, VFLM1, FLM1, and FLM2) from the timing controller 250. For example, the first scan driver 211 may sequentially supply the first scan signal to the first scan lines S11 to S1j. When the first scan signal is sequentially supplied to the first scan lines S11 to S1j, the first pixels PXL1 may be sequentially selected in units of horizontal lines.

[0105] In addition, the first scan driver 211 can simultaneously supply the first scan signal to the first scan lines S11 to S1j. For example, the first scan signal can be simultaneously supplied to the odd-numbered first scan lines S11, S13, S15, ..., and at the same time, the first scan signal can be simultaneously supplied to the even-numbered first scan lines S12, S14, S16, ...

[0106] The second scan driver 212 may supply the scan signal to the second scan lines S21 to S2n in response to the second scan control signal (CLK1 and CLK2) from the timing controller 250. For example, the second scan driver 212 may sequentially supply the second scan signal to the second scan lines S21 to S2n. When the second scan signal is sequentially supplied to the second scan lines S21 to S2n, the second pixels PXL2 may be sequentially selected in units of horizontal lines.

[0107] The third scan driver 213 may supply scan signals to the third scan lines S31 to S3 k in response to the third scan control signals ( CLK1 , CLK2 , MCS1 , MCS2 , and VFLM2 ) from the timing controller 250 .

[0108] For example, the third scan driver 213 may sequentially supply the third scan signal to the third scan lines S31 to S3k. When the third scan signal is sequentially supplied to the third scan lines S31 to S3k, the third pixels PXL3 may be sequentially selected in units of horizontal lines.

[0109] In addition, the third scan driver 213 can simultaneously supply the third scan signal to the third scan lines S31 to S3k. For example, the third scan signal can be simultaneously supplied to the odd third scan lines S31, S33, S35, ..., and the third scan signal can be simultaneously supplied to the even third scan lines S32, S34, S36, ...

[0110] The first scanning signal, the second scanning signal, and the third scanning signal may be set to a voltage that turns on the corresponding transistor. As far as the entire display device 10 is concerned, when the display device 10 is driven in the second mode, the first pixel PXL1 may be sequentially selected in units of horizontal lines, then the second pixel PXL2 may be sequentially selected in units of horizontal lines, and finally, the third pixel PXL3 may be sequentially selected in units of horizontal lines. In addition, when the display device 10 is driven in the first mode, the first pixel PXL1 in the odd horizontal lines may be selected at the same time, the first pixel PXL1 in the even horizontal lines may be selected at the same time, the third pixel PXL3 in the odd horizontal lines may be selected at the same time, and the third pixel PXL3 located in the even horizontal lines may be selected at the same time. Finally, the second pixel PXL2 may be sequentially selected in units of horizontal lines.

[0111] According to some example embodiments, the display driver may further include a memory 240. According to some example embodiments, when the display device 10 is driven in the first mode, the memory 240 may store dummy data signals to be supplied to the first and third pixels PXL1 and PXL3.

[0112] For example, the memory 240 may store a data signal supplied to a second pixel adjacent to the first pixel area AA1 among the second pixels PXL2 (e.g., the second pixel PXL2 connected to the first second scan line S21) during the previous frame as a first dummy data signal. The first dummy data signal may be supplied to the first pixel PXL1 in the current frame in the first mode.

[0113] In addition, the data signal supplied to the second pixel adjacent to the third pixel area AA3 among the second pixels PXL2 (e.g., the second pixel PXL2 connected to the last second scan line S2n) may be stored as a second dummy data signal in the memory 240. The second dummy data signal may be supplied to the third pixel PXL3 in the current frame in the first mode.

[0114] The data driver 230 may supply data signals to the data lines D1 to Dm in response to the data control signal DCS. The data signals supplied to the data lines D1 to Dm may be supplied to the pixels PXL1, PXL2, and PXL3 selected by the scan signal. The timing controller 250 may supply scan control signals generated based on externally supplied timing signals to the scan drivers 211, 212, and 213.

[0115] The first scan control signal may include switch control signals MCS1 and MCS2, clock signals CLK1 and CLK2, start signals FLM1 and FLM2, and a first sub start signal VFLM1. The first start signal FLM1 and the first sub start signal VFLM1 may be supplied to control the supply timing of the first scan signal, and the clock signals CLK1 and CLK2 may be supplied to shift the first start signal FLM1. In addition, the switch control signals MCS1 and MCS2 may be supplied to determine an output signal of a multiplexer to be described below.

[0116] The second scan control signal may include clock signals CLK1 and CLK2. The clock signals CLK1 and CLK2 may be used to shift the last scan signal SS1j of the first scan driver. The third scan control signal may include switch control signals MCS1 and MCS2, clock signals CLK1 and CLK2, and a second sub-start signal VFLM2. The second sub-start signal VFLM2 may be applied to control the supply timing of the third scan signal, and the switch control signals MCS1 and MCS2 may be applied to determine the output signal of the multiplexer to be described below.

[0117] The timing controller 250 may supply a data control signal DCS to the data driver 230. In addition, the timing controller 250 may convert external input image data into image data DATA that meets the specifications of the data driver 230. The data control signal DCS may include a source start signal, a source output enable signal, and a source sampling clock. The source start signal may be supplied to control the data sampling start point of the data driver 230. The source sampling clock may control the sampling operation of the data driver 230 based on a rising edge or a falling edge. The source output enable signal may control the output timing of the data driver 230.

[0118] Figure 3 The scan drivers 211, 212 and 213, the data driver 230, the memory 240 and the timing controller 250 are shown as separate components. However, according to some example embodiments, at least some of the components may be incorporated into the same component. In addition, the scan drivers 211, 212 and 213, the data driver 230, the memory 240 and the timing controller 250 may be provided by various methods, such as chip on glass, chip on plastic, tape package, and chip on film.

[0119] Figure 4 yes Figure 3 For ease of explanation, Figure 4 The diagram is connected to Figure 3 The first pixel PXL1 of the j-th first scan line S1j and the m-th data line Dm shown in FIG. Figure 4 , the first pixel PXL1 may include a pixel circuit PC connected to the organic light emitting diode OLED, the mth data line Dm, and the jth first scan line S1j and configured to control the organic light emitting diode OLED. An anode of the organic light emitting diode OLED may be connected to the pixel circuit PC, and a cathode of the organic light emitting diode OLED may be connected to the second power source ELVSS.

[0120] The organic light emitting diode OLED may generate light (e.g., of a predetermined brightness) in response to a current supplied from the pixel circuit PC. When a scan signal is supplied to the j-th first scan line S1j, the pixel circuit PC may store a data signal supplied to the m-th data line Dm, and control the amount of current flowing to the organic light emitting diode OLED in response to the stored data signal. For example, the pixel circuit PC may include a first transistor M1, a second transistor M2, and a storage capacitor Cst.

[0121] The first transistor M1 may be connected between the mth data line Dm and the second transistor M2. For example, the first transistor M1 may have a gate electrode connected to the jth first scan line S1j, a first electrode connected to the mth data line Dm, and a second electrode connected to the gate electrode of the second transistor M2. When a scan signal is supplied from the jth first scan line S1j, the first transistor M1 may be turned on and supply the data signal from the mth data line Dm to the storage capacitor Cst. The storage capacitor Cst may be charged with a voltage corresponding to the data signal. The second transistor M2 may be connected between the first power source ELVDD and the organic light emitting diode OLED.

[0122] For example, the second transistor M2 may have a gate electrode connected to the first electrode of the storage capacitor Cst and the second electrode of the first transistor M1, a first electrode connected to the second electrode of the storage capacitor Cst and the first power source ELVDD, and a second electrode connected to the anode of the organic light emitting diode OLED.

[0123] The second transistor M2 may be a driving transistor and controls the amount of current flowing from the first power source ELVDD to the second power source ELVSS via the organic light emitting diode OLED in response to the voltage value stored in the storage capacitor Cst. The organic light emitting diode OLED may generate light corresponding to the amount of current supplied from the second transistor M2.

[0124] The first electrode of each of the transistors M1 and M2 may be set as one of the source electrode and the drain electrode, and the second electrode of each of the transistors M1 and M2 may be set as the other electrode. For example, when the first electrode is set as the source electrode, the second electrode may be set as the drain electrode. Figure 4 As shown in FIG. 1 , for example, transistors M1 and M2 may be PMOS transistors. According to another embodiment, transistors M1 and M2 may be NMOS transistors.

[0125] Figure 4 The structure of the pixel shown in the embodiment may correspond to the embodiment. The first pixel PXL1 of the present invention is not limited to the above pixel structure. The first pixel PXL1 may have a circuit configuration so that current can be supplied to the organic light emitting diode OLED. Any of various configurations currently known in the art may be used as the circuit configuration of the first pixel PXL1.

[0126] The first power source ELVDD may be a high potential power source, and the second power source ELVSS may be a low potential power source. For example, the first power source ELVDD may be set to a positive voltage, and the second power source ELVSS may be set to a negative voltage or a ground voltage.

[0127] Each of the second pixel PXL2 and the third pixel PXL3 may have the same (or substantially the same) circuit configuration as the first pixel PXL1. Therefore, a repetitive description of the second pixel PXL2 and the third pixel PXL3 will be omitted.

[0128] Figure 5 It is a graphic Figure 3 Schematic diagram of the configuration of the first scan driver, the second scan driver and the third scan driver shown in FIG. For ease of explanation, Figure 5 The diagram shows three scanning stages SST11, SST12, and SST1j included in the first scanning driver 211, two scanning stages SST21 and SST2n included in the second scanning driver 212, and two scanning stages SST31 and SST3k included in the third scanning driver 213. Figure 5 , the first scan driver 211 may include a plurality of scan stages SST11 to SST1j and a first multiplexer 217a. The scan stages SST11 to SST1j of the first scan driver 211 may be connected to ends of the first scan lines S11 to S1j and supply first scan signals to the first scan lines S11 to S1j, respectively. In addition, the first multiplexer 217a may be connected to the scan stages SST11 to SST1j of the first scan driver 211, respectively.

[0129] According to an embodiment, the first multiplexer 217a may include a first switch TR1 and a second switch TR2. Each of the first switch TR1 and the second switch TR2 may be formed of a transistor. A gate electrode of the first switch TR1 may be connected to the first switch control line 510, a first electrode of the first switch TR1 may be connected to the first sub-start signal line 530 or the second start signal line, and a second electrode of the first switch TR1 may be connected to the scanning stages SST11 to SST1j.

[0130] For example, the first electrode of the first switch TR1 connected to each of the first to j-1th scanning stages SST11 to SST1j-1 may be connected to the first sub-start signal line 530, and the first electrode of the first switch TR1 connected to the last scanning stage SST1j may be connected to the second start signal line.

[0131] A gate electrode of the second switch TR2 may be connected to the second switch control line 520, a first electrode of the second switch TR2 may be connected to a start signal line or a scan line connected to a scan stage of a previous stage, and a second electrode of the second switch TR2 may be connected to each of the scan stages SST11 to SST1j.

[0132] The scan stages SST11 to SST1j of the first scan driver 211 may operate in response to a first switch control signal MCS1 supplied through the first switch control line 510 and a second switch control signal MCS2 supplied through the second switch control line 520. For example, when the display device 10 is driven in the second mode, the first switch TR1 may be turned off and the second switch TR2 may be turned on in response to the first switch control signal MCS1 and the second switch control signal MCS2.

[0133] In other words, the first first scanning stage SST11 can supply the first scanning signal to the first first scanning line S11 in response to the first start signal FLM1, and the second first scanning stage SST12 can supply the first scanning signal to the second first scanning line S12 in response to the output signal from the first first scanning stage SST11 (the first scanning signal supplied to the first first scanning line S11).

[0134] On the other hand, when the display device 10 is driven in the first mode, the first switch TR1 may be turned on and the second switch TR2 may be turned off by the first switch control signal MCS1 and the second switch control signal MCS2 , respectively.

[0135] In other words, the scanning stages SST11 to SST1j-1 of the first scanning driver 211 may supply the scanning signals to the first scanning lines S11 to S1j-1 in response to the first sub-starting signal VFLM1. The last scanning stage SST1j may supply the scanning signals in response to the second start-up signal FLM2. The scanning stages SST11 to SST1j may have the same circuit structure.

[0136] Subsequently, the second scan driver 212 may include a plurality of scan stages SST21 to SST2n. Each of the scan stages SST21 to SST2n of the second scan driver 212 may be connected to one end of each of the second scan lines S21 to S2n and supply a second scan signal to each of the second scan lines S21 to S2n.

[0137] Each of the scanning stages SST21 to SST2n can receive an output signal (i.e., a scanning signal) of a previous scanning stage. For example, the first scanning stage SST21 can receive an output signal from the last scanning stage SST1j of the first scanning driver 211, and the last scanning stage SST2n can receive an output signal from the n-1th scanning stage SST2n-1.

[0138] The scanning stages SST21 to SST2n may be configured by the same circuit. In addition, the scanning stages SST11 to SST1j of the first scanning driver 211 and the scanning stages SST21 to SST2n of the second scanning driver 212 may be configured by the same circuit.

[0139] The third scan driver 213 may include a plurality of scan stages SST31 to SST3k and a second multiplexer 217b. Each of the scan stages SST31 to SST3k of the third scan driver 213 may be connected to one end of each of the third scan lines S31 to S3k and supply a third scan signal to each of the third scan lines S31 to S3k.

[0140] In addition, each of the second multiplexers 217b may be connected to each of the scan stages SST31 to SST3k of the third scan driver 213. The second multiplexer 217b may include a first switch TR1 and a second switch TR2. Each of the first switch TR1 and the second switch TR2 may include a transistor.

[0141] A gate electrode of the first switch TR1 may be connected to the first switching control line 510 , a first electrode of the first switch TR1 may be connected to the second sub start signal line 540 , and a second electrode of the first switch TR1 may be connected to each of the scan stages SST31 to SST3 k.

[0142] A gate electrode of the second switch TR2 may be connected to the second switching control line 520 , a first electrode of the second switch TR2 may be connected to a scan line connected to a previous scan stage, and a second electrode of the second switch TR2 may be connected to each of the scan stages SST31 to SST3 k.

[0143] The scan stages SST31 to SST3 k of the third scan driver 213 may operate in response to the first switching control signal MCS1 supplied through the first switching control line 510 and the second switching control signal MCS2 supplied through the second switching control line 520 .

[0144] For example, when the display device 10 is driven in the second mode, the first switch TR1 may be turned off and the second switch TR2 may be turned on in response to the first switch control signal MCS1 and the second switch control signal MCS2 , respectively.

[0145] In other words, the first third scanning stage SST31 may supply the third scan signal to the first third scan line S31 in response to the scan signal output from the last second scanning stage SST2n. The second third scanning stage SST32 may supply the third scan signal to the second third scan line S32 in response to the output signal (the third scan signal supplied to the third scan line S31) from the first third scanning stage SST31.

[0146] On the other hand, when the display device 10 is driven in the first mode, the first switch TR1 can be turned on and the second switch TR2 can be turned off by the first switch control signal MCS1 and the second switch control signal MCS2, respectively. In other words, the scan stages SST31 to SST3k of the third scan driver 213 can supply scan signals to the third scan lines S31 to S3k in response to the second sub-start signal VFLM2.

[0147] The scanning stages SST31 to SST3k may have the same circuit structure. In addition, the scanning stages SST11 to SST1j of the first scan driver 211 and the scanning stages SST31 to SST3k of the third scan driver 213 may have the same circuit structure.

[0148] According to an embodiment, Figure 5 As shown in , the switches TR1 and TR2 may be formed of PMOS transistors. However, according to another embodiment, the switches TR1 and TR2 may be formed of NMOS transistors. Each of the scanning stages SST11 to SST1j, SST21 to SST2n, and SST31 to SST3k may receive a first clock signal CLK1 and a second clock signal CKL2.

[0149] The first clock signal CLK1 and the second clock signal CLK2 may have the same period and non-overlapping phases. For example, when the display device 10 is driven in the second mode, if a scan signal is supplied to a single scan line during one horizontal period 1H, each of the clock signals CLK1 and CLK2 may have a period corresponding to 2H. In addition, the clock signals CLK1 and CLK2 may be supplied during different horizontal periods.

[0150] Figure 6 is a diagram showing the driving of the display device 10 in the second mode. Figure 5 The waveform diagram of the scanning level method is shown in FIG. Figure 6 , the first clock signal CLK1 and the second clock signal CLK2 may each have a period of two horizontal periods 2H and be supplied during the horizontal period. In other words, the second clock signal CLK2 may be set to shift the first clock signal CLK1 by half a period (i.e., one horizontal period). Each of the first clock signal CLK1 and the second clock signal CLK2 may be set to a first width w1.

[0151] When the display device 10 is driven in the second mode, the first switch control signal MCS1 having a high level may be supplied to the first switch control line 510, and the second switch control signal MCS2 having a low level may be supplied to the second switch control line 520. Therefore, all the first switches TR1 of the first multiplexer 217a may be turned off and all the second switches TR2 of the multiplexer 217a may be turned on.

[0152] In other words, the first start signal FLM1 may be supplied to the first scanning stage SST11 of the first scanning driver 211 , and an output signal from a previous scanning stage may be supplied to the remaining scanning stages ( SST12 to SST1j , SST21 to SST2n , and SST31 to SST3k ).

[0153] The first scanning stage SST11 may receive the first start signal FLM1 and output the second clock signal CLK2 overlapping the first start signal FLM1 as the scan signal SS11 through the first scan line S11. Subsequently, the second scanning stage SST12 may receive the scan signal SS11 outputted from the first scanning stage SST11.

[0154] The second scanning stage SST12 may output the first clock signal CLK1 adjacent to the scanning signal SS11 as the scanning signal SS12 through the second first scanning line S12. According to an embodiment, the scanning stages SST11 to SST1j, SST21 to SST2n, and SST31 to SST3k may repeat the above process and sequentially output the scanning signals to the remaining scanning lines (S13 to S1j, S21 to S2n, and S31 to S3k) until the third scanning signal SS3k is output from the last scanning stage SST3k.

[0155] Since each of the first clock signal CLK1 and the second clock signal CLK2 has the first width w1, each of the scanning signals SS11 to SS3k may have the first width w1. In other words, when the display device 10 is driven in the second mode, the first clock signal CLK1 and the second clock signal CLK2 supplied to the scanning stages SST11 to SST1j, SST21 to SST2n, and SST31 to SST3k and the scanning signals SS11 to SS3k output from the scanning stages SST11 to SST1j, SST21 to SST2n, and SST31 to SST3k may have the first width w1.

[0156] According to some example embodiments, among the scanning stages SST11 to SST1j, SST21 to SST2n, and SST31 to SST3k, the scanning signals output from the odd-numbered scanning stages SST11, SST13, SST15, ... may overlap with the second clock signal CLK2. In addition, the scanning signals output from the even-numbered scanning stages SST12, SST14, SST16, ... may overlap with the first clock signal CLK1.

[0157] However, the exemplary embodiments of the present invention are not limited thereto. According to the configuration of the scanning stages SST11 to SST1j, SST21 to SST2n, and SST31 to SST3k, the scanning signals output from the odd scanning stages SST11, SST13, SST15, ... may overlap with the first clock signal CLK1, and the scanning signals output from the even scanning stages SST12, SST14, SST16, ... may overlap with the second clock signal CLK2.

[0158] Figure 7 is a schematic diagram illustrating an image display method according to an embodiment. Figure 7 , each frame may include a first subframe period FS1 and a second subframe period FS2. During the first subframe period FS1, an image may not be displayed or an image corresponding to dummy data may be displayed. During the second subframe period FS2, a valid image corresponding to valid data may be displayed. When the display device 10 is driven in the second mode, during the second subframe period FS2, a scan signal may be supplied to the pixels PXL1, PXL2, and PXL3 through the first first scan line S11 to the last third scan line S3k.

[0159] When the display device 10 is driven in the first mode, during the second subframe period FS2, the scan signal may be supplied to the second pixel PXL2 through the first second scan line S21 to the last second scan line S2n. In addition, during the first subframe period FS1, the scan signal may be supplied to the first pixel PXL1 through the first first scan line S11 to the last first scan line S1j, and the scan signal may be supplied to the third pixel PXL3 through the first third scan line S31 to the last third scan line S3k.

[0160] When the scan signal is supplied to the first pixel PXL1 through the first to last first scan lines S11 to S1j, the data signal supplied to the pixel PXL2 connected to the first second scan line during the previous frame may be supplied to the first pixel PXL1.

[0161] For example, during the first subframe period FS1 of the i-th frame, the data signal supplied to the pixel PXL2 connected to the first second scan line of the (i-1)-th frame is supplied to the first pixel PXL1.

[0162] In addition, when the scan signal is supplied to the third pixel PXL3 through the first third scan line S31 to the last third scan line S3k, the data signal supplied to the pixel PXL2 connected to the last second scan line S2n during the previous frame can be supplied to the third pixel PXL3. For example, during the first subframe period FS1 of the i-th frame, the data signal supplied to the pixel PXL2 connected to the last second scan line S2n of the (i-1)-th frame can be supplied to the third pixel PXL3.

[0163] like Figure 7 As illustrated in FIG. 1 , the first subframe period FS1 and the second subframe period FS2 may be sequentially arranged in a single frame. However, example embodiments of the present invention are not limited thereto. The order in which the first subframe period FS1 and the second subframe period FS2 are arranged may be changed.

[0164] Figure 8 is a diagram showing the driving of the display device 10 in the first mode. Figure 5 The waveform diagram of the scanning level method is shown in FIG. Figure 8 , the first clock signal CLK1 and the second clock signal CLK2 may have a period longer than two horizontal periods 2H and may not overlap with each other.

[0165] For example, the first clock signal CLK1 and the second clock signal CLK2 may have a cycle of six horizontal periods 6H, and the second clock signal CLK2 may shift the first clock signal CLK1 by half a cycle (i.e., three horizontal periods). When the display device 10 is driven in the first mode, the first clock signal CLK1 and the second clock signal CLK2 supplied to the first scanning stage and the third scanning stage may be set to a second width w2 greater than the first width w1.

[0166] When the display device 10 is driven in the first mode, the first switch control signal MCS1 having a low level may be supplied to the first switch control line 510, and the second switch control signal MCS2 having a high level may be supplied to the second switch control line 520. Therefore, all the first switches TR1 of the first multiplexer 217a may be turned on and all the second switches TR2 of the first multiplexer 217a may be turned off. When the first switch control signal MCS1 having a low level is supplied, the first sub start signal VFLM1 and the second sub start signal VFLM2 may be sequentially supplied.

[0167] Each of the first and second sub-starting signals VFLM1 and VFLM2 may maintain a low level during each or more cycles of the first and second clock signals CLK1 and CLK2. For example, each of the first and second sub-starting signals VFLM1 and VFLM2 may maintain a low level during six or more horizontal periods.

[0168] First, the first sub-start signal VFLM1 may be simultaneously supplied to the scanning stages SST11 to SST1j of the first scanning driver 211. When the first sub-start signal VFLM1 is supplied to the scanning stages SST11 to SST1j of the first scanning driver 211, the odd-numbered scanning stages SST11, SST13, SST15, ... may output the second clock signal CLK2 overlapping the first sub-start signal VFLM1 as a scanning signal.

[0169] Therefore, if Figure 8 As shown in , the first and third first scan signals SS11 and SS13 may be supplied simultaneously. When scan signals are supplied to scan lines S11, S13, S15, . . . corresponding to odd-numbered horizontal lines, dummy data may be supplied from the data driver 230 to the first pixel area AA1.

[0170] The dummy data supplied to the first pixel area AA1 may be data previously supplied to the pixel PXL2 located in the first horizontal line of the second pixel area AA2 during the previous frame. Subsequently, the even-numbered scanning stages SST12, SST14, SST16, ... may supply the first clock signal CLK1 adjacent to the first sub-start signal VFLM1 as a scanning signal. Therefore, as Figure 8 As shown in FIG. 1 , the second first scan signal SS12 and the fourth first scan signal SS14 may be supplied simultaneously.

[0171] When the scan signal is supplied to the scan lines S12, S14, S16, ... corresponding to the even-numbered horizontal lines, the dummy data from the data driver 230 may be supplied to the first pixel area AA1. The dummy data may be the same as the dummy data supplied to the pixel PXL1 located in the odd-numbered horizontal lines. In other words, the data supplied to the pixel PXL2 located in the first horizontal line of the second pixel area AA2 during the previous frame may be supplied to the pixel PXL1 located in the even-numbered horizontal lines.

[0172] After the first sub start signal VFLM1 is supplied, the second sub start signal VFLM2 may be simultaneously supplied to the scanning stages SST31 to SST3k of the third scan driver 213. When the second sub start signal VFLM2 is supplied to the scanning stages SST31 to SST3k of the third scan driver 213, the odd-numbered scanning stages SST31, SST33, SST35, ... may output the second clock signal CLK2 overlapping the second sub start signal VFLM2 as a scan signal.

[0173] Therefore, if Figure 8 As shown in , the first third scan signal SS31 and the third third scan signal SS33 may be supplied simultaneously. When the scan signals are supplied to the scan lines S31, S33, S35, ... corresponding to the odd horizontal lines, dummy data may be supplied to the third pixel area AA3 from the data driver 230. The dummy data supplied to the third pixel area AA3 may be data previously supplied to the pixel PXL2 located in the last horizontal line of the second pixel area AA2 during the previous frame.

[0174] Then, each of the even-numbered scanning stages SST32, SST34, SST36, . . . may output the first clock signal CLK1 adjacent to the second sub-start signal VFLM2 as a scanning signal. Figure 8 As shown in , the second third scan signal SS32 and the fourth third scan signal SS34 may be supplied simultaneously.

[0175] When scan signals corresponding to scan lines S32, S34, S36, ... corresponding to even horizontal lines are supplied, dummy data may be supplied to the third pixel area AA3 from the data driver 230. The dummy data may be the same as the dummy data supplied to the pixels PXL3 located in odd horizontal lines.

[0176] In other words, data supplied to the pixels PXL2 located in the last horizontal line of the second pixel area AA2 during the previous frame may be supplied to the pixels PXL3 located in the even-numbered horizontal lines.

[0177] When the display device 10 is driven in the first mode, the first clock signal CLK1 and the second clock signal CLK2 supplied to the first scanning stages SST11 to SST1j and the third scanning stages SST31 to SST3k may have a second width w2. Therefore, each of the first scanning signals SS11 to SS1j-1 and the third scanning signals SS31 to SS3k may also have a second width w2.

[0178] In other words, by controlling the width of each of the first scan signals SS11 to SS1j-1 and the third scan signals SS31 to SS3k, the brightness of the dummy image displayed on the first pixel area AA1 and the third pixel area AA3 may be controlled.

[0179] After the third scan signals SS31 to SS3k are output, the width of each of the first clock signal CLK1 and the second clock signal CLK2 may be changed from the second width w2 to a third width w3 that is smaller than the second width w2. Therefore, the second scan signal may have the third width w3. The second start signal FLM2 may be supplied to the last scan stage SST1j of the first scan driver 211 instead of the first sub start signal VFLM1. The last scan stage SST1j of the first scan driver 211 may generate and output a scan signal S1j corresponding to the second start signal FLM2, and the first stage circuit SST21 of the second scan driver 212 may generate a scan signal corresponding to the scan signal S1j output from the last scan stage SST1j of the first scan driver 211.

[0180] The second start signal FLM2 may be output after the scan signal is supplied to the third scan lines S31 to S3k. In other words, the second scan driver 212 may be started to be driven after each of the first scan driver 211 and the third scan driver 213 is stopped from being driven. The second scan driver 212 may sequentially supply the scan signal to the second scan lines S21 to S2n.

[0181] As described above, when the display device 10 is driven in the first mode, the first sub start signal VFLM1 and the second sub start signal VFLM2 may not overlap each other in order to supply different dummy data to the first pixel area AA1 and the third pixel area AA3 , respectively. However, the present invention is not limited thereto.

[0182] When the display device 10 is driven in the first mode, the same dummy data may be supplied to the first pixel area AA1 and the third pixel area AA3 because they are not viewed by the user frame by frame. The first sub start signal VFLM1 and the second sub start signal VFLM2 may be supplied simultaneously.

[0183] Fig. 9 is a detailed view illustrating a configuration of a display device 10' according to some example embodiments of the present invention. Fig. 9 A display device 10' according to another embodiment will be described. Figure 3 Some repetitive descriptions of the same components as those of the display device 10 shown in FIG. 1 and the same components as those of the display device 10′ will be omitted. Figure 3The components of the display device 10 shown in FIG. 1 are different components.

[0184] Reference Fig. 9 , the display device 10' may include pixels PXL1', PXL2' and PXL3' and a display driver. The display driver may include a first scan driver 211, a second scan driver 212, a third scan driver 213, a first emission driver 311, a second emission driver 312, a third emission driver 313, a data driver 230, a memory 240 and a timing controller 250. The first pixel PXL1' may be located in a first pixel area AA1 divided by first scan lines S11 to S1j, first emission lines E11 to E1j and data lines D1 to Dm. The second pixel PXL2' may be located in a second pixel area AA2 divided by second scan lines S21 to S2n, second emission lines E21 to E2n and data lines D1 to Dm. The third pixel PXL3' may be located in a third pixel area AA3 divided by third scan lines S31 to S3k, third emission lines E31 to E3k and data lines D1 to Dm. The first emission driver 311 may supply the first emission signals to the first emission lines E11 to E1 j in response to the first emission control signals ( CLK3 , CLK4 , MCS3 , MCS4 , VFLM3 , FLM3 , and FLM4 ) from the timing controller 250 .

[0185] For example, in the second mode, the first transmit driver 311 may sequentially supply the first transmit signal to the first transmit lines E11 to E1j. In addition, in the first mode, the first transmit driver 311 may simultaneously supply the first transmit signal to the first transmit lines E11 to E1j. For example, the first transmit driver 311 may supply the first transmit signal to the odd-numbered first transmit lines E11, E13, E15, ..., and may supply the first transmit signal to the even-numbered first transmit lines E12, E14, E16, ...

[0186] These emission signals may be supplied to control the emission time of the first pixel PXL1'. The first emission signal may be set to have a greater width than the scan signal. The second emission driver 312 may supply the second emission signal to the second emission lines E21 to E2n in response to the second emission control signal (CLK3 and CLK4) from the timing controller 250.

[0187] For example, in the first mode and the second mode, the second emission driver 312 may sequentially supply the second emission signal to the second emission lines E21 to E2n. The second emission signal may be set to control the emission time of the second pixel PXL2'. The second emission signal may be set to have a greater width than the scan signal. The third emission driver 313 may supply the third emission signal to the third emission lines E31 to E3k.

[0188] For example, in the second mode, the third emission driver 313 may sequentially supply the third emission signals to the third emission lines E31 to E3 k in response to the third emission control signals ( CLK3 , CLK4 , MCS3 , MCS4 , and VFLM4 ) from the timing controller 250 .

[0189] In addition, in the first mode, the third emission driver 313 can simultaneously supply the third emission signal to the plurality of third emission lines E31 to E3k. For example, the third emission driver 313 can simultaneously supply the third emission signal to the odd third emission lines E31, E33, E35, ..., and can simultaneously supply the third emission signal to the even third emission lines E32, E34, E36, ...

[0190] A third emission signal may be supplied to control the emission time of the third pixel PXL3'. The emission signal may be set to have a width greater than that of the scan signal. The first to third emission signals may be set to a gate-off voltage (e.g., a high voltage) so that the transistors included in the pixels PXL1', PXL2', and PXL3' may be turned off. The scan signal may be set to a gate-on voltage (e.g., a low voltage) so that the transistors included in the pixels PXL1', PXL2', and PXL3' may be turned on.

[0191] When the display device 10 is driven in the first mode, the first pixels PXL1 ′ located in odd-numbered horizontal lines may emit light at the same time, and the first pixels PXL1 ′ located in even-numbered horizontal lines may emit light at the same time.

[0192] Subsequently, the third pixels PXL3' located in odd-numbered horizontal lines may emit light at the same time, and the third pixels PXL3' located in even-numbered horizontal lines may emit light at the same time. Subsequently, the second pixels PXL2' may sequentially emit light in units of horizontal lines.

[0193] On the other hand, when the display device 10 is driven in the second mode, the first pixel PXL1 ′ may start emitting light in units of horizontal lines; then, the second pixel PXL2 ′ may start emitting light in units of horizontal lines; and finally, the third pixel PXL3 ′ may start emitting light in units of horizontal lines.

[0194] The timing controller 250 may supply emission control signals generated based on externally supplied timing signals to the emission drivers 311, 312, and 313. The first emission control signals may include switch control signals MCS3 and MCS4, clock signals CLK3 and CLK4, start signals FLM3 and FLM4, and a third sub start signal VFLM3.

[0195] The third start signal FLM3 and the third sub start signal VFLM3 may be supplied to control the supply timing of the first emission signal, and the clock signals CLK3 and CLK4 may be used to shift the third start signal FLM3. In addition, the switch control signals MCS3 and MCS4 may be used to determine the output signal of the multiplexer to be described below.

[0196] The second emission control signal may include clock signals CLK3 and CLK4. The clock signals CLK3 and CLK4 may be used to shift the last emission signal E1j of the first emission driver 311. The third emission control signal may include switch control signals MCS3 and MCS4, clock signals CLK3 and CLK4, and a fourth sub start signal VFLM4.

[0197] The fourth sub start signal VFLM4 may be supplied to control the supply timing of the third emission signal, and the switch control signals MCS3 and MCS4 may be supplied to determine an output signal of a multiplexer to be described below.

[0198] Fig.10 It is a graphic Fig. 9 Schematic diagram of an embodiment of a first pixel PXL1' is shown in FIG. Fig.10 As shown in , the first pixel PXL1' may be connected to the jth first scan line S1j and the mth data line Dm. Fig.10 According to an embodiment, the first pixel PXL1 ′ may include an organic light emitting diode OLED, first to seventh transistors T1 to T7 , and a storage capacitor Cst.

[0199] The anode of the organic light emitting diode OLED may be connected to the first transistor T1 through the sixth transistor T6, and the cathode of the organic light emitting diode OLED may be connected to the second power source ELVSS. The organic light emitting diode OLED may generate light of a predetermined brightness in response to the amount of current supplied from the first transistor T1.

[0200] The first power source ELVDD may be set to a voltage higher than the second power source ELVSS so that current may flow through the organic light emitting diode OLED.

[0201] The seventh transistor T7 may be connected between the initialization power supply Vint and the anode of the organic light emitting diode OLED. In addition, the gate electrode of the seventh transistor T7 may be connected to the j-th first scan line S1j. When the scan signal is supplied to the j-th first scan line S1j, the seventh transistor T7 may be turned on, and the voltage of the initialization power supply Vint may be supplied to the anode of the organic light emitting diode OLED. The initialization power supply Vint may be set to a voltage lower than the data signal.

[0202] The sixth transistor T6 may be connected between the first transistor T1 and the organic light emitting diode OLED. A gate electrode of the sixth transistor T6 may be connected to the jth first emission line E1j. When an emission control signal is supplied to the jth first emission line E1j, the sixth transistor T6 may be turned off; and otherwise, the sixth transistor T6 may be turned on.

[0203] The fifth transistor T5 may be connected between the first power source ELVDD and the first transistor T1. In addition, the gate electrode of the fifth transistor T5 may be connected to the j-th first emission line E1j. When the emission control signal is supplied to the j-th first emission line E1j, the fifth transistor T5 may be turned off; and otherwise, the fifth transistor T5 may be turned on.

[0204] A first electrode of the first transistor T1 (driving transistor) may be connected to the first power source ELVDD through the fifth transistor T5, and a second electrode of the first transistor T1 may be connected to the anode of the organic light emitting diode OLED through the sixth transistor T6. A gate electrode of the first transistor T1 may be connected to the first node N1. The first transistor T1 may control the amount of current flowing from the first power source ELVDD through the organic light emitting diode OLED to the second power source ELVSS in response to a voltage of the first node N1.

[0205] The third transistor T3 may be connected to the second electrode of the first transistor T1 and the first node N1. The gate electrode of the third transistor T3 may be connected to the j-th first scan line S1j. When the scan signal is supplied to the j-th first scan line S1j, the third transistor T3 may be turned on and may electrically connect the second electrode of the first transistor T1 and the first node N1. Therefore, when the third transistor T3 is turned on, the first transistor T1 may be connected in a diode form.

[0206] The fourth transistor T4 may be connected between the first node N1 and the initialization power supply Vint. In addition, the gate electrode of the fourth transistor T4 may be connected to the j-1th first scan line S1j-1. When the scan signal is supplied to the j-1th first scan line S1j-1, the fourth transistor T4 may be turned on and the voltage of the initialization power supply Vint may be supplied to the first node N1.

[0207] The second transistor T2 may be connected between the mth data line Dm and the first electrode of the first transistor T1. In addition, the gate electrode of the second transistor T2 may be connected to the jth first scan line S1j. When a scan signal is supplied to the jth first scan line S1j, the second transistor T2 may be turned on and may electrically connect the mth data line Dm to the first electrode of the first transistor T1.

[0208] The storage capacitor Cst may be connected between the first power source ELVDD and the first node N1. The storage capacitor Cst may store a voltage corresponding to the data signal and a threshold voltage of the first transistor T1.

[0209] although Fig.10 The pixel structure shown in corresponds to an embodiment of the present invention, but the first pixel PXL1' is not limited thereto. The first pixel PXL1' may have any one of various circuit configurations currently known in the art as its circuit configuration, so that the first pixel PXL1' can supply current to the organic light emitting diode OLED.

[0210] The first power source ELVDD may be a high potential power source, and the second power source ELVSS may be a low potential power source. For example, the first power source ELVDD may be set to a positive voltage and the second power source ELVSS may be set to a negative voltage or a ground voltage.

[0211] Each of the second pixel PXL2 ′ and the third pixel PXL3 ′ to be described below may be configured by the same circuit as the first pixel PXL1 ′. Therefore, a detailed description of the second pixel PXL2 ′ and the third pixel PXL3 ′ will be omitted.

[0212] because Fig. 9 The configuration and function of the scan driver shown in are the same as those of the above-described scan driver, so the configuration and function of the emission driver will be described below.

[0213] Fig.11 It is a graphic driver Fig.10 Schematic diagram of the method of the pixel PXL1 'as shown in FIG. Fig.11 , the emission signal may be supplied to the emission line Ej. When the emission signal is supplied to the emission line Ej, the fifth transistor T5 and the sixth transistor T6 may be turned off. Therefore, the pixel PXL1 ′ may be set to a non-emission state.

[0214] Subsequently, a scan signal may be supplied to the j-1th scan line Sj-1 to turn on the fourth transistor T4. When the fourth transistor T4 is turned on, the voltage of the initialization power supply Vint may be supplied to the first node N1 so that the first node N1 may be initialized to the voltage of the initialization power supply Vint.

[0215] After the first node N1 is initialized to the voltage of the initialization power source Vint, the scan signal may be supplied to the j-th scan line Sj. When the scan signal is supplied to the j-th scan line Sj, the second transistor T2, the third transistor T3, and the seventh transistor T7 may be turned on.

[0216] When the seventh transistor T7 is turned on, the voltage of the initialization power source Vint may be supplied to the anode of the organic light emitting diode OLED. Therefore, the parasitic capacitor parasitically formed in the organic light emitting diode OLED may be discharged, so that the black expression capability may be improved.

[0217] For example, the parasitic capacitor of the organic light emitting diode OLED may be charged with a predetermined voltage in response to the current supplied during the previous frame. When a black grayscale is displayed during the current frame, the organic light emitting diode OLED may have to maintain a non-emitting state. When the parasitic capacitor of the organic light emitting diode OLED remains charged, the organic light emitting diode OLED may emit light slightly by the leakage current of the first transistor T1.

[0218] On the other hand, when the parasitic capacitor of the organic light emitting diode OLED is discharged, the leakage current of the first transistor T1 may precharge the parasitic capacitor of the organic light emitting diode OLED, and thus, the organic light emitting diode OLED may maintain a non-emission state.

[0219] When the third transistor T3 is turned on, the first transistor T1 may be connected in a diode form. When the second transistor T2 is turned on, the data signal from the data line Dm may be supplied to the first electrode of the first transistor T1. Because the first node N1 is initialized to a voltage lower than the initialization power supply Vint of the data signal, the first transistor T1 may be turned on. When the first transistor T1 is turned on, a voltage obtained by subtracting the threshold voltage of the first transistor T1 from the data signal may be supplied to the first node N1. The storage capacitor Cst may store a voltage corresponding to the data signal applied to the first node N1 and the threshold voltage of the first transistor T1.

[0220] After storing a voltage corresponding to the data signal applied to the first node N1 and the threshold voltage of the first transistor T1 in the storage capacitor Cst, the supply of the emission signal to the emission line Ej may be stopped. When the supply of the emission signal to the emission line Ej is stopped, the fifth transistor T5 and the sixth transistor T6 may be turned on. As a result, a current path may be formed from the first power source ELVDD through the fifth transistor T5, the first transistor T1, the sixth transistor T6, and the organic light emitting diode OELD to the second power source ELVSS.

[0221] The first transistor T1 may control the amount of current flowing from the first power source ELVDD to the second power source ELVSS through the organic light emitting diode OLED in response to the voltage of the first node N1. The organic light emitting diode OLED may generate light of predetermined brightness in response to the amount of current supplied from the first transistor T1.

[0222] The emission signal supplied to the emission line Ej may be supplied to overlap with at least one scanning signal so that when the data signal is charged into each of the pixels PXL1', PXL2' and PXL3', each of the pixels PXL1', PXL2' and PXL3' may be set to a non-emission state. The timing of supplying the emission signal may be set by various methods currently known in the art.

[0223] Fig.12 is a diagram illustrating some example embodiments according to the present invention Fig. 9 For ease of explanation, Fig.12 The illustration shows three first emission stages (EST11, EST12, and EST1j) included in the first emission driver 311, two second emission stages EST21 and EST2n included in the second emission driver 312, and third emission stages EST31 and EST3k included in the third emission driver 313.

[0224] Reference Fig.12 , the first transmission driver 311 may include a plurality of transmission stages EST11 to EST1j and a third multiplexer 219a. Each of the transmission stages EST11 to EST1j of the first transmission driver 311 may be connected to one end of each of the first transmission lines E11 to E1j and supply a first transmission signal to each of the first transmission lines E11 to E1j.

[0225] In addition, each of the third multiplexers 219a may be connected to each of the emission stages EST11 to EST1j of the first emission driver 311. According to an embodiment, the third multiplexer 219a may include a first switch TR1 and a second switch TR2. Each of the first switch TR1 and the second switch TR2 may be composed of a transistor.

[0226] A gate electrode of the first switch TR1 may be connected to the third switching control line 515 , a first electrode of the first switch TR1 may be connected to the third sub start signal line 535 or the fourth start signal line, and a second electrode of the first switch TR1 may be connected to each of the emitter stages EST11 to EST1j.

[0227] For example, the first electrode of the first switch TR1 connected to each of the first to j-1th emitter stages EST11 to EST1j-1 can be connected to the third sub-start signal line 535, and the first electrode of the first switch TR1 connected to the last emitter stage EST1j can be connected to the fourth start signal line.

[0228] A gate electrode of the second switch TR2 can be connected to the fourth switch control line 525, a first electrode of the second switch TR2 can be connected to the third start signal line or the first emission line connected to the previous emission stage, and a second electrode of the second switch TR2 can be connected to each of the emission stages EST11 to EST1j.

[0229] The emission stages ETS11 to EST1 j of the first emission driver 311 may operate in response to the third switching control signal MCS3 supplied through the third switching control line 515 and the fourth switching control signal MSC4 supplied through the fourth switching control line 525 .

[0230] For example, when the display device 10 is driven in the second mode, the first switch TR1 may be turned off and the second switch TR2 may be turned on by the third switch control signal MCS3 and the fourth switch control signal MCS4 .

[0231] In other words, the first first emission stage EST11 may supply the first emission signal to the first first emission line E11 in response to the third start signal FLM3. The second first emission stage EST12 may supply the first emission signal to the second first emission line E12 in response to the output signal (the first emission signal supplied to the first emission line E11) from the first first emission stage EST11.

[0232] On the other hand, when the display device 10 is driven in the first mode, the first switch TR1 may be turned on and the second switch TR2 may be turned off by the third switch control signal MCS3 and the fourth switch control signal MCS4 , respectively.

[0233] In other words, the emission stages EST11 to EST1j-1 of the first emission driver 311 may supply emission signals to the first emission lines E11 to E1j-1 in response to the third sub start signal VFLM3. The last emission stage EST1j may supply an emission signal in response to the fourth start signal FLM4.

[0234] Each of the transmitting stages EST11 to EST1j may be constituted by the same circuit. The second transmitting driver 312 may include a plurality of transmitting stages EST21 to EST2n.

[0235] The second emission stages EST21 to EST2n of the second emission driver 312 may be connected to respective ends of the second emission lines E21 to E2n and supply second emission signals to the second emission lines E21 to E2n, respectively.

[0236] Each of the second emission stages EST21 to EST2n can receive an output signal (i.e., an emission signal) of a previous emission stage. For example, the first emission stage EST211 can receive an output signal from the last emission stage EST1j of the first emission driver 311, and the last emission stage EST2n can receive an output signal of the n-1th emission stage EST2n-1.

[0237] Each of the second emission stages EST21 to EST2n may have the same circuit. In addition, each of the emission stages EST11 to EST1j of the first emission driver 311 and the emission stages EST21 to EST2n of the second emission driver 312 may be configured by the same circuit.

[0238] The third emission driver 313 may include a plurality of emission stages EST31 to EST3k and a fourth multiplexer 219b. The third emission stages EST31 to EST3k of the third emission driver 313 may be connected to respective ends of the third emission lines E31 to E3k and supply third emission signals to the third emission lines E31 to E3k, respectively.

[0239] In addition, each of the fourth multiplexers 219b may be connected to each of the emission stages EST31 to EST3k of the third emission driver 313. The fourth multiplexer 219b may include a first switch TR1 and a second switch TR2. Each of the first switch TR1 and the second switch TR2 may be composed of a transistor.

[0240] A gate electrode of the first switch TR1 may be connected to the third switching control line 515 , a first electrode of the first switch TR1 may be connected to the fourth sub start signal line 545 , and a second electrode of the first switch TR1 may be connected to each of the emission stages EST31 to EST3 k.

[0241] A gate electrode of the second switch TR2 may be connected to the fourth switch control line 525 , a first electrode of the second switch TR2 may be connected to an emission line connected to a previous emission stage, and a second electrode of the second switch TR2 may be connected to each of the emission stages EST31 to EST3k.

[0242] The third emission stages EST31 to EST3k of the third emission driver 313 may operate in response to the third switch control signal MCS3 supplied through the third switch control line 515 and the fourth switch control signal MCS4 supplied through the fourth switch control line 525. For example, when the display device 10 is driven in the second mode, the first switch TR1 may be turned off and the second switch TR2 may be turned on by the third switch control signal MCS3 and the fourth switch control signal MCS4.

[0243] In other words, the first third emission stage EST31 may supply the third emission signal to the first third emission line E31 in response to the emission signal output from the last second emission stage EST2n. The second third emission stage EST32 may supply the third emission signal to the second third emission line E32 in response to the output signal from the first third emission stage EST31 (the third emission signal supplied to the first third emission line E31).

[0244] On the other hand, when the display device 10 is driven in the first mode, the first switch TR1 may be turned on and the second switch TR2 may be turned off by the third and fourth switch control signals MCS3 and MCS4 .

[0245] In other words, the emission stages EST31 to EST3j of the third emission driver 313 may supply emission signals to the third emission lines E31 to E3j in response to the fourth sub-start signal VFLM4. Each of the emission stages EST31 to EST3k may be composed of the same circuit. In addition, each of the first emission stages EST11 to EST1j of the first emission driver 311 and the third emission stages EST31 to EST3k of the third emission driver 313 may include the same circuit.

[0246] like Figure 5 As illustrated in , the switches TR1 and TR2 may include PMOS transistors. However, according to another embodiment, the switches TR1 and TR2 may include NMOS transistors. Each of the transmitting stages EST11 to EST1j, EST21 to EST2n, and EST31 to EST3k may receive the third clock signal CLK3 and the fourth clock signal CLK4.

[0247] The third clock signal CLK3 and the fourth clock signal CLK4 may have the same period and non-overlapping phases. The period of each of the third clock signal CLK3 and the fourth clock signal CLK4 may be longer than the period of each of the first clock signal CLK1 and the second clock signal CLK2. For example, each of the third clock signal CLK3 and the fourth clock signal CLK4 may have a period corresponding to 4 horizontal periods (4H).

[0248] Fig.13 is a diagram showing when the display device is driven in the first mode Fig. 9 and Fig.11 The waveform diagram of the transmit driver method is shown in FIG. Fig.13 , each of the third clock signal CLK3 and the fourth clock signal CLK4 may have a period corresponding to four horizontal periods 4H, and the fourth clock signal CLK4 may be set to a signal shifted from the third clock signal CLK3 by half a period (i.e., 2 horizontal periods). In other words, the third clock signal CLK3 and the fourth clock signal CLK4 may have a longer period than the first clock signal CLK1 and the second clock signal CLK2.

[0249] When the display device 10 is driven in the first mode, the third switching control signal MCS3 having a low level may be supplied to the third switching control line 515 , and the fourth switching control signal MCS4 having a high level may be supplied to the fourth switching control line 525 .

[0250] Therefore, all first switches TR1 of the multiplexer 219a may be turned on and all second switches TR2 of the multiplexer 219a may be turned off. When the third switch control signal MCS3 having a low level is supplied, the third and fourth sub start signals VFLM3 and VFLM4 may be sequentially supplied.

[0251] Each of the third and fourth sub-starting signals VFLM3 and VFLM4 may maintain a low level during each or more cycles of the third and fourth clock signals CLK3 and CLK4. First, the third sub-starting signal VFLM3 may be simultaneously supplied to the emission stages EST11 to EST1j of the first emission driver 311.

[0252] When the third sub start signal VFLM3 is supplied to the emission stages EST11 to EST1j of the first emission driver 311, supply of the emission signal EO1 output from the odd-numbered emission stages EST11, EST13, EST15, . . . may be stopped because the emission signal EO1 is synchronized with the fourth clock signal CLK4.

[0253] Fig. 9 The scan drivers 211, 212 and 213 shown in FIG. 1 may have the same Figures 5 to 8 Therefore, when the display device is driven in the first mode, scan signals may be simultaneously supplied to the odd-numbered first scan lines S11, S13, S15, ..., and dummy data may be supplied to the first pixel area AA1.

[0254] After the dummy data is supplied to the first pixel area AA1, supply of the emission signal EO1 outputted from the odd-numbered emission stages EST11, EST13, EST15, ... may be stopped. Therefore, the first pixels PXL1' located in the odd-numbered horizontal lines may simultaneously emit light in response to the dummy data.

[0255] Subsequently, the supply of the transmission signal EE1 output from the even-numbered transmission stages EST12, EST14, EST16, . . . may be stopped because the transmission signal EE1 is synchronized with the third clock signal CLK3.

[0256] When the display device 10 is driven in the first mode, the scan signals may be simultaneously supplied to the even-numbered first scan lines S12, S14, S16, ..., and the dummy data may be supplied to the first pixel area AA1. Subsequently, the supply of the emission signal EE1 output from the even-numbered emission stages EST12, EST14, EST16, ... may be stopped. Therefore, the first pixels PXL1' located in the even-numbered horizontal lines may simultaneously emit light in response to the dummy data.

[0257] After the third sub start signal VFLM3 is supplied, the fourth sub start signal VFLM4 may be supplied to the emission stages EST31 to EST3k of the third emission driver 313. When the fourth sub start signal VFLM4 is supplied to the emission stages EST31 to EST3k of the third emission driver 313, the supply of the emission signal EO3 output from the odd-numbered emission stages EST31, EST33, EST35, ... may be stopped because the emission signal EO3 is synchronized with the fourth clock signal CLK4.

[0258] because Fig. 9 The scan drivers 211, 212 and 213 shown in FIG. 1 have the same Figures 5 to 8 The scan drivers 211 , 212 and 213 are configured identically, so when the display device 10 is driven in the first mode, scan signals can be simultaneously supplied to the odd third scan lines S31 , S33 , S35 , . . . , and dummy data can be supplied to the third pixel area AA3 .

[0259] After the dummy data is supplied to the third pixel area AA3, supply of the emission signal EO3 outputted from the odd emission stages EST31, EST33, EST35, ... may be stopped. Therefore, the third pixels PXL3' located in the odd horizontal lines may simultaneously emit light in response to the dummy data.

[0260] Subsequently, supply of the emission signal EE3 output from the even-numbered emission stages EST32, EST34, EST36, ... may be stopped because the emission signal EE3 is synchronized with the clock signal CLK3. When the display device 10 is driven in the first mode, the scan signal may be supplied to the even-numbered third scan lines S32, S34, S36, ..., and dummy data may be supplied to the third pixel area AA3.

[0261] Subsequently, supply of the emission signal EE3 output from the even-numbered emission stages EST32, EST34, EST36, ... may be stopped. The third pixels PXL3' located in the even-numbered horizontal lines may simultaneously emit light in response to the dummy data.

[0262] The fourth start signal FLM4 instead of the third sub start signal VFLM3 may be supplied to the last emission stage EST1j of the first emission driver 311. The last emission stage EST1j of the first emission driver 311 may generate and output an emission signal E1j corresponding to the fourth start signal FLM4. The first emission stage EST21 of the second emission driver 312 may generate an emission signal in response to the emission signal E1j output from the last emission stage EST1j of the first emission driver 311.

[0263] After the emission signal is supplied to the third emission lines E31 to E3k, the fourth start signal FLM4 may be output. In other words, the second pixel PXL2' may emit light after the first pixel PXL1' and the third pixel PXL3' emit light. The second emission driver 312 may sequentially supply the emission signal to the second emission lines E21 to E2n.

[0264] Fig.14 is a waveform diagram illustrating a method of driving an emission driver according to another embodiment when a display device is driven in a first mode according to some example embodiments of the present invention. Fig.14 , when the display device is driven in the first mode, the third switch control signal MCS3 having a low level may be supplied to the third switch control line 515 , and the fourth switch control signal MCS4 having a high level may be supplied to the fourth switch control line 525 .

[0265] Therefore, all the first switches TR1 of the multiplexer 219a may be turned on and all the second switches TR2 of the multiplexer 219a may be turned off. When the third switch control signal MCS3 having a low level is supplied, the third sub start signal VFLM3' and the fourth sub start signal VFLM4' may not be supplied. For example, each of the third sub start signal VFLM3' and the fourth sub start signal VFLM4' may have a high level.

[0266] When the third sub-start signal VFLM3' having a high level is supplied to the emission stages EST11 to EST1j of the first emission driver 311, the emission signal EO1' output from each of the odd-numbered emission stages EST11, EST13, EST15,... and the emission signal EE1' output from each of the even-numbered emission stages EST12, EST14, EST16,... can each have a high level.

[0267] In other words, because the emission signal continues to be output, so that the first pixel PXL1 ′ may be set to a non-emission state, the first pixel PXL1 ′ may not emit light although the dummy data is supplied to the first pixel PXL1 ′.

[0268] In addition, when the fourth sub-start signal VFLM4' having a high level is supplied to the emission stages EST31 to EST3k of the third emission driver 313, the emission signal EO3' output from each of the odd emission stages EST31, EST33, EST35,... and the emission signal EE3' output from each of the even emission stages EST32, EST34, EST36,... can each have a high level.

[0269] In other words, because the emission signal continues to be output, so that the third pixel PXL3 ′ may be set to a non-emission state, the third pixel PXL3 ′ may not emit light although the dummy data is supplied to the third pixel PXL3 ′.

[0270] Fig.15 is a schematic diagram illustrating a display device 10" according to some example embodiments of the present invention. Fig.15 When describing a display device 10" according to another embodiment, Fig. 9 The same components as those of the display device 10 ′ shown in FIG. 1 are given the same reference numerals, and a detailed description thereof will be omitted.

[0271] Reference Fig.15 The display device 10″ may include pixels PXL1′, PXL2′, and PXL3′ and a display driver. The display driver may include a first scan driver 211 and 211′, a second scan driver 212 and 212′, a third scan driver 213 and 213′, a first emission driver 311 and 311′, a second emission driver 312 and 312′, a third emission driver 313 and 313′, a data driver 230, a memory 240, and a timing controller 250.

[0272] The first scan drivers 211 and 211', the second scan drivers 212 and 212', and the third scan drivers 213 and 213' of the display device 10" may be located at both sides, with the pixels PXL1', PXL2', and PXL3' interposed therebetween.

[0273] Since the configurations and functions of the last emission stage EST1j, the second scan drivers 212 and 212', and the third scan drivers 213 and 213' are the same as those of the above-described scan drivers, a detailed description thereof will be omitted.

[0274] In addition, the first emission drivers 311 and 311', the second emission drivers 312 and 312', and the third emission drivers 313 and 313' may be located at both sides, and the pixels PXL1', PXL2', and PXL3' of the display device 10" are inserted between the first emission drivers 311 and 311', the second emission drivers 312 and 312', and the third emission drivers 313 and 313'.

[0275] Since the configurations and functions of the first emission drivers 311 and 311 ′, the second emission drivers 312 and 312 ′, and the third emission drivers 313 and 313 ′ are the same as those of the above-described emission drivers, a detailed description thereof will be omitted.

[0276] As described above, when the scan driver and the emission driver are connected to both sides of the pixel unit, signal delay can be avoided. According to some example embodiments of the present invention, when the display device is mounted on a wearable device and driven in a first mode, a dummy image can be displayed on a non-viewing area, so that different characteristics between driving transistors located in different areas can be prevented. Therefore, a display device with improved display quality can be provided.

[0277] Although some example embodiments are described herein, these embodiments should not be construed as limiting. It should be appreciated by those skilled in the art that various changes in form and detail may be made without departing from the spirit and scope of the present invention. Further, it will be appreciated by those skilled in the art that the present invention described herein will provide solutions adapted to other tasks and other applications. The applicant intends to cover all of these uses of the present invention by the claims herein, as well as those changes and modifications that may be made to the example embodiments of the present invention herein, selected for the purpose of disclosure, all without departing from the spirit and scope of the present invention. Therefore, the example embodiments of the present invention should be considered in all respects to be illustrative and not restrictive, and the spirit and scope of the present invention are indicated by the appended claims and their equivalents.

Claims

1. An electronic device, comprising: a frame including a first connecting portion; a tether connected to the frame; a display device mounted on the frame and including a second connection portion connected to the first connection portion; as well as a lens, located in the frame, Wherein, the display device comprises: a substrate having a first pixel region, a second pixel region, and a third pixel region, and including a first longer side and a shorter side adjacent to the first longer side; pixels on the substrate, the pixels comprising a first pixel in the first pixel area, a second pixel in the second pixel area, and a third pixel in the third pixel area; a first scan driver configured to simultaneously supply first scan signals to first scan lines connected to the first pixels in a first mode and sequentially supply the first scan signals to the first scan lines in a second mode different from the first mode; a second scan driver configured to sequentially supply a second scan signal to a second scan line connected to the second pixel in the first mode and the second mode; and a third scan driver configured to simultaneously supply a third scan signal to third scan lines connected to the third pixels in the first mode and sequentially supply the third scan signal to the third scan lines in the second mode, wherein the first pixel region, the second pixel region, and the third pixel region are arranged in a direction parallel to the shorter side, the first pixel region is adjacent to the first longer side, and the third pixel region is adjacent to a second longer side of the substrate opposite to the first longer side, The second pixel region is between the first pixel region and the third pixel region, and Wherein, in the first mode, a pulse width of each of the first scan signal and the third scan signal is greater than a pulse width of each of the second scan signals.

2. The electronic device according to claim 1, wherein: The first connection portion and the second connection portion are electrically connected to each other to establish communication between the frame and the display device.

3. The electronic device according to claim 1, wherein: The first pixel region is adjacent to a first horizontal line of the second pixel region, and the third pixel region is adjacent to a last horizontal line of the second pixel region.

4. The electronic device according to claim 1, wherein: At least a portion of the first pixel region and at least a portion of the third pixel region are blocked by the frame.

5. The electronic device according to claim 1, wherein: The first pixel area and the third pixel area are non-viewing areas where an invalid image is displayed.

6. An electronic device comprising: a frame including a first connecting portion; a tether connected to the frame; a display device mounted on the frame and including a second connection portion connected to the first connection portion; as well as a lens, located in the frame, Wherein, the display device comprises: a substrate having a first pixel region, a second pixel region, and a third pixel region, and including a first shorter side and a longer side adjacent to the first shorter side; pixels on the substrate, the pixels comprising a first pixel in the first pixel area, a second pixel in the second pixel area, and a third pixel in the third pixel area; a first scan driver configured to simultaneously supply first scan signals to first scan lines connected to the first pixels in a first mode and sequentially supply the first scan signals to the first scan lines in a second mode different from the first mode; a second scan driver configured to sequentially supply a second scan signal to a second scan line connected to the second pixel in the first mode and the second mode; and a third scan driver configured to simultaneously supply a third scan signal to third scan lines connected to the third pixels in the first mode and sequentially supply the third scan signal to the third scan lines in the second mode, wherein the first pixel region, the second pixel region, and the third pixel region are arranged in a direction parallel to the longer side, the first pixel region is adjacent to the first shorter side, and the third pixel region is adjacent to a second shorter side of the substrate opposite to the first shorter side, The second pixel region is between the first pixel region and the third pixel region, and Wherein, in the first mode, a pulse width of each of the first scan signal and the third scan signal is greater than a pulse width of each of the second scan signals.

7. The electronic device according to claim 6, wherein: The first connection portion and the second connection portion are electrically connected to each other to establish communication between the frame and the display device.

8. The electronic device according to claim 6, wherein: The first pixel region is adjacent to a first horizontal line of the second pixel region, and the third pixel region is adjacent to a last horizontal line of the second pixel region.

9. The electronic device according to claim 6, wherein: At least a portion of the first pixel region and at least a portion of the third pixel region are blocked by the frame.

10. A display device, comprising: a substrate having a first pixel region, a second pixel region, and a third pixel region, and including a first longer side and a shorter side adjacent to the first longer side; pixels on the substrate, the pixels comprising a first pixel in the first pixel area, a second pixel in the second pixel area, and a third pixel in the third pixel area; a first scan driver including a first multiplexer, the first scan driver configured to operate in response to a first mode and a second mode different from the first mode, and configured to simultaneously supply first scan signals to first scan lines connected to the first pixels in the first mode and sequentially supply the first scan signals to the first scan lines in the second mode; a second scan driver configured to sequentially supply a second scan signal to a second scan line connected to the second pixel in the first mode and the second mode; as well as a third scan driver including a second multiplexer, the third scan driver being configured to operate in response to the first mode and the second mode and configured to simultaneously supply third scan signals to third scan lines connected to the third pixels in the first mode and to sequentially supply the third scan signals to the third scan lines in the second mode; wherein the second pixel region is between the first pixel region and the third pixel region, and a size of a viewing area formed by the second pixel region in the first mode is different from a size of a viewing area formed by the first pixel region, the second pixel region, and the third pixel region in the second mode, and In which, in the first mode, during the current frame, the data signal of the first horizontal line in the direction in which the first pixel area, the second pixel area and the third pixel area are sequentially arranged, which was supplied to the second pixel area in the previous frame, will be supplied to at least one horizontal line of the first pixel area.

11. The display device according to claim 10, wherein: The first scan driver, the second scan driver, and the third scan driver are configured to sequentially output the second scan signal after outputting the first scan signal and the third scan signal in the first mode.

12. The display device according to claim 10, further comprising: The data driver is configured to supply data signals to data lines connected to the first pixel, the second pixel, and the third pixel.

13. The display device according to claim 12, further comprising: A memory configured to store first dummy data corresponding to the data signal of the first horizontal line supplied to the second pixel area and second dummy data corresponding to the data signal of the last horizontal line in the direction supplied to the second pixel area in the previous frame of the first mode.

14. The display device according to claim 13, wherein: The data driver is configured to supply the data signal corresponding to the first dummy data to the first pixel and supply the data signal corresponding to the second dummy data to the third pixel in the first mode.

15. A display device, comprising: a substrate having a first pixel region, a second pixel region, and a third pixel region, and including a first longer side and a shorter side adjacent to the first longer side; pixels on the substrate, the pixels comprising a first pixel in the first pixel area, a second pixel in the second pixel area, and a third pixel in the third pixel area; a first scan driver including a first multiplexer, the first scan driver configured to operate in response to a first mode and a second mode different from the first mode, and configured to simultaneously supply first scan signals to first scan lines connected to the first pixels in the first mode and sequentially supply the first scan signals to the first scan lines in the second mode; a second scan driver configured to sequentially supply a second scan signal to a second scan line connected to the second pixel in the first mode and the second mode; as well as a third scan driver including a second multiplexer, the third scan driver being configured to operate in response to the first mode and the second mode and configured to simultaneously supply third scan signals to third scan lines connected to the third pixels in the first mode and to sequentially supply the third scan signals to the third scan lines in the second mode; wherein the second pixel region is between the first pixel region and the third pixel region, and a size of a viewing area formed by the second pixel region in the first mode is different from a size of a viewing area formed by the first pixel region, the second pixel region, and the third pixel region in the second mode, and In which, in the first mode, during the current frame, the data signal of the last horizontal line in the direction in which the first pixel area, the second pixel area and the third pixel area are sequentially arranged, which was supplied to the second pixel area in the previous frame, will be supplied to at least one horizontal line of the third pixel area.

16. The display device according to claim 15, further comprising: The data driver is configured to supply data signals to data lines connected to the first pixel, the second pixel, and the third pixel.

17. The display device according to claim 16, further comprising: A memory configured to store first dummy data corresponding to the data signal of the first horizontal line in the direction supplied to the second pixel area in the previous frame of the first mode and second dummy data corresponding to the data signal of the last horizontal line supplied to the second pixel area.

18. The display device according to claim 17, wherein: The data driver is configured to supply the data signal corresponding to the first dummy data to the first pixel and supply the data signal corresponding to the second dummy data to the third pixel in the first mode.

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