Fpga tile control signal sharing

Abstract

Methods and apparatuses are described that provide FPGA tile-to-tile control signal sharing. In one embodiment, FPGA tile-to-tile multiplexing for control signals is added in a separate tile. In another embodiment, control signal multiplexing is distributed among the FPGA tiles and shared using cascaded configuration.

Description

[0001] Cross-reference to related applications

[0002] This application claims the benefit of U.S. Provisional Patent Application No. 63 / 152,125, filed February 22, 2021, entitled “FPGA INTER-TILE CONTROL SIGNAL SHARING,” which is incorporated herein by reference in its entirety. Technical Field

[0003] The embodiments described herein relate to the field of programmable gate architectures, and in particular, to programmable gate architectures with inter-tile control signal sharing. Background Technology

[0004] Typically, Field Programmable Gate Arrays (FPGAs) are constructed using repeating tiles, each tile comprising one or more Look-Up Tables (LUTs) and one or more Flip-Flops (FFs). Each tile has inputs multiplexed (repeated) by certain wires passing through it. Typically, the signals are divided into two types: data signals that drive the inputs of the LUTs or the data inputs of the FFs, and control signals (e.g., clock enable and preset / reset signals) that drive other inputs of the FFs.

[0005] Each tile has multiplexed data signals and control signals specifically for routing from the general routing lines, as well as "global" routing lines created specifically for routing clock and control signals. Typically, these global routing lines are implemented using a low-resistance metal, meaning their supply is limited.

[0006] In designs implemented on FPGAs, it is common for many fine-faceted fans (FFs) to have similar control signals. For example, the same reset signal can be used for all FFs in a design. Therefore, FPGA architectures typically share control signal input multiplexing across all FFs in a tile. For instance, there may be a total of two clock enable signals that can drive all FFs in a tile, and each FF may have multiplexing for introducing signals from local and global routing. Summary of the Invention

[0007] Methods and apparatus for providing control signal sharing between FPGA tiles are described. Embodiments described herein include an FPGA that shares control signals between tiles. In at least some embodiments, the FPGA device includes a plurality of FPGA tiles and control signal multiplexing circuitry shared among the FPGA tiles in the plurality of FPGA tiles. In at least some embodiments, multiplexing for the control signals is added in individual tiles to avoid multiplexing in each of the FPGA tiles. In another embodiment, the control signal multiplexing circuitry is distributed among FPGA tiles connected together in a cascaded configuration.

[0008] In at least some embodiments, the device includes a memory; and a processor coupled to the memory. The processor is configured to determine the routing of a plurality of FPGA tiles and to determine control signal multiplexing circuitry shared among the FPGA tiles in the plurality of FPGA tiles. In at least some embodiments, the multiplexing for control signals is added in individual tiles to avoid multiplexing in each of the FPGA tiles. In another embodiment, the control signal multiplexing circuitry is distributed among FPGA tiles connected together in a cascaded configuration.

[0009] In at least some embodiments, a non-transitory machine-readable medium is provided. The non-transitory machine-readable medium stores instructions that enable a data processing system to perform operations including: identifying a plurality of FPGA tiles; and identifying control signal multiplexing circuitry shared among the FPGA tiles in the plurality of FPGA tiles. In at least some embodiments, multiplexing for control signals is added to individual tiles to avoid multiplexing in each of the FPGA tiles. In another embodiment, the control signal multiplexing circuitry is distributed among FPGA tiles connected together in a cascaded configuration.

[0010] Other devices, methods, and machine-readable media for providing control signal sharing between FPGA tiles are also described. Attached Figure Description

[0011] Embodiments of this application can be best understood by referring to the following description and accompanying drawings, which illustrate embodiments of this application. In the drawings:

[0012] Figure 1 This is a view of a field-programmable gate array (FPGA) system architecture according to one embodiment.

[0013] Figure 2 This is a view of an FPGA system architecture according to one embodiment, including separate control signal multiplexing tiles configured to share control signals among LB tiles 202.

[0014] Figure 3This is a view of an FPGA system architecture according to another embodiment, including a control signal multiplexing circuit shared among FPGA tiles in multiple FPGA tiles.

[0015] Figure 4 This is a view of an FPGA system architecture according to another embodiment, including a control signal multiplexing circuit shared among FPGA tiles in multiple FPGA tiles.

[0016] Figure 5 This is a flowchart of a method for sharing control signals between FPGA tiles according to one embodiment. Detailed Implementation

[0017] Methods and apparatus for providing inter-FPGA tile control signal sharing are described. Embodiments described herein include FPGAs that share control signals among logic block tiles, thereby reducing the chip area required to provide multiplexing for each logic block tile. In at least some embodiments, the FPGA device includes a plurality of FPGA tiles and control signal multiplexing circuitry shared among the FPGA tiles in the plurality of FPGA tiles. In at least some embodiments, inter-tile multiplexing for control signals is added in separate tiles to avoid having the same multiplexing in each of the FPGA tiles. Separate control signal multiplexing tiles with control signal multiplexing shared among all FPGA tiles in a group are provided. Separate control signal multiplexing tiles as described herein avoid the need to reimplement the same multiplexing in each tile, thereby allowing the cost of multiplexing to be amortized across many FPGA logic block tiles. In at least some embodiments, multiplexing for control signals is added in separate tiles dedicated to control signal multiplexing. In at least some embodiments, multiplexing for control signals is added in existing separate tiles to support global signal routing.

[0018] In at least some embodiments, routing lines extend vertically or horizontally from one or both control signal routing tiles to logic block tiles. A logic block tile can choose any of the control signal routing lines to drive the FF contained within the logic block tile. This has the effect of distributing the area of ​​control signal multiplexing across all logic block tiles using the line. For example, if there is one control signal multiplexing tile for every 10 logic block tiles, the control signal multiplexing area for each tile is distributed among the 10 tiles. Compared to conventional techniques, this offers the advantage of increased flexibility in control signal multiplexing and a reduction in one or both of the areas dedicated to control signal multiplexing.

[0019] In another embodiment, control signals are multiplexed and distributed across different FPGA tiles, then shared using a cascaded configuration. In this case, to achieve control signal sharing between FPGA tiles, each logic block tile in a set of FPGA logic block tiles has a small control signal sharing multiplexer (multiplexer) with a reduced or minimal number of inputs to multiplex the control signals used for sharing. In at least some embodiments, determining whether control signals are routed via a cascaded path or directly via the multiplexer at the same location consuming the control signals is based on one or more design constraints. In at least some embodiments, the design constraints are timing constraints (e.g., the delay from the driver to the control signal receiver does not exceed 1 nanosecond (ns), or other predetermined delays). In at least some embodiments, the design constraints are power constraints to utilize cascading as much as possible to reduce wire load and thus reduce power consumption. In one embodiment, the number of inputs of the multiplexer used for multiplexing control signals for sharing is determined based on design constraints. In one embodiment, for a unidirectional cascaded configuration, the number of inputs of the multiplexer used for multiplexing control signals for distribution is two. In one embodiment, for a bidirectional cascaded configuration, the number of inputs to the multiplexer used for distributing control signals is three, as follows: Figure 3 and Figure 4 In further detail, the control signal sharing multiplexers for logical block tiles are connected in a cascaded configuration, enabling greater routing flexibility for a group of logical block tiles with the same control signal requirements compared to conventional technologies.

[0020] As described in this paper, inter-tile control signal sharing in FPGAs is particularly effective for FPGA architectures with a small number of LUTs and FFs per tile, such as fewer than approximately 8 LUTs and 16 FFs per tile. These architectures typically suffer from inefficient control signal multiplexing compared to FPGA architectures with more LUTs and FFs per tile. With the inter-tile control signal sharing in FPGAs described in this paper, the cost of control signal multiplexing is independent of the number of LUTs / FFs per tile.

[0021] Various embodiments and aspects of this disclosure will be described with reference to the details discussed below, and the accompanying drawings will illustrate the various embodiments. The following description and drawings are illustrative of this disclosure and should not be construed as limiting it. Numerous specific details are described to provide a thorough understanding of various embodiments of this disclosure. However, in some cases, well-known or conventional details are not described in order to provide a concise discussion of embodiments of this disclosure.

[0022] The term "an embodiment" or "embodiment" as used in this specification refers to a particular feature, structure, or characteristic described in connection with an embodiment that may be included in at least one embodiment of this disclosure. The phrase "in one embodiment" appearing in various places throughout the specification does not necessarily refer to the same embodiment.

[0023] Figure 1 This is a view 100 of a field-programmable gate array (FPGA) system architecture according to one embodiment. The FPGA system includes multiple FPGA tiles, such as FPGA tiles 101, 102, 103, 104, 105, 111, 113, 114, and 118 arranged in rows and columns. The tiles are connected using wires. Figure 1 As shown, tile 101 is connected to the wires of routing track 106 via wire 107. The wires of routing track 106 pass through tile 105. Tile 102 is connected to the wires of routing track 112 via wire 108. The wires of the routing track pass through tile 111. Figure 1 As shown, for example, some tiles in an FPGA, such as tiles 102, 103, 104, 113, and 114, are logic block tiles (LBs). For example, some tiles in an FPGA, such as tiles 105 and 111, are switch block tiles (SBs). Control signals are shared among FPGA tiles in multiple FPGA tiles. Typically, control signals refer to signals other than data signals, such as clock enable signals, preset / reset signals, synchronization load signals, synchronization clear signals, or other control signals. Many flip-flops on an FPGA tile can share control signals.

[0024] In at least some embodiments, control signals are multiplexed in separate control signal (CT) tiles, such as CT tile 101. CT tile 101 is configured to share control signal multiplexing among some tiles in an FPGA, such as between tiles 102 and 113, to avoid having the same multiplexing in each of these FPGA tiles. In at least some embodiments, CT tile 101 is not a logic block tile. In at least some embodiments, CT tile 101 does not have any logic associated with it. In at least some embodiments, CT tile 101 does not have FFs and LUTs associated with logic block tiles. CT tile 101 is a control signal multiplexing tile configured to obtain one or more control signals from a routing network such as a global routing network or a local routing network. Typically, for FPGA architectures, the term "cascaded" refers to passing signals continuously (in series) from one tile to another. CT tile 101 is configured to pass those control signals to dedicated wires connected to other tiles associated with that control signal block. Figure 1As shown, routing line 117 extends from CT tile 101 and transmits control signals shared among FPGA tiles, such as LB tiles 102 and 113. In at least some embodiments, the CT tile is smaller than the LB tile. In at least some embodiments, the FPGA system includes multiple CT tiles, such as CT tile 101, to share control signals with a group of LB tiles.

[0025] In at least some embodiments, the CT tile 101 includes one or more control signal shared multiplexers, such as control signal shared multiplexer 109. Figure 1 As shown, routing line 117 is driven from the output of multiplexer 109 to a set of FPGA tiles, such as LB tiles 102 and LB tiles 113. In at least some embodiments, control signals are shared. Each of the multiplexers outputs control signals on its respective routing line for sharing among the set of FPGA tiles. In at least some embodiments, the control signal routing line may extend horizontally toward a set of FPGA tiles arranged in a row, such as LB tiles 102 and LB tiles 111. In at least some embodiments, the control signal routing line may extend vertically toward a set of FPGA tiles arranged in a column, such as LB tiles 104 and LB tiles 118. In at least some embodiments, the FPGA tiles are cascaded and share the multiplexed control signals. Figure 1 As shown, the control signal routing line 117 reaches the tile 113 via LB tile 102.

[0026] In another embodiment, control signals are multiplexed and distributed across different FPGA tiles, such as tiles 104, 103, and 114 connected together in a cascaded configuration. Figure 1 As shown, each of FPGA tiles 104, 103, and 114 has a control signal multiplexer, such as multiplexer 119, multiplexer 115, and multiplexer 116. Multiplexers 119, 115, and 116 are interconnected in a cascaded configuration to share control signal multiplexing. Figure 1 As shown, multiplexer 115 is located in an adjacent tile of tile 104. Generally, if tile A is physically adjacent to tile B, then tile A is said to be an adjacent tile of tile B. A horizontally adjacent tile A is a tile where tile A is directly located east or west of tile B and there are no other tiles between tile A and tile B. A diagonally adjacent tile A is a tile where tile A is directly located northeast, northwest, southeast, or southwest of tile B and there are no other tiles between tile A and tile B. A vertically adjacent tile A is a tile where tile A is directly located north or south of tile B and there are no other tiles between tile A and tile B. 124 represents the north, south, east, and west directions on the FPGA architecture diagram. Figure 1As shown, tile 102 is directly east of tile 101, tile 103 is directly southeast of tile 101, and tile 104 is directly south of tile 101.

[0027] like Figure 1 As shown, input 121 of multiplexer 119 is connected to control signal line 123, output 122 of multiplexer 119 for transmitting control signals is connected to input of multiplexer 115, and output of multiplexer 115 is connected to input of multiplexer 116, such that control signals are shared among tiles 104, 103, and 114. In one embodiment, each of multiplexers 119, 115, and 116 has three inputs for a bidirectional cascaded configuration, as described below. Figure 3 Further detailed description. In one embodiment, each of the multiplexers 119, 115, and 116 has two inputs for a unidirectional cascading configuration, as described below regarding Figure 4 Further detailed description.

[0028] Figure 2 View 200 is a view 200 according to one embodiment of an FPGA system architecture including separate control signal multiplexed tiles 201 configured to share control signals among LB tiles 202. In at least some embodiments, view 200 represents... Figure 1 This is part of the described FPGA system architecture. (For example...) Figure 2 As shown, control signal multiplexing tile 201 includes a multiplexer (multiplexer) 204. The inputs of multiplexer 204 are connected to wires of routing track 207, such as wires 205 and 206. In one embodiment, at least one wire of routing track 207 is a global routing wire created for routing control signals. Control signal multiplexing in control signal multiplexing tile 201 is configured to pass a control signal on one of the inputs of multiplexer 204 to output 203 for distribution to N LB tiles 202-N, such as logic block tiles 202-1, 202-2, 202-3, where N is an integer greater than 1.

[0029] like Figure 2 As shown, input 209 of multiplexer 204 is connected to wire 205 of routing track. In one embodiment, wire 205 of routing track transmits control signals. Figure 2 As shown, routing line 208 extends from output 203 to transmit control signals for sharing among FPGA tiles 202-N. Figure 2As shown, routing line 208 drives FPGA tiles 202-1, 202-2, 202-3 until reaching 202-N. In this way, when control signals are passed in series to FPGA tiles 202-1, 202-2, 202-3, ..., 202-N, LB tile 202-N benefits from the increased flexibility of multiplexer 204 in control signal multiplexing tile 201.

[0030] Figure 3 View 300 is a view of an FPGA system architecture according to another embodiment, including control signal multiplexing circuitry shared among FPGA tiles in multiple FPGA tiles. In this scheme, control signal multiplexing is distributed among LB tiles and connected together in a cascaded configuration. In at least some embodiments, view 300 represents... Figure 1 This is part of the described FPGA system architecture. (For example...) Figure 3 As shown, the FPGA system architecture includes LB tiles, such as LB tile 301, LB tile 302, and LB tile 303. In an embodiment, the FPGA tiles include multiplexers interconnected in a cascaded configuration to share control signal multiplexing. In an embodiment, the cascaded configuration for sharing control signal multiplexing is a bidirectional cascaded configuration. Figure 3 As shown, LB tile 301 has a control signal multiplexer 304, LB tile 302 has a control signal multiplexer 305, and LB tile 303 has a control signal multiplexer 306. Each of the control signal multiplexers 304, 305, and 306 is a 3:1 multiplexer with three inputs and one output. Figure 3As shown, input 314 of multiplexer 305 is connected to output 307 of multiplexer 304. Input 315 of multiplexer 305 is connected to routing line 312. Input 316 of multiplexer 305 is connected to output 309 of multiplexer 306. Output 308 of multiplexer 305 is connected to input 321 of multiplexer 304 and input 317 of multiplexer 306. Input 318 of multiplexer 304 is configured to connect to the output of a multiplexer in the tile above tile 301. Input 319 of multiplexer 304 is connected to routing line 311. Output 307 of multiplexer 304 is configured to connect to the input of a multiplexer in the tile above tile 301. Input 322 of multiplexer 306 is connected to routing line 313. Input 323 of multiplexer 306 is configured to connect to the output of a multiplexer in the tile below tile 303. The output 309 of multiplexer 306 is configured to connect to the input of a multiplexer in the tile below tile 303. In this arrangement, each of the logic block tiles has a small (e.g., 3:1) control signal multiplexer with the output of the multiplexer in the lower tile, the output of the multiplexer in the upper tile, and one or more wires for routing as inputs. The end result is that for a group of logic block tiles with the same control signal requirements, the control signal can be distributed to all logic block tiles in the group, provided that the control signal can be routed on any of the wires accessed by any of the multiplexers in the group. For example, a control signal routed on the wire connected to routing line 312 accessed by multiplexer 305 can be bidirectionally distributed from tile 302 to all LB tiles in the group, including one or more tiles below or above tile 303, such as tiles 301 and 303. Control signals for routing on the wires connected to the routing line 311 accessed by multiplexer 304 are bidirectionally distributed from tile 301 to all LB tiles, such as tiles 302 and 303, in a group including one or more tiles below or above tile 301. Control signals for routing on the wires connected to the routing line 313 accessed by multiplexer 306 are bidirectionally distributed from tile 303 to all LB tiles, such as tiles 301 and 302, in a group including one or more tiles below or above tile 303.

[0031] Figure 4 View 400 is an FPGA system architecture according to another embodiment, including control signal multiplexing circuitry shared among FPGA tiles in multiple FPGA tiles. In this scheme, control signal multiplexing is distributed among LB tiles connected together in a unidirectional cascade configuration. In at least some embodiments, view 400 represents... Figure 1 This is part of the described FPGA system architecture. (For example...) Figure 4As shown, the FPGA system architecture includes LB tiles, such as LB tile 401, LB tile 402, and LB tile 403. In an embodiment, the FPGA tiles include multiplexers interconnected in a unidirectional cascade configuration to share control signal multiplexing. Figure 4 As shown, LB tile 401 has a control signal multiplexer 404, LB tile 402 has a control signal multiplexer 405, and LB tile 403 has a control signal multiplexer 406. Each of the control signal multiplexers 404, 405, and 406 is a 2:1 multiplexer with two inputs and one output. Figure 4 As shown, input 407 of multiplexer 404 is configured to connect to the output of a multiplexer in the tile above tile 401. Input 408 of multiplexer 404 is connected to routing line 417. Output 414 of multiplexer 404 is connected to input 409 of multiplexer 405. Input 411 of multiplexer 405 is connected to routing line 418. Output 415 of multiplexer 405 is connected to input 412 of multiplexer 406. Input 413 of multiplexer 406 is connected to routing line 419. Output 416 of multiplexer 406 is configured to connect to the input of a multiplexer in the tile below tile 403. In this embodiment, each of the logic block tiles has a 2:1 control signal multiplexer that takes the output of the multiplexer in the tile above as an input and has a wire connected to a line in the routing line. Control signals routed on the conductors of routing line 417 connected to multiplexer 404 are unidirectionally distributed from tile 401 to all LB tiles, such as tiles 402 and 403, in a group of one or more tiles below tile 401. Control signals routed on the conductors of routing line 418 connected to multiplexer 405 are unidirectionally distributed from tile 402 to all LB tiles, such as tile 403, in a group of one or more tiles below tile 402. Control signals routed on the conductors of routing line 419 connected to multiplexer 406 are unidirectionally distributed from tile 403 to all LB tiles, such as tile 403, in a group of one or more tiles below tile 403. In an embodiment, control signals routed on the conductors of multiplexer access within an LB tile are distributed to one or more other LB tiles adjacent to that LB tile.

[0032] Figure 5This is a flowchart of a method 500 for providing control signal sharing between FPGA tiles according to one embodiment. Method 500 begins with operation 501 involving determining routes for a plurality of FPGA tiles. In at least some embodiments, the FPGA tiles include logic block tiles, as described above. In operation 502, control signal multiplexing circuitry shared among the FPGA tiles in the plurality of FPGA tiles is determined. In at least some embodiments, individual control signal multiplexing configured to share the control signal multiplexing to avoid having the same multiplexing in each of the FPGA tiles is determined, as described above. In at least some embodiments, routing lines extending from the control signal multiplexing to transmit control signals shared between the FPGA tiles are determined, as described above. In at least some embodiments, the control signal multiplexing includes one or more multiplexers. Each of the one or more multiplexers outputs control signals to be shared among a group of FPGA tiles, as described above. In at least some embodiments, the control signal multiplexing is distributed among FPGA tiles connected together in a cascaded configuration. In at least some embodiments, a route is determined for a first FPGA tile including a first multiplexer. A route is determined for a second FPGA tile including a second multiplexer. The second FPGA tile is an adjacent tile to the first FPGA tile. At least one input of the first multiplexer is connected to a control signal line, and the output of the first multiplexer is connected to the input of the second multiplexer, as described above.

[0033] The above detailed description is presented based on algorithms and symbolic representations of operations on data bits within computer memory. These algorithmic descriptions and representations are the means by which those skilled in the art of data processing most effectively communicate the essence of their work to others skilled in the art. Here, an algorithm is generally considered to be a self-consistent sequence of operations that produces the desired result. These operations are steps that require physical manipulation of physical quantities. Typically, though not always, these quantities take the form of electrical or magnetic signals that can be stored, transmitted, combined, compared, and further manipulated. Primarily for general reasons, it has proven convenient to sometimes refer to these signals as bits, values, elements, symbols, characters, terms, numbers, etc.

[0034] However, it should be remembered that all these and similar terms will be associated with appropriate physical quantities and are merely convenient labels applicable to those quantities. Unless otherwise explicitly stated in the discussion below, it should be understood that throughout this specification, discussions using terms such as “processing” or “calculating” or “deriving” or “determining” or “displaying” refer to the actions and processes of a computer system or similar electronic computing device that manipulates and converts data represented as physical (electronic) quantities within the registers and memory of the computer system into other data similarly represented as physical quantities within the computer system's memory or registers or other such information storage, transmission, or display devices.

[0035] The embodiments described herein also relate to a device for performing the operations described herein. This device may be specifically constructed for the desired purpose, or it may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk including floppy disks, optical disks, CD-ROMs, and magneto-optical disks, read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic cards, or optical cards, or any type of medium suitable for storing electronic instructions, and each may be connected to a computer system bus.

[0036] The algorithms and displays presented herein are inherently independent of any particular computer or other device. Various general-purpose systems can be used with the programs taught herein, or it may prove convenient to construct more specialized devices to perform the desired methodological operations. The necessary structures for various such systems will become apparent from the description herein. Furthermore, the embodiments of this disclosure are not described with reference to any particular programming language. It should be understood that various programming languages ​​can be used to implement the teachings of the embodiments described herein.

[0037] Machine-readable media include any mechanism for storing or transmitting information in a machine-readable (e.g., computer-readable) form. For example, machine-readable media include read-only memory (“ROM”); random access memory (“RAM”); magnetic disk storage media; optical storage media; flash memory devices; electrical, optical, acoustic, or other forms of propagation signals (e.g., carrier waves, infrared signals, digital signals, etc.); and so on.

[0038] In the foregoing description, embodiments of the present disclosure have been described with reference to specific exemplary embodiments thereof. It will be apparent that various modifications may be made to the present disclosure without departing from the broader spirit and scope of the disclosure set forth in the appended claims. Therefore, the description and drawings are to be regarded as illustrative rather than restrictive.

Claims

1. A field-programmable gate array (FPGA) device, comprising: Multiple FPGA tiles; as well as A control signal multiplexing circuit, also known as a control signal multiplexing circuit, takes one or more control signals from a routing network as input and outputs control signals from the control signal multiplexing circuit. These control signals are shared among a group of FPGA tiles connected in series, including a first FPGA tile and a second FPGA tile. A routing line is connected to the output of the control signal multiplexing circuit to transmit the control signals cascaded from the first FPGA tile to the second FPGA tile.

2. The device according to claim 1, further comprising: A control signal multiplexing tile, the control signal multiplexing tile including a control signal multiplexing circuit separate from the set of FPGA tiles.

3. The device of claim 1, wherein the control signal multiplexing circuit comprises one or more multiplexers, wherein each of the one or more multiplexers outputs the control signal shared among the set of FPGA tiles.

4. The device according to claim 1, wherein the control signal multiplexing circuit comprises: A multiplexer and a routing line, the routing line extending from the output of the multiplexer to the set of FPGA tiles.

5. The device of claim 1, wherein the set of FPGA tiles includes logic block tiles.

6. The device of claim 1, wherein the set of FPGA tiles is arranged in at least one of columns or rows.

7. The device of claim 1, wherein the control signal multiplexing is distributed among the set of FPGA tiles using a bidirectional cascaded configuration.

8. The device of claim 1, wherein the control signal multiplexing circuit is distributed in a unidirectional cascade configuration among the set of FPGA tiles.

9. The device of claim 1, wherein the set of FPGA tiles includes a multiplexer interconnected in a cascaded configuration to share the control signal multiplexing circuitry.

10. A field-programmable gate array (FPGA) device, comprising: Multiple FPGA tiles; as well as A control signal multiplexing circuit, also known as a control signal multiplexing circuit, takes one or more control signals from a routing network as input and outputs control signals from the control signal multiplexing circuit. These control signals are shared among a group of FPGA tiles, which includes a first FPGA tile and a second FPGA tile. The first FPGA tile includes a first multiplexer; the second FPGA tile includes a second multiplexer and is an adjacent tile of the first FPGA tile, wherein at least one input of the first multiplexer is connected to a control signal line, and the output of the first multiplexer is connected to the input of the second multiplexer.

11. An apparatus comprising: Memory; as well as The processor is connected to the memory. The processor is configured as follows: Determine the routing for multiple FPGA tiles; A control signal multiplexing circuit, also known as a multiplexing circuit, is defined. This control signal multiplexing circuit receives one or more control signals from a routing network and outputs control signals from itself. These control signals are shared among a group of FPGA tiles connected in series, comprising a first FPGA tile and a second FPGA tile. A routing line is determined, which extends from the control signal multiplexing circuit to transmit the control signals cascaded from the first FPGA tile to the second FPGA tile.

12. The device of claim 11, wherein the processor is further configured to determine control signal multiplexing tiles, the control signal multiplexing tiles being configured to share control signal multiplexing, the control signal multiplexing tiles being separate from the set of FPGA tiles.

13. The device of claim 11, wherein the control signal multiplexing circuitry comprises one or more multiplexers, wherein each of the one or more multiplexers outputs the control signal shared among the set of FPGA tiles.

14. The device of claim 12, wherein the set of FPGA tiles includes logic block tiles.

15. The device of claim 12, wherein the set of FPGA tiles is arranged in at least one of columns or rows.

16. The device of claim 11, wherein the control signals are multiplexed and distributed among FPGA tiles connected together in a cascaded configuration.

17. An apparatus comprising: Memory; as well as The processor is connected to the memory. The processor is configured as follows: Determine the routing for multiple FPGA tiles; A control signal multiplexing circuit, also known as a multiplexing circuit, is defined. This control signal multiplexing circuit takes one or more control signals from the routing network as input and outputs control signals from itself. These control signals are shared among a group of FPGA tiles, including a first FPGA tile and a second FPGA tile. The first FPGA tile includes a first multiplexer, the second FPGA tile includes a second multiplexer and is an adjacent tile of the first FPGA tile, and the processor is configured to connect at least one input of the first multiplexer to a control signal line and connect the output of the first multiplexer to an input of the second multiplexer.

18. A non-transitory machine-readable medium storing instructions that cause a data processing system to perform operations including: Identify multiple FPGA tiles; A control signal multiplexing circuit is defined, configured to input one or more control signals from a routing network and output control signals from the control signal multiplexing circuit. These control signals are shared among a group of FPGA tiles connected in series, comprising a first FPGA tile and a second FPGA tile. A routing line is determined, which extends from the control signal multiplexing circuit to transmit the control signals cascaded from the first FPGA tile to the second FPGA tile.

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