A system and method for evaluating single-event effect performance of FPGA high-speed serial transceivers

Abstract

A system and method for evaluating the single-particle effect performance of an FPGA high-speed serial transceiver, the evaluation system comprising a host computer, a main control system, and a system to be tested. The host computer is responsible for controlling the test process and displaying the test results. The main control system is responsible for receiving operating instructions from the host computer and controlling the system to be tested to complete the single-particle effect evaluation. The FPGA in the system to be tested is partially exposed to a particle beam to complete the single-particle test of the high-speed serial transceiver. Statistical methods are used to define single-particle upsets, recoverable single-particle functional interruptions, and irrecoverable single-particle functional interruptions, ultimately completing the single-particle effect evaluation of the FPGA high-speed serial transceiver to be tested. The present invention is a system-level single-particle effect evaluation method, which includes single-particle upsets and single-particle functional interruptions, and effectively and comprehensively evaluates the device's anti-single-particle performance.

Description

Technical Field

[0001] The present invention relates to a system and method for evaluating the single-particle effect performance of an FPGA high-speed serial transceiver, and belongs to the field of FPGA testing and irradiation testing. Background Art

[0002] In space applications, FPGA high-speed serial interface transceivers offer efficient transmission and processing capabilities. Serial data transmission utilizes LVDS (Low Voltage Differential Signaling). Differential signaling offers advantages such as low latency, long transmission distances, strong interference immunity, high speed, and large capacity, leading to its increasing application in aerospace systems. This requires not only high reliability but also radiation resistance. Therefore, prior to space system deployment, FPGA high-speed serial interface transceivers must undergo thorough radiation testing and evaluation. Single-event radiation testing is a fundamental method for evaluating the single-event effect resistance of FPGA high-speed serial interface transceivers.

[0003] Existing FPGA high-speed serial transceiver testing methods connect the transmit (TX) and receive (RX) channels of the device under test to perform an internal loopback test. Single-event effects (SEEs) from both TX and RX are counted uniformly, and then, based on the duration of the error, are determined to be either a single-event event or a link interruption. Furthermore, existing methods fail to verify the applicability of refresh strategies to FPGA high-speed serial transceiver modules. However, as FPGA process sizes continue to shrink and operating frequencies increase, quantitative analysis and systematic irradiation testing are needed to validate SEE evaluation results for high-speed serial transceivers. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to overcome the shortcomings of the existing technology and provide a single-event effect performance evaluation system and method for FPGA high-speed serial transceivers, which solves the problems of separate evaluation of transmitting and receiving channels, refresh strategy verification, single-event upset and single-event function interruption number recording, etc.

[0005] The purpose of the present invention is achieved through the following technical solutions:

[0006] An FPGA high-speed serial transceiver single event effect performance evaluation system includes a host computer, a main control system, and a system to be tested;

[0007] The host computer is used to perform test settings, test process control and test result display;

[0008] The main control system includes a control processing FPGA, a configuration FLASH, and a DDR memory; the control processing FPGA communicates with the DDR memory, the configuration FLASH, and the host computer respectively, and is connected to the FPGA under test in the system under test through a high-speed serial interface; the DDR memory is used to store the test code stream for configuring the FPGA under test, and the configuration FLASH is used to store the configuration code stream for configuring the control processing FPGA;

[0009] The control processing FPGA includes a communication module, a process control module, a single particle detection module, a configuration refresh module, a high-speed serial data transceiver module, and a DDR read / write module;

[0010] The communication module is used to receive control instructions and FPGA configuration code streams sent by the host computer;

[0011] The process control module sends the control instructions to the DDR read-write module and the configuration refresh module; the DDR read-write module stores the FPGA configuration code stream to be tested received by the communication module in the DDR memory;

[0012] The single particle detection module records the number of single event upsets and single event function interruptions during particle irradiation through a high-speed serial data transceiver module;

[0013] The configuration refresh module is used to configure and refresh the FPGA to be tested;

[0014] The high-speed serial data transceiver module is used to perform high-speed serial data communication with the FPGA to be tested; specifically, after generating a PRBS code and sending it to the FPGA to be tested, the PRBS code fed back by the FPGA to be tested is received for detection;

[0015] The system to be tested is used to carry the FPGA to be tested, and the FPGA to be tested is placed in the irradiation test area.

[0016] Preferably, the high-speed serial data transceiver module includes a PRBS generation module, a TX transmission module, a PRBS detection module, and an RX receiving module. The PRBS generation module is used to generate a PRBS code and send it to the FPGA to be tested via the TX transmission module; the FPGA to be tested feeds back the PRBS code and reaches the PRBS detection module via the RX receiving module.

[0017] Preferably, the configuration refresh module configures and refreshes the FPGA to be tested through a Select MAP interface.

[0018] Preferably, the system under test uses a shielding plate with windows to expose part or all of the FPGA under test to radiation conditions.

[0019] Preferably, when the high-speed serial data transceiver module detects a data error, it is recorded as a single event upset.

[0020] Preferably, the single event functional interruption includes a recoverable single event functional interruption and an irrecoverable single event functional interruption.

[0021] Preferably, when the high-speed serial data transceiver module detects that in a data packet consisting of m consecutive words, one or more bit errors are detected in each word, which is recorded as an error code and counted as Num_error;

[0022] When Num_error in the data packet is greater than the preset threshold and the duration is less than or equal to the preset time t, a recoverable single event function interruption is counted; otherwise, an unrecoverable single event function interruption is counted.

[0023] A method for evaluating the single event effect performance of an FPGA high-speed serial transceiver, using the above-mentioned evaluation system, includes:

[0024] The host computer sends a handshake command to the control processing FPGA. If successful, it sends the configuration code stream of the FPGA to be tested. The control processing FPGA writes the configuration code stream of the FPGA to be tested into the DDR memory.

[0025] The host computer sends a configuration command to control the FPGA to configure the FPGA configuration stream stored in the DDR memory to the FPGA under test and start the timed refresh;

[0026] Turn on the irradiation condition, and the host computer sends high-speed serial transceiver test instructions, which are divided into TX test instructions and RX test instructions;

[0027] TX test instruction: The CH3 channel in the control processing FPGA generates a PRBS code and sends it to the CH0 channel in the FPGA under test. The CH0 channel in the FPGA under test sends the data to the CH3 channel in the FPGA under test. The CH3 channel in the FPGA under test sends the data to the CH0 channel in the control processing FPGA.

[0028] RX test instruction: The CH0 channel in the control processing FPGA generates a PRBS code and sends it to the CH3 channel in the FPGA under test. The CH3 channel in the FPGA under test sends the data to the CH0 channel in the FPGA under test. The CH0 channel in the FPGA under test sends the data to the CH3 channel in the control processing FPGA.

[0029] The control processing FPGA performs data detection and counts the number of single event upsets that occur in the FPGA under test.

[0030] Preferably, 16 bits of data in the PRBS code constitute one word, and m consecutive words constitute a data packet. If one or more bits in each word are wrong, it is an error code, which is counted as Num_error.

[0031] If the Num_error in the data packet is greater than the preset threshold e, the threshold signal is pulled high. If the high-level duration of the threshold signal is less than or equal to the preset time t, a recoverable single-event functional interrupt is counted; if the high-level duration of the threshold signal is greater than the preset time t, an unrecoverable single-event functional interrupt is counted.

[0032] Preferably, if an unrecoverable single event functional interruption occurs, the control processing FPGA resets the test system, restarts the irradiation condition and performs the test.

[0033] Compared with the prior art, the present invention has the following beneficial effects:

[0034] (1) The present invention is a system-level single-event effect evaluation method, which includes single-event upset and single-event functional interruption, and effectively and comprehensively evaluates the device's single-event resistance performance.

[0035] (2) The present invention utilizes data transmission between different channels (CH) in the same QUAD, distinguishes between module sending and receiving modules, and can perform single event effect assessment separately.

[0036] (3) The present invention uses statistical methods to distinguish between recoverable and non-recoverable events in single-particle functional interrupt effects, which is of great significance to the design of FPGA circuits and aerospace-level applications.

[0037] (4) The present invention can evaluate the single-particle functional interrupt effect of the standby system of an FPGA high-speed serial transceiver with a refresh strategy.

[0038] (5) In the present invention, if an unrecoverable single-particle functional interruption occurs, the control processing system resets the test system and restarts the test, which can save time. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 This is the overall structural framework diagram of the test system of the present invention;

[0040] Figure 2 Flow chart of the test method process of the present invention. DETAILED DESCRIPTION

[0041] To make the objectives, technical solutions and advantages of the present invention more clear, the embodiments of the present invention will be described in further detail below with reference to the accompanying drawings.

[0042] A single event effect evaluation system for FPGA high-speed serial interface transceiver includes a host computer, a main control system and a system to be tested, such as Figure 1 shown.

[0043] The host computer is used for test setting, test process control and test result display.

[0044] The main control system includes a control processing FPGA, a configuration FLASH, and a DDR memory.

[0045] The control processing FPGA is connected to the DDR memory, configuration FLASH, and host computer respectively, and is connected to the FPGA of the system under test through a high-speed serial interface. The DDR memory is used to store the test code stream used to configure the FPGA under test, and the configuration FLASH is used to store the configuration code stream for configuring the control processing FPGA.

[0046] The control processing FPGA includes a communication module, a process control module, a single particle detection module, a configuration refresh module of the FPGA to be tested, a high-speed serial data transceiver module, and a DDR read / write module.

[0047] The communication module includes a control instruction module for receiving a USB communication interface and a module for receiving a configuration code stream of an FPGA to be tested.

[0048] The process control module sends the control instruction to the single particle detection module and the DDR read-write module, and stores the received FPGA configuration code stream to be tested in the DDR memory through the DDR read-write module.

[0049] The single particle detection module receives data from the PRBS generation module and the PRBS detection module for comparison, and records the number of single event upsets and single event function interruptions during particle irradiation.

[0050] The FPGA configuration refresh module receives instructions from the process control module, configures and refreshes the FPGA to be tested through the Select MAP interface, and verifies the impact of the refresh strategy on the single-event effect of the FPGA high-speed serial transceiver.

[0051] The high-speed serial data transceiver module mainly includes a PRBS generation module, a TX transmission module, a PRBS detection module, and an RX reception module.

[0052] The system to be tested mainly includes the FPGA to be tested, which is placed in the irradiation test area.

[0053] Each QUAD in the FPGA high-speed serial interface transceiver under test contains four channels. CH3 is selected as the channel under test, and RX and TX are tested separately. CH0 is selected to receive and transmit data transmitted between the control FPGA and the FPGA under test. A shielding plate with a window size of 3mm x 3mm is used to expose the tested part CH3 to the particle beam.

[0054] The present invention also includes a single event effect evaluation method for FPGA high-speed serial interface transceivers, specifically targeting the single event effects of FPGA high-speed serial interface transceivers using the following three statistical methods:

[0055] 1. Single event upset: A single bit or multiple bits upset occurs in a short period of time.

[0056] 2. Recoverable single-event functional interrupt: A functional interrupt caused by a flip of a functional signal or global signal can be recovered by refreshing. A recoverable single-event functional interrupt is defined as one whose duration is less than the refresh period t.

[0057] 3. Unrecoverable single-event functional interruption: A functional interruption that is unrecoverable for a long period of time. An unrecoverable single-event functional interruption is defined as one whose duration is greater than the refresh period t.

[0058] The single event effect evaluation method includes the following steps: Figure 2 As shown:

[0059] (1) The host computer sends a handshake command to the control processing FPGA. If successful, it continues to send the configuration code stream of the FPGA to be tested. The control processing FPGA writes the code stream to be tested into the DDR memory.

[0060] (2) The host computer sends a configuration command to control the FPGA to configure the FPGA under test through the SelectMAP interface with the code stream stored in the DDR memory, and start the timed refresh.

[0061] (3) The irradiation condition is turned on, and the host computer sends a high-speed serial transceiver test instruction, which is a TX test instruction or an RX test instruction.

[0062] (4) TX test instruction: CH3 in the control processing FPGA generates a PRBS code and sends it to CH0 in the FPGA under test. CH0 in the FPGA under test sends the data to CH3, and CH3 in the FPGA under test sends the data to CH0 in the control FPGA.

[0063] (5) RX test instruction: CH0 in the control FPGA generates a PRBS code and sends it to CH3 in the FPGA under test. CH3 in the FPGA under test sends the data to CH0, and CH0 in the FPGA under test sends the data to CH3 in the control FPGA.

[0064] (6) Control the Check data in FPGA. If a data error occurs, a single event upset occurs and the upset number Num_SEU increases by 1.

[0065] (7) 16-bit data constitutes a word, and m consecutive words constitute a data packet. If one or more bits in each word are wrong, it is an error code, which is counted as Num_error.

[0066] (8) If Num_error in the data packet is greater than e, the threshold signal is pulled high. If the duration of the high level of the threshold signal is less than or equal to t, a recoverable single-event functional interruption is counted, that is, Num_rec is increased by 1. Conversely, if the duration of the high level of the threshold signal reaches t, an unrecoverable single-event functional interruption is counted, that is, Num_unrec is increased by 1.

[0067] (9) If an unrecoverable single-particle functional interrupt occurs, the control processing FPGA resets the test system and jumps to (3).

[0068] In this invention, a master control system receives commands from a host computer and controls the system under test to complete single-event effect evaluation. The FPGA in the system under test is partially exposed to a particle beam to perform single-event testing of a high-speed serial transceiver. Statistical methods are used to define single-event upsets, recoverable single-event functional interruptions, and non-recoverable single-event functional interruptions, ultimately completing the single-event effect evaluation of the FPGA's high-speed serial transceiver under test.

[0069] The contents not described in detail in the specification of the present invention belong to the common knowledge of those skilled in the art.

[0070] Although the present invention has been disclosed above in terms of preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art may make possible changes and modifications to the technical solutions of the present invention by using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solutions of the present invention shall fall within the scope of protection of the technical solutions of the present invention.

Claims

1. A single event effect performance evaluation system for FPGA high-speed serial transceivers, characterized in that: Including host computer, main control system and system under test; The host computer is used to perform test settings, test process control and test result display; The main control system includes a control processing FPGA, a configuration FLASH, and a DDR memory; the control processing FPGA communicates with the DDR memory, the configuration FLASH, and the host computer respectively, and is connected to the FPGA under test in the system under test through a high-speed serial interface; the DDR memory is used to store the test code stream for configuring the FPGA under test, and the configuration FLASH is used to store the configuration code stream for configuring the control processing FPGA; The control processing FPGA includes a communication module, a process control module, a single particle detection module, a configuration refresh module, a high-speed serial data transceiver module, and a DDR read / write module; The communication module is used to receive control instructions and FPGA configuration code streams sent by the host computer; The process control module sends the control instructions to the DDR read-write module and the configuration refresh module; the DDR read-write module stores the FPGA configuration code stream to be tested received by the communication module in the DDR memory; The single particle detection module records the number of single event upsets and single event function interruptions during particle irradiation through a high-speed serial data transceiver module; Single-event functional interrupts include recoverable single-event functional interrupts and unrecoverable single-event functional interrupts. When the high-speed serial data transceiver module detects that in a data packet consisting of m consecutive words, one or more bit errors are recorded as error codes, and one Num_error is counted. When Num_error in the data packet is greater than a preset threshold and the duration is less than or equal to the preset time t, a recoverable single-event functional interrupt is counted, otherwise an unrecoverable single-event functional interrupt is counted. The configuration refresh module is used to configure and refresh the FPGA to be tested; The high-speed serial data transceiver module is used to perform high-speed serial data communication with the FPGA to be tested; specifically, after generating a PRBS code and sending it to the FPGA to be tested, the PRBS code fed back by the FPGA to be tested is received for detection; when the irradiation condition is turned on, the host computer sends a high-speed serial transceiver test instruction, and the instruction is divided into a TX test instruction and an RX test instruction; TX test instruction: the CH3 channel in the control processing FPGA generates a PRBS code and sends it to the CH0 channel in the FPGA to be tested, the CH0 channel in the FPGA to be tested sends data to the CH3 channel in the FPGA to be tested, and the CH3 channel in the FPGA to be tested sends data to the CH0 channel in the control processing FPGA; RX test instruction: the CH0 channel in the control processing FPGA generates a PRBS code and sends it to the CH3 channel in the FPGA to be tested, the CH3 channel in the FPGA to be tested sends data to the CH0 channel in the FPGA to be tested, and the CH0 channel in the FPGA to be tested sends data to the CH3 channel in the control processing FPGA; The system to be tested is used to carry the FPGA to be tested, and the FPGA to be tested is placed in the irradiation test area.

2. The single event effects performance evaluation system according to claim 1, wherein: The high-speed serial data transceiver module includes a PRBS generation module, a TX transmission module, a PRBS detection module, and an RX receiving module. The PRBS generation module is used to generate a PRBS code and then send it to the FPGA to be tested via the TX transmission module; the FPGA to be tested feeds back the PRBS code and reaches the PRBS detection module via the RX receiving module.

3. The single event effects performance evaluation system according to claim 1, wherein: The configuration refresh module configures and refreshes the FPGA to be tested through the Select MAP interface.

4. The single event effects performance evaluation system according to claim 1, wherein: The system under test uses a shielding plate with windows to expose part or all of the FPGA under test to radiation conditions.

5. The single event effects performance evaluation system according to claim 1, wherein: When the high-speed serial data transceiver module detects a data error, it is recorded as a single event upset.

6. A method for evaluating single event effect performance of FPGA high-speed serial transceiver, characterized in that: An evaluation system according to any one of claims 1 to 5, comprising: The host computer sends a handshake command to the control processing FPGA. If successful, it sends the configuration code stream of the FPGA to be tested. The control processing FPGA writes the configuration code stream of the FPGA to be tested into the DDR memory. The host computer sends a configuration command to control the FPGA to configure the FPGA configuration stream stored in the DDR memory to the FPGA under test and start the timed refresh; Turn on the irradiation condition, and the host computer sends high-speed serial transceiver test instructions, which are divided into TX test instructions and RX test instructions; TX test instruction: The CH3 channel in the control processing FPGA generates a PRBS code and sends it to the CH0 channel in the FPGA under test. The CH0 channel in the FPGA under test sends the data to the CH3 channel in the FPGA under test. The CH3 channel in the FPGA under test sends the data to the CH0 channel in the control processing FPGA. RX test instruction: The CH0 channel in the control processing FPGA generates a PRBS code and sends it to the CH3 channel in the FPGA under test. The CH3 channel in the FPGA under test sends the data to the CH0 channel in the FPGA under test. The CH0 channel in the FPGA under test sends the data to the CH3 channel in the control processing FPGA. The control processing FPGA performs data detection and counts the number of single event upsets that occur in the FPGA under test.

7. The single event effect performance evaluation method according to claim 6, characterized in that: In the PRBS code, 16 bits of data form a word, and m consecutive words form a data packet. If one or more bits in each word are wrong, it is an error code, which is counted as Num_error. If the Num_error in the data packet is greater than the preset threshold e, the threshold signal is pulled high. If the high-level duration of the threshold signal is less than or equal to the preset time t, a recoverable single-event functional interrupt is counted; if the high-level duration of the threshold signal is greater than the preset time t, an unrecoverable single-event functional interrupt is counted.

8. The single event effect performance evaluation method according to claim 7, characterized in that: If an unrecoverable single-event functional interrupt occurs, the control processing FPGA resets the test system, restarts the irradiation conditions and performs the test.

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