Single-step category-level object pose estimation

Abstract

Single-step category-level object pose estimation is disclosed, specifically, apparatus, systems, and techniques for determining the pose and relative size of an object from an image. In at least one embodiment, the pose and relative size of the object are determined from the image based at least in part on features, such as those of the image itself.

Description

[0001] Claiming priority

[0002] This application claims the benefit of U.S. Provisional Application No. 63 / 151,387, filed February 19, 2021, entitled “Single-Stage Category-Level Object Pose Estimation with Point Representation,” the entire contents of which are incorporated herein by reference. Technical Field

[0003] At least one embodiment relates to processing resources for determining the pose and relative size of an object from an image. For example, at least one embodiment relates to a processor or computer system for determining the pose and relative size of an object from an image using the various novel techniques described herein. Background Technology

[0004] Determining the pose and relative size of an object from an image is an important task in many environments. In many cases, such as when the image lacks associated depth information, determining the pose and relative size of an object from an image can be difficult. Therefore, techniques for determining the pose and relative size of objects from images can be improved. Attached Figure Description

[0005] Figure 1 An example of a system for object pose estimation according to at least one embodiment is shown;

[0006] Figure 2 Examples of six-degree-of-freedom (6-DoF) poses and relative dimensions according to at least one embodiment are shown;

[0007] Figure 3 An example of the results of a system for object pose estimation according to at least one embodiment is shown;

[0008] Figure 4 An example of the resulting values ​​of a system for object pose estimation according to at least one embodiment is shown;

[0009] Figure 5 Another example of the resulting values ​​of a system for object pose estimation according to at least one embodiment is shown;

[0010] Figure 6 Another example of the resulting values ​​of a system for object pose estimation according to at least one embodiment is shown;

[0011] Figure 7 An example of key point representation according to at least one embodiment is shown;

[0012] Figure 8 Another example of the results of a system for object pose estimation according to at least one embodiment is shown;

[0013] Figure 9 An example of the process of a system for object pose estimation according to at least one embodiment is shown;

[0014] Figure 10A The inference and / or training logic according to at least one embodiment is illustrated;

[0015] Figure 10B The inference and / or training logic according to at least one embodiment is illustrated;

[0016] Figure 11 The training and deployment of a neural network according to at least one embodiment are illustrated;

[0017] Figure 12 An example data center system according to at least one embodiment is shown;

[0018] Figure 13A An example of an autonomous vehicle according to at least one embodiment is shown;

[0019] Figure 13B The illustration shows an embodiment according to at least one of the embodiments. Figure 13A Examples of camera positions and field of view for autonomous vehicles;

[0020] Figure 13C This is an illustration based on at least one embodiment. Figure 13A A block diagram of an example system architecture for an autonomous vehicle;

[0021] Figure 13D The illustration, according to at least one embodiment, is for one or more cloud-based servers and Figure 13A A diagram of a system for communication between autonomous vehicles;

[0022] Figure 14 This is a block diagram illustrating a computer system according to at least one embodiment;

[0023] Figure 15 This is a block diagram illustrating a computer system according to at least one embodiment;

[0024] Figure 16 A computer system according to at least one embodiment is shown;

[0025] Figure 17 A computer system according to at least one embodiment is shown;

[0026] Figure 18A A computer system according to at least one embodiment is shown;

[0027] Figure 18B A computer system according to at least one embodiment is shown;

[0028] Figure 18C A computer system according to at least one embodiment is shown;

[0029] Figure 18D A computer system according to at least one embodiment is shown;

[0030] Figure 18E and Figure 18F A shared programming model according to at least one embodiment is shown;

[0031] Figure 19 An exemplary integrated circuit and a related graphics processor according to at least one embodiment are shown;

[0032] Figure 20A and Figure 20B An exemplary integrated circuit and an associated graphics processor according to at least one embodiment are shown;

[0033] Figure 21A and Figure 21B Additional exemplary graphics processor logic according to at least one embodiment is shown;

[0034] Figure 22 A computer system according to at least one embodiment is shown;

[0035] Figure 23A A parallel processor according to at least one embodiment is shown;

[0036] Figure 23B A partitioning unit according to at least one embodiment is shown;

[0037] Figure 23C A processing cluster according to at least one embodiment is shown;

[0038] Figure 23D A graphics multiprocessor according to at least one embodiment is shown;

[0039] Figure 24 A multi-graphics processing unit (GPU) system according to at least one embodiment is illustrated;

[0040] Figure 25 A graphics processor according to at least one embodiment is shown;

[0041] Figure 26 It is a block diagram illustrating a processor microarchitecture for a processor according to at least one embodiment;

[0042] Figure 27A deep learning application processor according to at least one embodiment is shown;

[0043] Figure 28 A block diagram of an example neuromorphic processor is shown according to at least one embodiment;

[0044] Figure 29 At least a portion of a graphics processor according to one or more embodiments is shown;

[0045] Figure 30 At least a portion of a graphics processor according to one or more embodiments is shown;

[0046] Figure 31 At least a portion of a graphics processor according to one or more embodiments is shown;

[0047] Figure 32 A block diagram of a graphics processing engine of a graphics processor is shown according to at least one embodiment;

[0048] Figure 33 This is a block diagram illustrating at least a portion of a graphics processor core according to at least one embodiment;

[0049] Figure 34A and Figure 34B The diagram illustrates thread execution logic according to at least one embodiment, which includes an array of processing elements of a graphics processor core;

[0050] Figure 35 A parallel processing unit (“PPU”) according to at least one embodiment is shown;

[0051] Figure 36 A general-purpose processing cluster (“GPC”) according to at least one embodiment is illustrated;

[0052] Figure 37 A memory partition unit of a parallel processing unit (“PPU”) according to at least one embodiment is shown;

[0053] Figure 38 A streaming multiprocessor according to at least one embodiment is illustrated;

[0054] Figure 39 This is an example data flow diagram of an advanced computing pipeline according to at least one embodiment;

[0055] Figure 40 This is a system diagram of an example system for training, adapting, instantiating, and deploying machine learning models in an advanced computing pipeline, according to at least one embodiment;

[0056] Figure 41Example illustrations include an advanced computing pipeline 4010A for processing imaging data according to at least one embodiment;

[0057] Figure 42A Includes example data flow diagrams of virtual instruments supporting ultrasound equipment according to at least one embodiment;

[0058] Figure 42B Includes example data flow diagrams of virtual instruments supporting CT scanners according to at least one embodiment;

[0059] Figure 43A A data flow diagram illustrating the process for training a machine learning model according to at least one embodiment is shown; and

[0060] Figure 43B This is an example illustration of a client-server architecture that utilizes a pre-trained annotation model to enhance an annotation tool, according to at least one embodiment. Detailed Implementation

[0061] The techniques and systems described in this paper relate to methods for determining the six-degree-of-freedom (6-DoF and / or 6DOF) pose and relative dimensions of an object from an image using one or more neural networks. The 6-DoF pose can refer to the object's three-dimensional (3D) position and orientation. The relative dimensions of the object can refer to the relative dimensions of the object's 3D enclosing cuboid, and can be expressed as the ratio of the width, height, and length of the 3D enclosing cuboid. The system for object pose estimation can calculate the object's 6-DoF pose and relative dimensions from an image depicting the object.

[0062] In one embodiment, the system for object pose estimation acquires RGB (red-green-blue) images depicting objects of a specific category. The category can refer to a classification or class of objects, where objects belonging to that category can be similar; for example, a category referred to as "mug" could include instances of mugs with different colors, sizes, with or without handles, and / or variations thereof. The system can utilize a neural network to extract features from the image and compute individual outputs based at least in part on the extracted features. In some embodiments, the output includes an indication of the object's bounding box center, an indication of the bounding box size, an indication of the vertices of the cuboid the object surrounds, and the relative dimensions of the cuboid. The system can decode one or more of these outputs and utilize an n-point perspective (PnP) algorithm to compute the object's 6-DoF pose and relative dimensions. The system can be trained using various training images depicting objects with annotations indicating the object's 6-DoF pose and relative dimensions.

[0063] The system can perform category-level object pose estimation using a single-stage, keypoint-based approach, and can detect, compute 6-DoF poses, and estimate the relative dimensions of unseen object instances within known categories. The system can utilize neural networks to perform 2D object detection, keypoint detection, and regression of the relative dimensions of the enclosing cuboid, which can be estimated sequentially. The system may include post-processing steps to extract the cuboid's vertex coordinates and relative dimensions. The system can be used in various contexts, such as for robotic grasping of unknown objects. For example, a robotic arm operating in an unconstrained environment can use the system to determine what objects are nearby and where they are located (e.g., 6-DoF poses), allowing the robotic arm to grasp objects in a semantically meaningful manner.

[0064] In various embodiments, the system performs category-level pose estimation, which involves inferring the pose and relative size of all objects within a specific category using RGB images processed by a single neural network. The system can handle all instances within a specific category. The system can be based on an RGB-based method (e.g., without depth) and may require 3D bounding box annotations during training. The system can be trained using various datasets, such as the Objectron dataset or any suitable dataset.

[0065] This system can utilize a single-step neural network to regress object locations in an image, 2D keypoint projections of 3D bounding box vertices, and the relative size of the bounding box. To handle intra-class shape variations, the system can utilize dual representations of displacement and heatmaps for keypoint detection. During inference, since objects within the same class can have different 3D aspect ratios, the system can estimate the relative cuboid size using various PnP algorithms. The system can group network output patterns according to complexity and compute each output group using convolutionally gated recurrent units (convGRUs) that sequentially refine the hidden states from the bottom layer; in this way, the complexity and / or difficulty of predicting subsequent groups can be reduced by using information from previous groups stored in the hidden states.

[0066] In one embodiment, the system utilizes a single-step keypoint-based network to detect previously unseen objects of known categories from RGB images (e.g., without depth) and estimates their 6-DoF pose and relative bounding box size. The system can perform 2D keypoint detection using a combined representation of displacement and heatmaps and can estimate the relative size of a 3D bounding box. In some examples, the system leverages sequential feature associations to improve the accuracy of estimating multiple groups of outputs from the network.

[0067] Various techniques have been described above and below. For illustrative purposes, specific configurations and details have been presented to provide a thorough understanding of the possible ways to implement these techniques. However, it is also apparent that the techniques described below can be practiced in different configurations without specific details. Furthermore, well-known features may be omitted or simplified to avoid obscuring the described techniques.

[0068] The techniques described and suggested in this disclosure improve the field of object pose estimation by providing a system that determines the 6-DoF pose and relative dimensions of an object from a single RGB image depicting the object. Furthermore, the techniques described and suggested in this disclosure improve the speed and accuracy of robotic systems that require 6-DoF pose and / or relative dimension information for individual object grasping tasks. Moreover, the techniques described and suggested in this disclosure must be rooted in computer technology to overcome the specific problems that arise from using a single RGB image of an object to determine its 6-DoF pose and / or relative dimensions.

[0069] Figure 1 Example 100 of a system for object pose estimation according to at least one embodiment is illustrated. In some examples, system 102 for object pose estimation is referred to as a single-step keypoint-based category-level object pose estimation from an RGB image system and / or its variants. System 102 for object pose estimation can predict the 2D projection of the corners of a 3D-enclosing cuboid, followed by a PnP algorithm. System 102 for object pose estimation can directly estimate all predictions via a single-step network, including the relative dimensions of the cuboid, which can be used in the PnP algorithm. System 102 for object pose estimation can include a ratio Figure 1 The components shown may be fewer or more components, which may include any suitable functionality.

[0070] In at least one embodiment, the system 102 for object pose estimation is a collection of one or more hardware and / or software computing resources having instructions, when executed, to calculate the 6-DoF pose and relative size of an object depicted in an image. The system 102 for object pose estimation can be a software program, application program, software module, and / or variations thereof, executing on computer hardware. In some examples, one or more processes of the system 102 for object pose estimation are executed by any suitable processing system or unit (e.g., graphics processing unit (GPU), parallel processing unit (PPU), central processing unit (CPU)) in any suitable manner, including sequential, parallel, and / or variations thereof.

[0071] System 102 for object pose estimation may receive or otherwise acquire input image 104 and provide input image 104 to feature extraction 106 for computation of feature maps. Feature extraction 106 may output feature maps to groups 108, 116, and 124. Group 108 may compute object center heatmap 110, object center offset 112, and 2D bounding box size 114; group 116 may compute keypoint heatmap 118, keypoint offset 120, and XY displacement 122; and group 124 may compute relative size 126. Groups 108, 116, and 124 may be part of a convGRU network. The 2D keypoint output decoder 128 can process the object center heatmap 110, object center offset 112, 2D bounding box size 114, keypoint heatmap 118, keypoint offset 120, and XY displacement 122, and the PnP algorithm 130 can process the output of the 2D keypoint output decoder 128, relative size 126, and camera intrinsic parameters 132 to calculate 6-DoF pose and size 134.

[0072] In one embodiment, the input image 104 is an image of any suitable image format (e.g., red-green-blue (RGB) image, black / white (B / W) image, grayscale image, RGB-D image, and / or variations thereof), which may be stored or otherwise encoded using any suitable image file format (e.g., bitmap image file, JPEG (Joint Image Experts Group) file, SVG (Scalable Vector Graphics) file, and / or variations). The input image 104 may be a video frame. The input image 104 may be captured by one or more image and / or video capture systems. In one embodiment, the input image 104 may be captured from one or more systems of an autonomous device (such as a robot). The input image 104 may be captured from any suitable system, such as a vehicle system (e.g., an autonomous vehicle, a semi-autonomous vehicle), a medical device (e.g., a medical imaging device), an autonomous device (e.g., a robot), and / or any suitable system.

[0073] In some examples, the input image 104 is an RGB image with a resolution (e.g., height × width) represented by H × W. The system 102 for object pose estimation can rescale and / or pad the input image 104 such that W = H = 512. The input image 104 can be represented as Input image 104 can be provided to feature extraction 106. In at least one embodiment, feature extraction 106 is a collection of one or more hardware and / or software computing resources having instructions that, when executed, compute one or more feature maps from the image. Feature extraction 106 can be a software program, application program, software module, and / or variations thereof executing on computer hardware, and may be part of system 102 for object pose estimation.

[0074] Feature extraction 106 can implement various neural network processes to generate feature maps from input image 104. Feature extraction 106 can perform any suitable feature extraction process, such as those including operations such as convolution, pooling, upsampling, downsampling, aggregation, concatenation, skip connections, activation functions, projection, interpolation, normalization, and / or variations thereof, to generate feature maps. In one embodiment, a feature map, which may be called an activation map, is a set of data used to indicate the output activation of a given filter. Feature maps can indicate the output of one or more operations applied to the input. Feature maps can indicate various features of the image. In some examples, the channels of the feature map correspond to various features and / or aspects of the feature map. In at least one embodiment, each channel of the feature map represents an aspect of information, such as a particular feature (e.g., edge, corner), a particular color (e.g., red, blue, green), and / or variations thereof. Feature extraction 106 can perform any suitable process for determining feature maps from input image 104. Feature maps can be represented as...

[0075] In one embodiment, feature extraction 106 implements a neural network such as a Deep Aggregation (DLA) 34 network combined with upsampling, where hierarchical aggregation connections are enhanced by deformable convolutional layers. Feature extraction 106 can generate multiple intermediate feature maps at different resolutions, ranging from H / 4×W / 4 to H / 32×W / 32, or any suitable resolution, which can be aggregated into a single output (with H / 4×W / 4 resolution or any suitable resolution). Feature extraction 106 can output the feature maps to groups 108, 116, and 124.

[0076] Groups 108, 116, and 124 can be part of a convGRU network. In one embodiment, the convGRU network is a neural network utilizing one or more gated recurrent units (GRUs) and one or more convolutional operations. The convGRU network can utilize fully convolutional networks, recurrent neural networks, and / or variants thereof. The convGRU network can output various data (e.g., object center heatmap 110, object center offset 112, 2D bounding box size 114, keypoint heatmap 118, keypoint offset 120, XY displacement 122, and relative size 126), where groups 108, 116, and 124 can each correspond to one or more outputs. The convGRU module can associate features with three consecutive groups and regress on a total of seven different outputs, where each output can be... In this context, c represents the number of channels. In one embodiment, groups 108, 116, and 124 each correspond to one or more layers of the convGRU network. In some examples, some network outputs of this network are more complex and / or harder to learn than the network outputs of other networks, where the outputs can be divided into three groups (e.g., groups 108, 116, and 124).

[0077] Group 108 may correspond to object center heatmap 110, object center offset 112, and 2D bounding box size 114. Group 116 may correspond to keypoint heatmap 118, keypoint offset 120, and XY displacement 122. Group 124 may correspond to relative size 126, also known as relative cuboid size. Group 124 may be complex and / or difficult to estimate because, in some examples, the 3D structure is implicitly derived from the 2D appearance. In some embodiments, once the object centroid and 2D bounding box are estimated, keypoints are easier to find, and similarly, once the keypoints are found, the bounding box size is easier to determine. One or more systems may assign different output groups to different time steps in a recurrent neural network. In one embodiment, for system 102 for object pose estimation, given an input image denoted as I, the i-th output (e.g., i = 1, ..., 7, corresponding to object center heatmap 110, object center offset 112, 2D bounding box size 114, keypoint heatmap 118, keypoint offset 120, XY displacement 122, and relative size 126, respectively) is expressed by the following formula, although any variations thereof may be used:

[0078] y i =Ψ i (G t (Φ(I), h t-1 ))

[0079] Where Φ(I) represents the feature map from the backbone network (e.g., feature extraction 106), G t(·) represents the GRU at time step t, h t-1 =G t-1 (Φ(I), h t-2 ) represents the hidden state generated by the GRU unit at the previous time step h0 = 0, while Ψ i Let represent the fully convolutional network with the i-th output. Time steps t = 1, 2, 3 can correspond to three output groups (e.g., group 108, group 116, and group 124).

[0080] System 102 for object pose estimation can implement various output grouping and sequential feature association processes. System 102 for object pose estimation can utilize a single-layer convolutional GRU network, where all convolutional layers in the convGRU are set to stride = 1, kernel size = 3, and output channels = 64, although any suitable values ​​can be used. The output at a later time step can access the hidden states flowing from its previous time step. The network can have seven output heads (e.g., corresponding to object center heatmap 110, object center offset 112, 2D bounding box size 114, keypoint heatmap 118, keypoint offset 120, XY displacement 122, and relative size 126), arranged in three groups (e.g., group 108, group 116, and group 124). Output heads can refer to one or more layers, processes, etc., of the neural network that produce the output. For each output head, the system 102 for object pose estimation can utilize a 3×3 convolutional layer with 256 channels, followed by a 1×1 convolutional layer, to produce the output, or any suitable layer of appropriate size and / or channels. In one embodiment, the output is predicted as a dense heatmap or regression map, but sparsely accessed corresponding to the detected object centers, as described in further detail herein.

[0081] In at least one embodiment, group 108 is a collection of one or more hardware and / or software computing resources having instructions that, when executed, perform one or more neural network processes. Group 108 may be a software program, application program, software module, and / or variations thereof executing on computer hardware, which may be part of system 102 for object pose estimation. Group 108 may implement one or more layers and / or processes of a neural network that process feature maps to output object center heatmap 110, object center offset 112, and 2D bounding box size 114. Group 108 may process a set of features (e.g., feature maps) to determine or otherwise predict a first set of data and / or values ​​indicative of object center heatmap 110, object center offset 112, and 2D bounding box size 114.

[0082] In one embodiment, object center heatmap 110 is a heatmap indicating one or more centers of one or more objects depicted in an image (e.g., input image 104). In some examples, the heatmap is a graphical representation of data that utilizes color coding to represent different values ​​and / or magnitudes of a phenomenon (e.g., color gradients, where lighter colors represent lower values ​​and / or magnitudes, darker colors represent higher values ​​and / or magnitudes, and / or variations thereof). The heatmap may be defined by color values ​​(e.g., confidence values) corresponding to the values ​​of the phenomenon. Object center heatmap 110 may be an image or other visualization. Object center heatmap 110 may include a confidence value corresponding to each pixel of input image 104. The confidence value may refer to a probability value determined by a neural network for the output, indicating the probability that the output is correct. As an illustrative example, the values ​​of object center heatmap 110 correspond to pixels of input image 104 and to confidence values ​​indicating the confidence level of a pixel's location corresponding to the center of an object.

[0083] The object center heatmap 110 may include peaks indicating the center of the 2D bounding box of all detected objects in the input image 104. In one embodiment, the peak of the heatmap refers to the location in the heatmap corresponding to the maximum confidence value (e.g., a first maximum, a second maximum, etc.). In some embodiments, other output maps are accessed relative to the object center, such that if in the (c x c y If the peak value is found in the heatmap of the object center at the location indicated by ), then the remaining output (c) x c y The value at () is associated with the object.

[0084] A bounding box can refer to a box or rectangular shape that indicates the location of an object. In some examples, a 2D bounding box is defined as the smallest rectangle that encloses the extreme points of the 3D bounding box surrounding the projection. Object center offset 112 can be a set of data indicating one or more offset values. Object center offset 112 can include two sets of data, each set including the value of each pixel in the input image 104. The first set of data can include offset values ​​in the x-axis direction, and the second set of data can include offset values ​​in the y-axis direction. The offset values ​​can be used by the system 102 for object pose estimation to recover discretization errors that may be caused by the resolution of the heatmap output. In some examples, the system 102 for object pose estimation (e.g., via 2D keypoint output decoding 128) determines the pixel coordinates of the input image 104 corresponding to the peak of the object center heatmap 110 and uses the offset values ​​from the object center offset 112 corresponding to the pixel coordinates to further refine the determination of the object center in the input image 104.

[0085] The 2D bounding box size 114 can be a set of data indicating the width and height values ​​of the object's bounding box. The 2D bounding box size 114 can include two sets of data, each including the value for each pixel of the input image 104. The first set of data can include width values, and the second set can include height values. The system 102 for object pose estimation can utilize the 2D bounding box size 114 to determine the size of the bounding box of the object depicted in the input image 104. In some embodiments, the system 102 for object pose estimation (e.g., via 2D keypoint output decoding 128) determines the pixel coordinates of the input image 104 corresponding to the center of the object and uses the width and height values ​​from the 2D bounding box size 114 corresponding to the pixel coordinates to determine the size of the object's bounding box.

[0086] In at least one embodiment, group 116 is a collection of one or more hardware and / or software computing resources having instructions that, when executed, perform one or more neural network processes. Group 116 may be a software program, application program, software module, and / or variant thereof executing on computer hardware, which may be part of system 102 for object pose estimation. Group 116 may implement one or more layers and / or processes of a neural network that process feature maps to output keypoint heatmap 118, keypoint offset 120, and XY displacement 122. Group 116 may process a set of features (e.g., feature maps) to compute or otherwise predict a second set of data indicating keypoint heatmap 118, keypoint offset 120, and XY displacement 122. System 102 for object pose estimation may utilize group 116 to determine the aspects of the enclosing cuboid of an object depicted in input image 104. The enclosing cuboid (also referred to as a 3D bounding box, 3D enclosing cuboid, and / or variant thereof) may refer to a cuboid indicating the 3D position and orientation of an object within an image.

[0087] In one embodiment, keypoint heatmap 118 is one or more heatmaps indicating keypoints of the 3D bounding box of an object depicted in an image (e.g., input image 104). Keypoint heatmap 118 may include one or more images or other visualizations. Each heatmap in keypoint heatmap 118 may include a confidence value corresponding to each pixel of input image 104. As an illustrative example, the values ​​of the heatmaps in keypoint heatmap 118 correspond to pixels in input image 104 and to confidence values ​​indicating the confidence level of a pixel's position relative to a vertex of the object's 3D bounding box. Keypoint heatmap 118 may include eight heatmaps, each of which may correspond to a keypoint of the 3D bounding box of the object in input image 104. The heatmaps in keypoint heatmap 118 may include peaks indicating keypoint positions. In one embodiment, a keypoint corresponds to a vertex of the 3D bounding box. Keypoints may be indicated by 2D coordinates projected onto the vertices of the 3D bounding box in image space. In one embodiment, the keypoint heatmap 118 includes a set of eight keypoint heatmaps, wherein the peaks of the heatmaps indicate the 2D coordinates of the projected 3D vertices.

[0088] Keypoint offset 120 can be a dataset indicating one or more offset values. Keypoint offset 120 can include 16 sets of data, where each set includes the value of each pixel in the input image 104. Each set of data in keypoint offset 120 can include an offset value in a specific direction (e.g., the x-axis or y-axis direction) for a particular keypoint. For each keypoint, a first set of data can include the offset value of the first keypoint in the x-axis direction, a second set of data can include the offset value of the first keypoint in the y-axis direction, a third set of data can include the offset value of the second keypoint in the x-axis direction, a fourth set of data can include the offset value of the second keypoint in the y-axis direction, and so on. In one embodiment, there are eight keypoints, where each keypoint corresponds to a vertex of a 3D bounding box. The offset values ​​can be used by the system 102 for object pose estimation to mitigate the discretization error of each vertex. In some examples, system 102 for object pose estimation (e.g., via 2D keypoint output decoding 128) determines the pixel coordinates of input image 104 corresponding to peaks in the heatmap of keypoint heatmap 118 corresponding to specific keypoints, and further refines the determination of specific keypoints using offset values ​​from keypoint offset 120 corresponding to the pixel coordinates. System 102 for object pose estimation (e.g., via 2D keypoint output decoding 128) can use keypoint heatmap 118 and keypoint offset 120 to determine the pixel coordinates of each keypoint of the 3D bounding box of the object depicted in input image 104.

[0089] XY displacement 122 can be a set of data indicating one or more vectors. XY displacement 122 can include sixteen sets of data, each indicating one or more vectors. XY displacement 122 can indicate vectors that indicate keypoint locations. In some examples, set 116 regresses XY displacement 122 from the bounding box center point. System 102 for object pose estimation (e.g., via 2D keypoint output decoding 128) can utilize keypoint heatmap 118, keypoint offset 120, and / or XY displacement 122 to compute the pixel coordinates of each keypoint. In one embodiment, during training, a Gaussian kernel centered on ground truth keypoint coordinates, with its variance determined by the size of the 2D bounding box.

[0090] In at least one embodiment, group 124 is a collection of one or more hardware and / or software computing resources having instructions that, when executed, perform one or more neural network processes. Group 124 may be a software program, application program, software module, and / or variations thereof executing on computer hardware, which may be part of a system for object pose estimation 102. Group 124 may implement one or more layers and / or processes of a neural network that process feature maps to output relative dimensions 126. Group 124 may compute or otherwise predict a set of values ​​indicating relative dimensions 126. The relative dimensions of an object (e.g., an object depicted in an image) may refer to the relative dimensions of the object's enclosing cuboid and may be expressed as the ratio of the width, height, and length of the enclosing cuboid.

[0091] The relative size 126 can be a dataset indicating the estimated relative dimensions (e.g., width, height, length) of the 3D enclosing cuboid. The relative size 126 can include three sets of data, each including the value for each pixel of the input image 104. The first set of data can include width values, the second set can include height values, and the third set can include length values. In some examples, the relative values ​​enable the system 102 for object pose estimation to process images acquired using different camera intrinsic parameters without having to retrain one or more networks for object pose estimation. The system 102 for object pose estimation can utilize the y-axis as the principal axis. The ground truth scale can be processed as (x / y, 1, z / y), where the respective ratios x / y and z / y are estimated by the system 102 for object pose estimation. The system 102 for object pose estimation can directly regress each ratio. The system 102 for object pose estimation can utilize the relative size 126 to determine the relative dimensions of the enclosing cuboid of the object depicted in the input image 104.

[0092] In at least one embodiment, the 2D keypoint output decoder 128 is a collection of one or more hardware and / or software computing resources with instructions that, when executed, perform one or more decoding processes. The 2D keypoint output decoder 128 may be a software program, application program, software module, and / or variant thereof executing on computer hardware, and may be part of the system 102 for object pose estimation. The 2D keypoint output decoder 128 may calculate keypoint positions based at least in part on object center heatmap 110, object center offset 112, 2D bounding box size 114, keypoint heatmap 118, keypoint offset 120, and / or XY displacement 122.

[0093] The 2D keypoint output decoder 128 can apply pooling operations (e.g., 3×3 max pooling) to a heatmap of the 2D object's center (e.g., object center heatmap 110) to search for all local maxima within a window. For each detected center point, the displacement-based keypoint location can be indicated by the keypoint coordinate offset below the center point (e.g., XY displacement 122). The 2D keypoint output decoder 128 can extract heatmap-based keypoint locations by determining high-confidence peaks in the corresponding heatmap (e.g., keypoint heatmap 118) within the bounding box of the 2D object. The 2D keypoint output decoder 128 can adjust the keypoint location estimate based on the offset (e.g., the offset in keypoint offset 120). The 2D keypoint output decoder 128 can process a first set of data and a second set of data to compute a set of coordinates indicating the keypoint location, which may correspond to the vertices of the object's bounding box. The 2D keypoint output decoder 128 can input the keypoint location into the PnP algorithm 130, where the keypoint location can be indicated by the coordinates of the keypoint location.

[0094] PnP algorithm 130 can acquire keypoint positions calculated by 2D keypoint output decoding 128, relative dimensions 126, and camera intrinsic parameters 132. In at least one embodiment, PnP algorithm 130 is a collection of one or more hardware and / or software computing resources having instructions that, when executed, perform one or more PnP processes. PnP algorithm 130 can be a software program, application program, software module, and / or variant thereof executing on computer hardware, which can be part of a system for object pose estimation 102. PnP algorithm 130 can perform various PnP processes, which can refer to the process of estimating the relative pose (e.g., 3D position and orientation) between a calibrated perspective camera and a 3D object (or between the camera and the entire 3D scene) from a set of visible 3D points with known object coordinates and their 2D projections with known pixel coordinates. PnP algorithm 130 can implement one or more PnP algorithms, such as EPnP, a Levenberg-Marquardt version of PnP, or any suitable PnP algorithm.

[0095] Camera intrinsic parameters 132 may be a set of data indicating intrinsic parameters of the image and / or video capture device used to capture the input image 104. In one embodiment, camera intrinsic parameters, also referred to as camera intrinsic parameters or camera internal parameters, are parameters and / or other information inherent to the image and / or video capture device (such as a camera). Camera intrinsic parameters may include information such as focal length, lens distortion, optical center, and / or variations thereof. The system 102 for object pose estimation may obtain or otherwise provide camera intrinsic parameters 132 from one or more systems connected to one or more image and / or video capture devices. In one embodiment, one or more systems capture the input image 104 and provide camera intrinsic parameters 132 to the system 102 for object pose estimation. Camera intrinsic parameters 132 may also be referred to as a set of data corresponding to an image capture device (e.g., the image capture device that captures the input image 104).

[0096] The PnP algorithm 130 can process keypoint positions calculated from 2D keypoint output decoding 128, relative dimensions 126, and camera intrinsic parameters 132 to output 6-DoF pose and dimensions 134. The PnP algorithm 130 can output a set of values ​​indicating the 6-DoF pose and dimensions 134. The 6-DoF pose and dimensions 134 can be a set of data indicating the 6-DoF pose of an object depicted in the input image 104 and the relative dimensions of its enclosing cuboid. The 6-DoF pose can be indicated by one or more values ​​corresponding to x-axis position, y-axis position, z-axis position, roll axis angle, pitch axis angle, and / or yaw axis angle. The 6-DoF pose can be indicated by the enclosing cuboid (e.g., the coordinates of the vertices of the enclosing cuboid). The 6-DoF pose can be related to the camera's position and / or orientation or any suitable reference point or reference plane. The relative dimensions can be indicated by one or more values ​​corresponding to the aspect ratio of the object's enclosing cuboid. In one embodiment, the reference... Figure 1 The 6-DoF pose and dimension 134 are visually represented by the surrounding cuboid, and the relative dimensions in the 6-DoF pose and dimension 134 are represented by "[W:H:L]", which indicates the ratio of the width (e.g., "W") to the height (e.g., "H") to the length (e.g., "L") of the surrounding cuboid. In some examples, the relative dimensions of the surrounding cuboid are represented by "[W:H:L]", "[W / H / L]", and / or any suitable notation indicating the ratio of the width (e.g., "W") to the height (e.g., "H") to the length (e.g., "L") of the surrounding cuboid.

[0097] The system 102 for object pose estimation can be specific to one or more object categories. The system 102 for object pose estimation can be trained with training data such that it is specific to the object category (e.g., the training data includes images depicting objects of that category). As an illustrative example, the system 102 for object pose estimation is trained to be specific to a class of objects called “mugs,” wherein the system 102 can calculate the 6-DoF pose and relative size of objects depicted in an image belonging to the object category called “mugs,” which can include “mug” objects with different colors, sizes, orientations, and / or variations thereof. In some embodiments, one or more neural networks of the system 102 for object pose estimation can be replicated and trained using training data such that the system 102 is dedicated to objects of one or more categories.

[0098] As an illustrative example, the first set of neural networks in the system 102 for object pose estimation is trained using training data specific to a first class of objects, and the second set of neural networks in the system 102 for object pose estimation is trained using training data specific to a second class of objects. The system 102 for object pose estimation can calculate the 6-DoF pose and relative size of an object in an image that belongs to either the first or second class of objects. Continuing this example, the system for object pose estimation can acquire an image depicting an object in an object class (e.g., the first class), determine one or more features at least in part based on the image, and predict a set of values ​​based on the one or more features that at least indicate the position and relative size of the object in the image. Further continuing this example, the system for object pose estimation can also acquire another image depicting a different object in a different class of objects (e.g., the second class), determine another or more features at least in part based on the other image, and predict another set of values ​​based on the other or more features that at least indicate another position and another relative size of the different object in the other image.

[0099] One or more neural networks and / or various other components of the system 102 for object pose estimation can be copied, modified and / or trained using any suitable training data, such that the system 102 for object pose estimation can calculate the 6-DoF pose and relative size of an object in an image that belongs to any suitable object category.

[0100] One or more systems (such as a training framework) can train one or more neural networks for object pose estimation in system 102. One or more systems may acquire training data from one or more datasets or other systems and utilize that training data to train one or more neural networks for object pose estimation in system 102. The training data may include images showing the 6-DoF pose of the object depicted in the illustrated image and the relative dimensions of its enclosing cuboid. The training data may include images and ground truth data (e.g., indicating the 6-DoF pose of the object depicted in the image and the relative dimensions of its enclosing cuboid). The training data may include images, where each image is associated with a 2D point (e.g., a vertex), centroid, and relative dimensions of the enclosing cuboid of the object depicted in the image.

[0101] In one embodiment, one or more systems utilize heatmaps of the center point and other key points in a point-by-point manner, respectively. and The penalty-reduced focal losses can be represented by the following function, although any variations thereof may be used:

[0102]

[0103] in Y represents the predicted score at the heatmap location represented by (i, j). ij This represents the ground truth value assigned to each point by the Gaussian kernel. In one embodiment, N represents the number of center points in the image, and α and β represent hyperparameters of the focus loss. In some examples, α = 2 and β = 4, although the values ​​can be any suitable values.

[0104] One or more systems can use L1 loss to exploit the... The center offset loss is represented. The predicted offset can be represented by p, the ground truth center point can be represented by R, and the output stride can be represented by R. The low-resolution equivalent of p can be... The offset loss can be defined by the following formula, although any variations thereof can be used:

[0105]

[0106] One or more systems can be calculated, at least in part, based on one or more formulas and / or processes (as described herein). The keypoint offset loss is represented. One or more systems can use L1 loss relative to label (e.g., ground truth) values ​​to compute the 2D bounding box size loss (by...). (represented), key point displacement loss (by) (represented) and relative size loss (by) express).

[0107] One or more systems can compute one or more neural networks of system 102 for object pose estimation. The total loss, which can be a weighted combination of one or more loss terms, can be expressed by the following formula, although any variations thereof may be used:

[0108]

[0109] in Or any suitable value, and λ_bbox = 0.1, or any suitable value. One or more systems can train one or more neural networks for object pose estimation system 102 by computing losses using at least one or more loss functions (such as those described herein) and updating one or more weights, biases, and / or structural connections of one or more neural networks to minimize the loss. One or more systems can continuously compute the loss of one or more neural networks and update one or more neural networks until the computed loss is below a defined threshold, which can be any suitable value. System 102 for object pose estimation can be trained such that the computed loss of one or more neural networks for object pose estimation system 102 is below the defined threshold.

[0110] Figure 2 Example 200 of 6-DoF pose and relative size according to at least one embodiment is shown. The 6-DoF pose and relative size can be consistent with those described herein. A system for object pose estimation can process an image to calculate the 6-DoF pose and relative size of an object depicted in the image, which can be visualized via 6-DoF pose and size visualization 202.

[0111] In one embodiment, 6-DoF pose refers to 3D position and orientation. The 6-DoF pose of an object can be represented by a 3D bounding box (also called a bounding cuboid) or other suitable representation. The 3D bounding box can be indicated by the vertex coordinates of the 3D bounding box. In some examples, the 3D bounding box is visualized on a 2D image and defined by the vertex coordinates of the 3D bounding box within the 2D image.

[0112] The relative dimensions of a 3D bounding box can refer to a set of values ​​indicating the size of the 3D bounding box (e.g., the width, length, and / or height of the 3D bounding box) relative to each other. In one embodiment, the relative dimensions of a 3D bounding box include width, height, and length values ​​that form the width-to-height-to-length ratio of the 3D bounding box (e.g., width, height, and length values). In some examples, the width, height, and length values ​​of the relative dimensions represent the width, height, and length values ​​of the 3D bounding box relative to each other, respectively. The relative dimensions of a 3D bounding box can be represented by the aspect ratio of the 3D bounding box, which indicates the ratio of the width to the height to the length of the 3D bounding box. In various embodiments, the height value is set to a value of 1, and the width and length values ​​are calculated relative to the height value of 1. In various embodiments, any suitable value of the relative dimensions (e.g., width, height, and / or length values) is set to a value of 1, where the remaining two values ​​are calculated relative to the suitable value set to a value of 1. The relative dimensions can be represented by any suitable set of values ​​corresponding to the dimensions of the 3D bounding box and / or the object.

[0113] Systems for object pose estimation can acquire images depicting an object and determine its 6-DoF pose and relative dimensions. (Reference) Figure 2 As an illustrative example, the image depicts a car object, and the system used for object pose estimation determines the car object's 6-DoF pose and relative dimensions. The object's 6-DoF pose and relative dimensions can be visualized using 6-DoF pose and dimension visualization 202.

[0114] In one embodiment, 6-DoF pose and size visualization 202 is a visualization of the 6-DoF pose and relative size of an object in a 2D image. 6-DoF pose and size visualization 202 may include a visualization of a 3D bounding box indicating the 6-DoF pose of the object, and relative size values ​​corresponding to the dimensions of the 3D bounding box. (Reference) Figure 2 As an illustrative example, for an image depicting a car object, the 6-DoF pose and size visualization 202 includes a visualization of a 3D bounding box indicating the 6-DoF pose of the car object, and includes a width value of 2.2, a height value of 1, and a length value of 4.7 (e.g., in...). Figure 2 The relative size values ​​described in the figure are [2.2 / 1 / 4.7], which indicate that the aspect ratio of the 3D bounding box of the car object is 2.2:1:4.7.

[0115] It should be noted that while the example embodiments described herein may relate to six degrees of freedom (6DOF) pose, the techniques described herein are applicable to any suitable pose representation. Systems for object pose estimation can determine the pose of an object from an image, where the pose may correspond to any suitable degree of freedom (e.g., 8DOF, 7DOF, 5DOF, 4DOF, 3DOF, and / or variations thereof), which may correspond to any suitable translation and / or rotation.

[0116] Figure 3 An example 300 of the result of a system for object pose estimation according to at least one embodiment is shown. The system for object pose estimation can process input 302 to compute output 304 using one or more procedures such as those described herein.

[0117] Input 302 can be an input image and can depict one or more objects. See [reference needed] for an illustrative example. Figure 3Input 302 depicts four objects, referred to as a category called a mug. In one embodiment, a category is a classification of objects, where objects categorized into that category can share various characteristics. As an illustrative example, a category called a car could include instances of car objects with different colors, sizes, having or not having specific features and / or variations thereof. A system for object pose estimation can process input 302 and calculate the 6-DoF pose of each object depicted in input 302 and its relative dimensions to the enclosing cuboid to determine output 304.

[0118] Output 304 may include the 6-DoF pose of the object depicted in input 302 and an indication of the relative dimensions of its enclosing cuboid. The 6-DoF pose and relative dimensions can be indicated by values ​​of the enclosing cuboid and relative dimensions. In some examples, the system visualizes the 6-DoF pose and relative dimensions of the object by overlaying the values ​​of the enclosing cuboid and relative dimensions onto the object depicted in the image. See [reference needed] for an illustrative example. Figure 3 Output 304 includes a visualization of the enclosing cuboid of the object depicted in input 302 and the relative size values ​​of the enclosing cuboid.

[0119] One or more systems may use a batch size of 32 or any suitable value, employing one or more GPUs (such as NVIDIA's V-100 GPU) to train one or more neural networks for object pose estimation for 140 epochs or any suitable number of epochs, starting with pre-trained weights from a network such as ImageNet, although in some embodiments, pre-trained weights are not used. Data augmentation may include random flipping, scaling, cropping, color jittering, and / or variations thereof. One or more systems may use an optimizer, such as the Adam optimizer with any suitable learning rate (such as an initial learning rate of 2.5e-4), and may decrease by a factor of 10 over 90 to 120 epochs or any suitable number of epochs. In one embodiment, one or more systems may require approximately 36 hours to train a single class (e.g., using training images between 8k and 32k depending on the class). On a GPU such as NVIDIA's GTX 1080Ti GPU, the inference speed may be approximately 10 frames per second (fps).

[0120] One or more systems can be trained using a dataset such as the Objectron dataset, although any suitable dataset can be used. The dataset can include 15k annotated video clips with more than 4M annotated frames, or any appropriate number of annotated video clips and / or frames. Objects can come from nine categories: bicycle, book, bottle, camera, cereal box, chair, cup, laptop, and shoe, although any suitable category can be used. In one embodiment, each object is annotated with its 3D bounding cuboid, which describes the object's position and orientation relative to the camera, as well as the cuboid's dimensions. For each video recording, the camera may move around the stationary object, capturing it from different angles. Additional metadata may include camera pose, sparse point cloud, and surface planes, the latter assuming the object is located on a ground plane, which may introduce an absolute scaling factor.

[0121] For training, to improve efficiency, one or more systems can extract frames by temporally downsampling the original video at fps (such as 15fps). For testing, one or more systems can evaluate the top 5000 test samples in each category of the dataset, or any suitable number of test samples that can be randomly shuffled. In some examples, the cup category includes both cups and mugs, where the former has no handle. Therefore, one or more systems can manually distinguish these by training separate networks for each. One or more systems can rotate certain ground reality bounding boxes by 180 degrees to ensure consistent orientation.

[0122] For symmetrical objects like cups, one or more systems can generate a set of {y1, ..., y2}. |θ| The system represents multiple ground-based labels, which, during this training phase, are rotated around an axis of symmetry |θ|, where |θ| = 12 or any suitable value. One or more systems can compute the values ​​generated by... The symmetric loss is represented by, where Indicates prediction, This indicates asymmetric loss.

[0123] One or more systems may utilize various metrics of the results from the system used for object pose estimation. In one embodiment, to evaluate 3D detection and object size estimation, one or more systems utilize the average precision (AP) of a 3D IoU metric with a threshold of 50%, or any suitable metric and / or threshold. A 2D pixel projection error metric can be calculated as the mean-normalized distance between the projections of keypoints in the 3D bounding box of a given estimated pose and the ground-based pose. For viewpoint estimation, one or more systems may utilize the AP for azimuth and elevation angles, with thresholds of 15° and 10°, respectively, or any suitable values. For symmetrical object categories (e.g., bottles and cups), one or more systems may rotate the ground-based bounding box N times (e.g., N = 100) along the axis of symmetry and evaluate the prediction with respect to each rotation instance. In one embodiment, the reported number is the instance that maximizes 3D IoU or minimizes 2D pixel projection error, respectively. Although the cup category may include asymmetrical mug instances, one or more systems may treat them as symmetrical. For ablation studies of relative size prediction, one or more systems can utilize the mean relative size error, which calculates the relative error of all predictions of the relative size, by... It means that among them This represents a prediction, and y i It represents the actual ground conditions, although any appropriate error can be utilized.

[0124] Figure 4 Example 400 of the result values ​​of a system for object pose estimation according to at least one embodiment is shown. In one embodiment, Figure 4 Results for one or more class-level 6-DoF pose and size estimation tasks are described. One or more systems can be compared to one or more systems such as one-step MobilePose and two-step networks. One or more systems can utilize datasets such as the Objectron dataset. Figure 4 The system can depict the results of 3D IoU, 2D pixel projection error, and azimuth and elevation angles. The system for object pose estimation outperforms MobilePose on all metrics, while the two-step method achieves better performance on 2D correlation metrics but lags behind on 3D IoU metrics.

[0125] Figure 5 Another example 500 of the resulting values ​​of a system for object pose estimation according to at least one embodiment is shown. In one embodiment, Figure 5The results of ablation experiments on different keypoint representations are depicted. Systems for object pose estimation can utilize heatmaps and displacement representations for 2D keypoint detection. One or more systems can utilize ablation experiments to compare various ways of utilizing this representation, such as, for example, although any of its variations can be used: 1) displacement, ignoring the heatmap; 2) heatmap, ignoring displacement; 3) heatmap and displacement; 4) distance, where a heuristic is used to select points to use from either displacement or heatmap; 5) sampling, where a Gaussian mixture model is applied to heatmap peak estimation, and displacement predictions for each keypoint and multiple points (represented by N (e.g., N=20)) are sampled to obtain possible pose distributions. Reference Figure 5 As shown, a system for object pose estimation outperforms one or more other systems by utilizing heatmaps and displacements.

[0126] Figure 6 Another example 600 of the resulting values ​​of a system for object pose estimation according to at least one embodiment is shown. In one embodiment, Figure 6 The results of ablation experiments regarding the prediction of cuboid dimensions are described. Figure 6 Ablation experiments of convGRU for predicting relative cuboid dimensions can be depicted. One or more systems can be compared to variations of systems used for object pose estimation, such as, for example, although any of its variations can be utilized: 1) oracle, which can refer to a system capable of accessing ground-real 3D aspect ratios (e.g., relative dimensions); 2) keypoint lifting, where the final pose can be retrieved using only 2D projected cuboid keypoints using one or more post-processing steps; 3) without convGRU, where the convGRU layer is removed from the system used for object pose estimation; and 4) with convGRU, also referred to as a system used for object pose estimation. In one embodiment, Figure 6 The results using 3D IoU metrics are depicted. In some examples, the maximum improvement is calculated for two specific categories (e.g., books and laptops), which can be complex due to different 3D aspect ratios (e.g., whether the laptop is open or closed). When using PnP algorithms (such as simplified EPnP variants), one or more systems can determine this performance degradation, indicating that predicting the relative size of the category-level pose estimate from monocular RGB input is a complete process.

[0127] Figure 7 Example 700 illustrating key point representations according to at least one embodiment is shown. In one embodiment, Figure 7 Two different keypoint representations are depicted, as described herein. The cycle can be determined by this displacement, and the heatmap keypoints can be overlaid with shadows corresponding to their intensity. In one embodiment, reference... Figure 7On the left, the heatmap is more accurate when the corners of the bounding box are visible and aligned with the object, while on the right, the displacement is better when the corners of the bounding box are not tightly fitted to the target surface (e.g., the top of a laptop).

[0128] Figure 8 Another example 800 of the results of a system for object pose estimation according to at least one embodiment is shown. In one embodiment, Figure 8 One or more enclosing cuboids are depicted. Cuboid 802 may represent a ground reality cuboid, cuboid 804 may represent a system for object pose estimation cuboids without a feature association module (e.g., convGRU), and cuboid 806 may represent a system for object pose estimation cuboids with such a module.

[0129] In some examples, estimating the thickness of a thin object is complex when viewed from an angle (e.g., an azimuth angle close to 90°). In one embodiment, Figure 8 This describes the ability of a convGRU (e.g., cuboid 806) to retrieve the 3D aspect ratio (e.g., relative size) of an object when comparing it without a convGRU (e.g., cuboid 804), even if the 2D keypoints may appear accurate. In one embodiment, one or more systems calculate a 3D IoU (↑) value of 0.5059 (with convGRU) versus 0.3204 (without convGRU), although the value can be any suitable value. In one embodiment, one or more systems evaluate the system for object pose estimation with and without convGRU on a relative aspect ratio metric, although the value can be any suitable value, resulting in an error of 0.38 (without convGRU) versus 0.34 (with convGRU), indicating that convGRU helps retrieve the cuboid aspect ratio. Improvements for the book and notebook categories might be values ​​of 0.80 versus 0.68, and 0.92 versus 0.64, although the value can be any suitable value.

[0130] In some examples, one or more systems utilize systems for object pose estimation within various robotic systems. Systems for object pose estimation can be used for robotic grasping tasks. In some embodiments, a robotic gripper is used in conjunction with a robot arm, and one or more systems use a camera mounted on another arm of the robot to capture images. In one embodiment, a ReFlex TakkTile2 gripper and a Baxter robot, or any suitable robotic hardware, are used. When an object is detected and its pose is estimated (e.g., via the system for object pose estimation), the gripper can be moved to a position intended to be slightly above the object, after which the gripper can be closed and lifted a specific distance (e.g., 15 cm). The robotic system can grasp previously unseen instances from each of three object categories: cereal boxes, cups, and shoes. In one embodiment, all objects were successfully grasped in two attempts, with a 93.3% grasp rate on the first attempt.

[0131] It should be noted that while the various results and / or result values ​​described herein can be indicated by specific results and / or result values, the results and / or result values ​​can be any suitable results and / or result values, which may depend on the conditions and / or variations thereof used to determine the results and / or result values. Variations in results and / or result values ​​are within the scope of this disclosure.

[0132] Systems for object pose estimation can perform single-step, class-level 6-DoF pose prediction for previously unseen object instances. These systems may not require various 3D models of instances during training and / or testing, and training may not require synthetic data. For 2D keypoint detection, systems for object pose estimation can mitigate uncertainty by leveraging a combination of displacement and heatmap representations. Systems for object pose estimation can estimate the relative dimensions of a 3D bounding box. To further improve accuracy, systems for object pose estimation can utilize convGRU sequence feature associations. Systems for object pose estimation can be evaluated using datasets such as the Objectron dataset, in conjunction with one or more other systems. Systems for object pose estimation can be leveraged in a variety of contexts, including robotic grasping tasks and various other real-world applications. Systems for object pose estimation can be class-specific, combined with differential rendering, and utilize post-iterative refinement.

[0133] Figure 9An example of a process 900 for a system for object pose estimation according to at least one embodiment is illustrated. In at least one embodiment, part or all of process 900 (or any other process described herein, or variations and / or combinations thereof) is executed under the control of one or more computer systems configured with computer-executable instructions and implemented as code (e.g., computer-executable instructions, one or more computer programs, or one or more application programs) jointly executed on one or more processors by hardware, software, or a combination thereof. In at least one embodiment, the code is stored in the form of a computer program on a computer-readable storage medium comprising a plurality of computer-readable instructions executable by one or more processors. In at least one embodiment, the computer-readable storage medium is a non-transitory computer-readable medium. In at least one embodiment, at least some of the computer-readable instructions available for executing process 900 are not stored using only transient signals (e.g., propagating transient electrical or electromagnetic transmissions). In at least one embodiment, the non-transitory computer-readable medium does not necessarily include non-transitory data storage circuitry (e.g., buffers, caches, and queues) within a transient signal transceiver. In at least one embodiment, process 900 is executed at least partially on a computer system such as those described elsewhere in this disclosure. In one embodiment, process 900 is performed by a system for object pose estimation.

[0134] In at least one embodiment, the system performing at least a portion of process 900 includes executable code for acquiring 902 an image depicting an object of the first category. In one embodiment, the image is an image of any suitable image format (e.g., red-green-blue (RGB) image, black / white (B / W) image, grayscale image, RGB-D image, and / or variations thereof), which may be stored or otherwise encoded using any suitable image file format that encodes image data (e.g., bitmap image file, JPEG (Joint Image Experts Group) file, SVG (Scalable Vector Graphics) file, and / or variations thereof). The image may be a video frame. Any suitable system can be used to capture the image, such as vehicle systems (e.g., autonomous vehicles, semi-autonomous vehicles), medical devices (e.g., medical imaging equipment), autonomous devices (e.g., robots), and / or any suitable system.

[0135] The image may depict objects of the first category. The image may depict objects in any suitable environment or background. The first category may correspond to any suitable category. In some examples, a category is defined as a family of similar objects; for example, a category called "mug" may include instances of mugs with different colors, sizes, handles or not, and / or variations thereof. The image may also depict one or more other objects that may or may not belong to the first category.

[0136] In at least one embodiment, a system performing at least a portion of process 900 includes executable code for generating 904 one or more features at least partially based on an image. The system may utilize neural networks, such as Deep Aggregation (DLA)34 networks with incorporating upsampling, where hierarchical aggregation connections can be enhanced by deformable convolutional layers to generate one or more features from the image. One or more features (also referred to as a set of features) may comprise one or more feature maps at one or more resolutions. In some examples, the system generates multiple intermediate feature maps at different resolutions, ranging from H / 4×W / 4 to H / 32×W / 32, or any suitable resolution, which may be aggregated into a single output with a resolution of H / 4×W / 4, or any suitable resolution, where H represents the height of the image (e.g., measured in pixels) and W represents the width of the image (e.g., measured in pixels).

[0137] In at least one embodiment, a system performing at least a portion of process 900 includes executable code for processing the one or more features using one or more neural networks to determine at least one or more coordinate values ​​and one or more relative size values ​​corresponding to the object. The one or more neural networks may include one or more convGRU networks. The system may use one or more neural networks to process one or more features to determine a first set of data corresponding to the object. The first set of data may include an object center heatmap, an object center offset, and a 2D bounding box size, which may correspond to the object and / or the object's 2D bounding box. In some examples, the first set of data includes a first set of values ​​(e.g., color values) from the object center heatmap. The object center heatmap may be referred to as the first set of heatmaps.

[0138] The system can compute a second set of data based at least in part on one or more features and the determination of a first set of data. The system can use one or more neural networks to compute the second set of data. The system can compute the second set of data based on the determination of the first set of data by utilizing one or more hidden states associated with and / or utilized in the determination of the first set of data. A hidden state can refer to a representation of one or more inputs of the neural network, which can be processed by one or more processes of the neural network. The system can cause one or more neural networks to compute the second set of data using one or more hidden states associated with the determination of the first set of data. The second set of data may include a keypoint heatmap, keypoint offsets, and XY displacements, which may correspond to an object and / or a 3D bounding box of the object. In some embodiments, the second set of data includes a second set of values ​​(e.g., color values) of the keypoint heatmap. The keypoint heatmap may be referred to as the second set of heatmaps. The XY displacements may include a set of vectors corresponding to the vertices of the bounding box of the object.

[0139] The system can calculate a set of values ​​corresponding to the relative dimensions of an object, at least in part, based on calculations of a second set of data. The relative dimensions of the object may refer to the relative dimensions of the object's 3D bounding box. The system can use one or more neural networks to calculate this set of values. The system can calculate the set of values ​​based on calculations of the second set of data by utilizing one or more hidden states associated with and / or used in the calculations of the second set of data. The system can cause one or more neural networks to use one or more hidden states associated with the calculations of the second set of data to calculate the set of values. This set of values ​​may include width, height, and length values, which can form the ratio of the width to the height to the length of the object's 3D bounding box (e.g., the ratio of the width value to the height value to the length value).

[0140] The system can determine one or more coordinate values ​​based on a first set of data and a second set of data. The system can apply pooling operations (e.g., 3×3 max pooling) to a heatmap of the 2D object's center (e.g., an object center heatmap) to search for all local maxima within a window. For each detected center point, the displacement-based keypoint location can be indicated by the keypoint coordinate offset below the center point. The system can extract heatmap-based keypoint locations by determining high-confidence peaks in the corresponding heatmap (e.g., a keypoint heatmap) within the boundary of the 2D object's bounding box. The system can adjust the keypoint location estimate based on the offset (e.g., the offset in a keypoint offset). The system can determine one or more coordinate values ​​indicating the keypoint location. Keypoints can correspond to vertices of the object's 3D bounding box. One or more coordinate values ​​can indicate the coordinates of the keypoint location within the image. In some embodiments, this set of values ​​forms one or more relative size values. Further information regarding the determination of one or more coordinate values ​​and one or more relative size values ​​can be found in... Figure 1 It was found in the description.

[0141] In at least one embodiment, the system performing at least a portion of process 900 includes executable code for processing one or more coordinate values ​​and one or more relative size values ​​using one or more algorithms to calculate the six-degree-of-freedom (6DOF) pose of an object. The one or more algorithms may include one or more PnP algorithms. In some embodiments, the one or more algorithms include one or more neural network models, algorithms, and / or variations thereof. In some embodiments, the system acquires a set of data corresponding to an image capture device that captures images (e.g., camera intrinsic parameters), which may be part of the system, and inputs this set of data into one or more algorithms. The system may enable one or more algorithms to process one or more coordinate values ​​and / or one or more relative size values, wherein one or more algorithms may output the 6DOF pose of the object.

[0142] The 6DOF pose can be indicated by one or more values ​​corresponding to the object's x-axis position, y-axis position, z-axis position, roll axis angle, pitch axis angle, and / or yaw axis angle. The 6DOF pose can be indicated by the coordinates of the vertices of the enclosing cuboid (e.g., the coordinates of the vertices of the enclosing cuboid within the image). The 6DOF pose can be related to the position and / or orientation of the camera (e.g., the camera that captured the image) or any suitable reference point or plane. One or more relative dimension values ​​can be indicated by one or more values ​​corresponding to the aspect ratio of the object's enclosing cuboid.

[0143] In some embodiments, the system (e.g., a system for object pose estimation) calculates the absolute scale based at least in part on one or more relative size values. The absolute scale of an object, also known as absolute size, can refer to the size of the object in the real world. In some examples, the absolute scale of an object corresponds to the size of the enclosing cuboid of the object in the real world. The system may acquire depth information to calculate the absolute scale of the object based on one or more relative size values.

[0144] For example, the system acquires depth information from an image and / or video capture device that captures the image, or other systems associated with that device (e.g., a depth sensor), and uses this depth information to scale one or more relative size values ​​to calculate the absolute scale of the object. In various embodiments, the image and / or video capture device that captures the image is a stereo device (e.g., a stereo camera), where the system utilizes depth information determined based on one or more images captured by the device to scale one or more relative size values ​​to calculate the absolute scale of the object. The system can calculate the absolute scale of the object in any suitable manner.

[0145] As an illustrative example, the system is associated with an image and / or video capture device that moves relative to an object and captures multiple images of the object. The image and / or video capture device may be moved by a robotic appendage or other suitable system. Continuing the example, absolute camera motion information is provided to the system, which may include information such as one or more translations and / or rotations of the device when multiple images are captured. The system may obtain or otherwise have absolute camera motion information provided from various systems associated with robotic appendages, inertial measurement units (IMUs), and / or variations thereof. Further continuing the example, the system utilizes multiple images and absolute camera motion information to process one or more relative size values ​​to calculate an absolute scale of the object. In at least one embodiment, one or more neural networks of the system are trained using images depicting objects of approximately the same size and are trained to predict the absolute scale by regression or otherwise, with one or more neural networks outputting the absolute scale of the object in addition to or instead of one or more relative size values.

[0146] In some examples, the system is associated with one or more robotic systems that utilize the 6DOF pose of an object to perform a robotic grasping task. A robotic grasping task can refer to one or more processes and / or operations in which the robotic system grasps an object (e.g., via a gripper or other robotic appendage associated with the robotic system) and / or moves the object to one or more locations. One or more robotic systems may be located in an environment where the object can be accessed. The system can enable one or more robotic systems to perform object-related robotic grasping tasks using 6DOF poses. The system can send or otherwise transmit data indicating 6DOF poses to one or more robotic systems. In some embodiments, the system is part of and / or has access to one or more robotic systems.

[0147] One or more robotic systems can utilize 6DOF poses to grasp objects. One or more robotic systems can utilize 6DOF poses to determine how to grasp the object. In various embodiments, one or more robotic systems process 6DOF poses to calculate a specific configuration of the robotic gripper associated with the one or more robotic systems, such that the gripper can grasp the object. One or more robotic systems can then grasp the object (e.g., via the gripper) and perform a robotic grasping task, which may involve moving the grasped object (e.g., via the gripper) to one or more locations.

[0148] Systems for object pose estimation can be used in conjunction with any suitable robotic system, such as excavators, garbage trucks, vehicles with robotic appendages, factory robots, recycling center robots, robotic assistants, warehouse robots, and / or variations thereof. As an illustrative example, one or more systems of an excavator may utilize the system for object pose estimation to process images and / or videos captured in association with the excavator to determine the pose of an object depicted in the images and / or videos, wherein one or more systems of the excavator may utilize the determined pose to configure the excavator so that it is capable of grasping, transporting, and / or excavating objects. Systems for object pose estimation can be similarly used to process images and / or videos captured in connection with garbage trucks, vehicles with robotic attachments, factory robots, recycling center robots, robotic assistants, warehouse robots, and / or their variants, to determine the poses of various objects depicted in the images and / or videos. One or more of these systems can utilize the determined poses to enable them to grasp, transport, manipulate, and / or move various objects. Examples of robotic systems that can be used in conjunction with systems for object pose estimation are available. Figures 13A-13D Found it.

[0149] Reasoning and training logic

[0150] Figure 10A Inference and / or training logic 1015 for performing inference and / or training operations associated with one or more embodiments is shown. The following is in conjunction with... Figure 10A and / or Figure 10B Provide details about reasoning and / or training logic 1015.

[0151] In at least one embodiment, the inference and / or training logic 1015 may include, but is not limited to, code and / or data storage 1001 for storing forward and / or output weights and / or input / output data, and / or other parameters for configuring neurons or layers of a neural network trained for and / or used for inference in one or more embodiments. In at least one embodiment, the training logic 1015 may include or be coupled to code and / or data storage 1001 for storing graph code or other software to control timing and / or sequence, wherein weight and / or other parameter information is loaded to configure logic, including integer and / or floating-point units (collectively, arithmetic logic units (ALUs)). In at least one embodiment, code (such as graph code) loads weight or other parameter information into the processor ALU based on the architecture of the neural network to which the code corresponds. In at least one embodiment, the code and / or data storage 1001 stores weight parameters and / or input / output data of each layer of a neural network trained or used in one or more embodiments during forward propagation of input / output data and / or weight parameters during training and / or inference using one or more embodiments. In at least one embodiment, any portion of the code and / or data storage 1001 may be included within other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory.

[0152] In at least one embodiment, any portion of the code and / or data storage 1001 may be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, the code and / or data storage 1001 may be a cache memory, dynamic random-addressable memory (“DRAM”), static random-addressable memory (“SRAM”), non-volatile memory (e.g., flash memory), or other storage. In at least one embodiment, the choice of whether the code and / or data storage 1001 is internal or external to the processor, for example, or composed of DRAM, SRAM, flash memory, or some other storage type, may depend on the available on-chip or off-chip storage space, the latency requirements of the training and / or inference functions being performed, the batch size of the data used in the inference and / or training of the neural network, or some combination of these factors.

[0153] In at least one embodiment, the inference and / or training logic 1015 may include, but is not limited to, code and / or data storage 1005 to store backpropagation and / or output weights and / or input / output data neural networks corresponding to neurons or layers of a neural network trained and / or used for inference in one or more embodiments. In at least one embodiment, during training and / or inference using one or more embodiments, the code and / or data storage 1005 stores weight parameters and / or input / output data for each layer of a neural network trained or used in one or more embodiments during backpropagation of input / output data and / or weight parameters. In at least one embodiment, the training logic 1015 may include or be coupled to code and / or data storage 1005 for storing graph code or other software to control timing and / or sequence, wherein weight and / or other parameter information is loaded to configure logic including integer and / or floating-point units (collectively, arithmetic logic units (ALUs)).

[0154] In at least one embodiment, code (such as graph code) causes the architecture of the neural network corresponding to that code to load weights or other parameter information into the processor ALU. In at least one embodiment, any portion of the code and / or data storage 1005 may be included together with other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory. In at least one embodiment, any portion of the code and / or data storage 1005 may be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, the code and / or data storage 1005 may be cache memory, DRAM, SRAM, non-volatile memory (e.g., flash memory), or other storage. In at least one embodiment, the choice between the code and / or data storage 1005 being internal or external to the processor, for example, whether it consists of DRAM, SRAM, flash memory, or some other type of storage, depends on whether the available storage is on-chip or off-chip, the latency requirements of the training and / or inference functions being performed, the data batch size used in the inference and / or training of the neural network, or some combination of these factors.

[0155] In at least one embodiment, code and / or data storage 1001 and code and / or data storage 1005 may be separate storage structures. In at least one embodiment, code and / or data storage 1001 and code and / or data storage 1005 may be the same storage structure. In at least one embodiment, code and / or data storage 1001 and code and / or data storage 1005 may be partially combined and partially separated. In at least one embodiment, any portion of code and / or data storage 1001 and code and / or data storage 1005 may be included with other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory.

[0156] In at least one embodiment, the inference and / or training logic 1015 may include, but is not limited to, one or more arithmetic logic units (“ALUs”) 1010 (including integer and / or floating-point units) for performing logical and / or mathematical operations at least in part based on or instructed by training and / or inference code (e.g., graph code), the results of which may produce activations (e.g., output values ​​from layers or neurons within a neural network) stored in activation storage 1020, which are functions of input / output and / or weight parameter data stored in code and / or data storage 1001 and / or code and / or data storage 1005. In at least one embodiment, activation is activated in response to execution instructions or other code, and linear algebraic and / or matrix-based mathematical generation performed by ALU 1010 is stored in activation storage 1020, wherein weight values ​​stored in code and / or data storage 1005 and / or code and / or data storage 1001 are used as operands with other values, such as bias values, gradient information, momentum values, or other parameters or hyperparameters, and any or all of these can be stored in code and / or data storage 1005 or code and / or data storage 1001 or other on-chip or off-chip storage.

[0157] In at least one embodiment, one or more processors or other hardware logic devices or circuits include one or more ALUs 1010, while in another embodiment, one or more ALUs 1010 may be located outside the processor or other hardware logic device or the circuitry using them (e.g., a coprocessor). In at least one embodiment, one or more ALUs 1010 may be included within an execution unit of a processor, or otherwise included in a group of ALUs accessible by the execution unit of the processor, which may be within the same processor or distributed among different processors of different types (e.g., a central processing unit, a graphics processing unit, a fixed-function unit, etc.). In at least one embodiment, code and / or data storage 1001, code and / or data storage 1005, and activation storage 1020 may share a processor or other hardware logic device or circuitry, while in another embodiment, they may be located in different processors or other hardware logic devices or circuitry, or in some combination of the same and different processors or other hardware logic devices or circuitry. In at least one embodiment, any portion of activation storage 1020 may be included together with other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory. Furthermore, inference and / or training code may be stored together with other code accessible to the processor or other hardware logic or circuitry, and may be retrieved and / or processed using the processor’s fetch, decode, schedule, execute, exit, and / or other logic circuitry.

[0158] In at least one embodiment, the active memory 1020 may be a cache memory, DRAM, SRAM, non-volatile memory (e.g., flash memory), or other memory. In at least one embodiment, the active memory 1020 may be wholly or partially located inside or outside one or more processors or other logic circuits. In at least one embodiment, the choice of whether the active memory 1020 is internal to or external to the processor may depend on the available on-chip or off-chip storage, the latency requirements for training and / or inference functions, the batch size of data used in inference and / or training the neural network, or some combination of these factors. For example, it may include DRAM, SRAM, flash memory, or other memory types.

[0159] In at least one embodiment, Figure 10A The inference and / or training logic 1015 shown can be used in conjunction with an application-specific integrated circuit (“ASIC”), such as those from Google. Processing unit, from Graphcore TM Inference processing unit (IPU) or from Intel Corp. (e.g., "LakeCrest") processor. In at least one embodiment, Figure 10AThe inference and / or training logic 1015 shown can be used in conjunction with central processing unit (“CPU”) hardware, graphics processing unit (“GPU”) hardware or other hardware (such as field programmable gate array (“FPGA”)).

[0160] Figure 10B An inference and / or training logic 1015 according to at least one embodiment is illustrated. In at least one embodiment, the inference and / or training logic 1015 may include, but is not limited to, hardware logic, wherein computational resources are dedicated or otherwise uniquely used in conjunction with weight values ​​or other information corresponding to one or more layers of neurons within a neural network. In at least one embodiment, Figure 10B The inference and / or training logic 1015 shown can be used in conjunction with an application-specific integrated circuit (ASIC), such as those from Google. Processing unit, from Graphcore TM Inference processing unit (IPU) or from Intel Corp. (e.g., "LakeCrest") processor. In at least one embodiment, Figure 10B The inference and / or training logic 1015 shown can be used in conjunction with central processing unit (CPU) hardware, graphics processing unit (GPU) hardware, or other hardware (e.g., field-programmable gate array (FPGA)). In at least one embodiment, the inference and / or training logic 1015 includes, but is not limited to, code and / or data storage 1001 and code and / or data storage 1005, which can be used to store code (e.g., graph code), weight values, and / or other information, including bias values, gradient information, momentum values, and / or other parameter or hyperparameter information. Figure 10B In at least one embodiment shown, each of code and / or data storage 1001 and code and / or data storage 1005 is associated with dedicated computing resources (e.g., computing hardware 1002 and computing hardware 1006), respectively. In at least one embodiment, each of computing hardware 1002 and computing hardware 1006 includes one or more ALUs that perform mathematical functions (e.g., linear algebraic functions) only on the information stored in code and / or data storage 1001 and code and / or data storage 1005, respectively, and the results of the function execution are stored in activation storage 1020.

[0161] In at least one embodiment, each of the code and / or data storage 1001 and 1005 and the corresponding computing hardware 1002 and 1006 corresponds to a different layer of the neural network, such that activations obtained from one “store / computation pair 1001 / 1002” of the code and / or data storage 1001 and computing hardware 1002 provide input as input to the next “store / computation pair 1005 / 1006” of the code and / or data storage 1005 and computing hardware 1006, in order to reflect the conceptual organization of the neural network. In at least one embodiment, each store / computation pair 1001 / 1002 and 1005 / 1006 may correspond to more than one neural network layer. In at least one embodiment, additional store / computation pairs (not shown) may be included in the inference and / or training logic 1015 following or paralleling the store / computation pairs 1001 / 1002 and 1005 / 1006.

[0162] In at least one embodiment, utilizing Figures 10A-10B The system for object pose estimation is implemented using one or more systems described herein. In at least one embodiment, it utilizes... Figures 10A-10B The image describes one or more systems for determining the pose and relative size of objects from an image. In at least one embodiment, it utilizes... Figures 10A-10B The description of one or more systems implements one or more systems and / or processes, such as combining Figure 1-9 Those described.

[0163] Neural network training and deployment

[0164] Figure 11 Training and deployment of a deep neural network according to at least one embodiment are illustrated. In at least one embodiment, an untrained neural network 1106 is trained using a training dataset 1102. In at least one embodiment, the training framework 1104 is the PyTorch framework, while in other embodiments, the training framework 1104 is TensorFlow, Boost, Caffe, Microsoft Cognitive Toolkit / CNTK, MXNet, Chainer, Keras, Deeplearning4j, or other training frameworks. In at least one embodiment, the training framework 1104 trains the untrained neural network 1106 and enables it to be trained using the processing resources described herein to generate a trained neural network 1108. In at least one embodiment, the weights may be randomly selected or pre-trained using a deep belief network. In at least one embodiment, training may be performed in a supervised, partially supervised, or unsupervised manner.

[0165] In at least one embodiment, supervised learning is used to train an untrained neural network 1106, wherein the training dataset 1102 includes inputs paired with desired outputs for input, or wherein the training dataset 1102 includes inputs with known outputs and the neural network 1106 is manually graded output. In at least one embodiment, the untrained neural network 1106 is trained in a supervised manner, and inputs from the training dataset 1102 are processed, and the resulting outputs are compared with a set of expected or desired outputs. In at least one embodiment, errors are then propagated back through the untrained neural network 1106. In at least one embodiment, a training framework 1104 adjusts the weights controlling the untrained neural network 1106. In at least one embodiment, the training framework 1104 includes tools for monitoring the degree to which the untrained neural network 1106 converges to a model (e.g., a trained neural network 1108) adapted to generate the correct answer (e.g., result 1114) based on input data (e.g., a new dataset 1112). In at least one embodiment, the training framework 1104 repeatedly trains the untrained neural network 1106 while adjusting the weights to improve the output of the untrained neural network 1106 using a loss function and tuning algorithm (e.g., stochastic gradient descent). In at least one embodiment, the training framework 1104 trains the untrained neural network 1106 until the untrained neural network 1106 reaches the desired accuracy. In at least one embodiment, the trained neural network 1108 can then be deployed to implement any number of machine learning operations.

[0166] In at least one embodiment, unsupervised learning is used to train an untrained neural network 1106, wherein the untrained neural network 1106 attempts to train itself using unlabeled data. In at least one embodiment, the unsupervised learning training dataset 1102 will include input data without any associated output data or "ground truth" data. In at least one embodiment, the untrained neural network 1106 can learn groupings within the training dataset 1102 and can determine how each input relates to the untrained dataset 1102. In at least one embodiment, unsupervised training can be used to generate a self-organizing graph in a trained neural network 1108, which is capable of performing operations useful for reducing the dimensionality of the new dataset 1112. In at least one embodiment, unsupervised training can also be used to perform anomaly detection, which allows the identification of data points in the new dataset 1112 that deviate from the normal patterns of the new dataset 1112.

[0167] In at least one embodiment, semi-supervised learning can be used, a technique in which a mixture of labeled and unlabeled data is included in the training dataset 1102. In at least one embodiment, the training framework 1104 can be used to perform incremental learning, for example, through transfer learning techniques. In at least one embodiment, incremental learning enables the trained neural network 1108 to adapt to the new dataset 1112 without forgetting the knowledge injected into the trained neural network 1108 during initial training.

[0168] In at least one embodiment, the training framework 1104 is a framework that incorporates a software development kit such as the OpenVINO (Open Visual Inference and Neural Network Optimization) toolkit. In at least one embodiment, the OpenVINO toolkit is a toolkit such as that developed by Intel Corporation in Santa Clara, California.

[0169] In at least one embodiment, OpenVINO is a toolkit for facilitating the development of applications for various tasks and computations, such as human visual simulation, speech recognition, natural language processing, recommender systems, and / or variations, particularly neural network applications. In at least one embodiment, OpenVINO supports neural networks such as convolutional neural networks (CNNs), recurrent and / or attention-based neural networks, and / or various other neural network models. In at least one embodiment, OpenVINO supports various software libraries, such as OpenCV, OpenCL, and / or variations thereof.

[0170] In at least one embodiment, OpenVINO supports neural network models for a variety of tasks and operations, such as classification, segmentation, object detection, face recognition, speech recognition, pose estimation (e.g., human and / or object), monocular depth estimation, image inpainting, style transfer, action recognition, colorization, and / or variations thereof.

[0171] In at least one embodiment, OpenVINO includes one or more software tools and / or modules for model optimization, also referred to as a model optimizer. In at least one embodiment, the model optimizer is a command-line tool used to facilitate the transition between training and deployment of a neural network model. In at least one embodiment, the model optimizer optimizes the neural network model to execute on various devices and / or processing units, such as GPUs, CPUs, PPUs, GPGPUs, and / or variants thereof. In at least one embodiment, the model optimizer generates an internal representation of the model and optimizes the model to generate an intermediate representation. In at least one embodiment, the model optimizer reduces the number of layers in the model. In at least one embodiment, the model optimizer removes layers from the model used for training. In at least one embodiment, the model optimizer performs various neural network operations, such as modifying the model's input (e.g., adjusting the model's input size), modifying the model's input size (e.g., modifying the model's batch size), modifying the model's structure (e.g., modifying the model's layers), normalizing, standardizing, quantizing (e.g., converting the model's weights from a first representation (e.g., floating-point) to a second representation (e.g., integer)), and / or variants thereof.

[0172] In at least one embodiment, OpenVINO includes one or more software libraries for inference, also referred to as an inference engine. In at least one embodiment, the inference engine is a C++ library or any suitable programming language library. In at least one embodiment, the inference engine is used to infer input data. In at least one embodiment, the inference engine implements various classes to infer input data and generate one or more results. In at least one embodiment, the inference engine implements one or more API functions for processing intermediate representations, setting input and / or output formats, and / or executing models on one or more devices.

[0173] In at least one embodiment, OpenVINO provides various capabilities for heterogeneous execution of one or more neural network models. In at least one embodiment, heterogeneous execution or heterogeneous computing refers to one or more computational processes and / or systems utilizing one or more types of processors and / or cores. In at least one embodiment, OpenVINO provides various software functions for executing programs on one or more devices. In at least one embodiment, OpenVINO provides various software functions for executing programs and / or portions of programs on different devices. In at least one embodiment, OpenVINO provides various software functions for, for example, running a first portion of code on a CPU and a second portion of code on a GPU and / or FPGA. In at least one embodiment, OpenVINO provides various software functions for executing one or more layers of a neural network on one or more devices (e.g., executing a first set of layers on a first device (such as a GPU) and a second set of layers on a second device (such as a CPU).

[0174] In at least one embodiment, OpenVINO includes various functionalities similar to those associated with CUDA programming models, such as various neural network model operations associated with frameworks (such as TensorFlow, PyTorch, and / or variants thereof). In at least one embodiment, OpenVINO is used to perform one or more CUDA programming model operations. In at least one embodiment, the various systems, methods, and / or techniques described herein are implemented using OpenVINO.

[0175] In at least one embodiment, utilizing Figure 11 The system for object pose estimation is implemented using one or more systems described herein. In at least one embodiment, it utilizes... Figure 11 The image describes one or more systems for determining the pose and relative size of objects from an image. In at least one embodiment, it utilizes... Figure 11 The description of one or more systems implements one or more systems and / or processes, such as combining Figure 1-9 Those described.

[0176] Data Center

[0177] Figure 12 An example data center 1200 that can be used with at least one embodiment is shown. In at least one embodiment, the data center 1200 includes a data center infrastructure layer 1210, a framework layer 1220, a software layer 1230, and an application layer 1240.

[0178] In at least one embodiment, such as Figure 12As shown, the data center infrastructure layer 1210 may include a resource coordinator 1212, grouped computing resources 1214, and node computing resources (“nodes CR”) 1216(1)-1216(N), where “N” represents a positive integer (which may be an integer “N” different from the integers used in other diagrams). In at least one embodiment, nodes CR 1216(1)-1216(N) may include, but are not limited to, any number of central processing units (“CPUs”) or other processors (including accelerators, field-programmable gate arrays (FPGAs), graphics processors, etc.), memory storage devices 1218(1)-1218(N) (e.g., dynamic read-only memory, solid-state drives, or disk drives), network input / output (“NWI / O”) devices, network switches, virtual machines (“VMs”), power modules, and cooling modules, etc. In at least one embodiment, one or more nodes CR 1216(1)-1216(N) may be servers having one or more of the aforementioned computing resources.

[0179] In at least one embodiment, the grouped computing resources 1214 may include individual groups (not shown) of node CRs housed in one or more racks, or a plurality of racks (also not shown) housed in data centers in various geographical locations. In at least one embodiment, the individual groups of node CRs within the grouped computing resources 1214 may include computing, networking, memory, or storage resources that can be configured or allocated to support groups of one or more workloads. In at least one embodiment, several node CRs, including CPUs or processors, may be grouped within one or more racks to provide computing resources to support one or more workloads. In at least one embodiment, the one or more racks may also include any number of power modules, cooling modules, and network switches, in any combination.

[0180] In at least one embodiment, resource coordinator 1212 may be configured or otherwise control one or more nodes CR1216(1)-1216(N) and / or grouped computing resources 1214. In at least one embodiment, resource coordinator 1212 may include a Software Design Infrastructure (“SDI”) management entity for data center 1200. In at least one embodiment, resource coordinator 1012 may include hardware, software, or some combination thereof.

[0181] In at least one embodiment, such as Figure 12As shown, framework layer 1220 includes a job scheduler 1222, a configuration manager 1224, a resource manager 1226, and a distributed file system 1228. In at least one embodiment, framework layer 1220 may include a framework of software 1232 supporting software layer 1230 and / or one or more applications 1242 supporting application layer 1240. In at least one embodiment, software 1232 or application 1242 may respectively include web-based service software or applications, such as services or applications provided by Amazon Web Services, Google Cloud, and Microsoft Azure. In at least one embodiment, framework layer 1220 may be, but is not limited to, a free and open-source software web application framework, such as Apache Spark, which can utilize distributed file system 1228 for large-scale data processing (e.g., "big data"). TM (Hereinafter referred to as "Spark"). In at least one embodiment, the job scheduler 1222 may include a Spark driver to facilitate the scheduling of workloads supported by various layers of data center 1200. In at least one embodiment, the configuration manager 1224 may be able to configure different layers, such as software layer 1230 and framework layer 1220 including Spark and a distributed file system 1228 for supporting large-scale data processing. In at least one embodiment, the resource manager 1226 is able to manage cluster or group computing resources mapped to or allocated to support distributed file system 1228 and job scheduler 1222. In at least one embodiment, cluster or group computing resources may include group computing resources 1214 on data center infrastructure layer 1210. In at least one embodiment, the resource manager 1226 may coordinate with resource coordinator 1212 to manage these mapped or allocated computing resources.

[0182] In at least one embodiment, the software 1232 included in the software layer 1230 may include software used by at least a portion of the nodes CR1216(1)-1216(N), the grouped computing resources 1214, and / or the distributed file system 1228 of the framework layer 1220. In at least one embodiment, one or more types of software may include, but are not limited to, Internet web page search software, email virus scanning software, database software, and streaming video content software.

[0183] In at least one embodiment, one or more applications 1242 included in application layer 1240 may include one or more types of applications used by at least a portion of nodes CR1216(1)-1216(N), grouped computing resources 1214, and / or the distributed file system 1228 of framework layer 1220. In at least one embodiment, one or more types of applications may include, but are not limited to, any number of genomics applications, cognitive computing, applications, and machine learning applications, including training or inference software, machine learning framework software (e.g., PyTorch, TensorFlow, Caffe, etc.), or other machine learning applications used in conjunction with one or more embodiments.

[0184] In at least one embodiment, any of the configuration manager 1224, resource manager 1226, and resource coordinator 1212 can perform any number and type of self-modification actions based on any amount and type of data acquired in any technically feasible manner. In at least one embodiment, self-modification actions can mitigate potentially poor configuration decisions by data center operators of data center 1200 and can prevent underutilization and / or poor performance of the data center.

[0185] In at least one embodiment, data center 1200 may include tools, services, software, or other resources to train one or more machine learning models or to use one or more machine learning models to predict or infer information according to one or more embodiments described herein. For example, in at least one embodiment, a machine learning model can be trained by calculating weight parameters based on a neural network architecture using the software and computing resources described above with respect to data center 1200. In at least one embodiment, information can be inferred or predicted using trained machine learning models corresponding to one or more neural networks using the resources described above with respect to data center 1200, by using weight parameters calculated through one or more training techniques described herein.

[0186] In at least one embodiment, the data center may use a CPU, application-specific integrated circuit (ASIC), GPU, FPGA, or other hardware to utilize the aforementioned resources to perform training and / or inference. Furthermore, one or more of the aforementioned software and / or hardware resources may be configured as a service to allow a user to train or perform information inference, such as image recognition, speech recognition, or other artificial intelligence services.

[0187] Inference and / or training logic 1015 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 10A and / or Figure 10BDetails regarding the inference and / or training logic 1015 are provided. In at least one embodiment, the inference and / or training logic 1015 can be implemented in the system. Figure 12 Used in this context for inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0188] In at least one embodiment, utilizing Figure 12 The system for object pose estimation is implemented using one or more systems described herein. In at least one embodiment, it utilizes... Figure 12 The image describes one or more systems for determining the pose and relative size of objects from an image. In at least one embodiment, it utilizes... Figure 12 The description of one or more systems implements one or more systems and / or processes, such as combining Figure 1-9 Those described.

[0189] Autonomous vehicles

[0190] Figure 13A An example of an autonomous vehicle 1300 according to at least one embodiment is shown. In at least one embodiment, the autonomous vehicle 1300 (which may alternatively be referred to herein as "vehicle 1300") may be, but is not limited to, a passenger vehicle, such as a car, truck, bus, and / or another type of vehicle capable of accommodating one or more passengers. In at least one embodiment, vehicle 1300 may be a semi-tractor-trailer for hauling goods. In at least one embodiment, vehicle 1300 may be an aircraft, robotic vehicle, or other type of vehicle.

[0191] Autonomous vehicles can be described according to the levels of automation defined by the National Highway Traffic Safety Administration (“NHTSA”) and the Society of Automotive Engineers (“SAE”) of the U.S. Department of Transportation in their standard “Taxonomy and Definitions for Terms Related to Driving Automation Systems for On-Road Motor Vehicles” (e.g., standard number J3016-201806, published June 15, 2018; standard number J3016-201609, published September 30, 2016; and previous and future versions of this standard). In at least one embodiment, vehicle 1300 may be able to function according to one or more of the levels of autonomous driving from Level 1 to Level 5. For example, in at least one embodiment, vehicle 1300 may be able to perform conditional automation (Level 3), high automation (Level 4), and / or full automation (Level 5).

[0192] In at least one embodiment, vehicle 1300 may include, but is not limited to, components such as chassis, body, wheels (e.g., 2, 4, 6, 8, 18, etc.), tires, axles, and other vehicle components. In at least one embodiment, vehicle 1300 may include, but is not limited to, propulsion system 1350, such as an internal combustion engine, a hybrid powertrain, an all-electric motor, and / or another type of propulsion system. In at least one embodiment, propulsion system 1350 may be connected to the drivetrain of vehicle 1300, which may include, but is not limited to, a transmission, to enable propulsion of vehicle 1300. In at least one embodiment, propulsion system 1350 may be controlled in response to receiving a signal from throttle / accelerator 1352.

[0193] In at least one embodiment, when the propulsion system 1350 is operating (e.g., when the vehicle 1300 is traveling), the steering system 1354 (which may include, but is not limited to, a steering wheel) is used to steer the vehicle 1300 (e.g., along a desired path or route). In at least one embodiment, the steering system 1354 may receive signals from the steering actuator 1356. In at least one embodiment, the steering wheel may be optional for fully automated (Level 5) functionality. In at least one embodiment, the brake sensor system 1346 may be used to operate the vehicle brakes in response to signals received from the brake actuator 1348 and / or brake sensors.

[0194] In at least one embodiment, the controller 1336 may include, but is not limited to, one or more system-on-chips (“SoCs”). Figure 13AA controller 1336 (not shown) and / or a graphics processing unit (“GPU”) provides signals (e.g., representing commands) to one or more components and / or systems of vehicle 1300. For example, in at least one embodiment, controller 1336 may send signals to operate vehicle braking via brake actuator 1348, to operate steering system 1354 via one or more steering actuators 1356, and to operate propulsion system 1350 via one or more throttles / accelerators 1352. In at least one embodiment, one or more controllers 1336 may include one or more onboard (e.g., integrated) computing devices that process sensor signals and output operating commands (e.g., signals representing commands) to enable autonomous driving and / or assist a driver in driving vehicle 1300. In at least one embodiment, one or more controllers 1336 may include a first controller for autonomous driving functions, a second controller for functional safety functions, a third controller for artificial intelligence functions (e.g., computer vision), a fourth controller for infotainment functions, a fifth controller for redundancy in emergency situations, and / or other controllers. In at least one embodiment, a single controller may handle two or more of the functions described above, and two or more controllers may handle a single function and / or any combination thereof.

[0195] In at least one embodiment, one or more controllers 1336 provide signals for controlling one or more components and / or systems of vehicle 1300 in response to sensor data received from one or more sensors (e.g., sensor inputs). In at least one embodiment, sensor data can be received from sensors, including but not limited to one or more Global Navigation Satellite System (“GNSS”) sensors 1358 (e.g., one or more Global Positioning System sensors), one or more RADAR sensors 1360, one or more ultrasonic sensors 1362, one or more LIDAR sensors 1364, one or more inertial measurement unit (IMU) sensors 1366 (e.g., one or more accelerometers, one or more gyroscopes, one or more magnetic compasses, one or more magnetometers, etc.), one or more microphones 1396, one or more stereo cameras 1368, one or more wide-angle cameras 1370 (e.g., fisheye cameras), one or more infrared cameras 1372, one or more surround cameras 1374 (e.g., 360-degree cameras), and remote cameras (…). Figure 13A (not shown in the image), medium-range camera ( Figure 13A(Not shown in the image) One or more speed sensors 1344 (e.g., for measuring the speed of vehicle 1300), one or more vibration sensors 1342, one or more steering sensors 1340, one or more brake sensors (e.g., as part of brake sensor system 1346) and / or other sensor types are received.

[0196] In at least one embodiment, one or more controllers 1336 may receive input (e.g., represented by input data) from the dashboard 1332 of the vehicle 1300 and provide output (e.g., represented by output data, display data, etc.) via a human-machine interface (“HMI”) display 1334, a voice signaler, a speaker, and / or other components of the vehicle 1300. In at least one embodiment, the output may include information such as vehicle speed, velocity, time, map data (e.g., high-definition map). Figure 13A The HMI display 1334 may display information such as (not shown in the image), location data (e.g., the location of vehicle 1300, for example, on a map), direction, the location of other vehicles (e.g., occupancy raster), information about objects, and the state of objects sensed by one or more controllers 1336. For example, in at least one embodiment, the HMI display 1334 may display information about the presence of one or more objects (e.g., road signs, warning signs, traffic light changes, etc.) and / or information about driving operations that the vehicle has already made, is making, or will make (e.g., changing lanes now, exiting exit 34B within two miles, etc.).

[0197] In at least one embodiment, vehicle 1300 further includes a network interface 1324 that can communicate over one or more networks using one or more wireless antennas 1326 and / or one or more modems. For example, in at least one embodiment, network interface 1324 may be able to communicate over Long Term Evolution (“LTE”), Wideband Code Division Multiple Access (“WCDMA”), Universal Mobile Telecommunications System (“UMTS”), Global System for Mobile Communications (“GSM”), IMT-CDMA Multicarrier (“CDMA2000”) networks, etc. In at least one embodiment, one or more wireless antennas 1326 may also enable communication between objects in the environment (e.g., vehicles, mobile devices) using one or more local area networks (e.g., Bluetooth, Bluetooth Low Energy (LE), Z-Wave, ZigBee, etc.) and / or one or more low-power wide area networks (hereinafter “LPWAN”) (e.g., LoRaWAN, SigFox, etc. protocols).

[0198] Inference and / or training logic 1015 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 10A and / or Figure 10B Details regarding the inference and / or training logic 1015 are provided. In at least one embodiment, the inference and / or training logic 1015 can be implemented in the system. Figure 13A The operation is used to infer or predict the operation based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures or neural network use cases described herein.

[0199] Figure 13B The illustration shows an embodiment according to at least one of the embodiments. Figure 13A Examples of camera positions and fields of view for an autonomous vehicle 1300. In at least one embodiment, the camera and its respective field of view are an example embodiment and are not intended to be limiting. For example, in at least one embodiment, additional and / or alternative cameras may be included and / or the cameras may be located at different positions on the vehicle 1300.

[0200] In at least one embodiment, the camera type used for the camera may include, but is not limited to, a digital camera suitable for use with components and / or systems of vehicle 1300. In at least one embodiment, one or more cameras may operate at Automotive Safety Integrity Level (“ASIL”) B and / or other ASILs. In at least one embodiment, the camera type may have any image capture rate, such as 60 frames per second (fps), 1220 fps, 240 fps, etc. In at least one embodiment, the camera may be able to use a rolling shutter, a global shutter, another type of shutter, or a combination thereof. In at least one embodiment, the color filter array may include a red-to-clear (“RCCC”) color filter array, a red-to-clear-blue (“RCCB”) color filter array, a red-blue-green (“RBGC”) color filter array, a Foveon X3 color filter array, a Bayer sensor (“RGGB”) color filter array, a monochrome sensor color filter array, and / or other types of color filter arrays. In at least one embodiment, a transparent pixel camera, such as a camera with an array of RCCC, RCCB and / or RBGC color filters, may be used to improve photosensitivity.

[0201] In at least one embodiment, one or more cameras may be used to perform advanced driver assistance system (“ADAS”) functions (e.g., as part of a redundancy or fail-safe design). For example, in at least one embodiment, a multi-function mono camera may be installed to provide functions including lane departure warning, traffic sign assist, and intelligent headlight control. In at least one embodiment, one or more cameras (e.g., all cameras) may simultaneously record and provide image data (e.g., video).

[0202] In at least one embodiment, one or more cameras may be mounted in a mounting assembly, such as a custom-designed (3D-printed) assembly, to cut out stray light and reflections within the vehicle 1300 (e.g., reflections from the dashboard in the windshield mirror), which may interfere with the camera's image data capture capabilities. Regarding the rearview mirror mounting assembly, in at least one embodiment, the rearview mirror assembly may be 3D-printed custom-made such that the camera mounting plate matches the shape of the rearview mirror. In at least one embodiment, one or more cameras may be integrated into the rearview mirror. In at least one embodiment, for side-view cameras, one or more cameras may also be integrated within four pillars at each corner of the cabin.

[0203] In at least one embodiment, a camera (e.g., a forward-facing camera) having a field of view including a portion of the environment in front of the vehicle 1300 can be used for surround view and, with the assistance of one or more controllers 1336 and / or control SoCs, to help identify forward paths and obstacles, thereby providing information crucial for generating an occupancy grid and / or determining a preferred vehicle path. In at least one embodiment, the forward-facing camera can be used to perform many ADAS functions similar to LIDAR, including but not limited to emergency braking, pedestrian detection, and collision avoidance. In at least one embodiment, the forward-facing camera can also be used for ADAS functions and systems, including but not limited to lane departure warning (“LDW”), adaptive cruise control (“ACC”), and / or other functions (e.g., traffic sign recognition).

[0204] In at least one embodiment, various cameras can be used in a forward-facing configuration, including, for example, a monocular camera platform including a CMOS (“complementary metal-oxide-semiconductor”) color imager. In at least one embodiment, a wide-angle camera 1370 can be used to sense objects entering from the periphery (e.g., pedestrians, crosswalkers, or bicycles). Although in Figure 13B Only one wide-angle camera 1370 is shown; however, in other embodiments, the vehicle 1300 may have any number (including zero) of wide-angle cameras. In at least one embodiment, any number of remote cameras 1398 (e.g., a pair of remote stereo cameras) can be used for depth-based object detection, especially for objects for which a neural network has not yet been trained. In at least one embodiment, the remote camera 1398 can also be used for object detection and classification, as well as basic object tracking.

[0205] In at least one embodiment, any number of stereo cameras 1368 may also be included in a forward configuration. In at least one embodiment, one or more stereo cameras 1368 may include an integrated control unit comprising a scalable processing unit that may provide programmable logic (“FPGA”) and a multi-core microprocessor with a controller area network (“CAN”) or Ethernet interface integrated on a single chip. In at least one embodiment, such a unit may be used to generate a 3D map of the environment of the vehicle 1300, including distance estimates for all points in the image. In at least one embodiment, one or more stereo cameras 1368 may include, but are not limited to, a compact stereo vision sensor, which may include, but is not limited to, two camera lenses (one on the left and one on the right) and an image processing chip that can measure the distance from the vehicle 1300 to a target object and use the generated information (e.g., metadata) to activate autonomous emergency braking and lane departure warning functions. In at least one embodiment, other types of stereo cameras 1368 may also be used in addition to those described herein.

[0206] In at least one embodiment, a camera (e.g., a side-view camera) having a field of view including a portion of the environment on the side of the vehicle 1300 can be used for surround viewing, thereby providing information for creating and updating the occupied grid, and generating a side collision warning. For example, in at least one embodiment, a surround camera 1374 (e.g., as...) Figure 13B The four surround cameras shown can be positioned on vehicle 1300. In at least one embodiment, one or more surround cameras 1374 can include, but are not limited to, any number and combination of wide-angle cameras, one or more fisheye lenses, one or more 360-degree cameras, and / or similar cameras. For example, in at least one embodiment, four fisheye lens cameras can be located at the front, rear, and sides of vehicle 1300. In at least one embodiment, vehicle 1300 can use three surround cameras 1374 (e.g., left, right, and rear) and can utilize one or more other cameras (e.g., forward-facing cameras) as a fourth surround-view camera.

[0207] In at least one embodiment, a camera (e.g., a rear-view camera) having a field of view including a portion of the environment behind the vehicle 1300 can be used for parking assistance, surround view, rear collision warning, and creating and updating occupancy raster. In at least one embodiment, a wide variety of cameras can be used, including but not limited to cameras that are also suitable as one or more forward-facing cameras (e.g., long-range camera 1398 and / or one or more mid-range cameras 1376, one or more stereo cameras 1368, one or more infrared cameras 1372, etc.), as described herein.

[0208] The inference and / or training logic 1015 is used to perform inference and / or training operations associated with one or more embodiments. Figure 10A and / or Figure 10B This document provides details regarding inference and / or training logic 1015. In at least one embodiment, inference and / or training logic 1015 can... Figure 13B Used in systems for reasoning or predicting operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0209] Figure 13C The illustration shows an embodiment according to at least one of the embodiments. Figure 13A A block diagram of an example system architecture for an autonomous vehicle 1300. In at least one embodiment, Figure 13C Each of one or more components, one or more features, and one or more systems of vehicle 1300 is shown as connected via bus 1302. In at least one embodiment, bus 1302 may include, but is not limited to, a CAN data interface (which may alternatively be referred to herein as “CAN bus”). In at least one embodiment, CAN may be a network within vehicle 1300 used to help control various features and functions of vehicle 1300, such as brake actuation, acceleration, braking, steering, windshield wipers, etc. In one embodiment, bus 1302 may be configured to have dozens or even hundreds of nodes, each node having its own unique identifier (e.g., CANID). In at least one embodiment, bus 1302 can be read to find steering wheel angle, ground speed, engine rotation speed (“RPM”), button position, and / or other vehicle status indicators. In at least one embodiment, bus 1302 may be an ASIL B compliant CAN bus.

[0210] In at least one embodiment, FlexRay and / or Ethernet protocols may be used in addition to or from CAN. In at least one embodiment, there may be any number of molded buses 1302, which may include, but are not limited to, zero or more CAN buses, zero or more FlexRay buses, zero or more Ethernet buses, and / or zero or more other types of buses using other protocols. In at least one embodiment, two or more buses may be used to perform different functions and / or may be used for redundancy. For example, a first bus may be used for a collision avoidance function, and a second bus may be used for actuation control. In at least one embodiment, each of the buses 1302 may communicate with any component of the vehicle 1300, and two or more buses 1302 may communicate with corresponding components. In at least one embodiment, each of any number of System-on-Chip (“SoC”) 1304 (e.g., SoC 1304(A) and SoC 1304(B)), each of one or more controllers 1336, and / or each computer within the vehicle may access the same input data (e.g., input from sensors of the vehicle 1300) and may be connected to a common bus, such as a CAN bus.

[0211] In at least one embodiment, vehicle 1300 may include one or more controllers 1336, such as those described herein. Figure 13A As described above. In at least one embodiment, controller 1336 can be used for a variety of functions. In at least one embodiment, controller 1336 can be coupled to any of various other components and systems of vehicle 1300 and can be used to control vehicle 1300, artificial intelligence of vehicle 1300, infotainment and / or other functions of vehicle 1300.

[0212] In at least one embodiment, vehicle 1300 may include any number of SoCs 1304. In at least one embodiment, each of the SoCs 1304 may include, but is not limited to, a central processing unit (“one or more CPUs”) 1306, a graphics processing unit (“one or more GPUs”) 1308, one or more processors 1310, one or more caches 1312, one or more accelerators 1314, one or more data storage 1316, and / or other components and features not shown. In at least one embodiment, one or more SoCs 1304 may be used to control vehicle 1300 on various platforms and systems. For example, in at least one embodiment, one or more SoCs 1304 may be combined with a high-definition (“HD”) map 1322 in a system (e.g., the system of vehicle 1300), the high-definition map 1322 being accessible from one or more servers via a network interface 1324. Figure 13C (Not shown in the image) Get map refresh and / or update.

[0213] In at least one embodiment, one or more CPUs 1306 may include CPU clusters or CPU complexes (which may alternatively be referred to herein as “CCPLEX”). In at least one embodiment, one or more CPUs 1306 may include multiple cores and / or a secondary (“L2”) cache. For example, in at least one embodiment, one or more CPUs 1306 may include eight cores in an intercoupled multiprocessor configuration. In at least one embodiment, one or more CPUs 1306 may include four dual-core clusters, each cluster having a dedicated L2 cache (e.g., 2MB L2 cache). In at least one embodiment, one or more CPUs 1306 (e.g., CCPLEX) may be configured to support simultaneous cluster operation, such that any combination of clusters of one or more CPUs 1306 can be active at any given time.

[0214] In at least one embodiment, one or more CPUs 1306 may implement power management functions, including but not limited to one or more of the following features: automatic clock gating of individual hardware modules to conserve dynamic power when idle; clock gating of each core when the core is not actively executing instructions due to executing Wait for Interrupt (“WFI”) / Event Wait (“WFE”) instructions; independent power supply for each core; independent clock gating for each core cluster when all cores are clock-gated or power-gated; and / or independent power gating for each core cluster when all cores are power-gated. In at least one embodiment, one or more CPUs 1306 may further implement an enhanced algorithm for managing power states, wherein allowed power states and expected wake-up times are specified, and the hardware / microcode determines the optimal power state for cores, clusters, and CCPLEX inputs. In at least one embodiment, the processing core may support a simplified power state input sequence in software, wherein the work is offloaded to the microcode.

[0215] In at least one embodiment, one or more GPUs 1308 may include integrated GPUs (or "iGPUs" herein). In at least one embodiment, one or more GPUs 1308 may be programmable and efficient for parallel workloads. In at least one embodiment, one or more GPUs 1308 may use an enhanced tensor instruction set. In at least one embodiment, one or more GPUs 1308 may include one or more streaming microprocessors, wherein each streaming microprocessor may include a Level 1 ("L1") cache (e.g., an L1 cache with at least 96KB of storage capacity), and two or more streaming microprocessors may share an L2 cache (e.g., an L2 cache with 512KB of storage capacity). In at least one embodiment, one or more GPUs 1308 may include at least eight streaming microprocessors. In at least one embodiment, one or more GPUs 1308 may use a computation application programming interface (API). In at least one embodiment, one or more GPUs 1308 may use one or more parallel computing platforms and / or programming models (e.g., NVIDIA's CUDA model).

[0216] In at least one embodiment, one or more GPU 1308s may be power-optimized for optimal performance in automotive and embedded use cases. For example, in at least one embodiment, one or more GPU 1308s may be fabricated on FinFET (“FinFET”) circuitry. In at least one embodiment, each streaming microprocessor may include multiple mixed-precision processing cores divided into multiple blocks, such as, but not limited to, dividing 64 PF32 cores and 32 PF64 cores into four processing blocks. In at least one embodiment, each processing block may be allocated 16 FP32 cores, 8 FP64 cores, 16 INT32 cores, two mixed-precision NVIDIA Tensor cores for deep learning matrix arithmetic, a level-zero (“L0”) instruction cache, a thread bundle scheduler, a dispatch unit, and / or a 64KB register file. In at least one embodiment, the streaming microprocessor may include independent parallel integer and floating-point data paths to provide efficient execution of workloads that mix computation and addressing operations. In at least one embodiment, the streaming microprocessor may include independent thread scheduling capabilities to enable finer-grained synchronization and collaboration between parallel threads. In at least one embodiment, the streaming microprocessor may include a combined L1 data cache and shared memory unit to improve performance while simplifying programming.

[0217] In at least one embodiment, one or more GPUs 1308 may include high-bandwidth memory (“HBM”) and / or a 16GB HBM2 memory subsystem to provide a peak storage bandwidth of approximately 900GB / s in some examples. In at least one embodiment, in addition to or instead of HBM memory, synchronous graphics random access memory (“SGRAM”) may be used, such as graphics double data rate type five synchronous random access memory (“GDDR5”).

[0218] In at least one embodiment, one or more GPUs 1308 may include unified memory technology. In at least one embodiment, address translation service (“ATS”) support may be used to allow one or more GPUs 1308 to directly access the page tables of one or more CPUs 1306. In at least one embodiment, when a memory management unit (“MMU”) of one or more GPUs 1308 experiences a miss, an address translation request may be sent to one or more CPUs 1306. In response, in at least one embodiment, two CPUs of one or more CPUs 1306 may look up the virtual-physical mapping of the address in their page tables and transfer the translation back to one or more GPUs 1308. In at least one embodiment, unified memory technology may allow a single unified virtual address space to be used for the memory of both one or more CPUs 1306 and one or more GPUs 1308, thereby simplifying the programming of one or more GPUs 1308 and the porting of applications to one or more GPUs 1308.

[0219] In at least one embodiment, one or more GPUs 1308 may include any number of access counters that can track the frequency with which one or more GPUs 1308 access the memory of other processors. In at least one embodiment, one or more access counters can help ensure that memory pages are moved to the physical memory of the processor that accesses the pages most frequently, thereby improving the efficiency of shared memory ranges between processors.

[0220] In at least one embodiment, one or more SoCs 1304 may include any number of caches 1312, including those described herein. For example, in at least one embodiment, one or more caches 1312 may include a Level 3 (“L3”) cache available for one or more CPUs 1306 and one or more GPUs 1308 (e.g., connected to CPUs 1306 and GPUs 1308). In at least one embodiment, one or more caches 1312 may include a write-back cache that can, for example, track the state of a line using a cache coherence protocol (e.g., MEI, MESI, MSI, etc.). In at least one embodiment, although a smaller cache size may be used, according to an embodiment, the L3 cache may include 4 MB of memory or more.

[0221] In at least one embodiment, one or more SoCs 1304 may include one or more accelerators 1314 (e.g., hardware accelerators, software accelerators, or combinations thereof). In at least one embodiment, one or more SoCs 1304 may include a hardware acceleration cluster, which may include optimized hardware accelerators and / or large on-chip memory. In at least one embodiment, large on-chip memory (e.g., 4MB of SRAM) enables the hardware acceleration cluster to accelerate neural networks and other computations. In at least one embodiment, the hardware acceleration cluster may be used to supplement one or more GPUs 1308 and offload some tasks from one or more GPUs 1308 (e.g., freeing up more cycles from one or more GPUs 1308 to perform other tasks). In at least one embodiment, one or more accelerators 1314 may be used for a target workload (e.g., perceptual, convolutional neural network (“CNN”), recurrent neural network (“RNN”), etc.) that is sufficiently stable to withstand acceleration testing. In at least one embodiment, the CNN may include region-based or region convolutional neural networks (“RCNN”) and fast RCNN (e.g., for object detection) or other types of CNNs.

[0222] In at least one embodiment, one or more accelerators 1314 (e.g., a hardware acceleration cluster) may include one or more deep learning accelerators (“DLAs”). In at least one embodiment, one or more DLAs may include, but are not limited to, one or more Tensor Processing Units (“TPUs”), which may be configured to provide an additional 10 trillion operations per second for deep learning applications and inference. In at least one embodiment, a TPU may be an accelerator configured and optimized for performing image processing functions (e.g., for CNNs, RCNNs, etc.). In at least one embodiment, one or more DLAs may be further optimized for specific sets of neural network types and floating-point operations and inference. In at least one embodiment, one or more DLAs are designed to provide higher performance per millimeter than typical general-purpose GPUs and typically significantly outperform CPUs. In at least one embodiment, one or more TPUs may perform several functions, including single-instance convolution functions supporting, for example, INT8, INT16, and FP16 data types for features and weights, as well as post-processor functions. In at least one embodiment, one or more DLAs can execute neural networks, particularly CNNs, quickly and efficiently on processed or unprocessed data for any of the various functions, including, but not limited to: CNNs for object recognition and detection using data from camera sensors; CNNs for distance estimation using data from camera sensors; CNNs for emergency vehicle detection, recognition, and identification using data from microphones; CNNs for face recognition and vehicle owner recognition using data from camera sensors; and / or CNNs for safety and / or safety-related events.

[0223] In at least one embodiment, the DLA can perform any function of one or more GPUs 1308, and by using inference accelerators, for example, the designer can target one or more DLAs or one or more GPUs 1308 for any function. For example, in at least one embodiment, the designer can concentrate the CNN processing and floating-point operations on one or more DLAs, leaving other functions to one or more GPUs 1308 and / or one or more accelerators 1314.

[0224] In at least one embodiment, one or more accelerators 1314 may include programmable vision accelerators (“PVAs”), which may alternatively be referred to herein as computer vision accelerators. In at least one embodiment, one or more PVAs may be designed and configured to accelerate computer vision algorithms for advanced driver assistance systems (“ADAS”) 1338, autonomous driving, augmented reality (“AR”) applications, and / or virtual reality (“VR”) applications. In at least one embodiment, one or more PVAs may strike a balance between performance and flexibility. For example, in at least one embodiment, each of one or more PVAs may include, for example, but not limited to, any number of reduced instruction set computer (“RISC”) cores, direct memory access (“DMA”), and / or any number of vector processors.

[0225] In at least one embodiment, the RISC core can interact with an image sensor (e.g., the image sensor of any camera described herein), an image signal processor, etc. In at least one embodiment, each RISC core may include any number of memories. In at least one embodiment, the RISC core may use any of a variety of protocols, depending on the embodiment. In at least one embodiment, the RISC core may execute a real-time operating system (“RTOS”). In at least one embodiment, the RISC core may be implemented using one or more integrated circuit devices, application-specific integrated circuits (“ASICs”), and / or storage devices. For example, in at least one embodiment, the RISC core may include an instruction cache and / or tightly coupled RAM.

[0226] In at least one embodiment, DMA enables components of the PVA to access system memory independently of one or more CPUs 1306. In at least one embodiment, DMA can support any number of features for providing optimization to the PVA, including but not limited to, support for multidimensional addressing and / or circular addressing. In at least one embodiment, DMA can support up to six or more addressing dimensions, which may include, but are not limited to, block width, block height, block depth, horizontal block step, vertical block step, and / or depth step.

[0227] In at least one embodiment, the vector processor may be a programmable processor designed to efficiently and flexibly execute programming for computer vision algorithms and provide signal processing capabilities. In at least one embodiment, the PVA may include a PVA core and two vector processing subsystem partitions. In at least one embodiment, the PVA core may include a processor subsystem, a DMA engine (e.g., two DMA engines), and / or other peripherals. In at least one embodiment, the vector processing subsystem may serve as the main processing engine of the PVA and may include a vector processing unit (“VPU”), an instruction cache, and / or a vector memory (e.g., “VMEM”). In at least one embodiment, the VPU core may include a digital signal processor, such as a Single Instruction Multiple Data (“SIMD”) or Very Long Instruction Word (“VLIW”) digital signal processor. In at least one embodiment, the combination of SIMD and VLIW can improve throughput and speed.

[0228] In at least one embodiment, each vector processor may include an instruction cache and may be coupled to dedicated memory. As a result, in at least one embodiment, each vector processor may be configured to execute independently of other vector processors. In at least one embodiment, the vector processors included in a particular PVA may be configured to employ data parallelism. For example, in at least one embodiment, multiple vector processors included in a single PVA may execute general-purpose computer vision algorithms, except on different regions of an image. In at least one embodiment, vector processors included in a particular PVA may execute different computer vision algorithms simultaneously on a single image, or even execute different algorithms on a sequence of images or portions of images. In at least one embodiment, among others, any number of PVAs may be included in the hardware-accelerated cluster, and any number of vector processors may be included in each PVA. In at least one embodiment, the PVA may include additional error-correcting code (“ECC”) memory to enhance overall system security.

[0229] In at least one embodiment, one or more accelerators 1314 may include an on-chip computer vision network and static random access memory (“SRAM”) for providing high-bandwidth, low-latency SRAM to one or more accelerators 1314. In at least one embodiment, the on-chip memory may include at least 4 MB of SRAM, comprising, for example, but not limited to, eight field-configurable memory blocks accessible to both the PVA and DLA. In at least one embodiment, each pair of memory blocks may include an Advanced Peripheral Bus (“APB”) interface, configuration circuitry, a controller, and a multiplexer. In at least one embodiment, any type of memory may be used. In at least one embodiment, the PVA and DLA may access the memory via a backbone providing high-speed access to the memory for both the PVA and DLA. In at least one embodiment, the backbone may include an on-chip computer vision network that interconnects the PVA and DLA to the memory (e.g., using an APB).

[0230] In at least one embodiment, the on-chip computer vision network may include an interface that determines that both the PVA and DLA provide ready and valid signals before transmitting any control signals / addresses / data. In at least one embodiment, the interface may provide separate phases and separate channels for transmitting control signals / addresses / data, as well as bursty communication for continuous data transmission. In at least one embodiment, although other standards and protocols may be used, the interface may conform to the International Organization for Standardization (“ISO”) 26262 or the International Electrotechnical Commission (“IEC”) 61508 standard.

[0231] In at least one embodiment, one or more SoCs 1304 may include a real-time eye-tracking hardware accelerator. In at least one embodiment, the real-time eye-tracking hardware accelerator may be used to quickly and efficiently determine the location and extent of an object (e.g., within a world model) to generate real-time visualization simulations for RADAR signal interpretation, for sound propagation synthesis and / or analysis, for SONAR system simulation, for general wave propagation simulation, for comparison with LIDAR data for localization and / or other functions, and / or for other purposes.

[0232] In at least one embodiment, one or more accelerators 1314 have broad applications for autonomous driving. In at least one embodiment, PVA can be used in critical processing stages in ADAS and autonomous vehicles. In at least one embodiment, the capabilities of PVA with low power consumption and low latency are well-matched to algorithmic domains requiring predictable processing. In other words, PVA performs well in semi-intensive or intensive conventional computations, even on small datasets that may require predictable runtimes with low latency and low power consumption. In at least one embodiment, such as in vehicle 1300, PVA may be designed to run classical computer vision algorithms, as they are efficient in object detection and integer mathematical operations.

[0233] For example, according to at least one embodiment of the technology, PVA is used to perform computer stereo vision. In at least one embodiment, a semi-global matching-based algorithm may be used in some examples, although this is not intended to be limiting. In at least one embodiment, applications for Level 3-5 autonomous driving use dynamic estimation / stereo matching during operation (e.g., structure recovery from motion, pedestrian recognition, lane detection, etc.). In at least one embodiment, PVA can perform computer stereo vision functions on input from two monocular cameras.

[0234] In at least one embodiment, the PVA can be used to perform intensive optical flow. For example, in at least one embodiment, the PVA can process raw RADAR data (e.g., using 4D Fast Fourier Transform) to provide processed RADAR data. In at least one embodiment, the PVA is used for time-of-flight depth processing, for example, by processing raw time-of-flight data to provide processed time-of-flight data.

[0235] In at least one embodiment, the DLA can be used to run any type of network to enhance control and driving safety, including, but not limited to, neural networks whose output is used for a confidence score for each object detection. In at least one embodiment, the confidence score can be represented or interpreted as a probability, or as providing a relative “weight” for each detection relative to other detections. In at least one embodiment, the confidence score measurement enables the system to make further decisions about which detections should be considered true positives rather than false positives. In at least one embodiment, the system can set a threshold for the confidence score and only consider detections exceeding the threshold as true positives. In embodiments using an Automatic Emergency Braking (“AEB”) system, false positives would cause the vehicle to automatically perform emergency braking, which is obviously undesirable. In at least one embodiment, a highly confident detection can be considered a trigger for AEB. In at least one embodiment, the DLA can run a neural network for regressing the confidence score value. In at least one embodiment, the neural network may take at least a subset of parameters as its input, such as bounding box size, acquired ground plane estimates (e.g., from another subsystem), and outputs of one or more IMU sensors 1366 related to vehicle 1300 orientation, distance, and 3D position estimates of the object acquired from the neural network and / or other sensors (e.g., one or more LiDAR sensors 1364 or one or more RADAR sensors 1360).

[0236] In at least one embodiment, one or more SoCs 1304 may include one or more data storage devices 1316 (e.g., memory). In at least one embodiment, one or more data storage devices 1316 may be on-chip memory of one or more SoCs 1304, which may store neural networks to be executed on one or more GPUs 1308 and / or DLAs. In at least one embodiment, one or more data storage devices 1316 may have a sufficiently large capacity to store multiple instances of the neural network for redundancy and security. In at least one embodiment, one or more data storage devices 1316 may include L2 or L3 caches.

[0237] In at least one embodiment, one or more SoCs 1304 may include any number of processors 1310 (e.g., embedded processors). In at least one embodiment, one or more processors 1310 may include a startup and power management processor, which may be a dedicated processor and subsystem for handling startup power and management functions, as well as associated security implementations. In at least one embodiment, the startup and power management processor may be part of a startup sequence of one or more SoCs 1304 and may provide runtime power management services. In at least one embodiment, the startup power and management processor may provide clock and voltage programming, assist system low-power state transitions, thermal and temperature sensor management of one or more SoCs 1304s, and / or power state management of one or more SoCs 1304s. In at least one embodiment, each temperature sensor may be implemented with its output frequency proportional to temperature, and one or more SoCs 1304s may use the ring oscillator to detect the temperature of one or more CPUs 1306s, one or more GPUs 1308s, and / or one or more accelerators 1314s. In at least one embodiment, if it is determined that the temperature exceeds a threshold, the startup and power management processor may enter a temperature fault routine and place one or more SoCs 1304s into a lower power state and / or place the vehicle 1300 into a driver's safe stopping pattern (e.g., bring the vehicle 1300 to a safe stop).

[0238] In at least one embodiment, one or more processors 1310 may further include a set of embedded processors that can serve as an audio processing engine. The audio processing engine may be an audio subsystem capable of providing full hardware support for multi-channel audio through multiple interfaces and a wide and flexible range of audio I / O interfaces. In at least one embodiment, the audio processing engine is a dedicated processor core with a digital signal processor having dedicated RAM.

[0239] In at least one embodiment, one or more processors 1310 may further include an always-on processor engine that can provide the necessary hardware features to support low-power sensor management and wake-up use cases. In at least one embodiment, the processor on the always-on processor engine may include, but is not limited to, a processor core, tightly coupled RAM, peripheral support devices (e.g., timers and interrupt controllers), various I / O controller peripherals, and routing logic.

[0240] In at least one embodiment, one or more processors 1310 may further include a secure clustering engine, which includes, but is not limited to, a dedicated processor subsystem for handling security management of automotive applications. In at least one embodiment, the secure clustering engine may include, but is not limited to, two or more processor cores, tightly coupled RAM, supporting peripherals (e.g., timers, interrupt controllers, etc.) and / or routing logic. In secure mode, in at least one embodiment, the two or more cores may operate in lockstep mode and may be used as a single core with comparison logic for detecting any differences between their operations. In at least one embodiment, one or more processors 1310 may further include a real-time camera engine, which may include, but is not limited to, a dedicated processor subsystem for handling real-time camera management. In at least one embodiment, one or more processors 1310 may further include a high dynamic range signal processor, which may include, but is not limited to, an image signal processor, which is a hardware engine as part of the camera processing pipeline.

[0241] In at least one embodiment, one or more processors 1310 may include a video image synthesizer, which may be a processing block (e.g., implemented on a microprocessor) that implements video post-processing functions required by the video playback application to produce the final video for the player window. In at least one embodiment, the video image synthesizer may perform lens distortion correction on one or more wide-angle cameras 1370, one or more surround cameras 1374, and / or one or more cabin monitoring camera sensors. In at least one embodiment, preferably, the cabin monitoring camera sensors are monitored by a neural network running on another instance of SoC 1304, the neural network being configured to recognize cabin events and respond accordingly. In at least one embodiment, the cabin system may perform, but is not limited to, lip reading to activate cellular service and make phone calls, instruct emails, change the vehicle's destination, activate or change the vehicle's infotainment system and settings, or provide voice-activated web browsing. In at least one embodiment, certain functions are available to the driver when the vehicle is operating in autonomous mode, and are otherwise disabled.

[0242] In at least one embodiment, the video image synthesizer may include enhanced temporal denoising for simultaneous spatial and temporal denoising. For example, in at least one embodiment, when motion occurs in the video, denoising appropriately weights spatial information, thereby reducing the weight of information provided by adjacent frames. In at least one embodiment, when the image or a portion of the image does not contain motion, temporal denoising performed by the video image synthesizer may use information from previous images to reduce noise in the current image.

[0243] In at least one embodiment, the video image compositor can also be configured to perform stereoscopic correction on the input stereo lens frames. In at least one embodiment, when using an operating system desktop, the video image compositor can also be used for user interface compositing and does not require one or more GPUs 1308 to continuously render new surfaces. In at least one embodiment, when one or more GPUs 1308 are powered and actively performing 3D rendering, the video image compositor can be used to offload one or more GPUs 1308 to improve performance and responsiveness.

[0244] In at least one embodiment, one or more SoCs of SoC 1304 may further include a Mobile Industrial Processor Interface (“MIPI”) camera serial interface, a high-speed interface, and / or a video input block that can be used for receiving video and input from a camera and associated pixel input functions. In at least one embodiment, one or more SoCs of SoC 1304 may further include an input / output controller that can be software controlled and can be used to receive I / O signals not assigned to a specific role.

[0245] In at least one embodiment, one or more SoCs of SoC 1304 may further include extensive peripheral interfaces to enable communication with peripheral devices, audio encoders / decoders (“codecs”), power management and / or other devices. In at least one embodiment, one or more SoCs of SoC 1304 may be used to process data from (e.g., connected via gigabit multimedia serial links and Ethernet channels) cameras, sensors (e.g., one or more LiDAR sensors 1364, one or more RADAR sensors 1360, etc., which may be connected via Ethernet channels), data from bus 1302 (e.g., vehicle 1300 speed, steering wheel position, etc.), data from one or more GNSS sensors 1358 (e.g., connected via Ethernet bus or CAN bus), etc. In at least one embodiment, one or more SoCs of SoC 1304 may further include a dedicated high-performance mass storage controller, which may include its own DMA engine and may be used to free one or more CPUs 1306 from routine data management tasks.

[0246] In at least one embodiment, one or more SoCs 1304 can be an end-to-end platform with a flexible architecture spanning automation levels 3-5, providing a comprehensive functional safety architecture that leverages and effectively utilizes computer vision and ADAS technologies to achieve diversity and redundancy. This provides a platform offering a flexible and reliable driving software stack as well as deep learning tools. In at least one embodiment, one or more SoCs 1304 can be faster, more reliable, and even more energy and space efficient than conventional systems. For example, in at least one embodiment, one or more accelerators 1314, when combined with one or more CPUs 1306, one or more GPUs 1308, and one or more data storage devices 1316, can provide a fast and efficient platform for Level 3-5 autonomous vehicles.

[0247] In at least one embodiment, the computer vision algorithm can be executed on a CPU, which can be configured using a high-level programming language (e.g., C) to execute multiple processing algorithms on a variety of visual data. However, in at least one embodiment, the CPU typically cannot meet the performance requirements of many computer vision applications, such as performance requirements related to execution time and power consumption. In at least one embodiment, many CPUs cannot execute complex object detection algorithms in real time, which are used in automotive ADAS applications and practical Level 3-5 autonomous vehicles.

[0248] The embodiments described herein allow multiple neural networks to be executed simultaneously and / or sequentially, and allow the results to be combined to achieve Level 3-5 autonomous driving capabilities. For example, in at least one embodiment, a CNN executed on a DLA or discrete GPU (e.g., one or more GPU1320s) may include text and word recognition, thereby allowing a supercomputer to read and understand traffic signs, including signs for which the neural network has not yet been specifically trained. In at least one embodiment, the DLA may also include a neural network capable of recognizing, interpreting, and providing semantic understanding of symbols, and passing this semantic understanding to a path planning module running on a CPU Complex.

[0249] In at least one embodiment, for drives of levels 3, 4, or 5, multiple neural networks can run simultaneously. For example, in at least one embodiment, a warning sign consisting of a light bulb accompanied by the warning sign “Caution: flashing lights indicate icy conditions” can be interpreted independently or jointly by multiple neural networks. In at least one embodiment, the warning sign itself can be recognized as a traffic sign by a first deployed neural network (e.g., a trained neural network), and the text “flashing lights indicate icy conditions” can be interpreted by a second deployed neural network, which informs the vehicle’s path planning software (preferably executed on a CPU Complex) that icing conditions exist when flashing lights are detected. In at least one embodiment, flashing lights can be identified by operating a third deployed neural network across multiple frames, informing the vehicle’s path planning software of the presence (or absence) of flashing lights. In at least one embodiment, all three neural networks can run simultaneously, for example within a DLA and / or on one or more GPUs 1308.

[0250] In at least one embodiment, the CNN for facial recognition and vehicle owner identification can use data from camera sensors to identify the presence of an authorized driver and / or the owner of vehicle 1300. In at least one embodiment, a normally open sensor processor engine can be used to unlock the vehicle when the owner approaches the driver's door and turns on the lights, and, in security mode, can be used to disable the vehicle when the owner leaves it. In this way, one or more SoCs 1304 provide protection against theft and / or carjacking.

[0251] In at least one embodiment, the CNN for emergency vehicle detection and identification can use data from microphone 1396 to detect and identify emergency vehicle sirens. In at least one embodiment, one or more SoCs 1304 use the CNN to classify environmental and urban sounds, as well as visual data. In at least one embodiment, the CNN running on DLA is trained to identify the relative approach speed of emergency vehicles (e.g., by using the Doppler effect). In at least one embodiment, the CNN can also be trained to identify emergency vehicles in the area where the vehicle is operating, as identified by one or more GNSS sensors 1358. In at least one embodiment, when operating in Europe, the CNN will seek to detect European sirens, while in North America, the CNN will seek to identify only North American sirens. In at least one embodiment, once an emergency vehicle is detected, a control program can be used, with the assistance of one or more ultrasonic sensors 1362, to execute emergency vehicle safety routines, slow the vehicle, pull the vehicle to the side of the road, stop, and / or leave the vehicle idle until the emergency vehicle passes.

[0252] In at least one embodiment, vehicle 1300 may include one or more CPUs 1318 (e.g., one or more discrete CPUs or one or more dCPUs) that may be coupled to one or more SoCs 1304 via high-speed interconnects (e.g., PCIe). In at least one embodiment, one or more CPUs 1318 may include x86 processors. For example, one or more CPUs 1318 may be used to perform any of the various functions, such as arbitrating the results of potential inconsistencies between ADAS sensors and one or more SoCs 1304, and / or monitoring the status and health of one or more monitoring controllers 1336 and / or on-chip information systems (“information SoCs”) 1330.

[0253] In at least one embodiment, vehicle 1300 may include one or more GPUs 1320 (e.g., one or more discrete GPUs or one or more dGPUs) coupled to one or more SoCs 1304 via high-speed interconnects (e.g., NVIDIA's NVLINK channels). In at least one embodiment, one or more GPUs 1320 may provide additional artificial intelligence capabilities, such as by executing redundant and / or different neural networks, and may be used to train and / or update the neural networks based at least in part on inputs from sensors of vehicle 1300 (e.g., sensor data).

[0254] In at least one embodiment, vehicle 1300 may further include a network interface 1324, which may include, but is not limited to, one or more wireless antennas 1326 (e.g., one or more wireless antennas for different communication protocols, such as cellular antennas, Bluetooth antennas, etc.). In at least one embodiment, network interface 1324 may be used to enable wireless connectivity with other vehicles and / or computing devices (e.g., passenger client devices) via Internet cloud services (e.g., using servers and / or other network devices). In at least one embodiment, for communication with other vehicles, a direct link and / or an indirect link (e.g., via a network and the Internet) may be established between vehicle 130 and another vehicle. In at least one embodiment, a vehicle-to-vehicle communication link may be used to provide a direct link. In at least one embodiment, the vehicle-to-vehicle communication link may provide vehicle 1300 with information about vehicles near vehicle 1300 (e.g., vehicles in front, to the side, and / or behind vehicle 1300). In at least one embodiment, the foregoing functionality may be part of a cooperative adaptive cruise control function of vehicle 1300.

[0255] In at least one embodiment, network interface 1324 may include a System-on-Chip (SoC) that provides modulation and demodulation functions and enables one or more controllers 1336 to communicate over a wireless network. In at least one embodiment, network interface 1324 may include a radio frequency (RF) front-end for up-conversion from baseband to RF and down-conversion from RF to baseband. In at least one embodiment, frequency conversion may be performed in any technically feasible manner. For example, frequency conversion may be performed using known processes and / or using a superheterodyne process. In at least one embodiment, the RF front-end functionality may be provided by a separate chip. In at least one embodiment, the network interface may include wireless functions for communication via LTE, WCDMA, UMTS, GSM, CDMA2000, Bluetooth, Bluetooth LE, Wi-Fi, Z-Wave, ZigBee, LoRaWAN, and / or other wireless protocols.

[0256] In at least one embodiment, vehicle 1300 may further include one or more data storage units 1328, which may include, but are not limited to, off-chip (e.g., one or more SoC 1304) storage. In at least one embodiment, one or more data storage units 1328 may include, but are not limited to, one or more storage elements, including RAM, SRAM, dynamic random access memory (“DRAM”), video random access memory (“VRAM”), flash memory, hard disk and / or other components and / or devices capable of storing at least one bit of data.

[0257] In at least one embodiment, the vehicle 1300 may further include one or more GNSS sensors 1358 (e.g., GPS and / or auxiliary GPS sensors) to assist in map creation, perception, occupancy raster generation, and / or path planning functions. In at least one embodiment, any number of GNSS sensors 1358 may be used, including, for example, but not limited to, GPS sensors connected to a serial interface (e.g., RS-232) bridge using a USB connector with Ethernet.

[0258] In at least one embodiment, vehicle 1300 may further include one or more RADAR sensors 1360. In at least one embodiment, one or more RADAR sensors 1360 may be used by vehicle 1300 for remote vehicle detection, even in dark and / or inclement weather conditions. In at least one embodiment, the RADAR functional safety level may be ASIL B. In at least one embodiment, one or more RADAR sensors 1360 may use a CAN bus and / or bus 1302 (e.g., to transmit data generated by one or more RADAR sensors 1360) for control and access to object tracking data, and in some examples may access an Ethernet channel to access raw data. In at least one embodiment, a wide variety of RADAR sensor types may be used. For example, but not limited to, one or more of the RADAR sensors 1360 may be suitable for front, rear, and side RADAR use. In at least one embodiment, one or more RADAR sensors 1360 are pulse Doppler RADAR sensors.

[0259] In at least one embodiment, one or more RADAR sensors 1360 may include different configurations, such as long-range with a narrow field of view, short-range with a wide field of view, short-range side coverage, etc. In at least one embodiment, the long-range RADAR can be used for adaptive cruise control functions. In at least one embodiment, the long-range RADAR system can provide a wide field of view achieved through two or more independent scans (e.g., within a 250m range). In at least one embodiment, one or more RADAR sensors 1360 can help distinguish between stationary and moving objects and can be used by the ADAS system 1338 for emergency braking assistance and forward collision warning. In at least one embodiment, one or more sensors 1360 included in the long-range RADAR system may include, but are not limited to, a monostatic multimode RADAR with multiple (e.g., six or more) fixed RADAR antennas and high-speed CAN and FlexRay interfaces. In at least one embodiment, having six antennas, with the four central antennas, can create a focused beammap designed to record the surrounding environment of the vehicle 1300 at a high speed while minimizing traffic interference from adjacent lanes. In at least one embodiment, the other two antennas can expand the field of view, thereby enabling rapid detection of vehicles 1300 entering or leaving the lane.

[0260] In at least one embodiment, as an example, a mid-range RADAR system may include, for example, a range of up to 160m (front) or 80m (rear), and a field of view of up to 42 degrees (front) or 150 degrees (rear). In at least one embodiment, a short-range RADAR system may include, but is not limited to, any number of RADAR sensors 1360 designed to be mounted at both ends of the rear bumper. When mounted at both ends of the rear bumper, in at least one embodiment, the RADAR sensor system may generate two beams that continuously monitor the rearward direction of the vehicle and nearby blind spots. In at least one embodiment, the short-range RADAR system may be used in ADAS system 1338 for blind spot detection and / or lane change assistance.

[0261] In at least one embodiment, the vehicle 1300 may further include one or more ultrasonic sensors 1362. In at least one embodiment, one or more ultrasonic sensors 1362, which may be positioned at the front, rear, and / or sides of the vehicle 1300, may be used for parking assistance and / or creating and updating occupancy detectors. In at least one embodiment, a wide variety of ultrasonic sensors 1362 may be used, and different ultrasonic sensors 1362 may be used for different detection ranges (e.g., 2.5m, 4m). In at least one embodiment, the ultrasonic sensors 1362 may operate at the ASILB functional safety level.

[0262] In at least one embodiment, vehicle 1300 may include one or more LiDAR sensors 1364. In at least one embodiment, one or more LiDAR sensors 1364 may be used for object and pedestrian detection, emergency braking, collision avoidance, and / or other functions. In at least one embodiment, one or more LiDAR sensors 1364 may operate at functional safety level ASIL B. In at least one embodiment, vehicle 1300 may include multiple (e.g., two, four, six, etc.) LiDAR sensors 1364 that can use Ethernet channels (e.g., providing data to a Gigabit Ethernet switch).

[0263] In at least one embodiment, one or more LiDAR sensors 1364 may be able to provide a list of objects and their distances for a 360-degree field of view. In at least one embodiment, one or more commercially available LiDAR sensors 1364 may, for example, have an advertising range of approximately 100m, an accuracy of 2cm-3cm, and support a 100Mbps Ethernet connection. In at least one embodiment, one or more non-protruding LiDAR sensors may be used. In such an embodiment, one or more LiDAR sensors 1364 may include small devices that can be embedded in the front, rear, side, and / or corner locations of vehicle 1300. In at least one embodiment, one or more LiDAR sensors 1364, in such an embodiment, can provide a horizontal field of view of up to 120 degrees and a vertical field of view of 35 degrees, even for objects with low reflectivity, and have a range of 200m. In at least one embodiment, one or more forward-facing LiDAR sensors 1364 may be configured for a horizontal field of view between 45 degrees and 135 degrees.

[0264] In at least one embodiment, LIDAR technology (such as 3D flash LIDAR) may also be used. In at least one embodiment, 3D flash LIDAR uses a laser flash as a transmission source to illuminate approximately 200m around vehicle 1300. In at least one embodiment, the flash LIDAR unit includes, but is not limited to, a receiver that records the laser pulse propagation time and reflected light on each pixel, which in turn corresponds to the range from vehicle 1300 to the object. In at least one embodiment, flash LIDAR can allow the generation of highly accurate and distortion-free images of the surrounding environment using each laser flash. In at least one embodiment, four flash LIDAR sensors may be deployed, one on each side of vehicle 1300. In at least one embodiment, the 3D flash LIDAR system includes, but is not limited to, a solid-state 3D line-of-sight array LIDAR camera with no moving parts other than a fan (e.g., a non-scanning LIDAR device). In at least one embodiment, the flash LIDAR device can use a 5-nanosecond Class I (eye-safe) laser pulse per frame and can capture reflected laser light as a 3D ranging point cloud and co-registered intensity data.

[0265] In at least one embodiment, vehicle 1300 may further include one or more IMU sensors 1366. In at least one embodiment, one or more IMU sensors 1366 may be located at the center of the rear axle of vehicle 1300. In at least one embodiment, one or more IMU sensors 1366 may include, for example, but not limited to, one or more accelerometers, one or more magnetometers, one or more gyroscopes, a magnetic compass, multiple magnetic compasses, and / or other sensor types. In at least one embodiment, for example in a six-axis application, one or more IMU sensors 1366 may include, but are not limited to, accelerometers and gyroscopes. In at least one embodiment, for example in a nine-axis application, one or more IMU sensors 1366 may include, but are not limited to, accelerometers, gyroscopes, and magnetometers.

[0266] In at least one embodiment, one or more IMU sensors 1366 may be implemented as a miniature, high-performance GPS-assisted inertial navigation system (“GPS / INS”) combining a microelectromechanical system (“MEMS”) inertial sensor, a high-sensitivity GPS receiver, and an advanced Kalman filtering algorithm to provide position, velocity, and attitude estimations; in at least one embodiment, one or more IMU sensors 1366 may enable vehicle 1300 to estimate heading without input from a magnetic sensor obtained by directly observing and correlating velocity changes from GPS to one or more IMU sensors 1366. In at least one embodiment, one or more IMU sensors 1366 and one or more GNSS sensors 1358 may be combined in a single integrated unit.

[0267] In at least one embodiment, vehicle 1300 may include one or more microphones 1396 placed inside and / or around vehicle 1300. In at least one embodiment, in addition, one or more microphones 1396 may be used for emergency vehicle detection and identification.

[0268] In at least one embodiment, vehicle 1300 may further include any number of camera types, including one or more stereo cameras 1368, one or more wide-angle cameras 1370, one or more infrared cameras 1372, one or more surround cameras 1374, one or more long-range cameras 1398, one or more mid-range cameras 1376, and / or other camera types. In at least one embodiment, the cameras can be used to capture image data around the entire perimeter of vehicle 1300. In at least one embodiment, the type of camera used depends on vehicle 1300. In at least one embodiment, any combination of camera types can be used to provide the necessary coverage around vehicle 1300. In at least one embodiment, the number of cameras deployed may vary depending on the embodiment. For example, in at least one embodiment, vehicle 1300 may include six cameras, seven cameras, ten cameras, twelve cameras, or other numbers of cameras. In at least one embodiment, the cameras may be, by way of example but not limited to, supporting gigabit multimedia serial link (“GMSL”) and / or gigabit Ethernet communication. In at least one embodiment, previously referenced herein Figure 13A and Figure 13B Each camera can be described in more detail.

[0269] In at least one embodiment, the vehicle 1300 may further include one or more vibration sensors 1342. In at least one embodiment, the one or more vibration sensors 1342 may measure vibrations of components of the vehicle 1300 (e.g., axles). For example, in at least one embodiment, changes in vibration may indicate changes in road surface conditions. In at least one embodiment, when two or more vibration sensors 1342 are used, differences between vibrations may be used to determine road surface friction or slippage (e.g., when there is a vibration difference between a power drive axle and a free-rotating axle).

[0270] In at least one embodiment, vehicle 1300 may include ADAS system 1338. In at least one embodiment, ADAS system 1338 may include, but is not limited to, SoC. In at least one embodiment, ADAS system 1338 may include, but is not limited to, any number of autonomous / adaptive / automatic cruise control (“ACC”) systems, cooperative adaptive cruise control (“CACC”) systems, forward collision warning (“FCW”) systems, automatic emergency braking (“AEB”) systems, lane departure warning (“LDW”) systems, lane keeping assist (“LKA”) systems, blind spot warning (“BSW”) systems, rear cross traffic warning (“RCTW”) systems, collision warning (“CW”) systems, lane centering (“LC”) systems, and / or other systems, features, and / or functions, and combinations thereof.

[0271] In at least one embodiment, the ACC system may use one or more RADAR sensors 1360, one or more LIDAR sensors 1364, and / or any number of cameras. In at least one embodiment, the ACC system may include a longitudinal ACC system and / or a lateral ACC system. In at least one embodiment, the longitudinal ACC system monitors and controls the distance to another vehicle adjacent to vehicle 1300 and automatically adjusts the speed of vehicle 1300 to maintain a safe distance from the vehicle ahead. In at least one embodiment, the lateral ACC system performs distance holding and suggests that vehicle 1300 change lanes if necessary. In at least one embodiment, lateral ACC is associated with other ADAS applications, such as LC and CW.

[0272] In at least one embodiment, the CACC system uses information from other vehicles, which may be received from other vehicles via network interface 1324 and / or one or more wireless antennas 1326 via a wireless link or indirectly via a network connection (e.g., via the Internet). In at least one embodiment, the direct link may be provided by a vehicle-to-vehicle (“V2V”) communication link, while the indirect link may be provided by an infrastructure-to-vehicle (“I2V”) communication link. Typically, V2V communication provides information about the vehicle immediately preceding it (e.g., a vehicle immediately in front of vehicle 1300 and in the same lane as it), while I2V communication provides information about traffic further ahead. In at least one embodiment, the CACC system may include one or both of the I2V and V2V information sources. In at least one embodiment, given information about vehicles preceding vehicle 1300, the CACC system can be more reliable and has the potential to improve traffic flow smoothness and reduce road congestion.

[0273] In at least one embodiment, the FCW system is designed to warn the driver of danger so that the driver can take corrective action. In at least one embodiment, the FCW system uses a forward-facing camera and / or one or more RADAR sensors 1360, coupled to a dedicated processor, DSP, FPGA, and / or ASIC, electrically coupled to components providing driver feedback, such as a display, speaker, and / or vibration. In at least one embodiment, the FCW system can provide warnings, for example, in the form of audible, visual warnings, vibrations, and / or rapid braking pulses.

[0274] In at least one embodiment, the AEB system detects an impending forward collision with another vehicle or other object and can automatically apply brakes if the driver does not take corrective action within a specified time or distance parameter. In at least one embodiment, the AEB system may use one or more forward-facing cameras and / or one or more RADAR sensors 1360 coupled to a dedicated processor, DSP, FPGA, and / or ASIC. In at least one embodiment, when the AEB system detects a hazard, it typically first warns the driver to take corrective action to avoid a collision, and if the driver does not take corrective action, the AEB system may automatically apply brakes to attempt to prevent or at least mitigate the effects of the predicted collision. In at least one embodiment, the AEB system may include techniques such as dynamic braking to support and / or brakes for impending collisions.

[0275] In at least one embodiment, when vehicle 1300 crosses lane markings, the LDW system provides visual, auditory, and / or tactile warnings, such as steering wheel or seat vibrations, to alert the driver. In at least one embodiment, the LDW system is inactive when the driver indicates intentional lane departure, such as by activating turn signals. In at least one embodiment, the LDW system may use a front-facing camera coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which is electrically coupled to provide driver feedback such as a display, speaker, and / or vibration components. In at least one embodiment, the LKA system is a variant of the LDW system. In at least one embodiment, if vehicle 1300 begins to leave the lane, the LKA system provides steering input or braking to correct vehicle 1300.

[0276] In at least one embodiment, the BSW system detects and warns the driver of a vehicle in the blind spot. In at least one embodiment, the BSW system can provide visual, auditory, and / or tactile alerts to indicate that merging or changing lanes is unsafe. In at least one embodiment, the BSW system can provide additional warnings when the driver uses the turn signal. In at least one embodiment, the BSW system can use one or more rear-facing cameras and / or one or more RADAR sensors 1360 coupled to a dedicated processor, DSP, FPGA, and / or ASIC, electrically coupled to driver feedback, such as a display, speaker, and / or vibration assembly.

[0277] In at least one embodiment, the RCTW system can provide visual, auditory, and / or tactile notifications when an object is detected outside the range of the rear camera while the vehicle 1300 is reversing. In at least one embodiment, the RCTW system includes an AEB system to ensure the applied vehicle brakes to avoid a collision. In at least one embodiment, the RCTW system may use one or more rear-facing RADAR sensors 1360 coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which are electrically coupled to provide driver feedback such as displays, speakers, and / or vibration components.

[0278] In at least one embodiment, conventional ADAS systems may be prone to generating false alarms, which can be annoying and distracting to the driver, but are generally not catastrophic because conventional ADAS systems warn the driver and allow the driver to determine whether a safe situation truly exists and take appropriate action. In at least one embodiment, in the event of conflicting results, the vehicle 1300 itself decides whether to follow the result of the main computer or the auxiliary computer (e.g., the first or second controller of controller 1336). For example, in at least one embodiment, ADAS system 1338 may be a backup and / or auxiliary computer for providing perception information to a backup computer rationality module. In at least one embodiment, the backup computer rationality monitor may run redundant software on hardware components to detect faults in perception and dynamic driving tasks. In at least one embodiment, the output from ADAS system 1338 may be provided to a monitoring MCU. In at least one embodiment, if the output from the main computer and the output from the auxiliary computer conflict, the monitoring MCU decides how to reconcile the conflict to ensure safe operation.

[0279] In at least one embodiment, the master computer may be configured to provide a confidence score to the supervisory MCU to indicate the master computer's confidence in the selected result. In at least one embodiment, if the confidence score exceeds a threshold, the supervisory MCU may follow the master computer's instructions regardless of whether the auxiliary computer provides conflicting or inconsistent results. In at least one embodiment, if the confidence score does not meet the threshold, and if the master computer and the auxiliary computer indicate different results (e.g., conflicting), the supervisory MCU may arbitrate between the computers to determine the appropriate result.

[0280] In at least one embodiment, the supervisory MCU may be configured to run a neural network trained and configured to determine, at least in part, the conditions under which the auxiliary computer provides a false alarm based on outputs from a host computer and an auxiliary computer. In at least one embodiment, the neural network in the supervisory MCU may learn when the outputs of the auxiliary computer can be trusted and when they cannot. For example, in at least one embodiment, when the auxiliary computer is a RADAR-based FCW system, the neural network in the supervisory MCU may learn when the FCW system recognizes a metallic object that is not actually dangerous, such as a drain grating or manhole cover that would trigger an alarm. In at least one embodiment, when the auxiliary computer is a camera-based LDW system, the neural network in the supervisory MCU may learn to override the LDW when a cyclist or pedestrian is present and lane departure is actually the safest operation. In at least one embodiment, the supervisory MCU may include at least one of a DLA or GPU suitable for running a neural network with associated memory. In at least one embodiment, the supervisory MCU may include and / or be included as a component of one or more SoC 1304s.

[0281] In at least one embodiment, the ADAS system 1338 may include an auxiliary computer that performs ADAS functions using conventional computer vision rules. In at least one embodiment, the auxiliary computer may use classic computer vision rules (if-then), and the presence of a neural network in the supervisory MCU can improve reliability, security, and performance. For example, in at least one embodiment, diverse implementations and intentional non-identity make the entire system more fault-tolerant, especially for failures caused by software (or software-hardware interface) functionality. For example, in at least one embodiment, if a software vulnerability or bug exists in the software running on the host computer, and different software code running on the auxiliary computer provides consistent overall results, the supervisory MCU can more confidently assume that the overall result is correct and that the vulnerability in the software or hardware on the host computer will not lead to a significant error.

[0282] In at least one embodiment, the output of the ADAS system 1338 can be input to the perception module and / or the dynamic driving task module of the host computer. For example, in at least one embodiment, if the ADAS system 1338 indicates a forward collision warning due to an object directly ahead, the perception block can use this information when identifying the object. In at least one embodiment, as described herein, the assistance computer can have its own neural network trained to reduce the risk of false alarms.

[0283] In at least one embodiment, vehicle 1300 may further include an infotainment SoC 1330 (e.g., an in-vehicle infotainment system (IVI)). Although shown and described as an SoC, in at least one embodiment, the infotainment system SoC 1330 may not be an SoC and may include, but is not limited to, two or more discrete components. In at least one embodiment, the infotainment SoC 1330 may include, but is not limited to, a combination of hardware and software that can be used to provide audio (e.g., music, personal digital assistant, navigation instructions, news, radio, etc.), video (e.g., television, movies, streaming media, etc.), telephone (e.g., hands-free calling), network connectivity (e.g., LTE, WiFi, etc.) and / or information services (e.g., navigation system, rear parking assist, radio data system, vehicle-related information such as fuel level, total coverage distance, brake fuel level, fuel level, door opening / closing, air filter information, etc.) to vehicle 1300. For example, the infotainment SoC 1330 may include a radio, disk player, navigation system, video player, USB and Bluetooth connectivity, automobile, in-vehicle entertainment system, WiFi, steering wheel audio controls, hands-free voice control, head-up display (“HUD”), HMI display 1334, telematics device, control panel (e.g., for controlling and / or interacting with various components, features and / or systems) and / or other components. In at least one embodiment, the infotainment SoC 1330 may further be used to provide information (e.g., visual and / or auditory) to a user of vehicle 1300, such as information from ADAS system 1338, autonomous driving information (such as planned vehicle maneuvers), trajectory, surrounding environment information (e.g., intersection information, vehicle information, road information, etc.) and / or other information.

[0284] In at least one embodiment, the infotainment SoC 1330 may include any number and type of GPU functionality. In at least one embodiment, the infotainment SoC 1330 may communicate with other devices, systems, and / or components of the vehicle 1300 via bus 1302. In at least one embodiment, the infotainment SoC 1330 may be coupled to a monitoring MCU, enabling the GPU of the infotainment system to perform some autonomous driving functions in the event of a failure of the main controller 1336 (e.g., the main computer and / or backup computer of the vehicle 1300). In at least one embodiment, the infotainment SoC 1330 may cause the vehicle 1300 to enter a driver-to-safe-stop mode, as described herein.

[0285] In at least one embodiment, vehicle 1300 may further include instrument panel 1332 (e.g., digital instrument panel, electronic instrument panel, digital instrument control panel, etc.). In at least one embodiment, instrument panel 1332 may include, but is not limited to, controllers and / or supercomputers (e.g., discrete controllers or supercomputers). In at least one embodiment, instrument panel 1332 may include, but is not limited to, any number and combination of a set of instruments, such as speedometer, fuel level, oil pressure, tachometer, odometer, turn indicator, shift position indicator, one or more seatbelt warning lights, one or more parking brake warning lights, one or more engine malfunction lights, auxiliary restraint system (e.g., airbag) information, lighting controls, safety system controls, navigation information, etc. In some examples, information may be displayed and / or shared between infotainment SoC 1330 and instrument panel 1332. In at least one embodiment, instrument panel 1332 may be included as part of infotainment SoC 1330, or vice versa.

[0286] Inference and / or training logic 1015 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 10A and / or Figure 10B Details regarding the inference and / or training logic 1015 are provided. In at least one embodiment, the inference and / or training logic 1015 can be implemented in the system. Figure 13C The operation is used to infer or predict the operation based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures or neural network use cases described herein.

[0287] Figure 13D It is based on at least one embodiment in a cloud-based server and Figure 13AA diagram of a system for communication between autonomous vehicles 1300. In at least one embodiment, the system may include, but is not limited to, one or more servers 1378, one or more networks 1390, and any number and type of vehicles, including vehicle 1300. In at least one embodiment, one or more servers 1378 may include, but is not limited to, multiple GPUs 1384(A)-1384(H) (collectively referred to herein as GPU 1384), PCIe switches 1382(A)-1382(D) (collectively referred to herein as PCIe switch 1382), and / or CPUs 1380(A)-1380(B) (collectively referred to herein as CPU 1380). GPU 1384, CPU 1380, and PCIe switch 1382 may be interconnected with high-speed cables, such as, but not limited to, NVLink interface 1388 developed by NVIDIA and / or PCIe connection 1386. In at least one embodiment, the GPU 1384 is connected via NVLink and / or NVSwitchSoC, and the GPU 1384 and PCIe switch 1382 are connected via PCIe interconnect. Although eight GPUs 1384, two CPUs 1380, and four PCIe switches 1382 are shown, this is not intended to be limiting. In at least one embodiment, each of one or more servers 1378 may include, but is not limited to, any combination of any number of GPUs 1384, CPUs 1380, and / or PCIe switches 1382. For example, in at least one embodiment, one or more servers 1378 may each include eight, sixteen, thirty-two, and / or more GPUs 1384.

[0288] In at least one embodiment, one or more servers 1378 may receive image data representing images from vehicles via one or more networks 1390, the images showing unexpected or changed road conditions, such as recently commenced roadworks. In at least one embodiment, one or more servers 1378 may transmit updated neural network 1392 and / or map information 1394, including but not limited to information about traffic and road conditions, to vehicles via one or more networks 1390. In at least one embodiment, updates to map information 1394 may include, but are not limited to, updates to HD map 1322, such as information about construction sites, potholes, sidewalks, floods, and / or other obstacles. In at least one embodiment, neural network 1392 and / or map information 1394 may be generated from new training and / or experience represented by data received from any number of vehicles in the environment, and / or at least based on training performed in a data center (e.g., using one or more servers 1378 and / or other servers).

[0289] In at least one embodiment, one or more servers 1378 may be used to train a machine learning model (e.g., a neural network) at least in part based on training data. In at least one embodiment, the training data may be generated by the vehicle, and / or may be generated in a simulation (e.g., using a game engine). In at least one embodiment, any amount of training data is labeled (e.g., where the associated neural network benefits from supervised learning) and / or undergoes other preprocessing. In at least one embodiment, no amount of training data is labeled and / or preprocessed (e.g., where the associated neural network does not require supervised learning). In at least one embodiment, once the machine learning model is trained, the machine learning model may be used by the vehicle (e.g., transmitted to the vehicle via one or more networks 1390), and / or the machine learning model may be used by one or more servers 1378 to remotely monitor the vehicle.

[0290] In at least one embodiment, one or more servers 1378 may receive data from the vehicle and apply the data to state-of-the-art real-time neural networks for real-time intelligent inference. In at least one embodiment, one or more servers 1378 may include a deep learning supercomputer and / or a dedicated AI computer powered by one or more GPUs 1384, such as the DGX and DGXStation machines developed by NVIDIA. However, in at least one embodiment, one or more servers 1378 may include a deep learning infrastructure in a data center using CPU power.

[0291] In at least one embodiment, the deep learning infrastructure of one or more servers 1378 may be capable of fast, real-time inference and may use this capability to assess and verify the health of the processor, software, and / or associated hardware in vehicle 1300. For example, in at least one embodiment, the deep learning infrastructure may receive periodic updates from vehicle 1300, such as image sequences and / or objects located by vehicle 1300 in the image sequence (e.g., via computer vision and / or other machine learning object classification techniques). In at least one embodiment, the deep learning infrastructure may run its own neural network to identify objects and compare them with objects identified by vehicle 1300, and if the results do not match and the deep learning infrastructure determines that the AI ​​in vehicle 1300 is malfunctioning, one or more servers 1378 may signal to vehicle 1300 to instruct the fail-safe computer of vehicle 1300 to take control, notify passengers, and complete a safe stopping operation.

[0292] In at least one embodiment, one or more servers 1378 may include one or more GPUs 1384 and one or more programmable inference accelerators (e.g., NVIDIA's TensorRT3 devices). In at least one embodiment, the combination of GPU-driven servers and inference acceleration enables real-time response. In at least one embodiment, for example, where performance is less critical, servers driven by CPUs, FPGAs, and other processors may be used for inference. In at least one embodiment, hardware architecture 1015 is used to execute one or more embodiments. This document incorporates... Figure 10A and / or Figure 10B Provide details about the hardware architecture 1015.

[0293] In at least one embodiment, utilizing Figures 13A-13D The system for object pose estimation is implemented using one or more systems described herein. In at least one embodiment, it utilizes... Figures 13A-13D The image describes one or more systems for determining the pose and relative size of objects from an image. In at least one embodiment, it utilizes... Figures 13A-13D The description of one or more systems implements one or more systems and / or processes, such as combining Figure 1-9 Those described.

[0294] Computer System

[0295] Figure 14 This is a block diagram illustrating an exemplary computer system according to at least one embodiment. The exemplary computer system may be a system of interconnected devices and components, a system-on-a-chip (SoC), or some combination thereof formed with a processor, which may include an execution unit to execute instructions. In at least one embodiment, according to this disclosure, such as the embodiments described herein, computer system 1400 may include, but is not limited to, components such as processor 1402, whose execution unit includes logic to execute algorithms for process data. In at least one embodiment, computer system 1400 may include a processor, such as one available from Intel Corporation of Santa Clara, California. Processor family, Xeon TM , XScale TM and / or StrongARM TM , Core TM or Nervana TMA microprocessor may be used, although other systems (including PCs, engineering workstations, set-top boxes, etc.) with other microprocessors may also be used. In at least one embodiment, computer system 1400 may execute a version of the Windows operating system available from Microsoft Corporation of Redmond, Washington, although other operating systems (such as UNIX and Linux), embedded software, and / or graphical user interfaces may also be used.

[0296] The embodiments can be used in other devices, such as handheld devices and embedded applications. Some examples of handheld devices include cellular phones, Internet Protocol (IP) devices, digital cameras, personal digital assistants (“PDAs”), and handheld PCs. In at least one embodiment, the embedded application may include a microcontroller, a digital signal processor (“DSP”), a system-on-a-chip (SoC), a network computer (“NetPC”), a set-top box, a network hub, a wide area network (“WAN”) switch, or any other system that can execute one or more instructions according to at least one embodiment.

[0297] In at least one embodiment, the computer system 1400 may include, but is not limited to, a processor 1402, which may include, but is not limited to, one or more execution units 1408, to perform machine learning model training and / or inference according to the techniques described herein. In at least one embodiment, the computer system 1400 is a single-processor desktop or server system, but in another embodiment, the computer system 1400 may be a multiprocessor system. In at least one embodiment, the processor 1402 may include, but is not limited to, a Complex Instruction Set Computer (“CISC”) microprocessor, a Reduced Instruction Set Computing (“RISC”) microprocessor, a Very Long Instruction Word (“VLIW”) microprocessor, a processor implementing instruction set combination, or any other processor device, such as a digital signal processor. In at least one embodiment, the processor 1402 may be coupled to a processor bus 1410, which can transmit data signals between the processor 1402 and other components in the computer system 1400.

[0298] In at least one embodiment, processor 1402 may include, but is not limited to, a Level 1 (“L1”) internal cache memory (“cache”) 1404. In at least one embodiment, processor 1402 may have a single internal cache or multiple levels of internal cache. In at least one embodiment, the cache memory may reside external to processor 1402. Depending on specific implementation and requirements, other embodiments may also include a combination of internal and external caches. In at least one embodiment, register file 1406 may store different types of data in various registers, including but not limited to integer registers, floating-point registers, status registers, and instruction pointer registers.

[0299] In at least one embodiment, an execution unit 1408, including but not limited to logic for performing integer and floating-point operations, is also located within processor 1402. In at least one embodiment, processor 1402 may further include a microcode (“ucode”) read-only memory (“ROM”) for storing microcode of certain macro instructions. In at least one embodiment, execution unit 1408 may include logic for processing a packaged instruction set 1409. In at least one embodiment, by including the packaged instruction set 1409 in the instruction set of a general-purpose processor, along with the associated circuitry for executing the instructions, the packaged data in processor 1402 can be used to perform operations used by numerous multimedia applications. In at least one embodiment, many multimedia applications can be executed more quickly and efficiently by using the full width of the processor’s data bus to perform operations on the packaged data, which may eliminate the need to transfer smaller data units on the processor’s data bus to perform one or more operations on one data element at a time.

[0300] In at least one embodiment, execution unit 1408 may also be used in a microcontroller, embedded processor, graphics device, DSP, and other types of logic circuitry. In at least one embodiment, computer system 1400 may include, but is not limited to, memory 1420. In at least one embodiment, memory 1420 may be a dynamic random access memory (“DRAM”) device, a static random access memory (“SRAM”) device, a flash memory device, or another storage device. In at least one embodiment, memory 1420 may store instructions 1419 and / or data 1421 represented by data signals that can be executed by processor 1402.

[0301] In at least one embodiment, the system logic chip may be coupled to processor bus 1410 and memory 1420. In at least one embodiment, the system logic chip may include, but is not limited to, a memory controller hub (“MCH”) 1416, and processor 1402 may communicate with MCH 1416 via processor bus 1410. In at least one embodiment, MCH 1416 may provide a high-bandwidth memory path 1418 to memory 1420 for instruction and data storage, as well as for storage of graphics commands, data, and textures. In at least one embodiment, MCH 1416 may initiate data signals between processor 1402, memory 1420, and other components in computer system 1400, and bridge data signals between processor bus 1410, memory 1420, and system I / O interface 1422. In at least one embodiment, the system logic chip may provide a graphics port for coupling to a graphics controller. In at least one embodiment, MCH 1416 may be coupled to memory 1420 via high-bandwidth memory path 1418, and graphics / video card 1412 may be coupled to MCH 1416 via Accelerated Graphics Port (“AGP”) interconnect 1414.

[0302] In at least one embodiment, the computer system 1400 may use the system I / O interface 1422 as a proprietary hub interface bus to couple the MCH 1416 to the I / O controller hub (“ICH”) 1430. In at least one embodiment, the ICH 1430 may provide direct connectivity to certain I / O devices via a local I / O bus. In at least one embodiment, the local I / O bus may include, but is not limited to, a high-speed I / O bus for connecting peripheral devices to the memory 1420, chipset, and processor 1402. Examples may include, but are not limited to, an audio controller 1429, a firmware hub (“FlashBIOS”) 1428, a wireless transceiver 1426, a data storage 1424, a conventional I / O controller 1423 including a user input and keyboard interface 1425, a serial expansion port 1427 (e.g., a Universal Serial Bus (USB) port), and a network controller 1434. In at least one embodiment, the data storage 1424 may include a hard disk drive, a floppy disk drive, a CD-ROM device, a flash memory device, or other mass storage device.

[0303] In at least one embodiment, Figure 14 A system including interconnected hardware devices or "chips" is shown, while in other embodiments, Figure 14 The SoC can be shown. In at least one embodiment, Figure 14The devices shown can be interconnected with proprietary interconnects, standardized interconnects (e.g., PCIe), or some combination thereof. In at least one embodiment, one or more components of the computer system 1400 are interconnected using a Compute Fast Link (CXL) interconnect.

[0304] The inference and / or training logic 1015 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 10A and / or Figure 10B Details regarding the inference and / or training logic 1015 are provided. In at least one embodiment, the inference and / or training logic 1015 can... Figure 14 Used in systems for reasoning or predicting operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures or neural network use cases described herein.

[0305] In at least one embodiment, utilizing Figure 14 The system for object pose estimation is implemented using one or more systems described herein. In at least one embodiment, it utilizes... Figure 14 The image describes one or more systems for determining the pose and relative size of objects from an image. In at least one embodiment, it utilizes... Figure 14 The description of one or more systems implements one or more systems and / or processes, such as combining Figure 1-9 Those described.

[0306] Figure 15 This is a block diagram illustrating an electronic device 1500 for utilizing a processor 1510 according to at least one embodiment. In at least one embodiment, the electronic device 1500 may be, for example, but not limited to, a laptop computer, tower server, rack server, blade server, laptop computer, desktop computer, tablet computer, mobile device, telephone, embedded computer, or any other suitable electronic device.

[0307] In at least one embodiment, the electronic device 1500 may include, but is not limited to, a processor 1510 communicatively coupled to any suitable number or type of components, peripherals, modules, or devices. In at least one embodiment, the processor 1510 is coupled using a bus or interface, such as I... 2 C-bus, System Management Bus (“SMBus”), Low Pin Count (LPC) bus, Serial Peripheral Interface (“SPI”), High Definition Audio (“HDA”) bus, Serial Advanced Technology Accessory (“SATA”) bus, Universal Serial Bus (“USB”) (versions 1, 2, 3, etc.), or Universal Asynchronous Receiver / Transmitter (“UART”) bus. In at least one embodiment, Figure 15The system shown includes interconnected hardware devices or "chips," while in other embodiments, Figure 15 An exemplary SoC can be shown. In at least one embodiment, Figure 15 The device shown can be interconnected with proprietary interconnects, standardized interconnects (e.g., PCIe), or some combination thereof. In at least one embodiment, Figure 15 One or more components are interconnected using Computational Fast Link (CXL) interconnects.

[0308] In at least one embodiment, Figure 15 It may include a display 1524, a touch screen 1525, a touchpad 1530, a near field communication unit (“NFC”) 1545, a sensor hub 1540, a thermal sensor 1546, a fast chipset (“EC”) 1535, a trusted platform module (“TPM”) 1538, a BIOS / firmware / flash (“BIOS, FWFlash”) 1522, a DSP 1560, a drive 1520 (e.g., a solid-state drive (“SSD”) or a hard disk drive (“HDD”)), a wireless local area network unit (“WLAN”) 1550, a Bluetooth unit 1552, a wireless wide area network unit (“WWAN”) 1556, a global positioning system (GPS) unit 1555, a camera (“USB 3.0 camera”) 1554 (e.g., a USB 3.0 camera) and / or a low-power double data rate (“LPDDR”) memory unit (“LPDDR3”) 1515 implemented in, for example, the LPDDR3 standard. These components can each be implemented in any suitable way.

[0309] In at least one embodiment, other components may be communicatively coupled to processor 1510 via the components described herein. In at least one embodiment, accelerometer 1541, ambient light sensor (“ALS”) 1542, compass 1543, and gyroscope 1544 may be communicatively coupled to sensor hub 1540. In at least one embodiment, thermal sensor 1539, fan 1537, keyboard 1536, and touchpad 1530 may be communicatively coupled to EC 1535. In at least one embodiment, speaker 1563, earphone 1564, and microphone (“mic”) 1565 may be communicatively coupled to audio unit (“audio codec and Class D amplifier”) 1562, which in turn may be communicatively coupled to DSP 1560. In at least one embodiment, audio unit 1562 may include, for example, but not limited to, audio encoder / decoder (“codec”) and Class D amplifier. In at least one embodiment, SIM card (“SIM”) 1557 may be communicatively coupled to WWAN unit 1556. In at least one embodiment, components such as WLAN unit 1550, Bluetooth unit 1552, and WWAN unit 1556 can be implemented as next-generation form factor (NGFF).

[0310] Inference and / or training logic 1015 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 10A and / or Figure 10B Details regarding the inference and / or training logic 1015 are provided. In at least one embodiment, the inference and / or training logic 1015 can be implemented in the system. Figure 15 It is used in the context of reasoning or predicting operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures or neural network use cases described herein.

[0311] In at least one embodiment, utilizing Figure 15 The system for object pose estimation is implemented using one or more systems described herein. In at least one embodiment, it utilizes... Figure 15 The image describes one or more systems for determining the pose and relative size of objects from an image. In at least one embodiment, it utilizes... Figure 15 The description of one or more systems implements one or more systems and / or processes, such as combining Figure 1-9 Those described.

[0312] Figure 16 A computer system 1600 according to at least one embodiment is shown. In at least one embodiment, the computer system 1600 is configured to implement various processes and methods described throughout this disclosure.

[0313] In at least one embodiment, the computer system 1600 includes, but is not limited to, at least one central processing unit (“CPU”) 1602 connected to a communication bus 1610 implemented using any suitable protocol, such as PCI (“Peripheral Interconnect”), Peripheral Component Interconnect Express (“PCI-Express”), AGP (“Accelerated Graphics Port”), HyperTransport, or any other bus or point-to-point communication protocol. In at least one embodiment, the computer system 1600 includes, but is not limited to, main memory 1604 and control logic (e.g., implemented in hardware, software, or a combination thereof), and data may be stored in main memory 1604 in the form of random access memory (“RAM”). In at least one embodiment, a network interface subsystem (“Network Interface”) 1622 provides an interface to other computing devices and networks for receiving data using the computer system 1600 and transferring data to other systems.

[0314] In at least one embodiment, the computer system 1600 includes, but is not limited to, an input device 1608, a parallel processing system 1612, and a display device 1606, which may be implemented using conventional cathode ray tube (“CRT”), liquid crystal display (“LCD”), light-emitting diode (“LED”) display, plasma display, or other suitable display technologies. In at least one embodiment, user input is received from the input device 1608 (such as a keyboard, mouse, touchpad, microphone, etc.). In at least one embodiment, each of the modules described herein may reside on a single semiconductor platform to form the processing system.

[0315] Inference and / or training logic 1015 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 10A and / or Figure 10B Details regarding the inference and / or training logic 1015 are provided. In at least one embodiment, the inference and / or training logic 1015 can be implemented in the system. Figure 16 It is used to perform inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architecture or neural network use cases described herein.

[0316] In at least one embodiment, utilizing Figure 16 The system for object pose estimation is implemented using one or more systems described herein. In at least one embodiment, it utilizes... Figure 16 The image describes one or more systems for determining the pose and relative size of objects from an image. In at least one embodiment, it utilizes... Figure 16 The description of one or more systems implements one or more systems and / or processes, such as combining Figure 1-9 Those described.

[0317] Figure 17 A computer system 1700 according to at least one embodiment is illustrated. In at least one embodiment, the computer system 1700 includes, but is not limited to, a computer 1710 and a USB flash drive 1720. In at least one embodiment, the computer 1710 may include, but is not limited to, any number and type of processors (not shown) and memory (not shown). In at least one embodiment, the computer 1710 includes, but is not limited to, a server, a cloud instance, a laptop computer, and a desktop computer.

[0318] In at least one embodiment, the USB flash drive 1720 includes, but is not limited to, a processing unit 1730, a USB interface 1740, and USB interface logic 1750. In at least one embodiment, the processing unit 1730 can be any instruction execution system, apparatus, or device capable of executing instructions. In at least one embodiment, the processing unit 1730 can include, but is not limited to, any number and type of processing cores (not shown). In at least one embodiment, the processing unit 1730 includes an application-specific integrated circuit (“ASIC”) optimized to perform any number and type of operations associated with machine learning. For example, in at least one embodiment, the processing unit 1730 is a tensor processing unit (“TPC”) optimized to perform machine learning inference operations. In at least one embodiment, the processing unit 1730 is a vision processing unit (“VPU”) optimized to perform machine vision and machine learning inference operations.

[0319] In at least one embodiment, the USB interface 1740 can be any type of USB connector or USB receptacle. For example, in at least one embodiment, the USB interface 1740 is a USB 3.0 Type-C receptacle for data and power. In at least one embodiment, the USB interface 1740 is a USB 3.0 Type-A connector. In at least one embodiment, the USB interface logic 1750 may include any amount and type of logic enabling the processing unit 1730 to connect to a device (e.g., computer 1710) via the USB connector 1740.

[0320] Inference and / or training logic 1015 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 10A and / or Figure 10B Details regarding the inference and / or training logic 1015 are provided. In at least one embodiment, the inference and / or training logic 1015 can be implemented in the system. Figure 17In use, at least in part, the operation is based on weight parameters, neural network functions and / or architectures computed using neural network training operations, or neural network use cases described herein to infer or predict operations.

[0321] In at least one embodiment, utilizing Figure 17 The system for object pose estimation is implemented using one or more systems described herein. In at least one embodiment, it utilizes... Figure 17 The image describes one or more systems for determining the pose and relative size of objects from an image. In at least one embodiment, it utilizes... Figure 17 The description of one or more systems implements one or more systems and / or processes, such as combining Figure 1-9 Those described.

[0322] Figure 18A An exemplary architecture is illustrated in which multiple GPUs 1810(1)-1810(N) are communicatively coupled to multiple multi-core processors 1805(1)-1805(M) via high-speed links 1840(1)-1840(N) (e.g., bus / point-to-point interconnect, etc.). In at least one embodiment, the high-speed links 1840(1)-1840(N) support communication throughput of 4GB / s, 30GB / s, 80GB / s, or higher. In at least one embodiment, various interconnect protocols may be used, including but not limited to PCIe 4.0 or 5.0 and NVLink 2.0. In the various figures, “N” and “M” represent positive integers, the values ​​of which may vary from figure to figure.

[0323] Furthermore, in at least one embodiment, two or more GPUs 1810 are interconnected via high-speed links 1829(1)-1829(2), which can be implemented using a protocol / link similar to or different from that used for high-speed links 1840(1)-1840(N). Similarly, two or more multi-core processors 1805 can be connected via high-speed link 1828, which can be a symmetric multiprocessor (SMP) bus operating at speeds of 20GB / s, 30GB / s, 120GB / s, or higher. Alternatively, similar protocols / links (e.g., via a common interconnect structure) can be used. Figure 18A This shows all communication between the various system components.

[0324] In at least one embodiment, each multi-core processor 1805 is communicatively coupled to processor memories 1801(1)-1801(M) via memory interconnects 1826(1)-1826(M), and each GPU 1810(1)-1810(N) is communicatively coupled to GPU memories 1820(1)-1820(N) via GPU memory interconnects 1850(1)-1850(N). In at least one embodiment, memory interconnects 1826 and 1850 may utilize similar or different memory access technologies. By way of example and not limitation, processor memories 1801(1)-1801(M) and GPU memories 1820 may be volatile memories, such as dynamic random access memory (DRAM) (including stacked DRAM), graphics DDR SDRAM (GDDR) (e.g., GDDR5, GDDR6), or high bandwidth memory (HBM), and / or may be non-volatile memories, such as 3DXPoint or Nano-Ram. In at least one embodiment, some portions of the processor memory 1801 may be volatile memory, while other portions may be non-volatile memory (e.g., using a two-level memory (2LM) hierarchy).

[0325] As described herein, although various multi-core processors 1805 and GPUs 1810 can be physically coupled to specific memories 1801 and 1820 respectively, and / or can implement a unified memory architecture, in which the virtual system address space (also known as the “effective address” space) is distributed among the various physical memories. For example, processor memories 1801(1)-1801(M) can each contain 64GB of system memory address space, and GPU memories 1820(1)-1820(N) can each contain 32GB of system memory address space, resulting in a total addressable memory size of 256GB when M=2 and N=4. N and M may also be other values.

[0326] Figure 18B Additional details are shown regarding the interconnection between a multi-core processor 1807 and a graphics acceleration module 1846 according to an exemplary embodiment. In at least one embodiment, the graphics acceleration module 1846 may include one or more GPU chips integrated on a line card coupled to the processor 1807 via a high-speed link 1840 (e.g., PCIe bus, NVLink, etc.). In at least one embodiment, the graphics acceleration module 1846 may optionally be integrated on a package or chip having the processor 1807.

[0327] In at least one embodiment, the processor 1807 includes a plurality of cores 1860A-1860D, each core having a translation back cover buffer (“TLB”) 1861A-1861D and one or more caches 1862A-1862D. In at least one embodiment, the cores 1860A-1860D may include various other components (not shown) for executing instructions and processing data. In at least one embodiment, the caches 1862A-1862D may include level 1 (L1) and level 2 (L2) caches. Furthermore, one or more shared caches 1856 may be included in the caches 1862A-1862D and shared by the respective groups of cores 1860A-1860D. For example, one embodiment of the processor 1807 includes 24 cores, each core having its own L1 cache, twelve shared L2 caches, and twelve shared L3 caches. In this embodiment, two adjacent cores share one or more L2 and L3 caches. In at least one embodiment, the processor 1807 and the graphics acceleration module 1846 are connected to a system memory 1814, which may include... Figure 18A The processor memory in the memory is 1801(1)-1801(M).

[0328] In at least one embodiment, consistency of data and instructions stored in the various caches 1862A-1862D, 1856 and system memory 1814 is maintained via inter-core communication through the consistency bus 1864. In at least one embodiment, for example, each cache may have associated cache consistency logic / circuit to communicate via the consistency bus 1864 in response to the detection of a read or write to a particular cache line. In at least one embodiment, a cache snooping protocol is implemented via the consistency bus 1864 to snoop on cache accesses.

[0329] In at least one embodiment, proxy circuitry 1825 communicatively couples graphics acceleration module 1846 to coherence bus 1864, thereby allowing graphics acceleration module 1846 to participate in cache coherence protocols as a peer of cores 1860A-1860D. Specifically, in at least one embodiment, interface 1835 provides connectivity to proxy circuitry 1825 via high-speed link 1840, and interface 1837 connects graphics acceleration module 1846 to high-speed link 1840.

[0330] In at least one embodiment, the accelerator integrated circuit 1836 provides cache management, memory access, context management, and interrupt management services for a plurality of graphics processing engines 1831(1)-1831(N) of the graphics acceleration module. In at least one embodiment, the graphics processing engines 1831(1)-1831(N) may each include a separate graphics processing unit (GPU). In at least one embodiment, the graphics processing engines 1831(1)-1831(N) may optionally include different types of graphics processing engines within the GPU, such as graphics execution units, media processing engines (e.g., video encoders / decoders), samplers, and blit engines. In at least one embodiment, the graphics acceleration module 1846 may be a GPU having a plurality of graphics processing engines 1831(1)-1831(N), or the graphics processing engines 1831(1)-1831(N) may be individual GPUs integrated on a general-purpose package, line card, or chip.

[0331] In at least one embodiment, the accelerator integrated circuit 1836 includes a memory management unit (MMU) 1839 for performing various memory management functions, such as virtual-to-physical memory translation (also known as effective-to-real memory translation), and a memory access protocol for accessing system memory 1814. In at least one embodiment, the MMU 1839 may also include a translation back buffer (“TLB”) (not shown) for caching virtual / effective-to-physical / real address translations. In at least one embodiment, a cache 1838 may store commands and data for efficient access by the graphics processing engines 1831(1)-1831(N). In at least one embodiment, a fetch unit 1844 may be used to keep data stored in the cache 1838 and graphics memories 1833(1)-1833(M) consistent with the core caches 1862A-1862D, 1856 and system memory 1814. As previously mentioned, this task can be accomplished via proxy circuitry 1825 representing cache 1838 and graphics memory 1833(1)-1833(M) (e.g., sending updates related to the modification / access of cache lines on processor caches 1862A-1862D, 1856 to cache 1838 and receiving updates from cache 1838).

[0332] In at least one embodiment, a set of registers 1845 stores context data of threads executed by graphics processing engines 1831(1)-1831(N), and context management circuitry 1848 manages the thread context. For example, context management circuitry 1848 can perform save and restore operations to save and restore the context of individual threads during context switching (e.g., saving the first thread and storing the second thread so that the second thread can be executed by the graphics processing engine). For example, during context switching, context management circuitry 1848 can store the current register value in a designated area of ​​memory (e.g., identified by a context pointer). The register value can then be restored when returning to the context. In at least one embodiment, interrupt management circuitry 1847 receives and processes interrupts received from system devices.

[0333] In at least one embodiment, MMU 1839 translates virtual / effective addresses from graphics processing engine 1831 into real / physical addresses in system memory 1814. In at least one embodiment, accelerator integrated circuit 1836 supports multiple (e.g., 4, 8, 16) graphics accelerator modules 1846 and / or other accelerator devices. In at least one embodiment, graphics accelerator module 1846 may be dedicated to a single application executing on processor 1807, or may be shared among multiple applications. In at least one embodiment, a virtualized graphics execution environment is presented, wherein resources of graphics processing engines 1831(1)-1831(N) are shared with multiple applications or virtual machines (VMs). In at least one embodiment, resources may be subdivided into “slices” based on processing requirements and priorities associated with VMs and / or applications, which are allocated to different VMs and / or applications.

[0334] In at least one embodiment, the accelerator integrated circuit 1836 acts as a bridge to the system of the graphics acceleration module 1846 and provides address translation and system memory caching services. Additionally, in at least one embodiment, the accelerator integrated circuit 1836 can provide virtualization facilities for the host processor to manage the virtualization, interrupt, and memory management of the graphics processing engines 1831(1)-1831(N).

[0335] In at least one embodiment, since the hardware resources of the graphics processing engines 1831(1)-1831(N) are explicitly mapped to the real address space seen by the host processor 1807, any host processor can directly address these resources using valid address values. In at least one embodiment, a function of the accelerator integrated circuit 1836 is to physically separate the graphics processing engines 1831(1)-1831(N) so that they appear as independent units to the system.

[0336] In at least one embodiment, one or more graphics memories 1833(1)-1833(M) are coupled to each graphics processing engine 1831(1)-1831(N), and N = M. In at least one embodiment, the graphics memories 1833(1)-1833(M) store instructions and data processed by each graphics processing engine 1831(1)-1831(N). In at least one embodiment, the graphics memories 1833(1)-1833(M) may be volatile memory, such as DRAM (including stacked DRAM), GDDR memory (e.g., GDDR5, GDDR6), or HBM, and / or may be non-volatile memory, such as 3DXPoint or Nano-RAM.

[0337] In at least one embodiment, to reduce data traffic on the high-speed link 1840, a biasing technique can be used to ensure that the data stored in the graphics memory 1833(1)-1833(M) is the data most frequently used by the graphics processing engine 1831(1)-1831(N), and preferably data that the cores 1860A-1860D do not use (or at least do not use frequently). Similarly, in at least one embodiment, the biasing mechanism attempts to keep the data needed by the cores (and preferably not the graphics processing engine 1831(-1)-1831(N)) in the caches 1862A-1862D, 1856 and system memory 1814.

[0338] Figure 18C Another exemplary embodiment is shown, in which the accelerator integrated circuit 1836 is integrated within the processor 1807. In this embodiment, the graphics processing engines 1831(1)-1831(N) communicate directly with the accelerator integrated circuit 1836 via a high-speed link 1840 through interfaces 1837 and 1835 (which may also be any form of bus or interface protocol). In at least one embodiment, the accelerator integrated circuit 1836 can perform operations related to... Figure 18B The described operation is similar to that of the accelerator integrated circuit. However, due to its close proximity to the coherence bus 1864 and caches 1862A-1862D, 1856, it may have higher throughput. In at least one embodiment, the accelerator integrated circuit supports different programming models, including a dedicated process programming model (without graphics acceleration module virtualization) and a shared programming model (with virtualization), which may include a programming model controlled by the accelerator integrated circuit 1836 and a programming model controlled by the graphics acceleration module 1846.

[0339] In at least one embodiment, graphics processing engines 1831(1)-1831(N) are dedicated to a single application or process under a single operating system. In at least one embodiment, a single application can funnel requests from other applications to graphics processing engines 1831(1)-1831(N), thereby providing virtualization within a VM / partition.

[0340] In at least one embodiment, graphics processing engines 1831(1)-1831(N) can be shared by multiple VM / application partitions. In at least one embodiment, the shared model can use a hypervisor to virtualize graphics processing engines 1831(1)-1831(N) to allow each operating system to access them. In at least one embodiment, for a single-partition system without a hypervisor, the operating system owns graphics processing engines 1831(1)-1831(N). In at least one embodiment, the operating system can virtualize graphics processing engines 1831(1)-1831(N) to provide access to each process or application.

[0341] In at least one embodiment, the graphics acceleration module 1846 or the individual graphics processing engine 1831(1)-1831(N) uses a process handle to select a process element. In at least one embodiment, the process element is stored in system memory 1814 and can be addressed using the effective address to real address translation techniques described herein. In at least one embodiment, the process handle may be an implementation-specific value provided to the host process when registering its context with the graphics processing engine 1831(1)-1831(N) (i.e., invoking system software to add the process element to the process element linked list). In at least one embodiment, the lower 16 bits of the process handle may be the offset of the process element in the process element linked list.

[0342] Figure 18DAn exemplary accelerator integration slice 1890 is illustrated. In at least one embodiment, a "slice" includes a designated portion of the processing resources of an accelerator integrated circuit 1836. In at least one embodiment, the application is an effective address space 1882 in system memory 1814, which stores process element 1883. In at least one embodiment, process element 1883 is stored in response to a GPU call 1881 from an application 1880 executing on processor 1807. In at least one embodiment, process element 1883 contains the process state of the corresponding application 1880. In one embodiment, a job descriptor (WD) 1884 contained in process element 1883 may be a single job requested by the application, or it may contain a pointer to a job queue. In at least one embodiment, WD 1884 is a pointer to a job request queue in the effective address space 1882 of the application.

[0343] In at least one embodiment, the graphics acceleration module 1846 and / or the various graphics processing engines 1831(1)-1831(N) may be shared by all processes or a subset of processes in the system. In at least one embodiment, infrastructure may be included for setting process states and sending WD 1884 to the graphics acceleration module 1846 to begin operations in a virtualized environment.

[0344] In at least one embodiment, the dedicated process programming model is implementation-specific. In at least one embodiment, in this model, a single process owns either the graphics acceleration module 1846 or an individual graphics processing engine 1831. In at least one embodiment, when the graphics acceleration module 1846 is owned by a single process, the hypervisor initializes the accelerator integrated circuit for the owned partition, and when the graphics acceleration module 1846 is assigned, the operating system initializes the accelerator integrated circuit 1836 for the owned process.

[0345] In at least one embodiment, during operation, the WD acquisition unit 1891 in the accelerator integration slice 1890 acquires the next WD 1884, which includes instructions for work to be performed by one or more graphics processing engines of the graphics acceleration module 1846. In at least one embodiment, data from the WD 1884 may be stored in register 1845 and used by the MMU 1839, interrupt management circuitry 1847, and / or context management circuitry 1848, as shown. For example, one embodiment of the MMU 1839 includes segment / page roaming circuitry for accessing segment / page tables 1886 within the OS virtual address space 1885. In at least one embodiment, the interrupt management circuitry 1847 may process an interrupt event 1892 received from the graphics acceleration module 1846. In at least one embodiment, when performing graphics operations, a valid address 1893 generated by the graphics processing engines 1831(1)-1831(N) is translated into a real address by the MMU 1839.

[0346] In at least one embodiment, register 1845 is copied for each graphics processing engine 1831(1)-1831(N) and / or graphics acceleration module 1846, and said register 1845 may be initialized by a hypervisor or operating system. In at least one embodiment, each of these copied registers may be included in accelerator integration slice 1890. Exemplary registers that may be initialized by a hypervisor are shown in Table 1.

[0347]

[0348] Table 2 shows exemplary registers that can be initialized by the operating system.

[0349]

[0350] In at least one embodiment, each WD 1884 is specific to a particular graphics acceleration module 1846 and / or graphics processing engine 1831(1)-1831(N). In at least one embodiment, it contains all the information required for the graphics processing engine 1831(1)-1831(N) to complete its work, or it may be a pointer to a memory location where the application has set up a command queue for the work to be completed.

[0351] Figure 18E Additional details of an exemplary embodiment of the shared model are shown. This embodiment includes a hypervisor real address space 1898, in which a list of process elements 1899 is stored. In at least one embodiment, the hypervisor real address space 1898 can be accessed via a hypervisor 1896, which virtualizes the graphics acceleration module engine for operating system 1895.

[0352] In at least one embodiment, the shared programming model allows all processes or subsets of processes from all partitions or subsets of partitions in the system to use the graphics acceleration module 1846. In at least one embodiment, there are two programming models in which the graphics acceleration module 1846 is shared by multiple processes and partitions, namely, time-slice sharing and graphics-oriented sharing.

[0353] In at least one embodiment, in this model, the hypervisor 1896 owns the graphics acceleration module 1846 and makes its functionality available to all operating systems 1895. In at least one embodiment, for the graphics acceleration module 1846 to support virtualization through the hypervisor 1896, the graphics acceleration module 1846 may comply with certain requirements, such as (1) the job requests of the application must be autonomous (i.e., no state needs to be maintained between jobs), or the graphics acceleration module 1846 must provide a context saving and recovery mechanism, (2) the graphics acceleration module 1846 guarantees that the job requests of the application are completed within a specified amount of time, including any conversion errors, or the graphics acceleration module 1846 provides the ability to preempt job processing, and (3) when operating in a directed shared programming model, fairness between the processes of the graphics acceleration module 1846 must be ensured.

[0354] In at least one embodiment, application 1880 needs to make operating system 1895 system calls using the graphics acceleration module type, working descriptor (WD), permission mask register (AMR) value, and context save / restore region pointer (CSRP). In at least one embodiment, the graphics acceleration module type describes the target acceleration function for the system call. In at least one embodiment, the graphics acceleration module type can be a system-specific value. In at least one embodiment, the WD is specifically formatted for graphics acceleration module 1846 and can take the form of graphics acceleration module 1846 commands, valid address pointers to user-defined structures, valid address pointers to command queues, or any other data structure describing the work to be performed by graphics acceleration module 1846.

[0355] In at least one embodiment, the AMR value is the AMR state for the current process. In at least one embodiment, the value passed to the operating system is similar to that of the application that sets the AMR. In at least one embodiment, if the implementation of the accelerator integrated circuit 1836 (not shown) and the graphics acceleration module 1846 does not support the User Rights Mask Overwrite Register (UAMOR), the operating system may apply the current UAMOR value to the AMR value before passing the AMR in the hypervisor call. In at least one embodiment, the hypervisor 1896 may selectively apply the current Rights Mask Overwrite Register (AMOR) value before placing the AMR into the process element 1883. In at least one embodiment, CSRP is one of the registers 1845 containing the effective address of a region in the effective address space 1882 of the application for the graphics acceleration module 1846 to save and restore the context state. In at least one embodiment, this pointer is optional if it is not necessary to save state between jobs or when a job is preempted. In at least one embodiment, the context save / restore region may be fixed system memory.

[0356] Upon receiving a system call, operating system 1895 can verify that application 1880 has been registered and granted permission to use graphics acceleration module 1846. Then, in at least one embodiment, operating system 1895 uses the information shown in Table 3 to invoke hypervisor 1896.

[0357]

[0358] In at least one embodiment, upon receiving a hypervisor call, hypervisor 1896 verifies that operating system 1895 has been registered and granted permission to use graphics acceleration module 1846. Then, in at least one embodiment, hypervisor 1896 adds process element 1883 to a linked list of process elements of the corresponding graphics acceleration module 1846 type. In at least one embodiment, the process element may include the information shown in Table 4.

[0359]

[0360]

[0361] In at least one embodiment, the hypervisor initializes multiple accelerator integration slice 1890 registers 1845.

[0362] like Figure 18FAs shown, in at least one embodiment, a unified memory is used, which is addressable via a common virtual memory address space for accessing physical processor memories 1801(1)-1801(N) and GPU memories 1820(1)-1820(N). In this implementation, operations performed on GPUs 1810(1)-1810(N) utilize the same virtual / effective memory address space to access processor memories 1801(1)-1801(M) and vice versa, thereby simplifying programmability. In at least one embodiment, a first portion of the virtual / effective address space is allocated to processor memory 1801(1), a second portion to second processor memory 1801(N), a third portion to GPU memory 1820(1), and so on. In at least one embodiment, the entire virtual / effective memory space (sometimes referred to as the effective address space) is thus distributed across each of processor memory 1801 and GPU memory 1820, thereby allowing any processor or GPU to access that memory using a virtual address mapped to any physical memory.

[0363] In at least one embodiment, the bias / coherence management circuitry 1894A-1894E within one or more MMUs 1839A-1839E ensures cache coherence between one or more host processors (e.g., 1805) and the cache of the GPU 1810, and implements biasing techniques to indicate the physical memory in which certain types of data should be stored. In at least one embodiment, although in Figure 18F Several instances of bias / coherence management circuits 1894A-1894E are shown, but bias / coherence circuits can be implemented within the MMU of one or more host processors 1805 and / or within the accelerator integrated circuit 1836.

[0364] One embodiment allows GPU memory 1820 to be mapped as part of system memory and accessed using shared virtual memory (SVM) technology without suffering the performance drawbacks associated with full system cache coherence. In at least one embodiment, the ability to access GPU memory 1820 as system memory without the heavy overhead of cache coherence provides a favorable operating environment for GPU offloading. In at least one embodiment, this arrangement allows the host processor 1805 to software-set operands and access computation results without the overhead of conventional I / ODMA data copying. In at least one embodiment, such conventional copying includes driver calls, interrupts, and memory-mapped I / O (MMIO) accesses, all of which are less efficient than simple memory accesses. In at least one embodiment, the ability to access GPU memory 1820 without cache coherence overhead can be critical to the execution time of offloaded computations. In at least one embodiment, for example, in cases with high streaming write memory traffic, cache coherence overhead can significantly reduce the effective write bandwidth seen by GPU 1810. In at least one embodiment, the efficiency of operand setting, the efficiency of result access, and the efficiency of GPU computation can play a role in determining the effectiveness of GPU offloading.

[0365] In at least one embodiment, the selection of GPU bias and host processor bias is driven by a bias tracker data structure. In at least one embodiment, for example, a bias table can be used, which may be a page-granular structure (e.g., controlled at the memory page level) comprising one or two bits of memory pages attached to each GPU. In at least one embodiment, with or without a bias cache (e.g., for caching frequently / recently used entries in the bias table) in GPU 1810, the bias table can be implemented across one or more stolen memory ranges of GPU memory 1820. Alternatively, in at least one embodiment, the entire bias table can be maintained within the GPU.

[0366] In at least one embodiment, prior to actual access to GPU memory, an access to the bias table entry associated with each access to GPU-attached memory 1820 is performed, resulting in the following operations: In at least one embodiment, a local request from GPU 1810 to find its page in the GPU bias is forwarded directly to the corresponding GPU memory 1820. In at least one embodiment, a local request from the GPU to find its page in the host bias is forwarded to processor 1805 (e.g., via the high-speed link described herein). In at least one embodiment, a request from processor 1805 to find the requested page in the host processor bias completes a request similar to a normal memory read. Alternatively, a request for a page pointing to the GPU bias can be forwarded to GPU 1810. In at least one embodiment, if the GPU is not currently using the page, the GPU may subsequently migrate the page to the host processor bias. In at least one embodiment, the page bias state can be changed through a software-based mechanism, a hardware-assisted software mechanism, or, in limited cases, a purely hardware-based mechanism.

[0367] In at least one embodiment, a mechanism for changing the bias state employs an API call (e.g., OpenCL), which subsequently invokes the GPU's device driver. The device driver then sends a message (or enqueues a command descriptor) to the GPU, instructing the GPU to change the bias state and, in some migration, performs a cache refresh operation on the host. In at least one embodiment, the cache refresh operation is used for migration from the host processor 1805 bias to the GPU bias, but not for the reverse migration.

[0368] In at least one embodiment, cache coherence is maintained by temporarily rendering GPU bias pages that the host processor 1805 cannot cache. In at least one embodiment, to access these pages, the processor 1805 may request access from the GPU 1810, which may or may not immediately grant access. Therefore, in at least one embodiment, to reduce communication between the processor 1805 and the GPU 1810, it is beneficial to ensure that the GPU bias pages are pages needed by the GPU, not those needed by the host processor 1805, and vice versa.

[0369] One or more hardware structures 1015 are used to execute one or more embodiments. This document may combine... Figure 10A and / or Figure 10B Provide details about one or more hardware structures 1015.

[0370] In at least one embodiment, utilizing Figures 18A-18FThe system for object pose estimation is implemented using one or more systems described herein. In at least one embodiment, it utilizes... Figures 18A-18F The image describes one or more systems for determining the pose and relative size of objects from an image. In at least one embodiment, it utilizes... Figures 18A-18F The description of one or more systems implements one or more systems and / or processes, such as combining Figure 1-9 Those described.

[0371] Figure 19 Exemplary integrated circuits and associated graphics processors according to various embodiments described herein are illustrated, which may be manufactured using one or more IP cores. In addition to the illustrations, at least one embodiment may include other logic and circuitry, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0372] Figure 19 This is a block diagram illustrating an exemplary system on a chip integrated circuit 1900 that can be fabricated using one or more IP cores according to at least one embodiment. In at least one embodiment, the integrated circuit 1900 includes one or more application processors 1905 (e.g., CPUs), at least one graphics processor 1910, and may additionally include an image processor 1915 and / or a video processor 1920, any of which may be a modular IP core. In at least one embodiment, the integrated circuit 1900 includes peripheral or bus logic, which includes a USB controller 1925, a UART controller 1930, an SPI / SDIO controller 1935, and an I... 2 2S / I 2 2C controller 1940. In at least one embodiment, integrated circuit 1900 may include display device 1945 coupled to one or more of High Definition Multimedia Interface (HDMI) controller 1950 and Mobile Industrial Processor Interface (MIPI) display interface 1955. In at least one embodiment, storage may be provided by flash memory subsystem 1960, including flash memory and flash memory controller. In at least one embodiment, a memory interface may be provided via memory controller 1965 for accessing SDRAM or SRAM memory devices. In at least one embodiment, some integrated circuits also include embedded security engine 1970.

[0373] Inference and / or training logic 1015 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 10A and / or Figure 10BDetails regarding inference and / or training logic 1015 are provided. In at least one embodiment, inference and / or training logic 1015 may be used in integrated circuit 1900 to infer or predict operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0374] In at least one embodiment, utilizing Figure 19 The system for object pose estimation is implemented using one or more systems described herein. In at least one embodiment, it utilizes... Figure 19 The image describes one or more systems for determining the pose and relative size of objects from an image. In at least one embodiment, it utilizes... Figure 19 The description of one or more systems implements one or more systems and / or processes, such as combining Figure 1-9 Those described.

[0375] Figures 20A-20B Exemplary integrated circuits and associated graphics processors according to various embodiments described herein are illustrated, which may be manufactured using one or more IP cores. In addition to the illustrations, at least one embodiment may include other logic and circuitry, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0376] Figures 20A-20B This is a block diagram illustrating an exemplary graphics processor used within a SoC according to embodiments described herein. Figure 20A An exemplary graphics processor 2010 of a system-on-a-chip according to at least one embodiment is shown, which can be manufactured using one or more IP cores. Figure 20B Further exemplary graphics processor 2040 of a system-on-a-chip according to at least one embodiment is shown, which can be manufactured using one or more IP cores. In at least one embodiment, Figure 20A The graphics processor 2010 is a low-power graphics processor core. In at least one embodiment, Figure 20B The graphics processor 2040 is a higher-performance graphics processor core. In at least one embodiment, each graphics processor 2010, 2040 may be... Figure 19 A variant of the 1910 graphics processor.

[0377] In at least one embodiment, the graphics processor 2010 includes a vertex processor 2005 and one or more fragment processors 2015A-2015N (e.g., 2015A, 2015B, 2015C, 2015D to 2015N-1 and 2015N). In at least one embodiment, the graphics processor 2010 may execute different shader programs via separate logic, such that the vertex processor 2005 is optimized to perform operations for the vertex shader program, while one or more fragment processors 2015A-2015N perform fragment (e.g., pixel) shading operations for fragments or pixels or shader programs. In at least one embodiment, the vertex processor 2005 performs the vertex processing stage of the 3D graphics pipeline and generates primitive and vertex data. In at least one embodiment, one or more fragment processors 2015A-2015N use the primitive and vertex data generated by the vertex processor 2005 to generate framebuffers for display on a display device. In at least one embodiment, one or more fragment processors 2015A-2015N are optimized to execute fragment shader programs as provided in the OpenGL API, which can be used to perform operations similar to those of pixel shader programs provided in the Direct3D API.

[0378] In at least one embodiment, the graphics processor 2010 additionally includes one or more memory management units (MMUs) 2020A-2020B, one or more caches 2025A-2025B, and one or more circuit interconnects 2030A-2030B. In at least one embodiment, the one or more MMUs 2020A-2020B provide a virtual-to-physical address mapping for the graphics processor 2010, including for the vertex processor 2005 and / or fragment processors 2015A-2015N, which can reference vertex or image / texture data stored in memory, in addition to vertex or image / texture data stored in the one or more caches 2025A-2025B. In at least one embodiment, the one or more MMUs 2020A-2020B can be synchronized with other MMUs within the system, including with… Figure 19 One or more application processors 1905, graphics processors 1915, and / or video processors 1920 are associated with one or more MMUs, enabling each processor 1905-1920 to participate in a shared or unified virtual memory system. In at least one embodiment, one or more circuit interconnects 2030A-2030B enable the graphics processor 2010 to connect to other IP cores within the SoC via the SoC's internal bus or via a direct connection.

[0379] In at least one embodiment, the graphics processor 2040 includes one or more shader cores 2055A-2055N (e.g., 2055A, 2055B, 2055C, 2055D, 2055E, 2055F to 2055N-1 and 2055N), such as Figure 20B As shown, it provides a unified shader core architecture, where a single core or type or core can execute all types of programmable shader code, including shader program code for implementing vertex shaders, fragment shaders, and / or compute shaders. In at least one embodiment, the number of shader cores can vary. In at least one embodiment, the graphics processor 2040 includes an inter-core task manager 2045, which acts as a thread dispatcher to assign execution threads to one or more shader cores 2055A-2055N and tile units 2058 to accelerate tile-based rendering operations, where scene rendering operations are subdivided in image space, for example, to utilize local spatial consistency within the scene or optimize the use of internal caches.

[0380] Inference and / or training logic 1015 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 10A and / or Figure 10B Details regarding the inference and / or training logic 1015 are provided. In at least one embodiment, the inference and / or training logic 1015 may be integrated into an integrated circuit. Figure 20A and / or Figure 20B The above is used for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functions or architectures, or neural network use cases described herein.

[0381] In at least one embodiment, utilizing Figures 20A-20B The system for object pose estimation is implemented using one or more systems described herein. In at least one embodiment, it utilizes... Figures 20A-20B The image describes one or more systems for determining the pose and relative size of objects from an image. In at least one embodiment, it utilizes... Figures 20A-20B The description of one or more systems implements one or more systems and / or processes, such as combining Figure 1-9 Those described.

[0382] Figures 21A-21B Additional exemplary graphics processor logic according to embodiments described herein is illustrated. In at least one embodiment, Figure 21A It shows that it can be included in Figure 19 The graphics core 2100 within the graphics processor 1910, and in at least one embodiment, may be as follows: Figure 20B The Unified Shader Cores 2055A-2055N are shown. Figure 21B A highly parallel general-purpose graphics processing unit (“GPGPU”) 2130 suitable for deployment on a multi-chip module is shown in at least one embodiment.

[0383] In at least one embodiment, the graphics core 2100 includes a shared instruction cache 2102, texture units 2118, and a cache / shared memory 2120, which are common to the execution resources within the graphics core 2100. In at least one embodiment, the graphics core 2100 may include multiple slices 2101A-2101N or partitions of each core, and the graphics processor may include multiple instances of the graphics core 2100. In at least one embodiment, slices 2101A-2101N may include supporting logic, including local instruction caches 2104A-2104N, thread schedulers 2106A-2106N, thread dispatchers 2108A-2108N, and a set of registers 2110A-2110N. In at least one embodiment, slices 2101A-2101N may include a set of additional functional units (AFU 2112A-2112N), floating-point units (FPU 2114A-2114N), integer arithmetic logic units (ALU 2116A-2116N), address calculation units (ACU 2113A-2113N), double-precision floating-point units (DPFPU 2115A-2115N), and matrix processing units (MPU 2117A-2117N).

[0384] In at least one embodiment, the FPU 2114A-2114N can perform single-precision (32-bit) and half-precision (16-bit) floating-point operations, while the DPFPU 2115A-2115N performs double-precision (64-bit) floating-point operations. In at least one embodiment, the ALU 2116A-2116N can perform variable-precision integer operations with 8-bit, 16-bit, and 32-bit precision, and can be configured for mixed-precision operations. In at least one embodiment, the MPU 2117A-2117N can also be configured for mixed-precision matrix operations, including half-precision floating-point operations and 8-bit integer operations. In at least one embodiment, the MPU 2117-2117N can perform various matrix operations to accelerate machine learning application frameworks, including enabling support for accelerated generalized matrix-to-matrix multiplication (GEMM). In at least one embodiment, the AFU 2112A-2112N can perform additional logical operations not supported by floating-point or integer units, including trigonometric operations (e.g., sine, cosine, etc.).

[0385] Inference and / or training logic 1015 is used to perform inference and / or training operations associated with one or more embodiments. This is combined with... Figure 10A and / or Figure 10BDetails regarding the inference and / or training logic 1015 are provided. In at least one embodiment, the inference and / or training logic 1015 may be used in the graphics core 2100 to infer or predict operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures or neural network use cases described herein.

[0386] Figure 21B A general-purpose processing unit (GPGPU) 2130 is illustrated in at least one embodiment, which can be configured to enable highly parallel computational operations to be performed by a set of graphics processing units. In at least one embodiment, the GPGPU 2130 can be directly linked to other instances of the GPGPU 2130 to create a multi-GPU cluster to improve the training speed for deep neural networks. In at least one embodiment, the GPGPU 2130 includes a host interface 2132 for connection to a host processor. In at least one embodiment, the host interface 2132 is a PCI Express interface. In at least one embodiment, the host interface 2132 may be a vendor-specific communication interface or communication structure. In at least one embodiment, the GPGPU 2130 receives commands from the host processor and uses a global scheduler 2134 to allocate execution threads associated with those commands to a set of compute clusters 2136A-2136H. In at least one embodiment, the compute clusters 2136A-2136H share a cache memory 2138. In at least one embodiment, cache memory 2138 can be used as a higher-level cache within the cache memory of computing clusters 2136A-2136H.

[0387] In at least one embodiment, the GPGPU 2130 includes memories 2144A-2144B, which are coupled to computing clusters 2136A-2136H via a set of memory controllers 2142A-2142B. In at least one embodiment, memories 2144A-2144B may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), which includes graphics double data rate (GDDR) memory.

[0388] In at least one embodiment, each of the computing clusters 2136A-2136H includes a set of graphics cores, for example... Figure 21AThe graphics core 2100 may include various types of integer and floating-point logic units that can perform computational operations across a range of precisions, including precisions suitable for machine learning computations. For example, in at least one embodiment, at least a subset of the floating-point units in each computing cluster 2136A-2136H may be configured to perform 16-bit or 32-bit floating-point operations, while different subsets of the floating-point units may be configured to perform 64-bit floating-point operations.

[0389] In at least one embodiment, multiple instances of GPGPU 2130 can be configured as a computing cluster. In at least one embodiment, the communication used for synchronization and data exchange by computing clusters 2136A-2136H varies between embodiments. In at least one embodiment, multiple instances of GPGPU 2130 communicate via host interface 2132. In at least one embodiment, GPGPU 2130 includes an I / O hub 2139 that couples GPGPU 2130 to GPU link 2140, enabling direct connection to other instances of GPGPU 2130. In at least one embodiment, GPU link 2140 is coupled to a dedicated GPU-to-GPU bridge, which enables communication and synchronization between multiple instances of GPGPU 2130. In at least one embodiment, GPU link 2140 is coupled to a high-speed interconnect for sending and receiving data to and from other GPGPUs or parallel processors. In at least one embodiment, multiple instances of GPGPU 2130 reside in a separate data processing system and communicate via network devices accessible through host interface 2132. In at least one embodiment, GPU link 2140 may be configured to enable connection to a host processor other than or as a replacement for host interface 2132.

[0390] In at least one embodiment, GPGPU 2130 can be configured to train a neural network. In at least one embodiment, GPGPU 2130 can be used within an inference platform. In at least one embodiment, when GPGPU 2130 is used for inference, GPGPU 2130 may include fewer compute clusters 2136A-2136H compared to when GPGPU 2130 is used to train a neural network. In at least one embodiment, the memory technology associated with memories 2144A-2144B can differ between inference and training configurations, wherein higher bandwidth memory technology is dedicated to the training configuration. In at least one embodiment, the inference configuration of GPGPU 2130 can support inference-specific instructions. For example, in at least one embodiment, the inference configuration can provide support for one or more 8-bit integer dot product instructions, which can be used during the inference operation of the deployed neural network.

[0391] Inference and / or training logic 1015 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 10A and / or Figure 10B Details regarding the inference and / or training logic 1015 are provided. In at least one embodiment, the inference and / or training logic 1015 may be used in the GPGPU 2130 for inferring or predicting operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architecture, or neural network use cases described herein.

[0392] In at least one embodiment, utilizing Figures 21A-21B The system for object pose estimation is implemented using one or more systems described herein. In at least one embodiment, it utilizes... Figures 21A-21B The image describes one or more systems for determining the pose and relative size of objects from an image. In at least one embodiment, it utilizes... Figures 21A-21B The description of one or more systems implements one or more systems and / or processes, such as combining Figure 1-9 Those described.

[0393] Figure 22 A block diagram of a computer system 2200 according to at least one embodiment is shown. In at least one embodiment, the computer system 2200 includes a processing subsystem 2201 having one or more processors 2202 and a system memory 2204 communicating via an interconnect path that may include a memory hub 2205. In at least one embodiment, the memory hub 2205 may be a separate component within a chipset component or may be integrated within one or more processors 2202. In at least one embodiment, the memory hub 2205 is coupled to an I / O subsystem 2211 via a communication link 2206. In one embodiment, the I / O subsystem 2211 includes an I / O hub 2207 that enables the computer system 2200 to receive input from one or more input devices 2208. In at least one embodiment, the I / O hub 2207 enables a display controller to provide output to one or more display devices 2210A, the display controller being included in one or more processors 2202. In at least one embodiment, one or more display devices 2210A coupled to I / O hub 2207 may include local, internal or embedded display devices.

[0394] In at least one embodiment, the processing subsystem 2201 includes one or more parallel processors 2212 coupled to the memory hub 2205 via a bus or other communication link 2213. In at least one embodiment, the communication link 2213 may use any of many standards-based communication link technologies or protocols, such as, but not limited to, PCI Express, or may be a vendor-specific communication interface or communication architecture. In at least one embodiment, one or more parallel processors 2212 form a compute-intensive parallel or vector processing system, which may include a large number of processing cores and / or processing clusters, such as a multi-core integrated (MIC) processor. In at least one embodiment, one or more parallel processors 2212 form a graphics processing subsystem that can output pixels to one or more display devices 2210A coupled via an I / O hub 2207. In at least one embodiment, the parallel processors 2212 may also include a display controller and a display interface (not shown) to enable direct connection to one or more display devices 2210B.

[0395] In at least one embodiment, system storage unit 2214 may be connected to I / O hub 2207 to provide a storage mechanism for computer system 2200. In at least one embodiment, I / O switch 2216 may be used to provide an interface mechanism to enable connectivity between I / O hub 2207 and other components, such as network adapter 2218 and / or wireless network adapter 2219 which may be integrated into the platform, and various other devices that can be added via one or more additional devices 2220. In at least one embodiment, network adapter 2218 may be an Ethernet adapter or another wired network adapter. In at least one embodiment, wireless network adapter 2219 may include one or more of Wi-Fi, Bluetooth, Near Field Communication (NFC), or other network devices including one or more wireless devices.

[0396] In at least one embodiment, the computer system 2200 may include other components not explicitly shown, such as USB or other port connections, optical storage drives, video capture devices, etc., which may also be connected to the I / O hub 2207. In at least one embodiment, the interconnection can be implemented using any suitable protocol (e.g., PCI-based protocols such as PCI-Express or other bus or point-to-point communication interfaces and / or protocols). Figure 22 The communication paths of the various components, such as NV-Link high-speed interconnect or interconnect protocols.

[0397] In at least one embodiment, one or more parallel processors 2212 include circuitry optimized for graphics and video processing, including, for example, video output circuitry, and constituting a graphics processing unit (GPU). In at least one embodiment, the parallel processor 2212 includes circuitry optimized for general-purpose processing. In at least one embodiment, components of the computer system 2200 may be integrated with one or more other system elements on a single integrated circuit. For example, in at least one embodiment, the parallel processor 2212, memory hub 2205, processor 2202, and I / O hub 2207 may be integrated into a system-on-a-chip (SoC) integrated circuit. In at least one embodiment, components of the computer system 2200 may be integrated into a single package to form a system-in-package (SIP) configuration. In at least one embodiment, at least a portion of the components of the computer system 2200 may be integrated into a multi-chip module (MCM) that can interconnect with other MCMs to a modular computer system.

[0398] Inference and / or training logic 1015 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 10A and / or Figure 10B Details regarding the inference and / or training logic 1015 are provided. In at least one embodiment, the inference and / or training logic 1015 can... Figure 22 The system 2200 is used for reasoning or predicting operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures or neural network use cases described herein.

[0399] In at least one embodiment, utilizing Figure 22 The system for object pose estimation is implemented using one or more systems described herein. In at least one embodiment, it utilizes... Figure 22 The image describes one or more systems for determining the pose and relative size of objects from an image. In at least one embodiment, it utilizes... Figure 22 The description of one or more systems implements one or more systems and / or processes, such as combining Figure 1-9 Those described.

[0400] processor

[0401] Figure 23A A parallel processor 2300 according to at least one embodiment is illustrated. In at least one embodiment, various components of the parallel processor 2300 may be implemented using one or more integrated circuit devices, such as programmable processors, application-specific integrated circuits (ASICs), or field-programmable gate arrays (FPGAs). In at least one embodiment, the illustrated parallel processor 2300 is according to an exemplary embodiment. Figure 22 The variant of the 2212, which includes one or more parallel processors, is shown.

[0402] In at least one embodiment, the parallel processor 2300 includes a parallel processing unit 2302. In at least one embodiment, the parallel processing unit 2302 includes an I / O unit 2304 that enables communication with other devices, including other instances of the parallel processing unit 2302. In at least one embodiment, the I / O unit 2304 can be directly connected to other devices. In at least one embodiment, the I / O unit 2304 is connected to other devices using a hub or switch interface (e.g., a memory hub 2105). In at least one embodiment, the connection between the memory hub 2305 and the I / O unit 2304 forms a communication link 2313. In at least one embodiment, the I / O unit 2304 is connected to a host interface 2306 and a memory crossbar switch 2316, wherein the host interface 2306 receives commands for performing processing operations, and the memory crossbar switch 2316 receives commands for performing memory operations.

[0403] In at least one embodiment, when host interface 2306 receives a command buffer via I / O unit 2304, host interface 2306 can direct work operations to execute those commands to front end 2308. In at least one embodiment, front end 2308 is coupled to scheduler 2310, which is configured to assign commands or other work items to processing cluster array 2312. In at least one embodiment, scheduler 2310 ensures that processing cluster array 2312 is correctly configured and in an active state before assigning tasks to processing cluster array 2312. In at least one embodiment, scheduler 2310 is implemented via firmware logic executed on a microcontroller. In at least one embodiment, the microcontroller-implemented scheduler 2310 can be configured to perform complex scheduling and work assignment operations at both coarse and fine granular levels, thereby enabling fast preemption and context switching of threads executing on processing array 2312. In at least one embodiment, host software can demonstrate workloads for scheduling on processing array 2312 via one of multiple graphics processing paths. In at least one embodiment, the workload can then be automatically distributed on the processing array 2312 by the scheduler 2310 logic within the microcontroller, which includes the scheduler 2310.

[0404] In at least one embodiment, the processing cluster array 2312 may include up to "N" processing clusters (e.g., clusters 2314A, 2314B to 2314N), where "N" represents a positive integer (which may be an integer different from the integer "N" used in other diagrams). In at least one embodiment, each cluster 2314A-2314N of the processing cluster array 2312 may execute a large number of concurrent threads. In at least one embodiment, the scheduler 2310 may use various scheduling and / or work allocation algorithms to allocate work to the clusters 2314A-2314N of the processing cluster array 2312, which may vary depending on the workload generated by each type of program or computation. In at least one embodiment, scheduling may be handled dynamically by the scheduler 2310, or may be partially assisted by compiler logic during the compilation of program logic configured to be executed by the processing cluster array 2312. In at least one embodiment, the different clusters 2314A-2314N of the processing cluster array 2312 may be assigned to process different types of programs or to perform different types of computations.

[0405] In at least one embodiment, the processing cluster array 2312 can be configured to perform various types of parallel processing operations. In at least one embodiment, the processing cluster array 2312 is configured to perform general-purpose parallel computing operations. For example, in at least one embodiment, the processing cluster array 2312 may include logic for performing processing tasks, including filtering video and / or audio data, performing modeling operations, including physical operations, and performing data transformations.

[0406] In at least one embodiment, the processing cluster array 2312 is configured to perform parallel graphics processing operations. In at least one embodiment, the processing cluster array 2312 may include additional logic to support the execution of such graphics processing operations, including but not limited to texture sampling logic for performing texture operations, as well as tessellation logic and other vertex processing logic. In at least one embodiment, the processing cluster array 2312 may be configured to execute shader programs related to graphics processing, such as, but not limited to, vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. In at least one embodiment, the parallel processing unit 2302 may transfer data from system memory via I / O unit 2304 for processing. In at least one embodiment, during processing, the transferred data may be stored in on-chip memory (e.g., parallel processor memory 2322) and then written back to system memory.

[0407] In at least one embodiment, when the parallel processing unit 2302 is used to perform graphics processing, the scheduler 2310 may be configured to divide the processing workload into tasks of approximately equal size to better distribute graphics processing operations among the multiple clusters 2314A-2314N of the processing cluster array 2312. In at least one embodiment, portions of the processing cluster array 2312 may be configured to perform different types of processing. For example, in at least one embodiment, a first portion may be configured to perform vertex shading and topology generation, a second portion may be configured to perform tessellation and geometry shading, and a third portion may be configured to perform pixel shading or other screen-space operations to generate a rendered image for display. In at least one embodiment, intermediate data generated by one or more of the clusters 2314A-2314N may be stored in a buffer to allow intermediate data to be transferred between the clusters 2314A-2314N for further processing.

[0408] In at least one embodiment, the processing cluster array 2312 may receive processing tasks to be executed via a scheduler 2310, which receives commands defining the processing tasks from a front end 2308. In at least one embodiment, the processing task may include an index of data to be processed, such as surface (patch) data, raw data, vertex data, and / or pixel data, as well as state parameters and commands defining how the data is processed (e.g., what program to execute). In at least one embodiment, the scheduler 2310 may be configured to acquire an index corresponding to a task, or may receive an index from the front end 2308. In at least one embodiment, the front end 2308 may be configured to ensure that the processing cluster array 2312 is configured to be active before initiating the workload specified by an incoming command buffer (e.g., a batch buffer, push buffer, etc.).

[0409] In at least one embodiment, each of one or more instances of the parallel processing unit 2302 may be coupled to the parallel processor memory 2322. In at least one embodiment, the parallel processor memory 2322 may be accessed via a memory crossbar switch 2316, which may receive memory requests from the processing cluster array 2312 and the I / O unit 2304. In at least one embodiment, the memory crossbar switch 2316 may access the parallel processor memory 2322 via a memory interface 2318. In at least one embodiment, the memory interface 2318 may include a plurality of partition units (e.g., partition units 2320A, 2320B to 2320N), each of which may be coupled to a portion (e.g., a memory cell) of the parallel processor memory 2322. In at least one embodiment, the plurality of partition units 2320A-2320N are configured to be equal to the number of memory units, such that the first partition unit 2320A has a corresponding first memory unit 2324A, the second partition unit 2320B has a corresponding memory unit 2324B, and the Nth partition unit 2320N has a corresponding Nth memory unit 2324N. In at least one embodiment, the number of partition units 2320A-2320N may not be equal to the number of memory units.

[0410] In at least one embodiment, memory cells 2324A-2324N may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory. In at least one embodiment, memory cells 2324A-2324N may also include 3D stacked memory, including but not limited to high bandwidth memory (HBM). In at least one embodiment, rendering targets such as frame buffers or texture maps may be stored across memory cells 2324A-2324N, allowing partitioning cells 2320A-2320N to write portions of each rendering target in parallel, to efficiently utilize the available bandwidth of the parallel processor memory 2322. In at least one embodiment, local instances of the parallel processor memory 2322 may be excluded to facilitate a unified memory design that combines system memory with local cache memory.

[0411] In at least one embodiment, any of the clusters 2314A-2314N of the processing cluster array 2312 can process data to be written to any memory cell 2324A-2324N within the parallel processor memory 2322. In at least one embodiment, the memory crossbar switch 2316 can be configured to transfer the output of each cluster 2314A-2314N to any partition cell 2320A-2320N or another cluster 2314A-2314N, and the clusters 2314A-2314N can perform further processing operations on the output. In at least one embodiment, each cluster 2314A-2314N can communicate with the memory interface 2318 via the memory crossbar switch 2316 to read from or write to various external storage devices. In at least one embodiment, the memory crossbar switch 2316 has a connection to a memory interface 2318 for communication with I / O unit 2304, and a connection to a local instance of parallel processor memory 2322, thereby enabling processing units within different processing clusters 2314A-2314N to communicate with system memory or other memory not local to parallel processing unit 2302. In at least one embodiment, the memory crossbar switch 2316 may use virtual channels to separate traffic flows between clusters 2314A-2314N and partition units 2320A-2320N.

[0412] In at least one embodiment, multiple instances of the parallel processing unit 2302 may be provided on a single insert card, or multiple insert cards may be interconnected. In at least one embodiment, different instances of the parallel processing unit 2302 may be configured to interoperate, even if the different instances have different numbers of processing cores, different numbers of local parallel processor memories, and / or other configuration differences. For example, in at least one embodiment, some instances of the parallel processing unit 2302 may include higher-precision floating-point units relative to other instances. In at least one embodiment, a system combining one or more instances of the parallel processing unit 2302 or the parallel processor 2300 may be implemented in various configurations and form factors, including but not limited to desktop, laptop, or handheld personal computers, servers, workstations, game consoles, and / or embedded systems.

[0413] Figure 23B This is a block diagram of a partitioning unit 2320 according to at least one embodiment. In at least one embodiment, the partitioning unit 2320 is... Figure 23AThis is an example of one of the partitioning units 2320A-2320N. In at least one embodiment, the partitioning unit 2320 includes an L2 cache 2321, a frame buffer interface 2325, and a ROP 2326 (raster operation unit). In at least one embodiment, the L2 cache 2321 is a read / write cache configured to perform load and store operations received from the memory crossbar switch 2316 and the ROP 2326. In at least one embodiment, the L2 cache 2321 outputs read misses and urgent write-back requests to the frame buffer interface 2325 for processing. In at least one embodiment, updates can also be sent to the frame buffer for processing via the frame buffer interface 2325. In at least one embodiment, the frame buffer interface 2325 communicates with memory cells in the parallel processor memory (such as...). Figure 23A It interacts with one of the memory cells 2324A-2324N (e.g., within the parallel processor memory 2322).

[0414] In at least one embodiment, ROP 2326 is a processing unit that performs raster operations such as stenciling, z-testing, blending, etc. In at least one embodiment, ROP 2326 then outputs processed graphics data stored in graphics memory. In at least one embodiment, ROP 2326 includes compression logic to compress depth or color data written to memory and decompress depth or color data read from memory. In at least one embodiment, the compression logic may be lossless compression logic utilizing one or more of a variety of compression algorithms. In at least one embodiment, the type of compression performed by ROP 2326 may vary based on the statistical characteristics of the data to be compressed. For example, in at least one embodiment, incremental color compression is performed based on depth and color data on a per-tile basis.

[0415] In at least one embodiment, ROP 2326 is included within each processing cluster (e.g., Figure 23A Clusters 2314A-2314N are used instead of partition units 2320. In at least one embodiment, read and write requests for pixel data are made via memory crossbar switch 2316 instead of pixel fragment data transfer. In at least one embodiment, the processed graphics data can be displayed on a display device (such as...). Figure 22 Displayed by one or more display devices 2210, routed by processor 2202 for further processing, or by... Figure 23A One of the processing entities within the parallel processor 2300 is routed for further processing.

[0416] Figure 23C This is a block diagram of a processing cluster 2314 within a parallel processing unit according to at least one embodiment. In at least one embodiment, the processing cluster is... Figure 23A An instance of one of the processing clusters 2314A-2314N. In at least one embodiment, the processing cluster 2314 can be configured to execute a number of threads in parallel, where a "thread" refers to an instance of a specific program executing on a particular set of input data. In at least one embodiment, a Single Instruction Multiple Data (SIMD) instruction issuing technique is used to support the parallel execution of a large number of threads without providing multiple independent instruction units. In at least one embodiment, a Single Instruction Multiple Threading (SIMT) technique is used to support the parallel execution of a large number of generally synchronous threads, which uses a common instruction unit configured to issue instructions to a set of processing engines within each processing cluster.

[0417] In at least one embodiment, the operation of the processing cluster 2314 can be controlled by a pipeline manager 2332 that assigns processing tasks to the SIMT parallel processors. In at least one embodiment, the pipeline manager 2332... Figure 23A The scheduler 2310 receives instructions and manages the execution of these instructions via the graphics multiprocessor 2334 and / or texture unit 2336. In at least one embodiment, the graphics multiprocessor 2334 is an exemplary instance of a SIMT parallel processor. However, in at least one embodiment, the processing cluster 2314 may include various types of SIMT parallel processors with different architectures. In at least one embodiment, the processing cluster 2314 may include one or more instances of the graphics multiprocessor 2334. In at least one embodiment, the graphics multiprocessor 2334 can process data, and the data cross switch 2340 can be used to distribute the processed data to one of a number of possible destinations (including other shader units). In at least one embodiment, the pipeline manager 2332 can facilitate the distribution of processed data by specifying the destination of the processed data to be distributed via the data cross switch 2340.

[0418] In at least one embodiment, each graphics multiprocessor 2334 within the processing cluster 2314 may include the same set of functional execution logic (e.g., arithmetic logic units, load-memory units, etc.). In at least one embodiment, the functional execution logic may be configured in a pipelined manner, wherein new instructions may be issued before previous instructions complete. In at least one embodiment, the functional execution logic supports a variety of operations, including integer and floating-point arithmetic, comparison operations, Boolean operations, shift operations, and computation of various algebraic functions. In at least one embodiment, the same functional unit hardware may be used to perform different operations, and any combination of functional units may exist.

[0419] In at least one embodiment, instructions sent to the processing cluster 2314 constitute threads. In at least one embodiment, a group of threads executed across a set of parallel processing engines is a thread group. In at least one embodiment, the thread group executes a general program on different input data. In at least one embodiment, each thread within the thread group may be assigned to a different processing engine within the graphics multiprocessor 2334. In at least one embodiment, the thread group may include fewer threads than the number of processing engines within the graphics multiprocessor 2334. In at least one embodiment, when the number of threads included in the thread group is less than the number of processing engines, one or more processing engines may be idle during a loop that is processing the thread group. In at least one embodiment, the thread group may also include more threads than the number of processing engines within the graphics multiprocessor 2334. In at least one embodiment, when the thread group includes more threads than the number of processing engines within the graphics multiprocessor 2334, processing can be performed in consecutive clock cycles. In at least one embodiment, multiple thread groups can be executed simultaneously on the graphics multiprocessor 2334.

[0420] In at least one embodiment, the graphics multiprocessor 2334 includes an internal cache memory for performing load and store operations. In at least one embodiment, the graphics multiprocessor 2334 may forgo the internal cache and use a cache memory within the processing cluster 2314 (e.g., L1 cache 2348). In at least one embodiment, each graphics multiprocessor 2334 may also access partition units (e.g., Figure 23A The L2 cache is located within partition units 2320A-2320N, which are shared among all processing clusters 2314 and can be used to transfer data between threads. In at least one embodiment, the graphics multiprocessor 2334 can also access off-chip global memory, which may include one or more of local parallel processor memory and / or system memory. In at least one embodiment, any memory outside of the parallel processing unit 2302 can be used as global memory. In at least one embodiment, the processing cluster 2314 includes multiple instances of the graphics multiprocessor 2334, which can share common instructions and data that can be stored in the L1 cache 2348.

[0421] In at least one embodiment, each processing cluster 2314 may include a memory management unit (“MMU”) 2345 configured to map virtual addresses to physical addresses. In at least one embodiment, one or more instances of the MMU 2345 may reside in Figure 23AThe memory interface 2318 is located within the MMU 2345. In at least one embodiment, the MMU 2345 includes a set of page table entries (PTEs) for mapping virtual addresses to physical addresses of tiles and optionally to cache line indices. In at least one embodiment, the MMU 2345 may include an address translation back buffer (TLB) or a cache that may reside within the graphics multiprocessor 2334, the L1 cache 2348, or the processing cluster 2314. In at least one embodiment, physical addresses are processed to allocate surface data access locality for efficient request interleaving between partition units. In at least one embodiment, cache line indices may be used to determine whether a request for a cache line is a hit or a miss.

[0422] In at least one embodiment, the processing cluster 2314 can be configured such that each graphics multiprocessor 2334 is coupled to a texture unit 2336 to perform texture mapping operations that determine texture sample locations, read texture data, and filter texture data. In at least one embodiment, texture data is read as needed from an internal texture L1 cache (not shown) or from an L1 cache within the graphics multiprocessor 2334, and texture data is also retrieved from an L2 cache, local parallel processor memory, or system memory. In at least one embodiment, each graphics multiprocessor 2334 outputs a processed task to a data crossbar switch 2340 to provide the processed task to another processing cluster 2314 for further processing or to store the processed task in an L2 cache, local parallel processor memory, or system memory via a memory crossbar switch 2316. In at least one embodiment, a preROP 2342 (pre-raster operation unit) is configured to receive data from the graphics multiprocessor 2334 and direct the data to a ROP unit, which can be associated with a partitioning unit (e.g., [missing information]). Figure 23A The PreROP 2342 unit is located together with the partitioning units 2320A-2320N. In at least one embodiment, the PreROP 2342 unit can perform optimizations for color blending, organize pixel color data, and perform address translation.

[0423] Inference and / or training logic 1015 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 10A and / or Figure 10B Details regarding inference and / or training logic 1015 are provided. In at least one embodiment, inference and / or training logic 1015 may be used in graphics processing cluster 2314 for inferring or predicting operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architecture, or neural network use cases described herein.

[0424] Figure 23D A graphics multiprocessor 2334 according to at least one embodiment is illustrated. In at least one embodiment, the graphics multiprocessor 2334 is coupled to a pipeline manager 2332 of a processing cluster 2314. In at least one embodiment, the graphics multiprocessor 2334 has an execution pipeline including, but not limited to, an instruction cache 2352, an instruction unit 2354, an address mapping unit 2356, a register file 2358, one or more general-purpose graphics processing unit (GPGPU) cores 2362, and one or more load / store units 2366. In at least one embodiment, the GPGPU cores 2362 and ...

Claims

1. A method for determining the pose and relative size of an object depicted in an image, the image having a set of features, the method comprising: Process this set of features to determine the first set of data corresponding to the object; The second set of data is calculated at least in part based on this set of features and the first set of data; A set of values ​​corresponding to the relative size of the object is calculated, at least in part, based on the second set of data; as well as The first set of data, the second set of data, and the set of values ​​are processed to determine the pose and relative size of the object depicted in the image.

2. The method according to claim 1, further comprising: Use the first set of data and the second set of data to calculate a set of coordinates; as well as The set of coordinates is processed using one or more n-point perspective PnP algorithms to determine the pose of the object.

3. The method of claim 2, wherein the set of coordinates corresponds to one or more vertices of the enclosing cuboid of the object.

4. The method of claim 1, wherein the first set of data at least indicates the center and size of the two-dimensional 2D bounding box of the object.

5. The method of claim 1, wherein the second set of data indicates at least one or more positions of one or more vertices of the three-dimensional 3D bounding box of the object.

6. The method of claim 1, wherein the relative size of the object corresponds to the enclosing cuboid of the object.

7. The method of claim 6, wherein the set of values ​​includes a width value, a height value, and a length value, which indicate the ratio of the width to the height to the length of the enclosing cuboid.

8. The method according to claim 1, further comprising: The absolute scale of the object is calculated at least in part based on its relative size.

9. A system comprising: One or more computers, each having one or more processors, are used to train one or more neural networks to: Get an image of an object that depicts an object category; One or more features are determined based at least in part on the image; as well as A set of values ​​is predicted based on one or more features, which at least indicates the position and relative size of the object in the image.

10. The system of claim 9, wherein the set of values ​​includes: The first set of values ​​corresponding to the first set of heatmaps; as well as The second set of values ​​corresponding to the second set of heatmaps.

11. The system of claim 10, wherein the first set of heat maps corresponds to the center of the object.

12. The system of claim 10, wherein the second set of heatmaps corresponds to the vertices of the three-dimensional 3D bounding box of the object.

13. The system of claim 12, wherein the set of values ​​includes one or more values ​​indicating the ratio between the dimensions of the 3D bounding box.

14. The system of claim 9, wherein the one or more neural networks are trained using training data, the training data comprising images of objects depicting the object category.

15. The system of claim 9, wherein the one or more processors use one or more L1 loss functions to train the one or more neural networks.

16. The system of claim 9, wherein the one or more processors are further configured to train the one or more neural networks to: Acquire another image, which depicts different objects of different object categories; Determining one or more features based at least in part on another image; and Predict another set of values ​​based on the other or more features, the other set of values ​​indicating at least another location and another relative size of the different object in the other image.

17. A processor, comprising: One or more circuits for using one or more neural networks to: Process a set of features corresponding to an image to determine a first set of data corresponding to an object depicted in the image; The second set of data is calculated at least in part based on this set of features and the first set of data; A set of values ​​corresponding to the relative size of the object is calculated, at least in part, based on the second set of data; as well as The first set of data, the second set of data, and the set of values ​​are processed to determine the pose and relative size of the object depicted in the image.

18. The processor of claim 17, wherein the one or more circuits are configured to use the one or more neural networks for: Using the first set of data and the second set of data, a set of coordinates is calculated, which corresponds to one or more vertices of the shape surrounding the object; and Use this set of coordinates to determine the pose of the object.

19. The processor of claim 17, wherein the one or more neural networks comprise one or more convolutionally gated recurrent unit (GRU) networks.

20. The processor of claim 17, wherein the first set of data is used at least to indicate the center and size of the two-dimensional 2D bounding box of the object.

21. The processor of claim 17, wherein the image is captured from one or more autonomous devices.

22. The processor of claim 17, wherein the set of values ​​includes width, height, and length values ​​indicating the ratio of the width, height, and length of the cuboid.

23. The processor of claim 17, wherein the one or more circuits are configured to obtain the set of features using the one or more neural networks through one or more convolution operations.

24. The processor of claim 17, wherein the second set of data is used to indicate at least one or more positions of one or more vertices of the three-dimensional 3D bounding box of the object.

25. The processor of claim 17, wherein the relative dimensions of the object correspond to the enclosing cuboid of the object.

26. The processor of claim 17, wherein the one or more circuits are configured to use the one or more neural networks to: calculate an absolute scale of the object at least in part based on the relative size of the object.

27. A non-transitory computer-readable storage medium having executable instructions stored thereon, which, as a result of execution of said executable instructions by one or more processors of a computer system, cause said computer system to at least: Obtain an image depicting an object of the first category; One or more features are generated, at least in part, based on the image; One or more neural networks are used to process the one or more features to determine at least one or more coordinate values ​​and one or more relative size values ​​of the object; as well as One or more algorithms are used to process the one or more coordinate values ​​and the one or more relative size values ​​to calculate the six-degree-of-freedom (6DOF) pose of the object.

28. The non-transitory computer-readable storage medium of claim 27, wherein the one or more coordinate values ​​are the coordinates of the vertices of the enclosing cuboid of the object within the image.

29. The non-transitory computer-readable storage medium of claim 27, wherein the instructions further comprise an instruction that, as a result of execution by the one or more processors of the computer system, causes the computer system to at least: Acquire a set of data corresponding to the image capture device that captured the image; and The 6DOF pose of the object is calculated using one or more of the algorithms and the set of data.

30. The non-transitory computer-readable storage medium of claim 27, wherein the one or more features comprise one or more feature maps of one or more resolutions.

31. The non-transitory computer-readable storage medium of claim 27, wherein the image is captured from one or more robotic systems.

32. The non-transitory computer-readable storage medium of claim 31, wherein the instructions further comprise instructions that, as a result of execution by one or more processors of the computer system, cause the computer system to at least cause the one or more robot systems to perform a robot grasping task related to the object using the 6DOF pose.

Images