Hybrid architecture for borderless displays

Abstract

The present invention relates to a hybrid architecture for zero-edge displays. This invention describes a hybrid architecture and method for operating a display panel. In one embodiment, row driver functionality and pixel driver functionality are combined into a set of trunk hybrid pixel driver chiplets, where global signal lines are distributed to the trunk hybrid pixel driver chiplet, where global signals are manipulated and distributed to a row of pixel driver chiplets.

Description

[0001] Description of the case

[0002] This application is a divisional application of the Chinese invention patent application with application number 201910434000.5 filed on May 23, 2019 and entitled “Hybrid Architecture for Zero Border Display”.

[0003] Related patent applications

[0004] This patent application claims priority to U.S. Provisional Application No. 62 / 686,297, filed on June 18, 2018, which is incorporated herein by reference. Technical Field

[0005] Embodiments described herein relate to display systems and, more particularly, to passive matrix displays and methods of operation. Background Art

[0006] Display panels are used in a variety of electronic devices. Common display panel types include active matrix display panels, in which each pixel element, such as a light emitting diode (LED), can be driven individually to display a frame of data, and passive matrix display panels, in which rows and columns of pixel elements can be driven in a frame of data. Both active and passive matrices have been proposed for making tiled displays, where the display panel size exceeds the limitations imposed by the substrate and device size restrictions. Summary of the Invention

[0007] The present invention describes a hybrid architecture display panel and an operating method. In one embodiment, the display panel includes a bus column of global signal lines, a plurality of rows of row function signal lines, and a plurality of rows of pixel driver chips, each row of pixel driver chips being connected to a corresponding row of row function signal lines, and each pixel driver chip being connected to a corresponding matrix of light-emitting diodes (LEDs). Each row of pixel driver chips may include a group of trunk hybrid pixel driver chips and a group of LED-driven pixel driver chips. The bus column of global signal lines is coupled to a group of trunk hybrid pixel driver chips for each row of pixel driver chips, and each independent trunk hybrid pixel driver chip includes an input connected to a corresponding global signal line, and an output connected to a corresponding row function signal line in a corresponding row of row function signal lines to transmit a corresponding control signal to the corresponding row of pixel driver chips.

[0008] In one embodiment, the hybrid pixel driver chip includes a VST driver circuit to determine whether a particular row is on or off and to propagate the VST signal from the top to the bottom of the display panel. Furthermore, the hybrid pixel driver chip includes a signal modulator circuit to select whether to use the global row function signal line or the backup line input and transmits the internal signal to the multiplexer driver circuit that generates the manipulated row function signal. Furthermore, the hybrid pixel driver chip includes an LED driver circuit 1460 for driving the corresponding LED matrix. Thus, the hybrid pixel driver chip includes a hybrid architecture to support both row driver and pixel driver functions.

[0009] In one embodiment, a method for programming a display is provided, the method comprising propagating a VST signal to a row of pixel driver chips, receiving token driver configuration data using a trunk hybrid pixel driver chip, receiving a global configuration update pulse using a trunk hybrid pixel driver chip, receiving row driver configuration data using a token-activated trunk hybrid pixel driver chip, and transmitting a manipulated configuration update signal from the trunk hybrid pixel driver chip to the row of pixel driver chips. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a schematic top view of a partial passive matrix display including multiple rows of hybrid pixel driver chips according to one embodiment.

[0011] Figure 2 is a schematic diagram of a light emitting diode (LED) matrix coupled to terminals of a hybrid pixel driver chip according to one embodiment.

[0012] Figure 3 is a schematic diagram of a matrix of redundant LED pairs driven by redundant hybrid pixel driver chip pairs according to one embodiment.

[0013] Figure 4 is a schematic top view of a tile-based display panel with cutouts and spline corners, according to one embodiment.

[0014] Figure 5A is a schematic top view of a tile-based display including a tile backbone with a hybrid pixel driver chip used as a row driver, according to one embodiment.

[0015] Figure 5B From the perspective of data and configuration updates according to an implementation plan Figure 5A Schematic top view of the display tile partition of the display.

[0016] Figure 6 is a routing diagram of the row functional partitioning within the hybrid pixel driver chip backbone according to one embodiment.

[0017] Figure 7 FIG. 1 is a layout diagram of row control signal redundancy and backup within a hybrid pixel driver chip backbone according to one embodiment.

[0018] Figure 8 is a routing diagram of transmit frame sync and transmit row sync buffers within a pixel driver chip row according to one embodiment.

[0019] Figure 9 is a routing diagram for vertical signal redundancy and transmit clock vertical and horizontal buffering according to one embodiment.

[0020] Figure 10 is a routing diagram of the backbone routing of global signal lines to rows and row signal lines of a hybrid pixel driver chip according to one embodiment.

[0021] Figure 11 is a routing diagram for horizontal control signal redundancy for VST and backup line connections according to one embodiment.

[0022] Figure 12 is a routing diagram for horizontal control signal redundancy for row function signal connections according to one embodiment.

[0023] Figure 13 is a routing diagram of global signal line and row signal line connections to and from the backbone of a tile-based display panel, according to one embodiment.

[0024] Figure 14 is a circuit block diagram of a backbone hybrid pixel driver chip according to one embodiment.

[0025] Figure 15 is a timing diagram for data loading of a hybrid pixel driver chip for token activation according to one embodiment.

[0026] Figure 16 is a flow chart of a method for programming a display tile by resetting according to one embodiment. DETAILED DESCRIPTION

[0027] The present invention describes a hybrid architecture and method for operating a display panel, in which row functionality and pixel driver functionality are combined in the backbone of a hybrid pixel driver chip. This reduces the overall silicon die area by eliminating a dedicated row driver chip. Furthermore, this arrangement facilitates the fabrication of tile-based display panel layouts with configurable sizes and shapes, reduced or zero borders, and the area traditionally reserved for driver bumps can be omitted.

[0028] In some embodiments, a tile-based display panel may include an arrangement of pixel driver chips to drive a local pixel matrix in a local passive matrix (LPM). Compared to a direct drive approach where each pin of the pixel driver is connected to one LED, the LPM arrangement according to the embodiments can significantly reduce the panel peak current, as well as the silicon area associated with the pixel driver. In some embodiments, the pixel driver chips are distributed between the LEDs. This configuration may include pixel driver chips located laterally between LEDs on the same side of the display substrate. Depending on the complexity, the pixel driver chips may be longer than the corresponding LED matrix they control (e.g., wider than the row length of the corresponding matrix). Thus, the pixel driver chips may be staggered in rows in a zigzag pattern, for example. There is no need to mount the pixel driver chips on the same surface as the LEDs, or between the LEDs. According to all embodiments described herein, the pixel driver chips may also be located within the display substrate and may be positioned face-up (e.g., with terminals facing toward the LEDs), face-down (e.g., with terminals facing away from the LEDs), or both (with terminals located on the top and bottom sides). Thus, where pixel driver chips are described herein as being distributed around or interspersed in a display area, it will be understood that the pixel driver chips may be located on a display substrate (e.g., surface mounted) or embedded within a display substrate. According to all embodiments described herein, the pixel driver chips may be adjacent to a corresponding plurality of pixels. Again, this includes two configurations of pixel driver chips on or within a display substrate, wherein the pixel driver chips are adjacent to LEDs on a display substrate. Tile-based LPM displays according to embodiments may be implemented in both large area displays as well as high resolution displays with high pixel density. Furthermore, the LED and pixel driver chip sizes are capable of scaling from macroscopic to microscopic sizes. In one embodiment, for a display with high resolution and pixel density, the pixel driver chip may have a maximum dimension of less than 200 μm, or even less than 100 μm, wherein the LED maximum dimension is less than 100 μm, or even less than 20 μm, such as less than 10 μm, or even less than 5 μm.

[0029] In various embodiments, description is made with reference to the accompanying drawings. However, certain embodiments may be implemented without one or more of these specific details or in combination with other known methods and configurations. In the following description, many specific details such as specific configurations, dimensional processes, etc. are shown to provide a thorough understanding of the embodiments. In other examples, well-known techniques and components have not been described in particular detail to avoid unnecessarily obscuring the embodiments. References to "one embodiment" throughout the specification refer to specific features, structures, configurations, or characteristics described in conjunction with the embodiments being included in at least one embodiment. Therefore, the phrase "in one embodiment" appearing in multiple places throughout the specification does not necessarily refer to the same embodiment. In addition, specific features, structures, configurations, or characteristics may be combined in one or more embodiments in any appropriate manner.

[0030] Figure 1 is a schematic top view of a partial passive matrix display 100 according to one embodiment, which includes rows [1, 2, .. N] of pixel driver chiplets 110. Each pixel driver chiplet 110 may include two portions or slices 0, 1 for operation of the pixel matrix 102 above and below the pixel driver chiplet 110. Slices 0, 1 may be arranged in a master / redundant configuration or a master / slave configuration. Each matrix 102 may include a plurality of LEDs 104 and a plurality of pixels 106. In some configurations, the rows of pixel driver chiplets 110 are arranged into rows where every other row is either a row of primary pixel driver chiplets (e.g., rows 1, 3, etc.) or a row of redundant pixel driver chiplets 110 (e.g., rows 2, 4, etc.). It should be understood that the number and size of pixel driver chiplets 110 within the display area 105 are not necessarily drawn to scale and are exaggerated for schematic illustration.

[0031] Generally speaking, the local passive matrix display 100 may include a display substrate 101, a display area 105, an optional column driver or signal line driver circuit, and an external control circuit 140 attached to the display substrate 101 to provide various control signals, video signals and power supply voltage to the display substrate 101.

[0032] Now see Figure 2 , according to one embodiment, a schematic diagram of a matrix 102 of light emitting diodes (LEDs) coupled to terminals of a pixel driver chip is provided. In one embodiment, a local passive matrix display includes a pixel driver chip 110, a plurality of pixels 106 arranged into a plurality of display rows, and a plurality of terminals 111 of the pixel driver chip 110 coupled to the LEDs 104 of the plurality of pixels 106. Figure 2As shown, a portion of the terminals 111 are coupled to corresponding row line switches and level shifters within the pixel driver chip 110 and corresponding rows of LEDs 104, and a portion of the terminals 111 are coupled to output drivers 116 of the pixel driver chip 110 and corresponding columns of LEDs 104. For example, the interconnects 112 may connect electrodes (e.g., cathodes) of a row of LEDs 104 to corresponding row line switches and level shifters, while the interconnects 114 may connect electrodes (e.g., anodes) of a column of LEDs 104 to corresponding output drivers 116, or vice versa. Figure 2 The particular embodiment shown shows the matrix 102 of LEDs 104 connected to a portion of a pixel driver chip 110, and more specifically, to "slice 1" of the pixel driver chip 110. Similar connections may also be provided for a second portion, or "slice 0," of the pixel driver chip 110. It should be understood that the use of the term "slice" is a simplification and in no way implies a geometric partitioning of the circuitry within the pixel driver chip 110, but rather is a simple reference to the top and bottom connections shown in the illustration. Additionally, the specific selection of eight rows and six columns of LEDs within the matrix is ​​exemplary, and the embodiments are not limited thereto.

[0033] In one embodiment, a first terminal 111A of the pixel driver chip 110 is coupled to a first row of light emitting diodes (LEDs) 104 in a plurality of pixels, a second terminal 111B of the pixel driver chip 110 is coupled to a second row of LEDs in a plurality of pixels, and a third terminal 111C is coupled to a first column of LEDs in a plurality of pixels, the first column of LEDs including a first LED in a first string (e.g., row) of LEDs and a first LED in a second string (e.g., row) of LEDs. A fourth terminal 111D is coupled to a second column of LEDs in a plurality of pixels, the second column of LEDs including a second LED in the first string of LEDs and a second LED in the second string of LEDs. As shown, the third terminal may be coupled to a first output driver 116 of the pixel driver chip, and the fourth terminal may be coupled to a second output driver 116 of the pixel driver chip. As shown Figure 1 As shown, the pixel driver chips 110 may be located in a row of pixel driver chips arranged in a row on the display substrate. In other embodiments, the row of pixel driver chips may be bent along the display area of ​​the display substrate.

[0034] In the embodiment shown, the rows of LEDs 104 correspond to different emission colors of the LEDs, such as red (R), green (G), blue (B) in an RGB pixel arrangement.Alternative pixel arrangements may also be used.

[0035] Figure 3 is a schematic diagram of a matrix of redundant LED pairs driven by redundant pairs of pixel driver chips, according to one embodiment. Figure 3Shows something like Figure 2 102 is shown in which redundant LEDs 104 are added within pixels 106. In such an embodiment, a portion (chip 1) of pixel driver chip 110N-1 includes terminals 111 coupled to LEDs 104, similar to those described with reference to FIG. Figure 2 Furthermore, within the same matrix 102, a portion of the pixel driver chiplet 110N (chiplet 0) (e.g., in the next row of pixel driver chips) is similarly coupled to the redundant LEDs 104 using separate interconnects 112 and 114. Thus, providing separate anode contacts and separate cathode contacts for pixel driver chiplet N-1 and pixel driver chiplet N avoids timing conflicts between the primary pixel driver portion and the redundant pixel driver portion (e.g., chiplet 0, chiplet 1) associated with the same matrix 102.

[0036] In one embodiment, such as Figure 3 As shown, separate cathodes can be provided for the primary and redundant portions or slices of the pixel driver chiplet 110. In one method of operation, half of the pixel driver chiplets 110 (e.g., the primary pixel driver chiplets 110) are active by default. Thus, every other row of pixel driver chiplets 110 is active. The LEDs 104 coupled to the pixel driver chiplets 110 can also be staggered, for example, to mitigate visual artifacts.

[0037] In some embodiments, for each pixel driver chip, the main portion or slice 0 of each pixel driver chip is defaulted to active, and the slave portion or slice 1 of each pixel driver chip is defaulted to passive. Therefore, the slave portion or redundant portion only becomes active if the main portion or main portion from the adjacent pixel driver chip is defective or passive. In some embodiments, the portion or slice 0, 1 of the main pixel driver chip is defaulted to active, and the corresponding portion or slice 0, 1 of the redundant pixel driver chip is defaulted to passive. Therefore, a portion or all of the redundant pixel driver chip only becomes active if the adjacent main pixel driver chip portion is defective or passive. According to the embodiment, the arrangement of the LED matrix, pixel driver chips and redundant configuration can result in a specific LED emission progression in the operation of the display panel.

[0038] Figure 4530 and a spline corner according to one embodiment. Specifically, the arrangement of the pixel driver chip 110 according to the embodiment can eliminate the need for driver protrusions on the edge of the display panel. As a result, the display substrate 101 can have a reduced or zero border outside the display area. This configuration can be advantageous for forming a display panel with curved edges and cutouts 530. In addition, this configuration can be advantageous for modular arrangements of display tiles 410, including miniature arrangements. Generally speaking, the control circuit 140 can be coupled to the edge of the display substrate 101. A bus column 515 of global signal lines can extend from the control circuit 140 to provide global signals to the display panel. For example, the global signal lines can include at least a data clock line 510 and a transmit clock line 520. The global signal lines are coupled to multiple "hybrid" pixel driver chiplets and together form the backbone of the display or display tile 410. The corresponding backbone hybrid pixel driver chip receives the global signal and then transmits the manipulated signal to its corresponding row 404 of row signal lines, which are connected to other pixel driver chips 110 in the same row. For example, the global data clock signal and the emission clock signal can be converted into manipulated signals and transmitted along the manipulated data clock line 510M and the manipulated emission clock line 520M to the row of pixel driver chips 110. For example, the manipulated signals can include only the necessary information for a particular row.

[0039] The tile-based display panel according to the embodiment can have display tiles 410 arranged in various ways. For example, the display tiles 410 can be arranged side by side (horizontally), stacked (vertically), a combination of both, or arranged in other configurations. In addition, the bus columns 515 of global signal lines can be aligned and connected to the stacked display tiles 410.

[0040] Figure 5A is a schematic top view of a tile-based display including a tile backbone 402 that functions as a hybrid pixel driver chiplet for row drivers, according to one embodiment. Figure 5B From the perspective of data and configuration updates according to one embodiment Figure 5A Schematic top view of a display tile partition of a display according to an embodiment. The display according to the embodiment may include a display panel including a plurality of tiles 410. The tiles 410 may be formed from the same or multiple display substrates 101. Figure 1The control circuitry 140 may be mounted on a printed circuit board 430 that is connected to the display substrate 101 using, for example, a flexible circuit or chip-on-film 432. Bus columns 515 and data lines 440 may extend from the control circuitry to the display substrate 101. Column drivers 430 may optionally be located on the display substrate 101 to buffer the global signal lines and / or data lines 440 in the bus columns 515. Each tile 410 may include one or more bus columns 515 for global signal lines, a plurality of rows 404 of row function signal lines, and a plurality of rows of pixel driver chiplets 110, wherein each row of pixel driver chiplets 110 is connected to a corresponding row 404 of row function signal lines. In addition, each pixel driver chiplet 110 is connected to a corresponding matrix 102 of LEDs 104, as shown with reference to FIG. Figure 1-3 described.

[0041] like Figure 5B As shown, each row of pixel driver chips 110 includes a group of trunk hybrid pixel driver chips 110B and a group of LED-driven pixel driver chips 110D. The bus column 515 and the routing selection of the trunk hybrid pixel driver chips 110B can form the trunk 402 of the tile 410. Each pixel driver chip in the trunk hybrid pixel driver chip 110B and the LED-driven pixel driver chip 110D can be a hybrid pixel driver chip, but is configured differently for different functions. Alternatively, the chips 110B and 110D can have different internal circuits. The trunk hybrid pixel driver chip 110B and the LED-driven pixel driver chip 110D can also be connected in different ways. According to an embodiment, each pixel driver chip in the trunk hybrid pixel driver chip 110B and the LED-driven pixel driver chip 110D is connected to a corresponding matrix 102 of LEDs 104, as shown in reference Figure 1-3 described.

[0042] According to an embodiment, the bus column 515 of global signal lines is coupled to a group of trunk hybrid pixel driver chips 110B for each row of pixel driver chips 110, and each independent trunk hybrid pixel driver chip 110B includes an input connected to the corresponding global signal line (e.g., 622, 621, 614, 613, 605, 680, 681), and an output connected to the corresponding row function signal line (e.g., 613M, 614M) within the corresponding row 404 of row function signal lines to transmit the corresponding repeated global signal to the corresponding row of pixel driver chips 110.

[0043] like Figure 5BAs specifically shown in FIG and described in more detail below, exemplary global signal lines forming bus column 515 may include global data clock_0 622, global data clock_1 621, hybrid driver configuration update_0 614, global configuration update_1 613, vertical select token (VST) 605, vertical select token scan clock 680, and vertical select token row capture clock 681, among others. In this case, since adjacent pairs of pixel driver chips 110 share a common data line 440, signal lines 0 / 1 are distinguished. Therefore, the same data signal can be sent to two pixel driver chips 110 in the same row, with global signal lines used to distinguish between chip pairs. Specifically, the trunk hybrid pixel driver chip 110B according to the embodiment is configured to receive a specified global signal and then transmit a manipulated row function signal (for example, manipulating the global signal to form a manipulated row function signal) to the corresponding row 404 of the row function signal line coupled to the corresponding row of the hybrid pixel driver chip 110, wherein the corresponding row of the hybrid pixel driver chip 110 includes a plurality of LED-driven pixel driver chips 110D within the row of pixel driver chips and one or more other trunk hybrid pixel driver chips 110B.

[0044] Figure 6 is a routing diagram of the row function partitioning within the hybrid pixel driver chip backbone according to one embodiment. It should be understood that Figure 6 The connections shown illustrate a general high-level partitioning, and the actual implementation may be more complex. As shown, the bus column 515 of global signal lines may include a global configuration update 610, a global data clock 620, a global emission row synchronization 630, and a global emission frame synchronization 640. A global emission clock line may also be included. In addition, in some embodiments, emission clock combinations may be used for different color-emitting LEDs, but this is not required. For example, there may be a global emission clock red 650 and a global emission clock blue-green 660. The corresponding trunk hybrid pixel driver chip 110B can then transmit the manipulated row signals 610M-660M to the corresponding rows 404 of the row signal lines. These manipulated row signals 610M-660M can be transmitted to some or all of the other trunk hybrid pixel driver chips 110B, as well as the pixel driver chips 110 driven by the LEDs in the corresponding rows of the pixel driver chip 110D. As will be apparent in the detailed examples below, global signal lines may also include odd / even indexed 1 / 0 or primary / redundant signal lines.

[0045] Figure 7: This is a layout diagram of row control signal redundancy and backup within a hybrid pixel driver chip backbone according to one embodiment. As shown, the rows of the hybrid pixel driver chip 110 and the rows 404 of the row signal lines can be divided into odd indexes and even indexes to provide control signal redundancy and backup in the event that the backbone hybrid pixel driver chip 110B fails. For example, the staggered arrangement of the pixel driver chip 110 may include odd partitions (e.g., upper chip) and even partitions (e.g., lower chip). The bus column 515 may include partitions of global signal lines, including global hybrid driver configuration update 0 / 1 (614, 613), global data clock 0 / 1 (622, 621), global emission row synchronization 0 / 1 (632, 631), global emission frame synchronization 0 / 1 (642, 641), global emission clock red 0 / 1 (652, 651), and global emission clock blue / green 0 / 1 (662, 661). The backbone may also include one or more backup hybrid pixel driver chips 700A, 700B. In one embodiment, the global hybrid driver configuration update 610 is input to the backup hybrid pixel driver chiplet 700A, and the global data clock 620 is input to the backup hybrid pixel driver chiplet 700B. Additional global signals 630, 640, 650, 660 may be input to both backup hybrid pixel driver chiplets 700A, 700B.

[0046] like Figure 7 As shown, the backup hybrid pixel driver chip 700A, 700B outputs the manipulated backup signal lines 711, 712, 721, 722 to the partitioned row 404 and the row of the hybrid pixel driver chip. The manipulated backup signal lines 711, 712, 721, 722 can be connected to the input of the main hybrid pixel driver chip configured for configuration update, data clock, frame synchronization and row synchronization functions. In operation, the backup hybrid pixel driver chip 700A, 700B uses a token to initialize its multiplexer output (e.g., a modified signal). A spare input pin is added to the main hybrid pixel driver chip configured for row function (configuration update, data clock, frame synchronization, row synchronization) to understand whether any of the backup hybrid pixel driver chip 700A, 700B is active and provide a modified row function signal to the row. In the embodiment shown, the manipulated backup signal lines 711, 712, 721, 722 are not input to the hybrid pixel driver chip configured for emission clock function. According to the embodiment, the backup hybrid pixel driver chiplets 700A, 700B can be programmed as a pixel driver chiplet for driving any LED, or perform the function of a failed main hybrid pixel driver chiplet within the same main row.

[0047] Figure 8FIG2 is a routing diagram of transmit frame sync and transmit row sync buffers within a pixel driver chip row, according to one embodiment. As shown, in addition to the optional division described above, global transmit row sync 630 and global transmit frame sync 640 can also be divided into multiple phases. While five phases Φ0-Φ4 are shown, this is exemplary and embodiments are not limited to a specific number of phases. In the specific embodiment shown, every fifth row shares the same phase.

[0048] Figure 9 is a routing diagram for vertical signal redundancy and transmit clock vertical and horizontal buffering according to one embodiment. As shown, in addition to the optional division described above, global transmit clocks 650, 660 can also be divided into multiple phases similar to global transmit line sync 630 and global transmit frame sync 640. Figure 9 The exemplary embodiment shown in FIG provides row partitioning with master / standby functionality. For example, odd-numbered partitions (e.g., 1) can be used as standby, and even-numbered partitions (e.g., 0) can be used as master. Thus, the function of the backbone hybrid pixel driver chiplet 110B can be determined by which odd / even chip in the row has the token. This can be determined by the VST inputs VST_0 612 (master) and VST_1 611 (standby). As described in more detail below, the global transmit clocks 650, 660 are repeated by the backbone hybrid pixel driver chiplets.

[0049] Now see Figure 10 , which provides a routing diagram of the trunk routing of the global signal lines to the rows and row signal lines of the trunk hybrid pixel driver chip according to one embodiment. According to the embodiment, Figure 10 The exemplary layout provided in the figure combines several features. As shown in the figure, separate phases (Φ0, Φ1) of the global emission row sync 630 and the global emission frame sync 640 signals are sent to different rows (N-1, N). In addition, separate phases (Φ0, Φ1) of the global emission clock red 650 and the global emission clock cyan 660 signals are sent to different rows (N-1, N). As shown in the figure, the repeated emission clock red and emission clock blue / green signal lines 650R, 660R are output from the corresponding trunk hybrid pixel driver chip to the next row (for example, every 5 rows). It should be noted that the specific connections for the global signal lines 630, 640, 650, 660 are different from the connections previously described and shown, but any configuration can be achieved by a combination of embodiments. Specifically, the corresponding trunk hybrid pixel driver chips connected to the global signal lines 630, 640, 650, 660 are divided by a pair of chips in odd segments or even segments, rather than by one chip in each odd segment and even segment.

[0050] Still see Figure 10, the global hybrid driver configuration update 0 / 1 (614, 613) and global data clock 0 / 1 (622, 621) signal lines are input to the corresponding trunk hybrid pixel driver chip pair. Similarly, the VST_0 612 and VST_1 611 signal lines are input to the trunk hybrid pixel driver chip coupled to the global hybrid driver configuration update 0 / 1 (614, 613) inputs, and one of each trunk hybrid pixel driver chip coupled to the global data clock 0 / 1 (622, 621) signal lines. The VST_out 617 signal line is output to both trunk hybrid pixel driver chips coupled to the global data clock 0 / 1 (622, 621) signal lines in the next row (N). The VST_out 617 signal line is also a repeating signal line that will collectively repeat the VST_0 612 and VST_1 611 signal lines to the next row.

[0051] use Figure 10 1. In the specific configuration shown, data clocks and hybrid pixel driver configuration updates are created separately for each row partition 0 / 1. In this particular illustration, partitions 0 / 1 correspond to right / left, rather than bottom / top (even / odd). In other embodiments, partitions 0 / 1 correspond to bottom / top (even / odd), as previously described. Each hybrid pixel driver chiplet row buffers transmit clock red, transmit clock blue / green, transmit frame sync, and transmit row sync for its associated clock phase. However, embodiments are not limited to this specific configuration, and each global signal line can be created separately for each row partition 0 / 1.

[0052] Figure 11 FIG. 4 is a routing diagram for horizontal control signal redundancy for VST and backup line connections according to an embodiment. Figure 11The selected global signal lines included in the scheme are VST scan clock 682, VST row capture clock 681, emission clock red_1 651 (spare), and emission clock green / blue_1 661 (spare). Therefore, in this case, row partitions 0 / 1 of the emission clock signal lines correspond to primary / spare. As shown in the figure, VST scan clock 682, VST row capture clock 681, as well as VST_0 612 and VST_1 611 are input to the trunk hybrid pixel driver chip, generating a manipulated hybrid driver configuration update 610M, a manipulated data clock 620M, a manipulated emission clock red 651M (or generally, 650M), and a manipulated emission clock cyan 661M (or generally, 660M) signal, which are then input to the backup trunk hybrid pixel driver chips 700A and 700B. The emission clock red_1 651 (spare) and the emission clock green / blue_1 661 (spare) are input to the trunk hybrid pixel driver chip to generate the manipulated emission clock red 651M (or generally, 650M) and manipulated emission clock cyan 661M (or generally, 660M) signals, and input to the spare trunk hybrid pixel driver chips 700A and 700B.

[0053] In the particular embodiment shown, the backup trunk hybrid pixel driver chiplet 700A output is connected to the backup indicator_0 618 and the backup line_0 712 within the row 404, while the backup trunk hybrid pixel driver chiplet 700B output is connected to the backup indicator_1 619 and the backup line_0 711 within the row 404. The backup indicators (e.g., 618, 619) indicate that the backup lines (e.g., 712, 711) are valid for providing backup functions. The backup indicator_0 618 is used together with the backup line_0 712, and the backup indicator_0 619 is used together with the backup line_0 711. In this way, the backup trunk hybrid pixel driver chip 700A, 700B can be programmed to backup the failed trunk hybrid pixel driver chip originally designed to buffer the global emission clock signal, and transmit the manipulated emission clock signal (e.g., generally, 651, 661 or 650, 660) to row 404 via backup line_0 712 or backup line_0 711.

[0054] Figure 12FIG2 is a routing diagram illustrating horizontal control signal redundancy for row function signal connections according to one embodiment. Row function partitioning (or chip partitioning) within the hybrid pixel driver chiplet backbone according to the embodiment requires utilizing one or more backbone hybrid pixel driver chiplets 110B to receive global signals and transmit manipulated signals from the one or more backbone hybrid pixel driver chiplets 110B to one or more other backbone hybrid pixel driver chiplets and an associated group of LED-driven pixel driver chiplets 110D within the corresponding row.

[0055] The specific global signal can be directly received by the plurality of trunk hybrid pixel driver chips 110B, while the control signal is generated by a designated trunk hybrid pixel driver chip 110B among the plurality of trunk hybrid pixel driver chips or by the spare trunk hybrid pixel driver chips 700A, 700B. Figure 12 In the illustrated embodiment, the global hybrid driver configuration update 610 and global data clock 620 signal lines are input to the corresponding backbone chip for which the control signal is generated, as well as the backbone chip programmed to modify the global transmit clock (e.g., 650, 660), and the spare chip (e.g., 700A, 700B). Similarly, the global transmit row sync 630 and global transmit frame sync 640 signal lines are input to the corresponding backbone chip for which the control signal is generated, as well as the backbone chip programmed to modify the global transmit clock (e.g., 650, 660), and the spare chip (e.g., 700A, 700B). In addition, as described with reference to Figure 11 As described, the global transmit clock red 650 and global transmit clock cyan 660 signal lines are input to the corresponding backbone chips for which control signals are generated, as well as the backup chips (eg, 700A, 700B).

[0056] In one embodiment, the display panel includes a bus column 515 of global signal lines, a plurality of rows 404 of row function signal lines, and a plurality of rows [1..N] of pixel driver chips 110, each row of pixel driver chips being connected to a corresponding row 404 of row function signal lines, each pixel driver chip being connected to a corresponding matrix 102 of light emitting diodes (LEDs) 104. Each row of pixel driver chips may include a set of trunk hybrid pixel driver chips 110B and a set of LED-driven pixel driver chips 110D. The bus column 515 of global signal lines is coupled to a set of trunk hybrid pixel driver chips 110B for each row of pixel driver chips, and each independent trunk hybrid pixel driver chip includes an input connected to a corresponding global signal line, and an output connected to a corresponding row function signal line within a corresponding row of row function signal lines to transmit a corresponding control signal to the corresponding row of pixel driver chips (e.g., Figure 14 1450M in).

[0057] The following exemplary implementation relates to data clock and configuration update routing. In one embodiment, each set of trunk hybrid pixel driver chiplets 110B includes a data clock trunk hybrid pixel driver chiplet having an input coupled to a global data clock 620 signal line and an output coupled to a corresponding row function signal line to transmit a manipulated data clock 620M signal to a corresponding row of pixel driver chiplets. Each set of trunk hybrid pixel driver chiplets may also include a configuration update trunk hybrid pixel driver chiplet having an input coupled to a global configuration update 610 signal line and an output coupled to a corresponding row function signal line to transmit a manipulated configuration update 610M signal to a corresponding row of pixel driver chiplets. In one embodiment, the data clock trunk hybrid pixel driver chiplet includes an input coupled to a global configuration update 610 signal line, and the configuration update trunk hybrid pixel driver chiplet includes an input coupled to a global data clock 620 signal line.

[0058] The following exemplary implementation involves VST routing and backup chips. In one embodiment, each set of trunk hybrid pixel driver chips includes backup trunk hybrid pixel driver chips 700A, 700B, wherein the backup trunk hybrid pixel driver chips 700A, 700B include inputs coupled to the global configuration update 610 signal line and inputs coupled to the global data clock 620 signal line. VST clock lines (e.g., VST scan clock 682, VST row capture clock 681) can be coupled to the inputs of the data clock trunk hybrid pixel driver chip, the configuration update trunk hybrid pixel driver chip, and the backup trunk hybrid pixel driver chip. The backup trunk hybrid pixel driver chip can also include outputs coupled to corresponding row function signal lines to transmit manipulated row function signals to the corresponding row of pixel driver chips (including the data clock trunk hybrid pixel driver chip and the configuration update trunk hybrid pixel driver chip).

[0059] The following exemplary embodiments cover another route, such as a route for synchronization. In one embodiment, each group of trunk hybrid pixel driver chips includes a first trunk hybrid pixel driver chip and a second trunk hybrid pixel driver chip, wherein the first trunk hybrid pixel driver chip has an input coupled to a first global signal line and a first output coupled to a corresponding first row functional signal line to transmit a first control signal to a corresponding row of the pixel driver chip, and the second trunk hybrid pixel driver chip has an input coupled to a second global signal line and a second output coupled to a corresponding second row functional signal line to transmit a second control signal to a corresponding row of the pixel driver chip. In one embodiment, the second row functional signal line is coupled to a third input of the first trunk hybrid pixel driver chip, and the first row functional signal line is coupled to a fourth input of the second trunk hybrid pixel driver chip. For example, the first global signal line can be a global emission row synchronization 630 line, and the second global signal line can be a global emission frame synchronization 640 line.

[0060] The display panel can distribute the global row function signals among the trunk hybrid pixel driver chiplets so that each trunk hybrid pixel driver chiplet is responsible for manipulating and / or repeating a specified global row function signal. In one embodiment, each group of trunk hybrid pixel driver chiplets includes a data clock trunk hybrid pixel driver chiplet having inputs coupled to a global data clock 620 signal line and a global configuration update 610 signal line, a configuration update trunk hybrid pixel driver chiplet having inputs coupled to a global data clock 620 signal line and a global configuration update 610 signal line, a frame sync trunk hybrid pixel driver chiplet having inputs coupled to a global frame sync 630 signal line, a row sync trunk hybrid pixel driver chiplet having inputs coupled to a global row sync 640 signal line, and an emission clock trunk hybrid pixel driver chiplet having inputs coupled to global emission clock (e.g., 650, 660) signal lines. Each set of trunk hybrid pixel driver chips may also include one or more backup trunk hybrid pixel driver chips 700A, 700B coupled to the global data clock 620 signal line, the global configuration update 610 signal line, the global frame synchronization 630 signal line, the global row synchronization 640 signal line and the global emission clock (e.g., 650, 660) signal line.

[0061] Figure 13 is a routing diagram of the global signal line and row signal line connections to and from the backbone of a tile-based display panel, according to one embodiment. Specifically, the routing diagram shows the global signal line inputs, the (manipulated) outputs from the odd / even indices of a set of backbone hybrid pixel driver chiplets 110B to the odd / even routing within row 404 of the row signal lines, and the repeated output to the next row. At a high level, Figure 13Provides input for odd / even indexing of a row of trunk hybrid pixel driver chips. Thus, the annotation of 110B shows the entire trunk row of trunk hybrid pixel driver chips 110B. In summary, Figure 13 The high-level connections to the odd / even indexed trunk rows 1300 of the trunk hybrid pixel driver chiplet 110B are shown. As shown, several global signals (which may be digital) are input to the trunk hybrid pixel driver chiplets of the odd / even group, including VST scan clock 682, VST row capture clock 681, transmit frame sync 640, and transmit row sync 630. Additional signal lines not previously discussed include the design of the hybrid pixel driver chiplet reset 690, token reset 692, and test control 694 signal lines. The global data clock_1 621 and global configuration update_1 613 signal lines are input only to the odd-indexed trunk hybrid pixel driver chiplets, while the global data clock_0 622 and global configuration update_0 614 are input only to the even-indexed trunk hybrid pixel driver chiplets.

[0062] Additionally, data signals are input to each of the odd / even arrays of backbone hybrid pixel driver chips including data 440 and configuration update 445 signal lines.

[0063] In addition, there are several vertically repeated global signals (e.g., digital) that are simultaneously input to the odd / even group of trunk hybrid pixel driver chips, including VST_0 (primary) 612, VST_1 (backup) 611, emission clock red_0 (primary) 652, emission clock red_1 (backup) 651, emission clock cyan_0 (primary) 662, and emission clock cyan_1 (backup) 661. Outputs from the odd / even indexed trunk hybrid pixel driver chiplet 110B include repeated emission clock cyan 662R, repeated emission clock red 652R, repeated emission clock cyan 661R, repeated emission clock red 651R, and VST out 617.

[0064] In this embodiment, the outputs from the odd-indexed trunk hybrid pixel driver chip 110B include manipulated data clock_1 621M, manipulated configuration update_1 613M, manipulated transmit frame sync_1 641M, manipulated transmit row sync_1 631M, manipulated transmit clock red_1 651M, manipulated transmit clock cyan_1 661M, backup line_1 711 and backup line_3 721.

[0065] In this embodiment, the outputs from the even-indexed trunk hybrid pixel driver chiplet 110B include manipulated data clock_0 622M, manipulated configuration update_0 614M, manipulated transmit frame sync_0 642M, manipulated transmit row sync_0 632M, manipulated transmit clock red_0 652M, manipulated transmit clock cyan_0 662M, backup line_0 712, and backup line_2 722.

[0066] Figure 14 FIG. 1 is a circuit block diagram of a trunk hybrid pixel driver chip according to one embodiment. In the embodiment shown, the trunk hybrid pixel driver chip includes a VST driver circuit 1410 , a signal modulator circuit 1430 , a multiplexer driver circuit 1440 , and an LED driver circuit 1460 .

[0067] The LED driver circuit 1460 portion provides the emission function for the hybrid pixel driver chip and stores pixel data and configuration data. The LED driver circuit 1460 portion includes a shift register 1462, a latch 1464, a memory 1466, and an emission clock counter 1468. At least the data 440 signal and the internal data clock 620I are input to the shift register 1462, and at least the internal emission clock red 650I and the internal emission clock cyan 660I are input to the emission clock counter 1468 to output emission pulses at the output driver 116. However, before emission, the hybrid pixel driver chip needs to be configured for the row function.

[0068] The VST driver circuit 1410 determines whether the row is on or off and provides VST propagation from the top to the bottom of the display panel. The actual token hybrid pixel driver chip receives the global VST signal, while the other hybrid pixel driver chip receives the VST signal from the backup hybrid pixel driver chip. As shown, the VST driver circuit 1410 includes inputs for the VST scan clock 682, the VST row capture clock 681, VST_0 612, and VST_1 611, and outputs for the token latch 1414 signal and the token 1412 signal. The token latch 141, token 1412, VST_0 612, and VST_1 611 signals are input to the signal modulator 1430.

[0069] Specifically, the VST driver circuit 1410 includes an OR gate 1470 coupled to the VST inputs 611 and 612, and a plurality of flip-flop circuits 1480 coupled to the VST clock inputs 681 and 682 and an output 1771 from the OR gate, the plurality of flip-flop circuits 1480 including a token 1412 output and a token latch 1414 output. In operation, if one or both inputs to the OR gate 1470 are high (1), the OR gate outputs a high output 1771 signal. If both inputs are not high, a low output (0) is generated. With respect to the flip-flop circuit 1480, when the VST clock input (e.g., 681 or 682) is low, the output is low. When the VST clock input (e.g., 681 or 682) is high, if the data input is high (1), the flip-flop circuit output is high (1), and if the data input is low (0), the output is low (0).

[0070] Specifically, the output of OR gate 1470 is coupled to the data inputs of flip-flop circuits 1480A and 1480C. One VST clock (e.g., VST scan clock 682) is coupled to the clock input of flip-flop circuit 1480A. Another VST clock (e.g., VST row capture clock 681) is coupled to the clock inputs of flip-flop circuits 1480C and 1480B. The data output from flip-flop circuit 1480A is coupled to the data input of flip-flop circuit 1480B, and the anode of the data output from flip-flop circuit 1480A is also coupled to multiplexer 1442 within multiplexer driver circuit 1440. Token 1412 is coupled to the data output of flip-flop circuit 1480C, and token latch 1414 is coupled to the data output of flip-flop circuit 1480B.

[0071] If VST driver circuit 1410 indicates that the row is on, signal modulator circuit 1430 selects whether to access the global row function signal or the backup line for any row function. Token latch 1414 and token 1412 are out of phase and, in conjunction with VST_0 612 and VST_1 611, indicate whether to use any of the backup lines 711 and 712 for any of the row function signals 610, 620, 630, 640, 650, and 660. Furthermore, signal modulator circuit 1430 modifies the global input signal into a steering signal specific to a particular row. Multiplexers 1432 output the internal (steering) row function signals from signal modulator 1430 to multiplexer driver 1440 and LED driver circuitry 1460. The outputs included may be internal configuration update 610I, internal data clock 620I, internal transmit line sync 630I, internal transmit frame sync 640I, internal transmit clock red 650I, and internal transmit clock cyan 660I.

[0072] The multiplexer driver circuit 1440 includes two sections, a repeater section 1440A and a row function output section 1440B. The output from the VST driver circuit 1410 is input to the multiplexer 1442 of the repeater section 1440A and then buffered by a buffer 1444 to output VST_out 617. An internal transmit clock may also be input to the multiplexer 1442 to alternately output a repeating transmit clock signal, such as a repeating transmit clock red 650R (651R, 652R) or a repeating transmit clock cyan 660R (661R, 662R). The internal row function signal from the signal modulator circuit 1430 is input to the multiplexer 1446 of the row function output section 1440B and then buffered by a buffer 1448 to output the manipulated multiplexer output 1450M signal (which is the manipulated signal output or repeated signal output of the programmed trunk hybrid pixel driver chip). Thus, the manipulated multiplexer output 1450M can be any of the aforementioned manipulated output signals or the backup signal, and is physically connected to a designated row function line within row 404 depending on the signal. Figure 13 In the exemplary embodiment shown, although the manipulated multiplexer output 1450M can be connected to any one of (621M, 613M, 641M, 631M, 651M, 661M, 711, 721, 622M, 614M, 642M, 632M, 652M, 662M, 712, 722), other configurations are possible.

[0073] According to an embodiment, for non-trunk hybrid pixel driver chips, the VST input terminals 611 and 612 are still connected to the backup indication signal to select the backup signal as one of the row functions. The scan clock 681 and row capture clock 682 inputs can be attached to the ground terminal to indicate that they are not trunk hybrid drivers, while the VST output 617 and the multiplexer output 1450M can be floating. Therefore, for the trunk hybrid pixel driver chip 110B and the driven hybrid pixel driver chip 110A, the circuit can remain the same, with only the programming and external connections being different.

[0074] In one embodiment, the hybrid pixel driver chip includes a vertical select token (VST) input (e.g., 611, 612), a VST clock input (e.g., 681, 682), and a VST driver circuit 1410 coupled to the VST input and the VST clock input, the VST driver circuit further including a token 1412 output and a token latch 1414 output. The hybrid pixel driver chip also includes a signal modulator circuit 1430 coupled to the token 1412 output and the token latch 1414 output, the signal modulator circuit 1430 also including a plurality of multiplexers 1432 coupled to a plurality of global signal inputs, and a plurality of internal signal outputs from the plurality of multiplexers 1432. The signal modulator circuit 1430 can also be coupled to the VST input (e.g., 611, 612). Additional components of the hybrid pixel driver chip may include a multiplexer driver circuit 1440 and an LED driver circuit 1460, wherein the multiplexer driver circuit 1440 includes a multiplexer 1446 coupled to multiple internal signal outputs, and a multiplexer output 1450M, and the LED driver circuit 1460 is coupled to one or more of the multiple internal signal outputs and a data 440 input, and the LED driver circuit 1460 further includes multiple output drivers 116.

[0075] In one embodiment, the multiplexer driver circuit 1440 includes a repeater portion 1440A coupled to the VST driver 1410 and a row function output portion 1440B coupled to the signal modulator 1430 .

[0076] In one embodiment, the VST driver circuit 1410 includes an OR gate 1470 coupled to a VST input (e.g., 611, 612), and a plurality of flip-flop circuits (1480A, 1480B, 1480C) coupled to a VST clock input (e.g., 681 or 682) and an output 1471 from the OR gate 1470, the plurality of flip-flop circuits including a token 1412 output and a token latch 1414 output.

[0077] Figure 15 is a timing diagram for data loading of a hybrid pixel driver chip for token activation according to one embodiment. Figure 15 The timing diagrams for the embodiments in FIG. 1 relate to a particular backbone hybrid pixel driver chip connected to the VST routing backbone (e.g., Figure 11 shown). Specifically, Figure 15 The timing diagram involves Figure 11 The two leftmost backbone hybrid pixel driver chips with global / repeated VST connections are shown in FIG.

[0078] Figure 15A particular aspect of an embodiment is shown in which a particular backbone hybrid pixel driver chip is programmed in two parts. First, the particular backbone hybrid pixel driver chip is configured. Then, the particular backbone hybrid pixel driver chip transmits the corresponding multiplexer output 1450M signal, specifically the manipulated configuration update 610M signal and the manipulated data clock 620 signal, to the other pixel driver chips connected to the corresponding row 404. Once the row is configured, the other data bits can be defined. Therefore, in one embodiment, a method of programming a backbone hybrid pixel driver chip includes the following general sequence: activate the token, once the token is high, program the data clock and configuration update to make the row available (send the manipulated data clock and manipulated configuration update to the rest of the row), and then write the rest of the configuration bits.

[0079] Figure 15 4 shows three different portions of data 440. Token driver configuration 1510 data includes data for optionally selecting backup lines 711 / 712 using signal modulator 1430, as well as data for manipulating the global data clock 620 signal and the global configuration update 610 signal. This token driver configuration 1510 data is used only by the token-activated trunk hybrid pixel driver chip hardwired to the VST signal line. Row driver configuration 1520 data includes data for selecting other row function signals using signal modulator 1430, and the LED configuration within a row. This row driver configuration 1520 data is used by all trunk hybrid pixel driver chips to transmit manipulated row function signals to the corresponding row 404. LED pixel data 1530 includes data for LED pixel data slices 0 / 1 for the hybrid pixel driver chip within the corresponding row.

[0080] like Figure 15 As shown, initially, the token reset 692 signal rises to reset the trunk hybrid pixel driver chip. In addition, the VST row capture clock 681 rises (rising edge) and the VST driver 1410 generates a high token 1412 signal. At this point, the trunk hybrid pixel driver chip for row 0 is activated by the token and is ready for configuration and data loading. However, before loading the LED pixel data, the hybrid pixel driver is first configured. If the VST is active on a row, it goes high (token). The token follows the global VST clocks (VST scan clock 682, VST row capture clock 681). In this embodiment, the VST scan clock 682 and the VST row capture clock 681 have the same frequency.

[0081] As described above, configuration is performed in two parts. First, the token driver configuration 1510 data is loaded to configure the specific hardwired backbone hybrid pixel driver chip for multiplexer select backup lines 0 / 1 712, 711 and for generating the manipulated data clock 620M signal and the manipulated configuration update 610M signal. The backup line configuration is included because it can be used for the manipulated data clock 620M or the manipulated configuration update 610M signal. The initial configuration is important because the manipulated data clock 620M signal and the manipulated configuration update 610M signal are required to identify the configuration bit or data bit. Second, the row driver configuration 1520 is loaded for multiplexer selection of other row function signals using the multiplexer output 1450M. Figure 15 The specific timing diagram involves Figure 11 The two leftmost backbone hybrid pixel driver chips with global / repeated VST connections are shown in FIG. Thus, the multiplexer output 1450M signal lines correspond to the manipulated data clock 620M signal and the manipulated configuration update 610M signal.

[0082] As shown, a pulse of the global configuration update 610 signal is applied and received by the hardwired backbone hybrid pixel driver chip. During the application of the global configuration update 610 signal, a corresponding internal data clock 620I and internal configuration update 610I are generated, and the manipulated signals (manipulated data clock 620M signal and manipulated configuration update 610M signal) are transmitted to the row through the multiplexer output 1450M signal line.

[0083] The global configuration update 610 signal is then de-asserted (falling edge), which causes the configuration complete 699 signal to rise. In addition, as shown in the figure, the subsequent falling edge of the global configuration 610 signal causes the configuration complete 699 signal to go low. The configuration complete 699 signal is an internal signal that allows the hybrid pixel driver chip to distinguish pixel data from configuration data and thereby write the LED pixel data 1530 to the memory 1466. During the row 1 time, the configuration complete 699 signal prohibits the driver from being configured with data 1510 because the configuration bits from the global data clock 620 are for the new row (row 1) driver. The pixel bits in time rows 0 and 1 are shared by the two drivers in the two rows. The memory 1466 is first written with several token driver configuration 1510 data bits, followed by the universal row driver configuration 1520 data, followed by the pixel data 1530, and then another set of pixel data in the row 1 time.

[0084] Figure 16 is a flow chart of a method for programming a display tile by resetting according to one embodiment. For clarity, Figure 16 Method description refer to Figure 15 、 Figure 14 and Figure 11 Generally speaking, the programming sequence proceeds along the backbone of the display tile, starting with row i=0 and ending with row i=N, where 0 is the first (top) row of the backbone hybrid pixel driver chiplet 110B and N is its last (bottom) row.

[0085] The sequence may begin at row i=0, with the hybrid driver reset 690 signal and the token reset 692 signal initially low. At operation 1610, the hybrid driver reset 690 signal and the token reset 692 signal are asserted high and released low. At operation 1620, the VST signal is propagated to row i=0. At operation 1630, the token driver configuration 1510 data is received by the trunk hybrid pixel driver chip with the token activated. Specifically, the token driver configuration 1510 data is received by the trunk hybrid pixel driver chip with the token 1412 signal high. This is due to the overlapping propagation of the VST row capture clock 692 to the row during the high token reset 681 signal. . The token signal is propagated row by row using the VST row capture clock 681. When the token 1412 is high, the hybrid pixel driver chip is turned on to receive data from the data 440 line. Additionally, a reset signal is generated at the beginning of the token 1412 signal to reset the existing token state in the activated hybrid pixel driver chip. At operation 1640, the trunk hybrid pixel driver chip receives the global configuration update 610 pulse and the row driver configuration 1520 data, and then generates and sends the manipulated configuration update 610M signal to the row of pixel driver chips 110. At operation 1650, the global configuration update 610 pulse is de-asserted, and the pixel data 1530 is sent to all pixel driver chips 110 in the row via the columns of the data 440 lines. At operation 1660, if is not equal to the number of rows N, the process is repeated for the next row, and if this is the last row, the process is complete.

[0086] In one embodiment, a method for programming a display is provided, the method comprising propagating a VST signal (e.g., any one of 611, 612, 681, 682) to a row of pixel driver chips 110, receiving token driver configuration data 1510 using a trunk hybrid pixel driver chip 110B, receiving a global configuration update 610 pulse using a trunk hybrid pixel driver chip 110B, receiving row driver configuration data 1520 using a token-activated trunk hybrid pixel driver chip 110B, and transmitting a manipulated configuration update signal 610M from the trunk hybrid pixel driver chip 110B to a row of pixel driver chips 110 (e.g., 1...N).

[0087] In one embodiment, the repeated VST signal 617 (eg, 611 , 612 ) propagates from the trunk hybrid pixel driver chiplet to a second trunk hybrid pixel driver chiplet in a second row of pixel driver chiplets.

[0088] In one embodiment, the method further includes asserting a token reset 692 signal and a VST clock (eg, 681 or 682) signal to the trunk hybrid pixel driver chiplet 110B to token activate the trunk hybrid pixel driver chiplet before propagating the VST signal to the row of pixel driver chips.

[0089] In utilizing various aspects of the embodiments, it will be apparent to those skilled in the art that combinations or variations of the above embodiments are possible for forming tile-based displays using a backbone hybrid pixel driver chip. Although the embodiments are described in language specific to structural features and / or methodological acts, it should be understood that the appended claims are not necessarily limited to the specific features or acts described. Instead, the specific features and acts disclosed should be understood as exemplary embodiments of the claims.

Claims

1. A display panel, comprising: A display substrate including an array of LED-driven pixel driver chips and a plurality of columns of backbone hybrid pixel driver chips; wherein each LED-driven pixel driver chiplet and each trunk hybrid pixel driver chiplet is connected to a corresponding matrix of light emitting diodes (LEDs), and each trunk hybrid pixel driver chiplet is connected to a corresponding row of LED-driven pixel driver chips within the array of LED-driven pixel driver chips; A bus column of global emission clock lines is connected to a column of trunk hybrid pixel driver chips, wherein the bus column of global emission clock lines comprises: a first emission clock line connected to the first trunk hybrid pixel driver chip of the first group to send a first emission clock signal; a second emission clock line connected to the second trunk hybrid pixel driver chip of the second group to send a second emission clock signal; and The third emission clock line is connected to the third trunk hybrid pixel driver chip of the third group to send a third emission clock signal. The first transmit clock signal, the second transmit clock signal and the third transmit clock signal have different phases. 2 . The display panel according to claim 1 , further comprising a control circuit attached to the display substrate to provide the first emission clock signal, the second emission clock signal, and the third emission clock signal.

3. The display panel of claim 2 , wherein each first trunk hybrid pixel driver chip comprises a first input coupled to the first emission clock line and a first output coupled to the corresponding first row functional signal line to transmit the manipulated emission clock signal to the corresponding row of LED-driven pixel driver chips.

4. The display panel according to claim 3, wherein the first emission clock line includes a first plurality of first repeated emission clock lines electrically connected to the first trunk pixel driver chip of the first group, so that the first emission clock line passes through the first trunk hybrid pixel driver chip of the first group in a cascade manner, wherein the first trunk hybrid pixel driver chip receives a buffered first repeated emission clock signal from the preceding first trunk hybrid pixel driver chip. 5 . The display panel of claim 4 , wherein each first trunk hybrid pixel driver chip comprises a first repetitive emission clock output, and the first repetitive emission clock line extending from the corresponding first repetitive emission clock output. 6 . The display panel according to claim 4 , wherein the first emission clock line is connected to a single first trunk hybrid pixel driver chip of a corresponding row of pixel driver chips for LED driving. 7 . The display panel according to claim 4 , wherein each first repetitive emission clock line is connected to a corresponding first row functional signal line and a first input of a downstream first trunk hybrid pixel driver chip. 8 . The display panel according to claim 4 , wherein the first emission clock line is connected to a pair of first trunk hybrid pixel driver chips of corresponding rows of pixel driver chips for LED driving.

9. The display panel of claim 3 , wherein each second trunk hybrid pixel driver chip comprises a second input coupled to the second emission clock line and an output coupled to a corresponding second row function signal line to transmit the manipulated row function signal to the corresponding row of LED-driven pixel driver chips.

10. The display panel according to claim 9, wherein the second emission clock line comprises a second plurality of second repeated emission clock lines electrically connected to the second trunk pixel driver chip of the second group, so that the second emission clock line passes through the second trunk hybrid pixel driver chip of the second group in a cascade manner, wherein the second trunk hybrid pixel driver chip receives a buffered second repeated emission clock signal from a preceding second trunk hybrid pixel driver chip. 11 . The display panel of claim 10 , wherein each second trunk hybrid pixel driver chip comprises a second repetitive emission clock output, and a second repetitive emission clock line extending from the corresponding second repetitive emission clock output. 12 . The display panel of claim 10 , wherein the second emission clock line is connected to a single second trunk hybrid pixel driver chip for a corresponding row of LED-driven pixel driver chips. 13 . The display panel according to claim 10 , wherein each second repetitive emission clock line is connected to a corresponding second row function signal line and a second input of a downstream second trunk hybrid pixel driver chip.

14. The display panel of claim 10, wherein the second emission clock line is connected to a pair of second trunk hybrid pixel driver chips for corresponding rows of pixel driver chips.

15. The display panel of claim 9 , wherein each third trunk hybrid pixel driver chip comprises a third input coupled to the third emission clock line and an output coupled to a corresponding third row function signal line to transmit the manipulated row function signal to the corresponding row of LED-driven pixel driver chips.

16. The display panel according to claim 15, wherein the third emission clock line comprises a third plurality of third repeated emission clock lines electrically connected to the third trunk pixel driver chip of the third group, so that the third emission clock line passes through the third trunk hybrid pixel driver chip of the third group in a cascade manner, wherein the third trunk hybrid pixel driver chip receives a buffered third repeated emission clock signal from the preceding third trunk hybrid pixel driver chip. 17 . The display panel of claim 16 , wherein each third trunk hybrid pixel driver chip comprises a third repetitive emission clock output, and the third repetitive emission clock line extending from the corresponding third repetitive emission clock output.

18. The display panel of claim 16, wherein the third emission clock line is connected to a single third trunk hybrid pixel driver chip of a corresponding row of pixel driver chips for LED driving.

19. The display panel of claim 16, wherein each third repetitive emission clock line is connected to a corresponding third row function signal line and a third input of a downstream third trunk hybrid pixel driver chip.

20. The display panel of claim 16, wherein the third emission clock line is connected to a pair of third trunk hybrid pixel driver chips of corresponding rows of pixel driver chips for LED driving.

21. The display panel of claim 16, wherein the bus column of the global emission clock lines includes additional emission clock lines connected to corresponding additional groups of trunk hybrid pixel driver chips to send additional emission clock signals.

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