memory devices

Abstract

This technology includes a memory device. The memory device includes: a memory cell; a page buffer configured to store sensing data obtained from the memory cell; a current sensing circuit configured to compare a sensing voltage generated based on the sensing data with a reference voltage generated based on an allowable failure bit code, and output a pass signal or a failure signal based on the comparison result; and a failure bit manager configured to increase the number of allowable failure bits included in the allowable failure bit code until the pass signal is output from the current sensing circuit, change the allowable failure bit code according to the number of allowable failure bits, and provide the allowable failure bit code to the current sensing circuit.

Description

Technical Field

[0001] This disclosure relates to a memory device, and more specifically, to a memory device capable of counting failure bits. Background Technology

[0002] A memory system may include a memory device for storing data and a controller for controlling that memory device. Memory devices are classified as volatile memory devices and non-volatile memory devices. Because volatile memory devices have different characteristics, they are used in electronic devices for various functions. For example, volatile memory devices are faster in programming and reading operations than non-volatile memory devices; however, the stored data is destroyed when power is cut off. Non-volatile memory devices are slower in programming and reading operations than volatile memory devices, but the stored data is retained even when power is cut off. Furthermore, because non-volatile memory devices can have a higher integration density than volatile memory devices, they can store larger amounts of data.

[0003] The memory device may include: a memory cell array in which data is stored; peripheral circuitry configured to program, read, or erase memory cells included in the memory cell array; and control logic circuitry capable of controlling the peripheral circuitry.

[0004] A memory cell array can include multiple memory blocks, and each of these memory blocks can include multiple memory cells. The method of storing one bit of data in a single memory cell is called the single-level cell (SLC) method, while the method of storing two or more bits of data is called the multi-level cell (MLC) method. Depending on the number of bits stored in the memory cell, the MLC method can be divided into the three-level cell (TLC) method or the four-level cell (QLC) method. In the TLC method, three bits of data can be stored in one memory cell, while in the QLC method, four bits of data can be stored in one memory cell.

[0005] The peripheral circuitry may include: a row decoder connected to multiple memory cells via word lines; and a set of page buffers connected to multiple memory cells via bit lines. Programming voltage, read voltage, verification voltage, or pass voltage can be applied to the memory cells via word lines, and data in the memory cells can be sensed via bit lines. Summary of the Invention

[0006] One embodiment of this disclosure provides a memory device that can reduce the size of circuitry capable of counting failure bits during a read operation and increase the speed of the read operation.

[0007] According to one embodiment of the present disclosure, a memory device includes: a memory cell; a page buffer configured to store sensing data obtained from the memory cell; a current sensing circuit configured to compare a sensing voltage generated based on the sensing data with a reference voltage generated based on an allowable failure bit code, and output a pass signal or a failure signal based on the comparison result; and a failure bit manager configured to increase the number of allowable failure bits included in the allowable failure bit code until the pass signal is output from the current sensing circuit, change the allowable failure bit code according to the number of allowable failure bits, and provide the allowable failure bit code to the current sensing circuit.

[0008] According to one embodiment of this disclosure, a memory device includes: a memory cell; a page buffer connected to the memory cell via a bit line and configured to sense current or voltage on the bit line during a read operation to store sensed data; a current sensing circuit configured to determine whether the read operation passes or fails based on the number of failure bits detected in the sensed data and the number of allowed failure bits, and to change the ratio of the number of detected failure bits to the number of allowed failure bits corresponding to the number of detected failure bits, wherein the ratio is determined based on a compensation value; and a failure bit manager configured to adjust the number of allowed failure bits until the read operation passes, and to adjust the amount of the compensation value when it is determined that the read operation still fails until the number of allowed failure bits reaches a maximum value.

[0009] According to one embodiment of this disclosure, a method for operating a memory device includes the following steps: determining whether a read operation has failed by comparing a sensed voltage and a reference voltage; when it is determined that the read operation has failed, adjusting the reference voltage and repeating the determination step based on the adjusted reference voltage until the reference voltage is adjusted to a set maximum reference voltage; and when it is determined that the read operation still fails despite the reference voltage being adjusted to the maximum reference voltage, adjusting the criterion used to determine whether the read operation is successful or failed, and repeating the determination step based on the adjusted criterion, wherein the sensed voltage corresponds to the number of failure bits detected in data sensed from a set of memory cells in the memory device, wherein the reference voltage corresponds to the number of allowed failure bits, wherein the criterion is adjusted according to a compensation code, the compensation code is changed when it is determined that the read operation still fails even after the reference voltage has been adjusted to the maximum reference voltage, and wherein when it is determined that the read operation still fails despite the adjustment of the criterion, the read operation is finally determined to have failed. Attached Figure Description

[0010] Figure 1This is a diagram illustrating a memory device according to one embodiment of the present disclosure.

[0011] Figure 2 This illustrates one embodiment according to the present disclosure. Figure 1 The diagram shows the memory cell array.

[0012] Figure 3 This illustrates one embodiment according to the present disclosure. Figure 2 A diagram of the storage blocks shown.

[0013] Figure 4 This illustrates one embodiment according to the present disclosure. Figure 1 The diagram shows the page buffer group.

[0014] Figure 5 This is a diagram illustrating a method for sensing selected pages on a block-by-block basis according to one embodiment of the present disclosure.

[0015] Figure 6 This is a circuit diagram illustrating a current sensing circuit according to one embodiment of the present disclosure.

[0016] Figures 7A to 7C This is a diagram illustrating a failure bit manager according to one embodiment of the present disclosure.

[0017] Figure 8A This is a diagram illustrating an embodiment of the present disclosure in which a pass signal is output by changing the number of allowable failure bits.

[0018] Figure 8B This is a diagram illustrating an embodiment of the present disclosure of outputting a signal by changing the amount of compensation value.

[0019] Figure 9 This is a diagram illustrating a failure bit counting operation according to one embodiment of the present disclosure.

[0020] Figure 10 This is a diagram showing the threshold voltage of a memory cell according to one embodiment of the present disclosure.

[0021] Figure 11 This is a diagram illustrating a failure bit counting operation performed during a read operation according to one embodiment of the present disclosure.

[0022] Figure 12 This is a diagram illustrating a memory system including a memory device according to one embodiment of the present disclosure.

[0023] Figure 13 This is a diagram illustrating another memory system including a memory device according to one embodiment of the present disclosure. Detailed Implementation

[0024] The specific structural or functional descriptions of embodiments based on the concepts disclosed in this specification are merely for the purpose of describing embodiments based on the concepts disclosed herein. Embodiments based on the concepts disclosed herein may be implemented in various forms and should not be construed as limited to the embodiments described herein.

[0025] Figure 1 This is a diagram illustrating a memory device 1100 according to one embodiment of the present disclosure.

[0026] refer to Figure 1 The memory device 1100 may include a memory cell array 110, a row decoder 120, a voltage generator 130, a page buffer group 140, a column decoder 150, an input / output circuit 160, a current sensing circuit 170, and a control logic circuit 180.

[0027] The memory cell array 110 may include one or more planes, and each plane may include multiple memory blocks therein for storing data. Each memory block may include multiple memory cells, and the memory cells may be implemented in a two-dimensional structure in which the memory cells are arranged parallel to the substrate, or in a three-dimensional structure in which the memory cells are stacked vertically on the substrate.

[0028] The row decoder 120 can select a memory block from among the memory blocks included in the memory cell array 110 in response to the row address RADD, and transmit the operating voltage Vop to the selected memory block.

[0029] Voltage generator 130 can generate and output the operating voltage Vop required for various operations in response to operation code OPCD. For example, voltage generator 130 can generate and output programming voltage, verification voltage, read voltage, erase voltage, and pass voltage.

[0030] Page buffer group 140 can be connected to memory cell array 110 via bit lines. For example, page buffer group 140 may include page buffers connected to individual bit lines. Page buffers can operate simultaneously in response to page buffer control signals PBSIGS and can temporarily store data during programming or read operations. Each page buffer may include multiple latches capable of storing data. During read or verification operations, sensed data SDT is sensed via bit lines. <k:1>It can be stored in one of multiple latches included in the page buffer. During a read operation or a verification operation, multiple page buffers can store the sense data SDT received via the bit line. <k:1>Sensor data SDT <k:1>It can be data sensed from all selected pages included in the selected storage block, or it can be data sensed from some chunks of the selected pages.

[0031] The column decoder 150 can output a column select signal CS in response to the column address CADD, and multiple page buffers included in the page buffer group 140 can store data loaded on the data line DL# in response to the column select signal CS.

[0032] Input / output circuit 160 can interconnect memory device 1100 and external device via input / output lines IO. Here, the external device can be a controller capable of controlling memory device 1100. Input / output circuit 160 can receive commands (CMD), addresses (ADD), and data via input / output lines IO, or output data to an external device, and can receive data output from page buffer group 140. Input / output circuit 160 can transmit commands (CMD) and addresses (ADD) received via input / output lines IO to control logic circuit 180 and transmit data to page buffer group 140.

[0033] The current sensing circuit 170 can include the sensing data SDT <k:1>The number of failure bits in (K is a positive integer) is compared with the number of allowed failure bits, and a pass signal PS or a failure signal FS is output based on the comparison result. For example, the current sensing circuit 170 can output a pass signal PS or a failure signal FS based on the compensation code CP. <a:1>(A is a positive integer) and the allowed failure bit code FB <n:1>(N is a positive integer) generates a reference current and based on the sensing data SDT <k:1>A sensing current is generated. The current sensing circuit 170 can generate a reference voltage based on a reference current and a sensing voltage based on the sensing current. The current sensing circuit 170 can generate a pass signal PS or a failure signal FS by comparing the reference voltage and the sensing voltage.

[0034] For example, when included in the sensing data SDT <k:1>When the number of failure bits in (K is a positive integer) is less than or equal to the number of allowed failure bits, the current sensing circuit 170 can output a pass signal PS, and when included in the sensing data SDT <k:1>When the number of failure bits in (K is a positive integer) is greater than the number of allowed failure bits, the current sensing circuit 170 can output a failure signal FS.

[0035] Control logic circuit 180 can output operation code OPCD, row address RADD, page buffer control signal PBSIGS, and column address CADD in response to command CMD and address ADD received from an external device via input / output line IO. For example, control logic circuit 180 may include software that performs algorithms for various operations in response to command CMD, and hardware configured to output various signals based on address ADD and the algorithm. During a read operation, control logic circuit 180 can output a ready signal RB to the external device to prevent receiving the next command from the external device via input / output line IO. For example, the external device may be a controller capable of controlling memory device 1100.

[0036] Control logic circuitry 180 may include a failure bit manager 190 configured to determine whether a verification or read operation passes or fails. Figure 1 In this embodiment, the failure bit manager 190 is included in the control logic circuit 180, but according to one implementation, the failure bit manager 190 may be set separately outside the control logic circuit 180.

[0037] The Failure Bit Manager 190 can output compensation code CP during verification or read operations. <a:1>and allow failure bit code FB <n:1>Furthermore, the compensation code CP can be stored or modified in response to either the PS signal or the FS failure signal. <a:1>and allow failure bit code FB <n:1>.

[0038] Figure 2 This illustrates one embodiment according to the present disclosure. Figure 1 A diagram of the memory cell array 110 shown.

[0039] refer to Figure 2 The memory cell array 110 may include multiple planes PL1 to PL4. Different Figure 1 Page buffer sets 140 can be connected to planes PL1 to PL4 respectively. Each of planes PL1 to PL4 can include multiple memory blocks BLK1 to BLKi (i is a positive integer). Different row addresses can be set in the multiple memory blocks BLK1 to BLKi. Figure 1 The control logic circuit 180 output Figure 1 Programming operations are performed on the memory block selected by the row address RADD. Different local lines, including word lines, can be connected to multiple memory blocks BLK1 to BLKi, and bit lines can be connected together.

[0040] The following is a detailed description Figure 2 One of the multiple storage blocks BLK1 to BLKi shown.

[0041] Figure 3 This illustrates one embodiment according to the present disclosure. Figure 2 A diagram of the storage blocks shown.

[0042] refer to Figure 3 , Figure 2 One of the multiple storage blocks BLK1 to BLKi shown is a storage block BLKi, which is illustrated as one implementation.

[0043] The memory block BLKi may include multiple strings ST connected between the first bit line BL1 to the m-th bit line BLm (m is a positive integer) and the source line SL. Each string ST may include a source selection transistor SST, a first memory cell C1 to the n-th memory cell Cn (n is a positive integer), and a drain selection transistor DST connected in series between the source line SL and the first bit line BL1 to the m-th bit line BLm (m is a positive integer).

[0044] because Figure 3 The memory block BLKi shown is a diagram illustrating the configuration of the memory block; therefore, the number of source selection transistors SST, first memory cells C1 to nth memory cells Cn, and drain selection transistors DST are not limited to... Figure 3 The quantities shown.

[0045] The gates of source select transistors SST connected to different strings ST can be connected to source select line SSL, the gates of each of the first memory cell C1 to the nth memory cell Cn can be connected to the first word line WL1 to the nth word line WLn, and the gates of drain select transistors DST can be connected to drain select line DSL.

[0046] A group of memory cells connected to the same word line and included in different strings (ST) can be configured as a page (PG). Programming or reading operations can be performed on a page (PG) basis.

[0047] Figure 4 This illustrates one embodiment according to the present disclosure. Figure 1 The diagram shows the page buffer group 140.

[0048] refer to Figure 4 Page buffer group 140 may include first page buffers PB1 to m-th page buffers PBm (m is a positive integer). First page buffers PB1 to m-th page buffers PBm may be connected to first bit lines BL1 to m-th bit lines BLm, respectively. Each of the first page buffers PB1 to m-th page buffers PBm may include multiple latches. During a verification or read operation on a selected page, the first page buffers PB1 to m-th page buffers PBm can sense data by sensing a current or voltage on the first bit lines BL1 to m-th bit lines BLm that varies according to the threshold voltage of the memory cell, and store sensed data in one of the multiple latches. That is, one bit of sensed data can be stored in each of the first page buffers PB1 to m-th page buffers PBm. Therefore, m bits of sensed data can be stored in all the first page buffers PB1 to m-th page buffers PBm.

[0049] Figure 5 This is a diagram illustrating a method for sensing selected pages on a block-by-block basis according to one embodiment of the present disclosure.

[0050] refer to Figure 5 Since multiple memory cells are included in a selected page Sel_PG among multiple pages included in the memory block, the number of memory cells is the same as the number of bits of sensed data. As the integration density of the memory device increases, the number of memory cells included in the selected page Sel_PG also increases.

[0051] As the number of memory cells included in the selected page Sel_PG increases, the number of bits of sense data that need to be processed simultaneously during verification or read operations increases. Therefore, in this embodiment, the selected page Sel_PG can be divided into multiple blocks, and sense data can be processed on a block-by-block basis.

[0052] For example, the selected page Sel_PG can be divided into blocks CK1 to p-th blocks CKp (where p is a positive integer), and multiple memory units can be included in blocks CK1 to p-th blocks CKp. That is, the memory units included in the selected page Sel_PG can be divided into p groups, and each group can be configured with one block.

[0053] During a verification or read operation, sensing data sensed from all memory cells included in the selected page Sel_PG can be simultaneously stored in page buffer group 140, and the sensing data stored in page buffer group 140 can be sequentially output to current sensing circuit 170 in blocks. For example, when each of the first block CK1 to the p-th block CKp includes K memory cells, the data sensed from the first block CK1 can be the first sensing block data CK1_SDT. <k:1>The data sensed from the second block CK2 can be the second sensing block data CK2_SDT2 <k:1>And the data sensed from the p-th block CKp can be the p-th sensing block data CKp_SDTp <k:1>That is, during a verification or read operation, when a sensing operation is performed on the selected page Sel_PG, the first sensing block data CK1_SDT... <k:1>Data up to the p-th sensing block CKp_SDTp <k:1>It can be stored in page buffer group 140. When the sensing operation is completed, page buffer group 140 can sequentially output the first sensing block data CK1_SDT. <k:1>Data up to the p-th sensing block CKp_SDTp <k:1>For example, page buffer group 140 can output the first sensing block data CK1_SDT. <k:1>And then output the second sensing block data CK2_SDT2 <k:1>.

[0054] The current sensing circuit 170 can follow the first sensing block data CK1_SDT <k:1>Data up to the p-th sensing block CKp_SDTp <k:1>The output order is used for failure bit counting. For example, when the first sensing block data CK1_SDT... <k:1>When the data is input to the current sensing circuit 170, the current sensing circuit 170 can perform data CK1_SDT on the first sensing block. <k:1>The failure bit counting operation is performed, and the output is for the first sensing block data CK1_SDT. <k:1>The signal is either PS (pass) or FS (failure). Subsequently, when the second sensing block data CK2_SDT2... <k:1>When the data is input to the current sensing circuit 170, the current sensing circuit 170 can process the data CK2_SDT2 for the second sensing block. <k:1>The failure bit counting operation is performed, and the output is for the second sensing block data CK2_SDT2. <k:1>The signal is either a pass signal PS or a failure signal FS. In this method, the current sensing circuit 170 can sequentially output data CK1_SDT for the first sensing block. <k:1>Data up to the p-th sensing block CKp_SDTp <k:1>Each of them has either a pass signal PS or a failure signal FS.

[0055] The current sensing circuit 170 can compare the number of failure bits included in the sensed data with the number of allowed failure bits, and output a pass signal PS or a failure signal FS based on the comparison result. In this embodiment, a method of using a current that changes according to the number of failure bits can be used instead of a method of counting the sensed data bit by bit. A current sensing circuit 170 according to one embodiment is described in detail below.

[0056] Figure 6 This is a circuit diagram showing a current sensing circuit 170 according to one embodiment of the present disclosure.

[0057] refer to Figure 6 The current sensing circuit 170 may include a first compensation circuit 61, a second compensation circuit 62, a voltage output circuit 63, a sensing data receiver 64, a failure bit receiver 65, and a comparison circuit 66.

[0058] The first compensation circuit 61 can be configured to respond to compensation code CP. <a:1>(A is a positive integer) and change the current of the first node D1, and the second compensation circuit 62 can be configured to respond to the compensation code CP. <a:1>This changes the current at the second node D2. That is, the first compensation circuit 61 and the second compensation circuit 62 can be configured with the same structure and can be connected to different first nodes D1 or second nodes D2. According to the compensation code CP... <a:1>It can determine the ratio of the number of failure bits to the number of allowed failure bits corresponding to the number of failure bits, and can change the reference used to output the pass signal PS or the failure signal FS according to this ratio. For example, when the ratio is 1, if the number of detected failure bits is greater than the number of allowed failure bits, the failure signal FS is output, and if the number of detected failure bits is less than the number of allowed failure bits, the pass signal PS is output.

[0059] The first compensation circuit 61 may include a first compensation switch P1 to an Ath compensation switch PA connected in parallel between a terminal supplied with power supply voltage VCC and a first node D1. The first compensation switch P1 to the Ath compensation switch PA may be implemented in response to a compensation code CP. <a:1>Each bit in the PMOS transistor is turned on or off. For example, the first compensation switch P1 can be configured to respond to the first compensation code CP. <1> The switch can be turned on or off, and the second compensation switch P2 can be configured to respond to the second compensation code CP. <2> And whether it is turned on or off.

[0060] The second compensation circuit 62 can be configured in the same way as the first compensation circuit 61. For example, the second compensation circuit 62 may include a first compensation switch N1 to an Ath compensation switch NA connected in parallel between the terminal supplied with the power supply voltage VCC and the second node D2.

[0061] The compensation code CP is input to the first compensation circuit 61 and the second compensation circuit 62. <a:1>It can be formed by combinations of 0, combinations of 0 and 1, or combinations of 1. For example, when 1 is defined as the compensation code CP. <a:1>When calculating the compensation value, the ratio of the number of failure bits to the number of allowed failure bits corresponding to the number of failure bits can be changed according to the number of compensation values. In this embodiment, 0 data is defined as the configuration compensation code CP. <a:1>The compensation value in the code can be defined as data according to the structure of the current sensing circuit 170. In one embodiment described below, the compensation value is 0 data.

[0062] The voltage output circuit 63 may include a first switch S1 and a second switch S2, configured to generate a sense voltage VP and a reference voltage VN. The first switch S1 is connected between a first node D1 and a third node D3 and can be implemented as a PMOS transistor outputting the sense voltage VP. The gate of the first switch S1 can be connected to the third node D3, and the sense voltage VP generated according to the compensation current Ip of the third node D3 can be output to the gate of the first switch S1. That is, the first switch S1 can generate the sense voltage VP according to the compensation current Ip flowing through the third node D3, and can adjust its conduction level according to the sense voltage VP applied to the gate of the first switch S1. The second switch S2 is connected between a second node D2 and a fourth node D4 and can be implemented as a PMOS transistor outputting the reference voltage VN. Since the gate of the second switch S2 is connected to the gate of the first switch S1, the conduction level of the second switch S2 is the same as the conduction level of the first switch S1. The reference voltage VN can be output via the fourth node D4, and the level of the reference voltage VN can be determined by the current flowing through the fourth node D4.

[0063] The sensing data receiver 64 can be configured to respond to the enable signal EN and the sensing data SDT. <k:1>This generates a compensation current Ip. For example, the sensing data receiver 64 may include a first enable switch Ep1 to a Kth enable switch EpK and a first sensing switch Sc1 to a Kth sensing switch ScK connected between the third node D3 and the ground terminal GND. The first enable switches Ep1 to Kth enable switches EpK and the first sensing switches Sc1 to Kth sensing switches ScK may be paired with each other. For example, the first enable switch Ep1 and the first sensing switch Sc1 may be paired with each other and connected in series between the third node D3 and the ground terminal GND, and the second enable switch Ep2 and the second sensing switch Sc2 may be paired with each other and connected in series between the third node D3 and the ground terminal GND. In such a method, the Kth enable switch EpK and the Kth sensing switch ScK may be paired with each other and connected between the third node D3 and the ground terminal GND.

[0064] The first enable switches Ep1 to the Kth enable switches EpK can be implemented as NMOS transistors connected between the third node D3 and the first sensing switches Sc1 to the Kth sensing switches ScK. The gates of the first enable switches Ep1 to the Kth enable switches EpK can be interconnected. Therefore, when an enable signal EN with a logic high level is applied to the gate of the first enable switches Ep1 to the Kth enable switches EpK, the first enable switches Ep1 to the Kth enable switches EpK can be turned on simultaneously. That is, when the enable signal EN has a logic high level, the current sensing circuit 170 can be activated, and when the enable signal EN has a logic low level, the current sensing circuit 170 can be deactivated.

[0065] The first sensing switches Sc1 to the Kth sensing switches ScK can be implemented as NMOS transistors connected between the first enable switch Ep1 to the Kth enable switch EpK and the ground terminal GND. The first sensing switches Sc1 to the Kth sensing switches ScK can be implemented in response to the sensing data SDT. <k:1>Each bit in the NMOS transistor is turned on or off. For example, the first sensing switch Sc1 can be configured to respond to the first sensing data SDT. <1> And the second sensing switch Sc2 can be configured to be turned on or off in response to the second sensing data SDT. <2> And thus, it is either turned on or off. In this method, the Kth sensing switch ScK can be configured to respond to the Kth sensing data SDT. <k>And whether it is turned on or off.

[0066] First to Kth Sensing Data SDT <k:1>The data can be sensed from the entire selected page or from blocks included in the selected page. This setting can be varied depending on the memory device. For example, when the number of memory cells included in the page is less than the reference number, the first to Kth sensed data SDT... <k:1>This can be data sensed across the entire selected page. When the number of memory cells included in the page is greater than or equal to the reference number, the first to Kth sensed data SDT... <k:1>This can be data sensed from blocks included in the selected page.

[0067] Since the first sensing switch Sc1 to the Kth sensing switch ScK are based on the first to Kth sensing data SDT <k:1>And whether it is turned on or off, therefore, with the first to the Kth sensing data SDT <k:1>As the number of bits with a logic high level increases, the number of switches that are turned on among the first sensing switch Sc1 to the Kth sensing switch ScK also increases.

[0068] When a bit with a logic high level has a value of 1 and the bit with a value of 1 is a detected failure bit, along with the first to the Kth sensing data SDT <k:1>As the number of bits with a value of 1 increases, the compensation current Ip can increase, and the level of the sensing voltage VP can also increase. That is, as the number of detected failure bits increases, the level of the sensing voltage VP can increase.

[0069] Failure bit receiver 65 can be configured to respond to enable signal EN and enable failure bit code FB. <n:1>A reference current In is generated. For example, the failure bit receiver 65 may include a first enable switch En1 to an Nth enable switch EnN and a first failure switch Sf1 to an Nth failure switch SfN connected between the fourth node D4 and the ground terminal GND. The first enable switches En1 to Nth enable switches EnN and the first failure switches Sf1 to Nth failure switches SfN may be paired with each other. For example, the first enable switch En1 and the first failure switch Sf1 may be paired with each other and connected in series between the fourth node D4 and the ground terminal GND, and the second enable switch En2 and the second failure switch Sf2 may be paired with each other and connected in series between the fourth node D4 and the ground terminal GND. In such a method, the Nth enable switch EnN and the Nth failure switch SfN may be paired with each other and connected between the fourth node D4 and the ground terminal GND.

[0070] The first enable switch En1 to the Nth enable switch EnN can be implemented as NMOS transistors connected between the fourth node D4 and the first failure switch Sf1 to the Nth failure switch SfN. The gates of the first enable switch En1 to the Nth enable switch EnN can be interconnected. Therefore, when an enable signal EN with a logic high level is applied to the gates of the first enable switch En1 to the Nth enable switch EnN, the first enable switch En1 to the Nth enable switch EnN can be turned on simultaneously. That is, when the enable signal EN has a logic high level, the current sensing circuit 170 can be activated, and when the enable signal EN has a logic low level, the current sensing circuit 170 can be deactivated.

[0071] The first failure switch Sf1 to the Nth failure switch SfN can be implemented as NMOS transistors connected between the first enable switch En1 to the Nth enable switch EnN and the ground terminal GND. The first failure switch Sf1 to the Nth failure switch SfN can be implemented in response to the included failure bit code FB. <n:1>Each bit in the NMOS transistor is turned on or off. For example, the first failure switch Sf1 can be configured to respond to the first enable failure bit code FB. <1> The second failure switch Sf2 can be configured to be turned on or off in response to the second failure-allowing bit code FB. <2> And it is either turned on or off. In such a method, the Nth failure switch SfN can be configured to respond to the Nth failure-allowing bit code FB. <n>And whether it is turned on or off.

[0072] First through Nth allowed failure bit codes FB <n:1>It can be based on Figure 1 The code is modified by the algorithm executed in the control logic circuit 180, and can be combined with the SDT included in the first to Kth sensing data. <k:1>The number of failure bits in the code is compared. That is, the first to Nth allowed failure bit codes FB. <n:1>It can be used to determine the SDT of the first to the Kth sensing data. <k:1>This serves as a reference for whether the sensing verification or reading operation passed or failed.

[0073] Since the first failure switch Sf1 to the Nth failure switch SfN are based on the first to Nth failure-allowing bit codes FB <n:1>And whether it is turned on or off, therefore, with the first to Nth allowed failure bit codes FB <n:1>As the number of bits with logic high level increases, the number of switches that are turned on from the first failure switch Sf1 to the Nth failure switch SfN also increases.

[0074] When a bit with a logic high level has a value of 1 and the bit with a value of 1 is a fail-allow bit code, along with the first to Nth fail-allow bit codes FB <n:1>As the number of bits with a value of 1 increases, the reference current In can increase and the level of the reference voltage VN can increase. That is, as the failure-allowing bit codes FB from the first to the Nth increase... <n:1>Increasing the number of bits with a value of 1 can increase the number of failed bits detected by verification or read operations.

[0075] The comparator circuit 66 may include a comparator configured to compare a sensed voltage VP and a reference voltage VN and output a pass signal PS or a failure signal FS based on the comparison result. For example, the comparator may be configured to apply the sensed voltage VP to a positive (plus) (+) input terminal and the reference voltage VN to a negative (-) input terminal. When the sensed voltage VP is less than or equal to the reference voltage VN, the comparator may output a pass signal PS with a logic low level, and when the sensed voltage VP is greater than the reference voltage VN, it may output a failure signal FS with a logic high level.

[0076] Figures 7A to 7C This is a diagram illustrating a failure bit manager according to one embodiment of the present disclosure.

[0077] refer to Figure 7A The failure bit manager 190 may include a code controller 71, a counter 72, a register 73, and a code output circuit 74.

[0078] The code controller 71 can be configured to generally control the failure bit manager 190 during verification or read operations. The code controller 71 can be configured to output a first compensation count signal 1CNT_C, a second compensation count signal 2CNT_C, a first failure count signal 1CNT_F, or a second failure count signal 2CNT_F in response to a signal PS or a failure signal FS. For example, when executing an algorithm for setting the failure bit, the code controller 71 can be configured to output the first failure count signal 1CNT_F or the second failure count signal 2CNT_F in response to a signal PS or a failure signal FS. When executing an algorithm for setting a compensation value, the code controller 71 can be configured to output the first compensation count signal 1CNT_C or the second compensation count signal 2CNT_C in response to a signal PS or a failure signal FS.

[0079] More specifically, when executing the algorithm for setting the failure bit, the code controller 71 can be configured to output a first failure count signal 1CNT_F in response to the failure signal FS, and to output a second failure count signal 2CNT_F in response to the signal PS. When executing the algorithm for setting the compensation value, the code controller 71 can be configured to output a first compensation count signal 1CNT_C in response to the failure signal FS, and to output a second compensation count signal 2CNT_C in response to the signal PS.

[0080] Counter 72 can be configured to set the allowed number of failure bits F# or the number of compensation values ​​C# in response to a first failure count signal 1CNT_F, a second failure count signal 2CNT_F, a first compensation count signal 1CNT_C, or a second compensation count signal 2CNT_C, and output the set allowed number of failure bits F# or the number of compensation values ​​C#. For example, counter 72 can output the incremented allowed number of failure bits F# each time it receives the first failure count signal 1CNT_F, and output the most recently set allowed number of failure bits F# when it receives the second failure count signal 2CNT_F. Counter 72 can also output the incremented number of compensation values ​​C# each time it receives the first compensation count signal 1CNT_C, and output the most recently set number of compensation values ​​C# when it receives the second compensation count signal 2CNT_C.

[0081] Register 73 can be configured to store the number of compensation values ​​C# and the number of allowed failure bits F# output from counter 72, and output the stored number of compensation values ​​C# and the number of allowed failure bits F#. For example, register 73 may include: a compensation value register REG_CP, which is configured to store and output the number of compensation values ​​C#; and a failure bit register REG_FB, which is configured to store and output the number of allowed failure bits F#.

[0082] The code output circuit 74 can be configured to output a compensation code CP in response to the number of compensation values ​​C# or the number of allowed failure bits F#. <a:1>Or allow failure bit code FB <n:1>For example, code output circuit 74 may include: a compensation code generator GEN_CP, which is configured to generate and output compensation code CP in response to the number of compensation values. <a:1>; and the failure bit generator GEN_FB, which is configured to output the allowable failure bit code FB in response to the allowable failure bit number F#. <n:1>Compensation code CP <a:1>It includes A bits of code, and allows failure bit code FB. <n:1>It consists of N bits of code. The compensation code generator GEN_CP can add to the compensation code CP each time the number of compensation values ​​in C# increases. <a:1>The number of bits with a value of 0. The failure bit generator GEN_FB can be increased each time the number of allowed failure bits F# increases, including the allowed failure bit code FB. <n:1>The number of bits with a value of 1 in the array.

[0083] refer to Figure 7B According to one embodiment of this disclosure, a compensation code CP can be generated based on the number of compensation values ​​C# and the number of allowed failure bits F#. <a:1>and allow failure bit code FB <n:1>One embodiment. In one implementation, A is 8, and the compensation value is 0 data. In this case, when the number of compensation values ​​C# is 0, the compensation code CP <a:1>It can be generated as 11111111, when the number of compensation values ​​(C#) is 1, the compensation code CP <a:1>It can be generated as 11111110, and when the number of compensation values ​​in C# is 4, the compensation code CP <a:1>It can be generated as 11110000. That is, it is included in the compensation code CP. <a:1>The number of bits with a value of 0 can be proportional to the number of compensation values ​​C#. In one implementation, when N is 10, the allowed failure bit code FB is 0 when the allowed failure bit number F# is 0. <n:1>It can be generated as 0000000000, when the allowed number of failure bits F# is 1, the allowed failure bit code FB is... <n:1>It can be generated as 0000000001, and when the number of allowed failure bits F# is 4, the allowed failure bit code FB is... <n:1>It can be generated as 0000001111. That is, it includes the allowed failure bit code FB. <n:1>The number of bits with a value of 1 in the array can be proportional to the number of allowed failure bits F#. Figure 7B In the embodiment shown, when the initial number of compensation values ​​(initial C#) and the initial allowed number of failure bits (initial F#) are set to 0 as the minimum value, the number of compensation values ​​(C#) and the number of allowed failure bits (F#) can be selected in an increasing order each time a read operation fails.

[0084] refer to Figure 7C The initial number of compensation values ​​"initial C#" and the initial allowed number of failure bits "initial F#" can be set to any number other than the minimum value. For example, when the initial number of compensation values ​​"initial C#" is set to 1, the number of compensation values ​​C# selected next can be reduced to 0, and the number of compensation values ​​C# selected next can be increased to 2. When the initial allowed number of failure bits "initial F#" is set to 2, the allowed number of failure bits F# can be sequentially reduced in the order of 1 and 0 each time a read operation fails. When it is determined that the read operation will fail even at the minimum value, the allowed number of failure bits F# can be increased to 3, and can be increased sequentially from 3.

[0085] Besides reference Figure 7B or Figure 7C In addition to the described implementation method, the initial number of compensation values ​​"initial C#" and the initial allowed number of failure bits "initial F#" can be set to various values, and the order of the selected numbers can be changed in various ways.

[0086] Figure 8A This is a diagram illustrating an embodiment of the present disclosure in which a pass signal is output by changing the number of allowable failure bits.

[0087] refer to Figure 8A The slope of the first reference line 1REF_L, which determines pass or fail based on the allowed number of failure bits AFB# and the detected number of failure bits DFB#, is constant. When the first detected number of failure bits DFB1 included in the sensed data is greater than the first allowed number of failure bits AFB1 based on the first reference line 1REF_L, the verification or read operation may fail. When the verification or read operation fails, Figure 1 The failure bit manager 190 can increase the first allowed number of failure bits AFB1 to the second allowed number of failure bits AFB2.

[0088] A verification or read operation can proceed when the second allowed number of failure bits, AFB2, based on the first reference line 1REF_L, is greater than the first detected number of failure bits, DFB1. Therefore, the first detected number of failure bits, DFB1, can be calculated by referring to the second allowed number of failure bits, AFB2, used when the verification or read operation passes. For example, the number of failure bits increased from the allowed number of failure bits, AFB1, to the allowed number of failure bits, AFB2, can be the detected number of failure bits, DFB1.

[0089] Figure 8B This is a diagram illustrating an embodiment of the present disclosure of outputting a signal by changing the amount of compensation value.

[0090] refer to Figure 8B When a verification or read operation fails, the allowed number of failure bits AFB# will not increase further until it reaches the maximum allowed number of failure bits AFBmax. In this case, Figure 1 The failure bit manager 190 can increase the first slope 1GRD of the reference line REF_L to a second slope 2GRD while maintaining the maximum allowed number of failure bits AFBmax. For example, since the first detection number DFB1 and the maximum allowed number of failure bits AFBmax are fixed, verification or read operations can proceed when the slope of the reference line REF_L is increased.

[0091] Figure 9 This is a diagram illustrating a failure bit counting operation according to one embodiment of the present disclosure.

[0092] refer to Figure 9 The failure bit counting operation performed during the read operation is described as an implementation method below.

[0093] When a read operation on the selected page begins, a read voltage can be applied to the selected word line connected to the selected page, and data in the memory cell can be sensed based on the read voltage (S91). For example, the sensed data can be stored in the page buffer as sensed data SDT.

[0094] Figure 1 The failure bit manager 190 can set the initial value of the number of compensation values ​​C# (S92) and the initial value of the number of allowed failure bits F# (S93). The initial value of the number of compensation values ​​C# can be set to 0 or a positive integer, and the initial value of the number of allowed failure bits F# can be set to 0 or a positive integer.

[0095] Subsequently, Figure 6 The current sensing circuit 170 can receive sensing data SDT output from the page buffer and compare the sensing voltage VP generated based on the sensing data SDT and the allowed failure bit with the reference voltage VN (S94).

[0096] Figure 6 The current sensing circuit 170 can determine whether a read operation is successful based on the reference voltage VN and the sensed voltage VP (S95). For example, when the sensed voltage VP is higher than the reference voltage VN, Figure 6 The current sensing circuit 170 can output a failure signal FS, and Figure 1 The failure bit manager 190 can determine that the read operation failed based on the failure signal FS (no in S95).

[0097] When it is determined in operation S95 that the read operation failed (no), Figure 1 The failure bit manager 190 checks whether the number of allowed failure bits F# is the maximum value (S96).

[0098] When the allowed number of failure bits F# is not the maximum value (no in S96), Figure 1 The failure bit manager 190 increases the number of allowed failure bits F# (S97). For example, Figure 1 The failure bit manager 190 can increase the number of allowed failure bits F# by 1, but depending on the memory device, Figure 1 The failure bit manager 190 can increase the number of allowed failure bits F# by a positive integer greater than 1.

[0099] Figure 1 The failure bit manager 190 can set the allowed failure bit count F#, which was changed in operation S97, to the allowed count to be used in the next read operation, and determine whether the read operation succeeds by repeating operations S94 and S95. That is, the operation of finding the allowed failure bit count F# when the read operation succeeds by repeating operations S93, S94, S95, S96, and S97 can correspond to the reference Figure 8A The described implementation method.

[0100] In operation S96, when the number of allowed failure bits F# reaches its maximum value (yes), Figure 1 The failure bit manager 190 checks whether the number of compensation values ​​in C# is used to change the slope of the reference line. Figure 8B The maximum value of 1GRD (S98). For example, Figure 1 The failure bit manager 190 can increase the number of compensation values ​​(C#), thereby increasing the ratio of failure bits to the number of allowed failure bits.

[0101] When the amount of compensation value in C# is not the maximum value (not in S98), Figure 1 The failure bit manager 190 increases the number of compensation values ​​in C# (S99). For example, Figure 1 The failure bit manager 190 can increase the number of 1 data included in the compensation value.

[0102] Figure 1 The failure bit manager 190 can calculate the number of failure bits included in the sensed data SDT based on the number of compensation values ​​C# changed in operation S99. That is, the operation of finding the number of compensation values ​​C# that allow the read operation to pass by repeating operations S93, S94, S95, S96, S98, and S99 can correspond to a reference. Figure 8B The described implementation method.

[0103] In operation S98, if operation S95 still fails even when the number of compensation values ​​C# reaches its maximum value, this means that the read operation still fails even when the number of compensation values ​​C# and the number of allowed failure bits F# each have their own maximum values. Therefore... Figure 1 The failure bit manager 190 can process the read operation as a failure (S100).

[0104] In operation S95, when the read operation passes (yes), Figure 1 The failure bit manager 190 can store the number of recently set compensation values ​​C# and the number of allowed failure bits F# (S101). That is, since the number of allowed failure bits F# gradually increases until operation S95, the number of failure bits included in the sensing data SDT can be calculated based on the number of allowed failure bits F# and the number of compensation values ​​C# stored when operation S95 is passed.

[0105] In methods for storing two or more bits of data in a single memory cell (e.g., MLC, TLC, QLC, etc.), the memory cell can be programmed to have multiple threshold voltage distributions. MLC refers to a multi-level cell method storing two bits of data in a single memory cell, TLC refers to a three-level cell method storing three bits of data in a single memory cell, and QLC refers to a four-level cell method storing four bits of data in a single memory cell. Therefore, in MLC or higher methods, multiple read voltages can be used for read operations, and different read voltages can be used in each read operation to perform the aforementioned implementation. In these methods, the read operation of the TLC method is described as an example.

[0106] Figure 10 This is a diagram showing the threshold voltage of a memory cell according to one embodiment of the present disclosure.

[0107] refer to Figure 10 In the TLC method, three bits of data can be stored in a single memory cell. Therefore, the memory cell can be maintained in an erased state ER, or it can be programmed to any of the first programming states P1 through the seventh programming states P7, depending on a threshold voltage. Therefore, read operations on memory cells programmed using the TLC method are also performed using the TLC method. For example, during a read operation, first read voltages Vr1 through seventh read voltages Vr7 can be used. The first read voltage Vr1 can be a voltage used to distinguish between the erased state ER and the first programming states P1 through P7, and the second read voltage Vr2 can be a voltage used to distinguish between memory cells corresponding to the erased state ER and the first programming state P1 and memory cells corresponding to the second programming states P2 through P7. The remaining third read voltages Vr3 through seventh read voltage Vr7 can also be set to distinguish memory cells corresponding to different programming states.

[0108] The order in which the first read voltage Vr1 to the seventh read voltage Vr7 can be set according to different memory devices, and a failure bit counting operation can be performed after the sensing operation of each read operation.

[0109] Figure 11 This is a diagram illustrating a failure bit counting operation performed during a read operation according to one embodiment of the present disclosure.

[0110] refer to Figure 10 and Figure 11 When the read operation on the selected page begins, Figure 1 The control logic circuit 180 can output a read busy signal RB with a logic low level from the time point 111 when the read operation 1READ starts to the time point 112 when all failure bit count operations 113 are completed, to prevent receiving another command during the read operation.

[0111] When the number of read voltages used in a read operation on the selected page is J (J is a positive integer), first read voltages to J read voltages can be used for first read operations 1READ to J read operations JREAD. Here, the order in which first read operations 1READ to J read operations JREAD are performed is independent of the levels of the first to J read voltages. For example, depending on the read operation algorithm, either the first read voltage Vr1 or the fourth read voltage Vr4 can be used in the first read operation 1READ. That is, the order of first read operations 1READ to J read operations JREAD can refer to the order in which the read operations are performed, and the read voltage used in each read operation can vary depending on the algorithm set in the memory device. In first read operations 1READ to J read operations JREAD, the read voltage can be applied to the selected word line connected to the selected page.

[0112] When the first read operation 1READ ends, a first sensing operation 1SEN can be performed simultaneously with a second read operation 2READ using a different read voltage. During the first sensing operation 1SEN to the Jth sensing operation JSEN, the current or voltage of the bit line changed by the previously performed read operation can be sensed, and the sensed data can be stored in the page buffer based on the sensed current or voltage.

[0113] When the first sensing operation 1SEN ends, a first check operation 1CHK can be performed simultaneously with the third read operation 3READ to check for failure bits in the sensing data sensed in the first sensing operation 1SEN. The first check operation 1CHK can be performed until the first read operation 1READ passes. For example, in the first check operation 1CHK, a reference... Figure 9 Operations S92 to S99 are described. That is, operations S92 to S99 can be performed until operation S95 passes, and the read operation can be processed as a failure when the number of compensation values ​​C# in operation S98 reaches its maximum value. When operation S95 passes in the first check operation 1CHK, a first storage operation 1S can be performed simultaneously with the fourth read operation 4READ, storing the number of allowed failure bits F# and the number of compensation values ​​C# last set in the first check operation 1CHK. The number of failure bits included in the sensing data SDT can be calculated based on the number of allowed failure bits F# and the number of compensation values ​​C# stored when operation S95 passes.

[0114] In the above method, after performing the first read operation 1READ, the remaining second read operations 2READ to JREAD can be performed, and the second sensing operations 2SEN to Jsen, the second checking operations 2CHK to JCHK, and the second storage operations 2S to J storage operations JS can be performed sequentially for the second read operations 2READ to JREAD.

[0115] Figure 12 This is a diagram illustrating a memory system 1000 including a memory device according to one embodiment of the present disclosure.

[0116] refer to Figure 12 The memory system 1000 may include: a memory device 1100 storing data therein; and a controller 1200 communicating between the memory device 1100 and the host 2000.

[0117] The memory system 1000 may include a plurality of memory devices 1100, and the memory devices 1100 may be connected to the controller 1200 via at least one channel. For example, the plurality of memory devices 1100 may be connected to one channel, and even if the plurality of channels are connected to the controller 1200, the plurality of memory devices 1100 may be connected to each channel. Figure 12 The memory device 1100 shown can be used with Figure 1 The memory device 1100 shown is implemented in the same way.

[0118] The controller 1200 can communicate between the host 2000 and the memory device 1100. The controller 1200 can control the memory device 1100 based on requests from the host 2000, or perform background operations to improve the performance of the memory system 1000 even without requests from the host 2000. The host 2000 can generate requests for various operations and output these requests to the memory system 1000. For example, these requests may include programming requests that control programming operations, read requests that control read operations, and erase requests that control erase operations.

[0119] The host 2000 can communicate with the memory system 1000 via various communication standards or interfaces such as Peripheral Component Interconnect Express (PCIe), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Serial Attached SCSI (SAS), Non-Volatile Memory Express (NVMe), Universal Serial Bus (USB), Multimedia Card (MMC), Enhanced Small Disk Interface (ESDI), or Integrated Drive Electronics (IDE).

[0120] Figure 13 This is a diagram illustrating another memory system 70000 including a memory device according to one embodiment of the present disclosure.

[0121] refer to Figure 13 The memory system 70000 can be implemented as a memory card or a smart card. The memory system 70000 may include a memory device 1100, a controller 1200, and a card interface 7100.

[0122] The controller 1200 can control the data exchange between the memory device 1100 and the card interface 7100. Figure 13 The memory device 1100 shown can be connected to Figure 1 The memory device 1100 shown is implemented in the same way.

[0123] The card interface 7100 can be a Secure Digital (SD) card interface or a Multimedia Card (MMC) interface, but is not limited to these.

[0124] Card interface 7100 can interface for data exchange between host 60000 and controller 1200 according to the protocol of host 60000. According to one embodiment, card interface 7100 can support Universal Serial Bus (USB) protocol and IC-USB protocol. Here, card interface 7100 can refer to hardware capable of supporting the protocol used by host 60000, software installed in the hardware, or signal transmission method.

[0125] When the memory system 70000 is connected to the host interface 6200 of the host 60000 (e.g., PC, tablet computer, digital camera, digital audio player, mobile phone, console video game hardware, or digital set-top box), the interface 6200 can communicate with the memory device 1100 via the card interface 7100 and the controller 1200 under the control of the microprocessor (μP) 6100.

[0126] While the invention has been described with respect to specific embodiments, it will be apparent to those skilled in the art that various changes and modifications can be made without departing from the spirit and scope of the invention as defined in the appended claims. Furthermore, embodiments can be combined to form other embodiments.

[0127] Cross-reference to related applications

[0128] This application claims priority to Korean Patent Application No. 10-2021-0022120, filed on February 18, 2021, the entire disclosure of which is incorporated herein by reference. < / n> < / k>

Claims

1. A memory device comprising: Memory unit; A page buffer stores sensing data obtained from the memory unit; Current sensing circuit, the current sensing circuit: The sensed voltage generated based on the sensed data received from the page buffer is compared with the reference voltage generated based on the allow failure bit code received from the failure bit manager, and Based on the comparison result, a pass signal or a failure signal will be output to the failure bit manager; and The failure bit manager: Increase the number of allowable failure bits included in the allowable failure bit code until the pass signal is output from the current sensing circuit. The allowed failure bit code is changed according to the number of allowed failure bits. Provide the failure-allowing bit code to the current sensing circuit, and When the pass signal is received from the current sensing circuit, the number of failure bits included in the sensing data is determined based on the number of allowed failure bits.

2. The memory device according to claim 1, wherein, The page buffer is connected to the memory cell via a bit line and stores the sensed data according to the current or voltage of the bit line.

3. The memory device according to claim 1, wherein, The current sensing circuit includes: A sensing data receiver, which generates a compensation current based on the sensing data; A failure bit receiver that generates a reference current based on the allowed failure bit code; A voltage output circuit, wherein the voltage output circuit outputs the sensed voltage according to the compensation current, and generates the reference voltage according to the reference current; and A comparison circuit compares the sensed voltage with the reference voltage and outputs a pass signal or a failure signal based on the comparison result.

4. The memory device according to claim 3, wherein, The sensing data receiver also increases the compensation current as the number of detected failure bits included in the sensing data increases.

5. The memory device according to claim 3, wherein, The failure bit receiver also increases the reference current as the number of allowable failure bits included in the allowable failure bit code increases.

6. The memory device according to claim 3, wherein, The voltage output circuit outputs a higher level sense voltage as the compensation current increases, and outputs a higher level reference voltage as the reference current increases.

7. The memory device according to claim 1, wherein, The failure bit manager includes: A code controller that outputs a first failure count signal or a second failure count signal in response to the pass signal or the failure signal; A counter that increments or decrements the number of allowed failure bits in response to the first failure count signal or the second failure count signal, and outputs the incremented or decremented number of allowed failure bits. A register that stores the number of allowed failure bits output from the counter; and A code output circuit that generates and outputs the allowed failure bit code based on the number of allowed failure bits stored in the register.

8. The memory device according to claim 7, wherein, The code controller outputs a first failure count signal in response to the failure signal, and outputs a second failure count signal in response to the pass signal.

9. The memory device according to claim 8, wherein, The counter increments or decrements the number of allowed failure bits in response to the first failure count signal, and maintains the most recently generated number of allowed failure bits in response to the second failure count signal.

10. The memory device according to claim 3, wherein, The current sensing circuit further includes a compensation circuit that changes the slope of the reference line used to determine the pass signal or the failure signal.

11. The memory device according to claim 10, wherein, When the failure signal is still output until the number of allowed failure bits reaches its maximum value, the failure bit manager generates compensation code to change the slope and outputs the compensation code to the current sensing circuit.

12. The memory device according to claim 11, wherein, The failure bit manager generates the compensation code to increase the slope and outputs the compensation code to the current sensing circuit until the pass signal is output.

13. A memory device comprising: Memory unit; Page buffer, which is connected to the memory cell via bit lines and senses the current or voltage of the bit lines during read operations to store sensed data; Current sensing circuit, the sensing circuit: The success or failure of the read operation is determined based on the number of detected failure bits and the number of allowed failure bits in the sensed data. The ratio of the number of detected failure bits to the number of allowed failure bits corresponding to the number of detected failure bits is changed, wherein the ratio is determined based on the number of compensation values; and Failure bit manager, the failure bit manager: Adjust the number of allowed failure bits until the read operation succeeds, and When it is determined that the read operation still fails until the number of allowed failure bits reaches its maximum value, the amount of compensation value is adjusted.

14. The memory device according to claim 13, wherein, The current sensing circuit includes: A compensation circuit that changes the voltage of the first node and the second node according to the amount of compensation value; A sensing data receiver that changes the current of the third node based on the number of detected failure bits; A failure bit receiver that changes the current of the fourth node according to the number of allowed failure bits; A voltage output circuit that outputs a sensed voltage based on the current between the first node and the third node, and outputs a reference voltage based on the current between the second node and the fourth node; and A comparison circuit compares the sensed voltage with the reference voltage and outputs a pass signal or a failure signal based on the comparison result.

15. The memory device according to claim 14, wherein, The compensation circuit also increases the ratio as the number of compensation values ​​increases.

16. The memory device according to claim 14, wherein, The current of the third node increases as the number of detected failure bits in the sensing data increases.

17. The memory device according to claim 14, wherein, The failure bit receiver increases the current of the fourth node as the number of allowed failure bits increases.

18. The memory device according to claim 14, wherein, The voltage output circuit outputs a higher level sensed voltage as the voltage of the first node or the current of the third node increases.

19. The memory device according to claim 14, wherein, The voltage output circuit outputs a reference voltage with a higher level as the voltage of the second node or the current of the fourth node increases.

20. The memory device according to claim 13, wherein, The failure bit manager includes: A code controller that outputs a compensation count signal or a failure count signal in response to a pass signal or a failure signal output from the current sensing circuit; A counter that changes the number of compensation values ​​or the number of allowed failure bits in response to the compensation count signal or the failure count signal; A register that stores the number of compensation values ​​changed by the counter or the number of allowed failure bits; and A code output circuit that outputs an allow failure bit code or a compensation code for changing the ratio based on the number of compensation values ​​or the number of allow failure bits stored in the register.

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