A CT detector module and data acquisition method

Abstract

The application provides a CT detector module and a data acquisition method. The CT detector module comprises an FPGA chip and an ADC chip. The pin group of the FPGA chip comprises the following pins: an MCLK pin for sending a main clock signal to the ADC chip; a CONV pin for sending a flip signal to the ADC chip; a DCLK pin for sending a driving clock signal from the ADC chip to the FPGA chip; and a Data pin for sending a data packet from the ADC chip to the FPGA chip. The data packet comprises: a packet header set by the FPGA chip, having start information and highest bit information; and data, storing control information. When the FPGA chip detects that the information in the packet header changes to the highest bit information, the driving clock signal received by the DCLK pin at this time is recorded as a start time, and the data packet is received from the start time as a starting point to the holding time in the driving clock signal as an ending point until the data packet turns to a low level. After the above technical scheme is adopted, the acquired data is stably output, and the image quality of the detector is improved.

Description

Technical Field

[0001] This invention relates to the field of medical devices, and more particularly to a CT detector module and a data acquisition method. Background Technology

[0002] With the widespread use of CT nuclear medicine imaging equipment in major hospitals, patients are now undergoing increasingly common imaging-assisted examinations in hospitals.

[0003] Currently, the ADC chip in the detector of CT nuclear medicine imaging equipment uses pulses to trigger the switching signal. Stable sampling requires that the data setup and hold times be kept consistent. As the number of detectors increases, the inconsistent path delay between the ADC chip and the FPGA chip means that although outputs are simultaneous, the arrival times at the FPGA chip's input pins are not uniform. At lower sampling frequencies, maintaining consistent setup and hold times is relatively easy, allowing for stable data sampling. However, as the number of detector rows increases, the number of analog channels in a single ADC chip also increases, leading to a greater amount of data converted and output per unit time. Therefore, a higher sampling frequency is needed. With increasing frequency, it becomes increasingly difficult to maintain consistent setup and hold times, compromising data sampling stability and resulting in artifacts in the final data.

[0004] Therefore, a novel CT detector module and data acquisition method are needed to ensure stable data sampling at increased frequency. Summary of the Invention

[0005] In order to overcome the above-mentioned technical defects, the purpose of this invention is to provide a CT detector module and a data acquisition method, so that the acquired data is output stably and the detector image quality is improved.

[0006] This invention discloses a CT detector module, including an FPGA chip and at least one ADC chip electrically connected to the FPGA chip via a pin group. The ADC chip receives analog outputs from a plurality of pixel arrays. The pin group of the FPGA chip consists of the following pins:

[0007] The MCLK pin sends the main clock signal to the ADC chip.

[0008] The CONV pin sends a toggle signal to the ADC chip to control the sampling frequency of the ADC chip.

[0009] The ADC chip sends the drive clock signal to the FPGA chip through the DCLK pin.

[0010] The Data pin is used by the ADC chip to send data packets to the FPGA chip. These data packets include:

[0011] The header, set by the FPGA chip, contains start information and most significant bit information;

[0012] The data contains control information.

[0013] When the FPGA chip detects that the information in the packet header has changed to the highest bit information, it records the drive clock signal received by the DCLK pin at this time as the start time, and receives data packets from the start time as the starting point and the hold time in the drive clock signal as the end point until the data packet turns low.

[0014] Preferably, the starting information is 0 and the highest bit information is 1;

[0015] When the FPGA chip sends a toggle signal via the CONV pin, the ADC chip resets its internal sampling circuit.

[0016] Preferably, the FPGA chip has a preset channel bit depth for each sampling channel;

[0017] When the FPGA chip acquires data packets during the sampling period from the start time to the hold time, it increments the number of bits by 1. When the accumulated number of bits reaches the channel bit number, it outputs parallelized data and valid signals to the downstream module connected to the FPGA chip.

[0018] After the parallel data of each sampling channel of the CT detector with the CT detector module has been collected, wait for the data packet to change from a tri-state to a low level to cut off.

[0019] Preferably, the FPGA chip also includes a unified clock circuit, which is connected to each ADC chip via the DCLK pin.

[0020] The unified clock circuit receives the DCLK clock domain of each ADC chip, and after passing through the clock domain, unifies all deserialized data and corresponding valid data signals into the unified clock domain.

[0021] This invention also discloses a data acquisition method for a CT detector module, comprising the following steps:

[0022] Configure a CT detector module, including an FPGA chip and at least one ADC chip electrically connected to the FPGA chip through a pin group. The ADC chip receives analog output with several pixel arrays.

[0023] Configure the pins of the FPGA chip. The pin group of the FPGA chip consists of the following pins:

[0024] The MCLK pin sends the main clock signal to the ADC chip.

[0025] The CONV pin sends a toggle signal to the ADC chip to control the sampling frequency of the ADC chip.

[0026] The ADC chip sends the drive clock signal to the FPGA chip through the DCLK pin.

[0027] The Data pin is used by the ADC chip to send data packets to the FPGA chip. These data packets include:

[0028] The header, set by the FPGA chip, contains start information and most significant bit information;

[0029] The data contains control information.

[0030] When the FPGA chip detects that the information in the packet header has changed to the highest bit information, it records the drive clock signal received by the DCLK pin at this time as the start time, and receives data packets from the start time as the starting point and the hold time in the drive clock signal as the end point until the data packet turns low.

[0031] Preferably, the starting information is 0 and the highest bit information is 1;

[0032] When the FPGA chip sends a toggle signal via the CONV pin, the ADC chip resets its internal sampling circuit.

[0033] Preferably, the FPGA chip has a preset channel bit depth for each sampling channel;

[0034] When the FPGA chip acquires data packets during the sampling period from the start time to the hold time, it increments the number of bits by 1. When the accumulated number of bits reaches the channel bit number, it outputs parallelized data and valid signals to the downstream module connected to the FPGA chip.

[0035] After the parallel data of each sampling channel of the CT detector with the CT detector module has been collected, wait for the data packet to change from a tri-state to a low level to cut off.

[0036] Preferably, the FPGA chip also includes a unified clock circuit, which is connected to each ADC chip via the DCLK pin.

[0037] The unified clock circuit receives the DCLK clock domain of each ADC chip, and after passing through the clock domain, unifies all deserialized data and corresponding valid data signals into the unified clock domain.

[0038] Compared with existing technologies, the above technical solution has the following advantages:

[0039] 1. The DVLD pin of the FPGA chip has been removed, freeing up more redundant resources on the FPGA chip;

[0040] 2. Increase sampling rate and reduce cost;

[0041] 3. Multiple CT detector modules are synchronized during data acquisition, and the data acquisition process is stable. Attached Figure Description

[0042] Figure 1 This is a schematic diagram of the CT detector module in a preferred embodiment of the present invention;

[0043] Figure 2 This is a schematic diagram illustrating the data acquisition relationship between the flip signal and the data packet in a preferred embodiment of the present invention;

[0044] Figure 3 A schematic diagram of the unified clock circuit in accordance with a preferred embodiment of the present invention. Detailed Implementation

[0045] The advantages of the present invention will be further illustrated below with reference to the accompanying drawings and specific embodiments.

[0046] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this disclosure. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this disclosure as detailed in the appended claims.

[0047] The terminology used in this disclosure is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. The singular forms “a,” “the,” and “the” as used in this disclosure and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any and all possible combinations of one or more of the associated listed items.

[0048] It should be understood that although the terms first, second, third, etc., may be used in this disclosure to describe various information, such information should not be limited to these terms. These terms are used only to distinguish information of the same type from one another. For example, without departing from the scope of this disclosure, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the word "if" as used herein may be interpreted as "when," "when," or "in response to determination."

[0049] In the description of this invention, it should be understood that the terms "longitudinal", "lateral", "up", "down", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0050] In the description of this invention, unless otherwise specified and limited, it should be noted that the terms "installation", "connection" and "linking" should be interpreted broadly. For example, they can refer to mechanical or electrical connections, or internal connections between two components. They can be direct connections or indirect connections through an intermediate medium. Those skilled in the art can understand the specific meaning of the above terms according to the specific circumstances.

[0051] In the following description, suffixes such as "module," "part," or "unit" used to denote elements are used only for the convenience of the description of the invention and have no specific meaning in themselves. Therefore, "module" and "part" can be used interchangeably.

[0052] See Figure 1 To synchronize the data sampling time of the ADC chip within each CT detector module, in this embodiment, the CT detector module includes an FPGA chip and an ADC chip. The FPGA chip has multiple pins integrated into a pin group (which can be physically integrated or independent in actual applications). Each FPGA chip can be connected to multiple ADC chips, and each ADC chip is connected to the FPGA chip through a pin group. On the other side of the ADC chip are connected analog outputs of several pixel arrays, which are converted into digital signals by the ADC chip. This pixel array is the X-ray acquisition module, and the data is ultimately sent to the FPGA chip for further processing by subsequent modules. In this invention, the pin group of the FPGA chip consists of the following pins:

[0053] The -MCLK pin transmits signals from the FPGA chip to the ADC chip, sending the master clock signal, which is the current time information stored in the FPGA chip, to the ADC chip.

[0054] -CONV pin, the signal transmission direction is from FPGA chip to ADC chip. The FPGA chip sends a toggle signal to the ADC chip to control the sampling frequency of the ADC chip. That is, when the FPGA chip sends a toggle signal through the CONV pin, the ADC chip converts all the channels of the pixel array connected to it into digital data and outputs them serially to the FPGA chip.

[0055] The -DCLK pin transmits signals from the ADC chip to the FPGA chip. It sends a drive clock signal from the ADC chip to the FPGA chip, which is the clock signal used to drive the ADC chip to output data.

[0056] The -Data pin transmits signals from the ADC chip to the FPGA chip. The main data sent from the ADC chip to the FPGA chip, i.e., the data packet, specifically includes a header and data. The data contains control information. The header is generally used to store the address and checksum, but in this embodiment, the data in the header is set by the FPGA chip (i.e., the FPGA chip can be pre-set to only accept data packets storing a specified type of data). This makes the header include start information and the most significant bit information, which represent the type change of the data packet (analogous to a level signal). In existing technology, once the toggle signal is sent to the ADC chip, subsequent received data packets and drive clock signals will not be clock synchronized. (See also...) Figure 2 However, after setting the start information and the most significant bit information, the FPGA chip's data acquisition does not rely on the toggle signal. Instead, it takes the received most significant bit information as the standard. That is, when the FPGA chip detects that the information in the packet header changes from the start information to the most significant bit information, it will start receiving the drive clock signal received by the DCLK pin as the start time. The data packet is received only during the period from the determined start time to the hold time, starting from the start time and ending at the hold time within the drive clock signal, until the signal of the data packet changes from the tri-state to the low level.

[0057] With the above configuration, even if the drive clock signal and data packet output to the FPGA chip by the DCLK and Data pins are at different times, the FPGA chip will no longer use its own transmitted toggle signal as the sampling start point. Instead, it will use the most significant bit information in the packet header as the sampling start point (even if it wastes some time, it is acceptable), ensuring that the setup time and hold time of the sampled data are always the same. Furthermore, it can be understood that the FPGA chip can establish the start time not based on the most significant bit information, but rather on any number between the start information and the most significant bit information.

[0058] On the other hand, compared with existing technologies, the FPGA chip no longer needs to set up a DVLD pin (i.e., the data validity signal output by the data packet originally accompanying the Data pin). In this embodiment, whether the data is valid can be determined simultaneously by the start information and the most significant bit information in the packet header. That is, if the start information and the most significant bit information are the same as the preset ones, then the data packet should be valid. In other words, in this way, the pins of the FPGA chip are freed up (the number of freed pins is the same as the number of ADC chips). For the FPGA chip, the freed pins can be used to connect more ADC chips.

[0059] In a preferred embodiment, the start information is defined as 0, and the most significant bit information is defined as 1. When the FPGA chip detects a change from 0 to 1 on the signal line of the Data pin, it can determine that the data for this toggle signal has begun to be output. Data can then be continuously acquired using the DCLK pin. Furthermore, when the FPGA chip sends a toggle signal via the CONV pin, the ADC chip will reset its internal sampling circuit. That is, the ADC chip's data sampling action is still triggered by the toggle signal, but the FPGA chip's data sampling action is no longer automatically triggered after the toggle signal is sent; instead, it is triggered by setting the most significant bit information in the packet header to 1. The clock for any data sampling action is synchronized.

[0060] Furthermore, the FPGA chip has a preset number of bits per sampling channel, which corresponds to the preset number of connected ADC chips. When the FPGA chip acquires data packets during the sampling period from the start time to the hold time, it increments the preset number of bits by 1 for each set of data packets sampled within a sampling period. When the number of bits accumulates to the channel number of bits, it indicates that the data of all pixel arrays of an ADC chip connected to the FPGA chip has been received. The FPGA chip then outputs parallelized data and valid signals to the subsequent modules. When the parallelized data of each sampling channel of the CT detector with the CT detector module has been acquired (i.e., all ADC chips have sent all data packets to the FPGA chip), the sampling of this switching signal is completed after the data packet signal changes from a tri-state (i.e., still in a state of high-low level transition) to a low level.

[0061] See Figure 3 Furthermore, the FPGA chip also includes a unified clock circuit, which is connected to each ADC chip via the DCLK pin. The unified clock circuit receives the DCLK clock domain of each ADC chip, and after passing through the clock domain, unifies all deserialized data and corresponding valid data signals into the unified clock domain, so that the clock domains of all ADC chips are the same.

[0062] This invention also discloses a data acquisition method for a CT detector module, comprising the following steps: configuring a CT detector module, including an FPGA chip and at least one ADC chip electrically connected to the FPGA chip via a pin group, wherein the ADC chip receives analog outputs of several pixel arrays; configuring the pins of the FPGA chip, wherein the pin group of the FPGA chip consists of the following pins: MCLK pin, for sending a master clock signal to the ADC chip; CONV pin, for sending a toggle signal to the ADC chip to control the sampling frequency of the ADC chip; DCLK pin, for which the ADC chip sends a drive clock signal to the FPGA chip; and Data pin, for which the ADC chip sends a data packet to the FPGA chip, wherein the data packet includes: a packet header, set by the FPGA chip, having start information and most significant bit information; and data, storing control information; when the FPGA chip detects that the information in the packet header has changed to the most significant bit information, it records the drive clock signal received by the DCLK pin at this time as the start time, and receives the data packet from the start time as the starting point and the hold time in the drive clock signal as the end point until the data packet turns low.

[0063] Preferably, the initial information is 0 and the highest bit information is 1; when the FPGA chip sends a toggle signal through the CONV pin, the ADC chip resets its internal sampling circuit.

[0064] Preferably, the FPGA chip has a preset number of bits for each sampling channel; when the FPGA chip collects data packets during the sampling period from the start time to the hold time, the number of bits is incremented by 1; when the accumulated number of bits reaches the number of channel bits, parallelized data and valid signals are output to the downstream module connected to the FPGA chip; after the parallelized data of each sampling channel of the CT detector with the CT detector module has been collected, the data packets are waited for to change from a tri-state to a low level to cut off.

[0065] Preferably, the FPGA chip also includes a unified clock circuit, which is connected to each ADC chip via the DCLK pin. The unified clock circuit receives the DCLK clock domain of each ADC chip, and after passing through the clock domain, unifies all deserialized data and corresponding valid data signals into the unified clock domain.

[0066] It should be noted that the embodiments of the present invention have better implementability and are not intended to limit the present invention in any way. Any person skilled in the art may use the above-disclosed technical content to change or modify it into equivalent effective embodiments. However, any modifications or equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention shall still fall within the scope of the technical solution of the present invention.

Claims

1. A CT detector module, comprising an FPGA chip and at least one ADC chip electrically connected to the FPGA chip via a pin group, the ADC chip receiving analog output from a plurality of pixel arrays, the pixel arrays being a X-ray acquisition module, characterized in that, The pin group of the FPGA chip consists of the following pins: The MCLK pin sends a master clock signal to the ADC chip, and the master clock signal is the current time information stored in the FPGA chip; The CONV pin sends a toggle signal to the ADC chip to control the sampling frequency of the ADC chip. When the FPGA chip sends the toggle signal through the CONV pin, the ADC chip converts all the channels of the pixel array connected to it into digital data and outputs them serially to the FPGA chip. When the FPGA chip sends the toggle signal through the CONV pin, the ADC chip resets its internal sampling circuit. The ADC chip sends a drive clock signal to the FPGA chip via the DCLK pin. The drive clock signal is the clock signal used to drive the ADC chip to output data. The ADC chip sends data packets to the FPGA chip via the Data pin, wherein the data packets include: The header, set by the FPGA chip, contains start information and most significant bit information; The data contains control information. When the FPGA chip detects that the information in the packet header has changed to the most significant bit, it records the drive clock signal received by the DCLK pin at this time as the start time. Starting from the start time, it receives data packets until the data packets turn low. This ensures that even if the drive clock signal and data packets output by the DCLK pin and the Data pin to the FPGA chip are not at the same time, the FPGA chip will no longer use its own toggle signal as the sampling start point, but will use the most significant bit in the packet header as the sampling start point. This ensures that the setup time and hold time of the sampled data are always the same. At the same time, the FPGA chip no longer needs to set the DVLD pin of the data packet output valid signal that originally accompanied the Data pin. The number of pins released is the same as the number of ADC chips. The released pins are used to connect more ADC chips.

2. The CT detector module as described in claim 1, characterized in that, The starting information is 0, and the highest bit information is 1.

3. The CT detector module as described in claim 2, characterized in that, The FPGA chip has a preset channel bit depth for each sampling channel; When the FPGA chip acquires data packets during the sampling period from the start time to the hold time, it increments the number of bits by 1. When the accumulated number of bits reaches the channel bit number, it outputs parallelized data and valid signals to the subsequent module connected to the FPGA chip. After the parallel data of each sampling channel of the CT detector with the CT detector module has been collected, wait for the data packet to change from a tri-state to a low level to cut off.

4. The CT detector module as described in claim 3, characterized in that, The FPGA chip also includes a unified clock circuit, which is connected to each ADC chip via the DCLK pin. The unified clock circuit receives the DCLK clock domain of each ADC chip, and after passing through the clock domain, unifies all deserialized data and corresponding valid data signals into the unified clock domain.

5. A data acquisition method for a CT detector module, characterized in that, Includes the following steps: A CT detector module is configured, including an FPGA chip and at least one ADC chip electrically connected to the FPGA chip through a pin group. The ADC chip receives an analog output of a plurality of pixel arrays, which are X-ray acquisition modules. Configure the pins of the FPGA chip, wherein the pin group of the FPGA chip consists of the following pins: The MCLK pin sends a master clock signal to the ADC chip, and the master clock signal is the current time information stored in the FPGA chip; The CONV pin sends a toggle signal to the ADC chip to control the sampling frequency of the ADC chip. When the FPGA chip sends the toggle signal through the CONV pin, the ADC chip converts all the channels of the pixel array connected to it into digital data and outputs them serially to the FPGA chip. When the FPGA chip sends the toggle signal through the CONV pin, the ADC chip resets its internal sampling circuit. The ADC chip sends a drive clock signal to the FPGA chip via the DCLK pin. The drive clock signal is the clock signal used to drive the ADC chip to output data. The ADC chip sends data packets to the FPGA chip via the Data pin, wherein the data packets include: The header, set by the FPGA chip, contains start information and most significant bit information; The data contains control information. When the FPGA chip detects that the information in the packet header has changed to the most significant bit, it records the drive clock signal received by the DCLK pin at this time as the start time. Starting from the start time, it receives data packets until the data packets turn low. This ensures that even if the drive clock signal and data packets output by the DCLK pin and the Data pin to the FPGA chip are not at the same time, the FPGA chip will no longer use its own toggle signal as the sampling start point, but will use the most significant bit in the packet header as the sampling start point. This ensures that the setup time and hold time of the sampled data are always the same. At the same time, the FPGA chip no longer needs to set the DVLD pin of the data packet output valid signal that originally accompanied the Data pin. The number of pins released is the same as the number of ADC chips. The released pins are used to connect more ADC chips.

6. The data acquisition method as described in claim 5, characterized in that, The starting information is 0, and the highest bit information is 1.

7. The data acquisition method as described in claim 6, characterized in that, The FPGA chip has a preset channel bit depth for each sampling channel; When the FPGA chip acquires data packets during the sampling period from the start time to the hold time, it increments the number of bits by 1. When the accumulated number of bits reaches the channel bit number, it outputs parallelized data and valid signals to the subsequent module connected to the FPGA chip. After the parallel data of each sampling channel of the CT detector with the CT detector module has been collected, wait for the data packet to change from a tri-state to a low level to cut off.

8. The data acquisition method as described in claim 7, characterized in that, The FPGA chip also includes a unified clock circuit, which is connected to each ADC chip via the DCLK pin. The unified clock circuit receives the DCLK clock domain of each ADC chip, and after passing through the clock domain, unifies all deserialized data and corresponding valid data signals into the unified clock domain.

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