Array substrate, manufacturing method thereof, and display device

Abstract

The present disclosure provides an array substrate, a manufacturing method thereof, and a display device. The array substrate includes: a substrate structure; an active layer on the substrate structure; a patterned first insulating layer on a side of the active layer away from the substrate structure, the first insulating layer having a first through hole exposing a part of the active layer; a first conductive layer in the first through hole and in contact with the active layer; and a first connecting member on a side of the first insulating layer away from the substrate structure, the first connecting member being in contact with the first conductive layer, the first connecting member covering a first part of the first conductive layer and not covering a second part of the first conductive layer. The present disclosure can reduce the possibility of the active layer having missing parts, thereby improving the performance of the array substrate and the display device formed therefrom.

Description

Technical Field

[0001] The present disclosure relates to the field of display technologies, and particularly to an array substrate, a manufacturing method thereof, and a display device. Background Art

[0002] Currently, OLED (Organic Light-Emitting Diode) technology is becoming increasingly mature. In some OLED display panels, the array substrate can adopt a 5-mask (which can be referred to as 5Mask) process. During the manufacturing process of the array substrate, it is necessary to manufacture TFT (Thin Film Transistor) transistors. Summary of the Invention

[0003] A technical problem solved by the present disclosure is that in the related art, during the process of forming the TFT of the array substrate, in the overlapping region between the source or drain and the active layer, since the active layer is etched twice, this causes a missing part in the active layer, reducing the performance of the display device.

[0004] According to one aspect of the present disclosure, an array substrate is provided, including: a substrate structure; an active layer on the substrate structure; a patterned first insulating layer on a side of the active layer away from the substrate structure, the first insulating layer having a first through hole exposing a part of the active layer; a first conductive layer in the first through hole and in contact with the active layer; and a first connecting member on a side of the first insulating layer away from the substrate structure, the first connecting member being in contact with the first conductive layer, the first connecting member covering a first part of the first conductive layer and not covering a second part of the first conductive layer.

[0005] In some embodiments, the first insulating layer further has a second through hole exposing another part of the active layer; the array substrate further includes: a second conductive layer in the second through hole; a second connecting member electrically connected to the second conductive layer; and a gate located on a side of the first insulating layer away from the active layer; wherein the second connecting member and the gate are in the same layer, and both the first connecting member and the second connecting member are isolated from the gate.

[0006] In some embodiments, the substrate structure includes: a substrate substrate; a light-shielding layer and a third conductive layer on the substrate substrate, a positive projection of the light-shielding layer on the substrate substrate at least partially overlaps with a positive projection of the active layer on the substrate substrate, wherein the third conductive layer covers the light-shielding layer, or the light-shielding layer covers the third conductive layer; and a buffer layer between the third conductive layer and the active layer.

[0007] In some embodiments, the orthographic projection of the first conductive layer on the substrate substrate at least partially overlaps with the orthographic projection of the light-shielding layer on the substrate substrate.

[0008] In some embodiments, the second through hole also exposes a part of the buffer layer; the second conductive layer includes: a third part on the surface of the active layer and a fourth part on the surface of the buffer layer.

[0009] In some embodiments, the materials of the first conductive layer, the second conductive layer, and the third conductive layer all include transparent conductive materials.

[0010] In some embodiments, the thickness of the third conductive layer is greater than the thickness of the second conductive layer, and the thickness of the second conductive layer is equal to the thickness of the first conductive layer.

[0011] In some embodiments, the thickness of the first conductive layer is greater than the thickness of the active layer.

[0012] In some embodiments, the area of the overlapping portion of the first connecting member and the first conductive layer is smaller than the area of the overlapping portion of the second connecting member and the second conductive layer.

[0013] In some embodiments, the first insulating layer includes a gate insulating layer under the gate; the active layer includes: a first conductive region electrically connected to the first connecting member, a second conductive region electrically connected to the second connecting member, and a channel region between the first conductive region and the second conductive region, and the channel region is flush with the edge of the gate insulating layer.

[0014] In some embodiments, the width of the overlapping portion of the first connecting member and the first conductive layer in the direction from the first connecting member to the gate is smaller than the distance between the edge of the first conductive layer and the channel region.

[0015] In some embodiments, the area of the first conductor layer is greater than the area of the overlapping portion of the first connecting member and the first conductive layer.

[0016] In some embodiments, the area of the first conductor layer is smaller than the area of the channel region.

[0017] In some embodiments, the width of the overlapping portion of the first conductive layer and the active layer in the direction from the first connecting member to the gate is smaller than the width of the overlapping portion of the second conductive layer and the active layer in the direction from the first connecting member to the gate.

[0018] In some embodiments, the distance between the first conductive layer and the gate is greater than the width of the overlapping portion of the first connecting member and the first conductive layer in the direction from the first connecting member to the gate, and the width of the overlapping portion of the first connecting member and the first conductive layer in the direction from the first connecting member to the gate is greater than the width of the second portion of the first conductive layer in the direction from the first connecting member to the gate.

[0019] In some embodiments, the array substrate further includes: a second insulating layer covering the first connecting member, the second connecting member, and the gate; a planarization layer on a side of the second insulating layer away from the substrate structure; a first electrode layer and a pixel defining layer on a side of the planarization layer away from the substrate structure, the first electrode layer being electrically connected to the second connecting member, the pixel defining layer having a first opening exposing at least a portion of the first electrode layer; a light emitting layer at least located in the first opening; and a second electrode layer electrically connected to the light emitting layer.

[0020] In some embodiments, the width of the overlapping portion between the orthographic projection of the second conductive layer on the substrate substrate and the orthographic projection of the third conductive layer on the substrate substrate in the direction from the first connecting member to the gate is less than the width of the overlapping portion between the orthographic projection of the second conductive layer on the substrate substrate and the orthographic projection of the first electrode layer on the substrate substrate in the direction from the first connecting member to the gate.

[0021] In some embodiments, the width of the overlapping portion between the orthographic projection of the second conductive layer on the substrate substrate and the orthographic projection of the third conductive layer on the substrate substrate in the direction from the first connecting member to the gate is less than the width of the overlapping portion between the orthographic projection of the third conductive layer on the substrate substrate and the orthographic projection of the first electrode layer on the substrate substrate in the direction from the first connecting member to the gate.

[0022] According to another aspect of the present disclosure, an array substrate is provided, including: a substrate structure; and thin film transistors on the substrate structure, the thin film transistors including: an active layer on the substrate structure; a patterned first insulating layer on a side of the active layer away from the substrate structure, the first insulating layer having a first through hole exposing a part of the active layer; a first conductive layer in the first through hole and in contact with the active layer; and a first connection member, a second connection member, and a gate on a side of the first insulating layer away from the substrate structure, wherein the first connection member is in contact with the first conductive layer, the first connection member, the second connection member, and the gate are in the same layer and isolated from each other, and the gate is located between the first connection member and the second connection member; wherein the active layer includes: a first conductorized region electrically connected to the first connection member, a second conductorized region electrically connected to the second connection member, and a channel region between the first conductorized region and the second conductorized region, the channel region being under the gate; the first conductive layer includes a first portion away from the gate and a second portion close to the gate, the first portion is completely covered by the first connection member, the second portion is not covered by the first connection member, and a positive projection of the first conductive layer on the substrate structure is located inside a positive projection of the active layer on the substrate structure.

[0023] In some embodiments, a width of the second portion in a direction from the first connection member to the gate is less than a width of the first portion in the direction from the first connection member to the gate.

[0024] In some embodiments, a width of the second portion in a direction from the first connection member to the gate is less than a width of the channel region in the direction from the first connection member to the gate.

[0025] In some embodiments, a thickness of the second portion is less than a thickness of the first portion.

[0026] In some embodiments, a width of the first portion is 2 to 5 times a width of the second portion.

[0027] In some embodiments, the active layer further includes a semiconductor region located on a side of the first conductorized region away from the channel region; wherein a width of the second portion in a direction from the first connection member to the gate is less than a width of the semiconductor region in the direction from the first connection member to the gate.

[0028] According to another aspect of the present disclosure, a display device is provided, including: the array substrate as described above.

[0029] According to another aspect of the present disclosure, a method for manufacturing an array substrate is provided, including: forming an active layer on a substrate structure; forming a patterned first insulating layer on a side of the active layer away from the substrate structure, the first insulating layer having a first through hole exposing a part of the active layer; performing a first conductivity treatment on the exposed part of the active layer; forming a first conductive layer in the first through hole in contact with the active layer; forming a connection material layer on a side of the first insulating layer away from the substrate structure by a deposition process; patterning the connection material layer by using a patterned mask layer to form a first connection member, the first connection member being in contact with the first conductive layer, the first connection member covering a first part of the first conductive layer and not covering a second part of the first conductive layer; etching the first insulating layer by using the mask layer through a self-alignment process to enlarge the first through hole, wherein the enlarged first through hole exposes another part of the active layer; and performing a second conductivity treatment on the exposed another part of the active layer.

[0030] The above-mentioned array substrate includes: a substrate structure; an active layer on the substrate structure; a patterned first insulating layer on a side of the active layer away from the substrate structure, the first insulating layer having a first through hole exposing a part of the active layer; a first conductive layer in the first through hole and in contact with the active layer; and a first connection member on a side of the first insulating layer away from the substrate structure, the first connection member being in contact with the first conductive layer, the first connection member covering a first part of the first conductive layer and not covering a second part of the first conductive layer. Since the first conductive layer is formed in the first through hole of the first insulating layer, during the manufacturing process, this first conductive layer can protect a part of the active layer below it to a certain extent, thereby reducing the possibility of missing parts in the active layer, and further improving the performance of the array substrate and the display device formed therefrom.

[0031] Other features and advantages of the present disclosure will become clear from the following detailed description of the exemplary embodiments of the present disclosure with reference to the accompanying drawings. Description of the Drawings

[0032] The drawings forming a part of the specification depict embodiments of the present disclosure and, together with the specification, are used to explain the principles of the present disclosure.

[0033] Referring to the accompanying drawings, the present disclosure can be more clearly understood from the following detailed description, wherein:

[0034] Figure 1 is a cross-sectional schematic view of an array substrate according to an embodiment of the present disclosure;

[0035] Figure 2 is a cross-sectional schematic view of an array substrate according to another embodiment of the present disclosure;

[0036] Figure 3 is a schematic enlarged view of the array substrate at box 201; Figure 1 in;

[0037] Figure 4 is a top view schematically showing a partial structure of an array substrate according to an embodiment of the present disclosure;

[0038] Figure 5 is a flowchart showing a manufacturing method of an array substrate according to an embodiment of the present disclosure;

[0039] Figures 6A to 6I is a cross-sectional schematic view showing the structures at several stages during the manufacturing process of an array substrate according to some embodiments of the present disclosure;

[0040] Figure 7 is a cross-sectional schematic view showing the structure at one stage during the manufacturing process of an array substrate according to another embodiment of the present disclosure;

[0041] Figure 8 is a cross-sectional schematic view showing the structure at one stage during the manufacturing process of an array substrate according to another embodiment of the present disclosure;

[0042] Figures 9A to 9C is a cross-sectional schematic view showing the structures at several stages during the manufacturing process of an array substrate according to some other embodiments of the present disclosure;

[0043] Figures 10A to 10C is a cross-sectional schematic view showing the structures at several stages during the manufacturing process of an array substrate according to some other embodiments of the present disclosure.

[0044] It should be understood that the sizes of the various parts shown in the drawings are not drawn according to actual proportional relationships. In addition, the same or similar reference numerals represent the same or similar components. Detailed Description of Specific Embodiments

[0045] Various exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. The description of the exemplary embodiments is merely illustrative and in no way limits the present disclosure and its application or use. The present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. These embodiments are provided to make the present disclosure thorough and complete, and to fully convey the scope of the present disclosure to those skilled in the art. It should be noted that: unless otherwise specifically stated, the relative arrangements of the components and steps, the compositions of the materials, the numerical expressions and values set forth in these embodiments should be construed as merely exemplary and not as limitations.

[0046] As used in this disclosure, terms such as "first", "second" and the like do not denote any order, quantity or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" mean that the elements before this word cover the elements listed after this word, and do not exclude the possibility of also covering other elements. Terms such as "upper", "lower", "left", "right" are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0047] In this disclosure, when it is described that a specific device is located between a first device and a second device, there may or may not be an intermediate device between the specific device and the first device or the second device. When it is described that a specific device is connected to other devices, the specific device may be directly connected to the other devices without an intermediate device, or may not be directly connected to the other devices and have an intermediate device.

[0048] All terms used in this disclosure (including technical terms or scientific terms) have the same meaning as understood by those of ordinary skill in the art to which this disclosure pertains, unless otherwise specifically defined. It should also be understood that terms defined in general dictionaries should be interpreted as having meanings consistent with their meanings in the context of the relevant art, and should not be interpreted in an idealized or overly formal sense, unless specifically defined as such here.

[0049] Techniques, methods and devices known to those of ordinary skill in the relevant art may not be discussed in detail, but where appropriate, the said techniques, methods and devices should be regarded as part of the specification.

[0050] The inventors of this disclosure have found that in the related art, during the process of forming the TFTs of the array substrate, in the overlapping region between the source or drain and the active layer, since the active layer is etched twice, this causes a missing part in the active layer. This makes the conduction channel in the overlapping region between the source or drain and the active layer very short, which may limit the current flowing ability, easily cause poor contact, and affect the performance of the display product.

[0051] In view of this, embodiments of this disclosure provide an array substrate to reduce the possibility of a missing part in the active layer.

[0052] Figure 1 It is a cross-sectional schematic diagram showing an array substrate according to an embodiment of this disclosure.

[0053] As Figure 1 shown, the array substrate includes a substrate structure 110.

[0054] As Figure 1As shown, the array substrate further includes an active layer 120 on the substrate structure 110. For example, the material of the active layer includes semiconductor materials such as IGZO (Indium Gallium Zinc Oxide).

[0055] As Figure 1 shown, the array substrate further includes a patterned first insulating layer 130 on the side of the active layer 120 away from the substrate structure. The first insulating layer 130 has a first through hole 141 exposing a part of the active layer 120. The first insulating layer 130 covers the active layer 120. For example, the material of the first insulating layer includes inorganic insulating materials (such as silicon dioxide or silicon nitride, etc.).

[0056] As Figure 1 shown, the array substrate further includes a first conductive layer 151 in the first through hole 141 and in contact with the active layer 120. In some embodiments, the material of the first conductive layer includes a metal material. For example, the material of the first conductive layer includes a transparent conductive material. For example, the transparent conductive material includes: ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide), etc. Here, using a transparent conductive material for the first conductive layer can improve the light transmittance of the array substrate.

[0057] As Figure 1 shown, the array substrate further includes a first connecting member 161 on the side of the first insulating layer 130 away from the substrate structure 110. The first connecting member 161 is in contact with the first conductive layer 151. The material of the first connecting member 161 includes a metal material such as copper. For example, the first connecting member can be a source electrode or a drain electrode. The first connecting member 161 covers a first part of the first conductive layer 151 and does not cover a second part of the first conductive layer 151 (which will be described in combination with Figure 3 the following).

[0058] So far, an array substrate according to some embodiments of the present disclosure has been provided. The array substrate includes: a substrate structure; an active layer on the substrate structure; a patterned first insulating layer on the side of the active layer away from the substrate structure, the first insulating layer having a first through hole exposing a part of the active layer; a first conductive layer in the first through hole and in contact with the active layer; and a first connecting member on the side of the first insulating layer away from the substrate structure, the first connecting member being in contact with the first conductive layer, the first connecting member covering a first part of the first conductive layer and not covering a second part of the first conductive layer. In this embodiment, since the first conductive layer is formed in the first through hole of the first insulating layer, during the manufacturing process, the first conductive layer can protect a part of the active layer below it to a certain extent, thereby reducing the possibility of the active layer having missing parts, and further improving the performance of the array substrate and the display device formed therefrom.

[0059] As shown Figure 1 The first insulating layer 130 further has a second through hole 142 exposing another part of the active layer 120.

[0060] In some embodiments, as shown in FIG. 1, the array substrate further includes a second conductive layer 152 in the second through hole 142. The second conductive layer 152 fills the second through hole 142. For example, the material of the second conductive layer includes a transparent conductive material. For example, the transparent conductive material includes: ITO or IZO, etc. Here, the second conductive layer is made of a transparent conductive material, which can improve the light transmittance of the array substrate.

[0061] Similar to the previous first conductive layer, the second conductive layer can protect a part of the active layer below it, thereby reducing the possibility of the active layer having missing parts, and further improving the performance of the array substrate and the display device formed therefrom.

[0062] In some embodiments, as shown Figure 1 The width of the overlapping portion of the first conductive layer 151 and the active layer 120 in the direction from the first connecting member to the gate is smaller than the width of the overlapping portion of the second conductive layer 152 and the active layer 120 in the direction from the first connecting member to the gate. In other words, the second conductive layer 152 is made relatively large. For example, the area or width of the second conductive layer 152 (i.e., the lateral dimension shown in the cross-sectional view) is larger than the area or width of the first conductive layer 151. In this way, the second conductive layer can also act as one electrode plate of a capacitor. This is beneficial to form a transparent capacitance structure and improve the capacitance and conductivity.

[0063] In some embodiments, as shown Figure 1 The array substrate further includes a second connecting member 162 electrically connected to the second conductive layer 152. The second connecting member 162 is in contact with the second conductive layer 152. The material of the second connecting member 162 includes a metal material such as copper. The second connecting member can be a source or a drain. For example, the first connecting member 161 is a source and the second connecting member 162 is a drain. Or, for example, the first connecting member 161 is a drain and the second connecting member 162 is a source.

[0064] In some embodiments, as shown Figure 1 The array substrate further includes a gate 163 on the side of the first insulating layer 130 away from the active layer 120. The material of the gate 163 includes a metal material such as copper.

[0065] As shown Figure 1 The second connecting member 162 and the gate 163 are in the same layer. The first connecting member 161 and the gate 163 are also in the same layer. The first connecting member 161 and the second connecting member 162 are both isolated from the gate 163. The gate 163 is located between the first connecting member 161 and the second connecting member 162.

[0066] It should be noted that "the same layer" refers to a layer structure formed by using the same film-forming process to form a film layer for forming a specific pattern, and then patterning the film layer by using the same mask through a single lithography process. For example, two structural layers in the same layer may be located on the same structural layer, or may be located on different structural layers. Two structural layers in the same layer may be at different heights or have different thicknesses.

[0067] In some embodiments, as Figure 1 shown, the substrate structure 110 includes a substrate substrate 111. The substrate substrate includes a rigid substrate or a flexible substrate, etc. For example, the substrate substrate may include a glass substrate, etc.

[0068] As Figure 1 shown, the substrate structure 110 further includes a light-shielding layer 112 on the substrate substrate 111. The orthographic projection of the light-shielding layer 112 on the substrate substrate 111 at least partially overlaps with the orthographic projection of the active layer 120 on the substrate substrate 111. For example, the material of the light-shielding layer includes metal materials such as aluminum, molybdenum, or copper.

[0069] As Figure 1 shown, the substrate structure 110 further includes a third conductive layer 113 covering the light-shielding layer 112. The third conductive layer may extend from the light-shielding layer 112 to the substrate substrate 111. The third conductive layer 113 may serve as another electrode plate of the capacitor.

[0070] It should be noted that in some other embodiments, the positions of the light-shielding layer 112 and the third conductive layer 113 may be interchanged. For example, the third conductive layer 113 may be located on the substrate substrate 111, and the light-shielding layer 112 is located on the side of the third conductive layer away from the substrate substrate, that is, the light-shielding layer covers the third conductive layer.

[0071] In some embodiments, the material of the third conductive layer 113 includes a transparent conductive material. For example, the transparent conductive material includes: ITO or IZO, etc. Here, using a transparent conductive material for the third conductive layer can improve the light transmittance of the array substrate.

[0072] As Figure 1 shown, the substrate structure 110 further includes a buffer layer 114 between the third conductive layer 113 and the active layer 120. For example, the buffer layer may include an inorganic insulating material such as silicon dioxide. The buffer layer 114 covers the third conductive layer 113 and the substrate substrate 111, etc.

[0073] In some embodiments, as Figure 1As shown, the substrate 110 may further include a trace 115. The first connector 161 may be electrically connected to the trace 115 through a third through hole (as a conductive through hole) 143 that passes through the first insulating layer 130 and the buffer layer 114. The trace 115 may be in the same layer as the light-shielding layer 112. For example, the material of the trace 115 is the same as that of the light-shielding layer 112. The trace 115 is isolated from the light-shielding layer 112.

[0074] In some embodiments, the orthographic projection of the first conductive layer 151 on the substrate 111 at least partially overlaps with the orthographic projection of the light-shielding layer 112 on the substrate 111. The light-shielding layer can function as a light shield.

[0075] In some embodiments, the thickness of the third conductive layer 113 is greater than the thickness of the second conductive layer 152. The thickness of the second conductive layer 152 is equal to the thickness of the first conductive layer 151. This makes the second conductive layer relatively thin, thereby further improving the light transmittance of the array substrate. Additionally, the relatively thick thickness of the third conductive layer 113 can reduce the resistance.

[0076] For example, the thickness of the third conductive layer 113 is from 3000 angstroms to 5000 angstroms. For example, the thickness of the second conductive layer 152 (or the first conductive layer 151) is from 500 angstroms to 1000 angstroms.

[0077] In some embodiments, the thickness of the first conductive layer 151 is greater than the thickness of the active layer 120. For example, the thickness of the active layer 120 is from 300 angstroms to 500 angstroms.

[0078] In some embodiments, the area of the overlapping portion of the first connector 161 and the first conductive layer 151 is smaller than the area of the overlapping portion of the second connector 162 and the second conductive layer 151. Here, the area of the overlapping portion of the second connector and the second conductive layer is relatively large, which can reduce the contact resistance.

[0079] In some embodiments, as Figure 1 shown, the first insulating layer 130 includes a gate insulating layer 131 located below the gate 163.

[0080] As Figure 1As shown, the active layer 120 includes: a first conductive region 121 electrically connected to the first connection member 161, a second conductive region 122 electrically connected to the second connection member 162, and a channel region 123 between the first conductive region 121 and the second conductive region 122. The channel region 123 is flush with the edge of the gate insulating layer 131. Here, the first conductive layer 151 contacts the first conductive region 121, and the second conductive layer 152 contacts the second conductive region 122. By partially conducting the regions on both sides of the channel region of the active layer, the contact resistance between the first conductive layer and the active layer and the contact resistance between the second conductive layer and the active layer can be reduced, facilitating current transmission and improving the performance of the array substrate and the display device formed therefrom.

[0081] Figure 3 is schematically shown Figure 1 an enlarged schematic view of the array substrate in FIG. 201 at the box 201.

[0082] As Figure 3 shown, the first conductive layer 151 includes a first portion 1511 away from the gate 163 and a second portion 1512 close to the gate 163. The first portion 1511 is completely covered by the first connection member 161, and the second portion 1512 is not covered by the first connection member 161.

[0083] In some embodiments, as Figure 3 shown, the overlapping portion of the first connection member 161 and the first conductive layer 151 has a width d1 in the direction from the first connection member 161 to the gate 163 that is less than the distance d4 between the edge of the first conductive layer 151 and the channel region 123.

[0084] In some embodiments, the area of the first conductive layer 151 is larger than the area of the overlapping portion of the first connection member 161 and the first conductive layer 151 (i.e., the portion corresponding to the width d1). This is beneficial for the full contact between the first connection member and the first conductive layer and prevents problems of poor contact.

[0085] In some embodiments, the area of the first conductive layer 151 is smaller than the area of the channel region 123. A relatively large area of the channel region is beneficial for improving the performance of the thin film transistor.

[0086] It should be noted that the "area" described in this disclosure refers to the area of the surface of the structural layer parallel to the plane of the substrate. For example, this area can be the area of the upper surface of the structural layer. For example, the area of the upper surface of the first conductive layer 151 is the area of the first conductive layer 151; the area of the upper surface of the channel region 123 is the area of the channel region 123, and so on.

[0087] In some embodiments, the distance d3 between the first conductive layer 151 and the gate 163 is greater than the width d1 of the overlapping portion of the first connecting member 161 and the first conductive layer 151 in the direction from the first connecting member to the gate, and the width d1 of the overlapping portion of the first connecting member 161 and the first conductive layer 151 in the direction from the first connecting member to the gate is greater than the width d2 of the second portion (i.e., the portion not covered by the first connecting member 161) 1512 of the first conductive layer 151 in the direction from the first connecting member to the gate. That is, d3>d1>d2. Such a dimension design is beneficial to improving the performance of the thin film transistor, thereby improving the performance of the array substrate and the display device formed therefrom.

[0088] In addition, as Figure 3 shown, there is a gap 301 between the first conductive layer 151 and the gate insulating layer 131.

[0089] Returning to Figure 1 , in some embodiments, the array substrate further includes a second insulating layer 171 covering the first connecting member 161, the second connecting member 162, and the gate 163. For example, the material of the second insulating layer 171 includes at least one of silicon dioxide, silicon nitride, etc.

[0090] As Figure 1 shown, the array substrate further includes a planarization layer 172 on the side of the second insulating layer 171 away from the substrate structure 110. For example, the material of the planarization layer includes organic insulating materials such as resins.

[0091] As Figure 1 shown, the array substrate further includes a first electrode layer 181 and a pixel defining layer 174 on the side of the planarization layer 172 away from the substrate structure 110. The first electrode layer 181 is electrically connected to the second connecting member 162 (e.g., through a conductive via). The pixel defining layer 174 has a first opening 1742 exposing at least a part of the first electrode layer 181. For example, the first electrode layer is an anode layer. For example, the material of the first electrode layer 181 includes metals such as copper, silver, aluminum, or aluminum alloy, or transparent conductive materials such as ITO or IZO.

[0092] As Figure 1 shown, the array substrate further includes a light emitting layer 180 at least located in the first opening 1742. The light emitting layer may include: a light emitting layer for emitting red light, a light emitting layer for emitting green light, or a light emitting layer for emitting blue light.

[0093] As Figure 1As shown, the array substrate further includes a second electrode layer 182 electrically connected to the light-emitting layer 180. The second electrode layer 182 covers the pixel defining layer 174 and the light-emitting layer 180. The second electrode layer may be a cathode layer. For example, the material of the second electrode layer 182 includes metals such as copper, silver, aluminum or aluminum alloy, or transparent conductive materials such as ITO or IZO.

[0094] In some embodiments, the array substrate may further include other functional layers between the first electrode layer 181 and the second electrode layer 182, such as, for example, an electron transport layer, a hole transport layer, an electron blocking layer or a hole blocking layer, and so on. Therefore, the scope of the present disclosure is not limited thereto.

[0095] In some embodiments, as Figure 1 shown, the width of the overlapping portion between the orthographic projection of the second conductive layer 152 on the substrate substrate 111 and the orthographic projection of the third conductive layer 113 on the substrate substrate 111 in the direction from the first connection member to the gate is smaller than the width of the overlapping portion between the orthographic projection of the second conductive layer 152 on the substrate substrate 111 and the orthographic projection of the first electrode layer 181 on the substrate substrate 111 in the direction from the first connection member to the gate. This is beneficial to improving the light transmittance of the array substrate.

[0096] In some embodiments, as Figure 1 shown, the width of the overlapping portion between the orthographic projection of the second conductive layer 152 on the substrate substrate 111 and the orthographic projection of the third conductive layer 113 on the substrate substrate 111 in the direction from the first connection member to the gate is smaller than the width of the overlapping portion between the orthographic projection of the third conductive layer 113 on the substrate substrate 111 and the orthographic projection of the first electrode layer 181 on the substrate substrate 111 in the direction from the first connection member to the gate. This is beneficial to improving the light transmittance of the array substrate.

[0097] The present disclosure provides an array substrate. As Figure 1 shown, the array substrate includes: a substrate structure 110 and thin-film transistors on the substrate structure 110.

[0098] The thin film transistor includes an active layer 120 on a substrate structure 110. The thin film transistor further includes a patterned first insulating layer 130 on a side of the active layer 120 away from the substrate structure. The first insulating layer 130 has a first through hole 141 exposing a part of the active layer 120. The thin film transistor further includes a first conductive layer 151 in the first through hole 141 and in contact with the active layer 120. The thin film transistor further includes a first connecting member 161, a second connecting member 162, and a gate 163 on a side of the first insulating layer 130 away from the substrate structure. The first connecting member 161 is in contact with the first conductive layer 151. The first connecting member 161, the second connecting member 162, and the gate 163 are in the same layer and isolated from each other. The gate 163 is located between the first connecting member 161 and the second connecting member 162.

[0099] As Figure 1 and Figure 3 shown, the active layer 120 includes: a first conductive region 121 electrically connected to the first connecting member 161, a second conductive region 122 electrically connected to the second connecting member 162, and a channel region 123 between the first conductive region 121 and the second conductive region 122. The channel region 123 is under the gate 163.

[0100] As Figure 3 shown, the first conductive layer 151 includes a first portion 1511 away from the gate 163 and a second portion 1512 close to the gate 163. The first portion 1511 is completely covered by the first connecting member 161, and the second portion 1512 is not covered by the first connecting member 161. The orthographic projection of the first conductive layer 151 on the substrate structure 110 is located inside the orthographic projection of the active layer 120 on the substrate structure 110.

[0101] In the above embodiment, since the first conductive layer is formed in the first through hole of the first insulating layer, during the manufacturing process, the first conductive layer can protect a part of the active layer below it to a certain extent, thereby reducing the possibility of missing parts in the active layer, and further improving the performance of the array substrate and the display device formed therefrom.

[0102] In some embodiments, as Figure 3 shown, the width d2 of the second portion 1512 in the direction from the first connecting member to the gate is less than the width d1 of the first portion 1511 in the direction from the first connecting member to the gate. Here, the width of the first portion 1511 is equal to the width of the overlapping portion of the first connecting member 161 and the first conductive layer 151, both being d1.

[0103] For example, the width d1 of the first portion 1511 is 2 to 5 times the width d2 of the second portion 1512.

[0104] In some embodiments, asFigure 3 As shown, the width d2 of the second portion 1512 in the direction from the first connection member to the gate is smaller than the width d5 of the channel region 123 in the direction from the first connection member to the gate.

[0105] In some embodiments, as Figure 3 shown, the thickness H2 of the second portion 1512 is smaller than the thickness H1 of the first portion 1511.

[0106] In some embodiments, as Figure 1 and Figure 3 shown, the active layer 120 may further include a semiconductor region (which may be referred to as the first semiconductor region) 124. The semiconductor region 124 is located on a side of the first conductive region 121 away from the channel region 123. The width d2 of the second portion 1512 in the direction from the first connection member to the gate is smaller than the width d6 of the semiconductor region 124 in the direction from the first connection member to the gate.

[0107] In some other embodiments, the active layer may further include another semiconductor region, which may be referred to as the second semiconductor region (not shown in the figure). The second semiconductor region is located on a side of the second conductive region 122 away from the channel region 123.

[0108] Figure 2 is a schematic cross-sectional view showing an array substrate according to another embodiment of the present disclosure.

[0109] The Figure 2 structure of the shown array substrate is similar to the Figure 1 structure of the shown array substrate. Different from the Figure 1 structure of the shown array substrate: Figure 2 In the shown array substrate, the second via 142 also exposes a part of the buffer layer 114, and the second conductive layer 152 includes: a third portion 1521 on the surface of the active layer 120 and a fourth portion 1522 on the surface of the buffer layer 114. For example, in the Figure 2 shown structure, the lateral dimension of the active layer 120 is smaller than the Figure 1 lateral dimension of the active layer in Figure 1 , and the area of the third portion of the second conductive layer 152 is smaller than the Figure 2 area of the overlapping portion of the second conductive layer and the active layer in . Therefore, in the Figure 2 shown array substrate, the area of the overlapping portion of the second conductive layer and the active layer is reduced, which can improve the light transmittance of the array substrate.

[0110] Figure 4 is a top view schematically showing a partial structure of an array substrate according to an embodiment of the present disclosure.

[0111] For the convenience of illustration,Figure 4 The first conductive region 121, the first conductive layer 151, and the first connection member 161 of the active layer of the array substrate are shown. As Figure 4 shown, due to the presence of the first conductive layer 151, there is no missing part in the first conductive region 121. Therefore, current can flow through the first conductive region 121 relatively uniformly from the first connection member, providing the signal transmission ability of the array substrate.

[0112] In some embodiments of the present disclosure, a display device is further provided, including the array substrate as described above. For example, Figure 1 or Figure 2 the array substrate shown. For example, the display device can be: a display panel, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, or any product or component with a display function.

[0113] Figure 5 is a flowchart showing a manufacturing method of an array substrate according to an embodiment of the present disclosure. As Figure 5 shown, the manufacturing method includes steps S502 to S508. Figures 6A to 6I is a cross-sectional schematic diagram showing the structures of several stages in the manufacturing process of an array substrate according to some embodiments of the present disclosure. Figures 9A to 9C is a cross-sectional schematic diagram showing the structures of several stages in the manufacturing process of an array substrate according to other embodiments of the present disclosure. The manufacturing process of the array substrate according to some embodiments of the present disclosure will be described in detail below in combination with Figure 5 , Figures 6A to 6I and Figures 9A to 9C .

[0114] As Figure 5 shown, in step S502, an active layer is formed on the substrate structure.

[0115] For example, as Figure 6A shown, an active layer 120 is formed on the substrate structure 110, for example, by a deposition process. The specific structure of the substrate structure 110 has been described in detail above and will not be elaborated here.

[0116] Returning to Figure 5 , in step S504, a patterned first insulating layer is formed on the side of the active layer away from the substrate structure. The first insulating layer has a first through hole exposing a part of the active layer.

[0117] For example, reference can be made to Figures 6A to 6F for a detailed description of the process of forming the patterned first insulating layer.

[0118] As Figure 6A shown, a first insulating layer 130 is formed on the side of the active layer 120 away from the substrate structure 110, for example, by a deposition process.

[0119] Next, as shown in Figure 6B , a first mask layer 610 is formed on the side of the first insulating layer 130 away from the substrate structure 110. For example, the material of the first mask layer is a positive photoresist.

[0120] Next, as shown in Figure 6B and Figure 6C , for example, through exposure and development techniques, the first mask layer 610 is patterned using the patterned first mask plate 621 to form a patterned first mask layer 610, such that the patterned first mask layer has a second opening 6102 exposing a part of the first insulating layer 130.

[0121] Next, as shown in Figure 6D and Figure 6E , using the patterned first mask layer 610, the part of the first insulating layer 130 exposed by the second opening 6102 is removed through an etching process (such as dry etching) to form a first through hole 141, thereby forming a patterned first insulating layer 130. The first through hole 141 exposes a part of the active layer 120.

[0122] Returning to Figure 5 , in step S506, a first conductorization process is performed on the exposed part of the active layer.

[0123] For example, as shown in Figure 6E , a first conductorization process can be performed on the exposed part of the active layer 120. For example, a dry etching process and He gas (helium gas) can be used to perform the first conductorization process.

[0124] Next, as shown in Figure 6F , the first mask layer 610 is removed.

[0125] Returning to Figure 5 , in step S508, a first conductive layer in contact with the active layer is formed in the first through hole.

[0126] For example, reference can be made to Figures 6G to 6I for a detailed description of the process of forming the first conductive layer.

[0127] For example, as shown in Figure 6G , a first conductive layer 151 is formed on the side of the patterned first insulating layer 130 away from the substrate structure 110 and in the first through hole 141 through a deposition process. For example, the material of the first conductive layer 151 includes a transparent conductive material.

[0128] Next, as shown in Figure 6HAs shown, a second mask layer 612 is formed on the side of the first conductive layer 151 away from the substrate structure 110, and the second mask layer 612 is exposed and developed using the first mask plate 621 described above, thereby forming Figure 6H the structure of the second mask layer 612 shown. For example, the material of the second mask layer is a negative photoresist.

[0129] Next, as Figure 6H shown, the first conductive layer 151 is etched to remove the portion of the first conductive layer 151 that is not covered by the second mask layer 612, and the portion of the first conductive layer 151 that is covered by the second mask layer 612 is retained, thereby forming as Figure 6I the structure shown.

[0130] Next, as Figure 6I shown, the second mask layer 612 is removed.

[0131] At this point, a patterned first conductive layer 151 is formed, and the first conductive layer 151 can protect the active layer 120 below it from being etched as much as possible.

[0132] Returning to Figure 5 , in step S510, a connection material layer is formed on the side of the first insulating layer away from the substrate structure by a deposition process.

[0133] For example, as Figure 9A shown, a connection material layer 160 is formed on the side of the first insulating layer 130 away from the substrate structure 110 by a deposition process. The material of the connection material layer 160 includes metals such as copper.

[0134] Returning to Figure 5 , in step S512, the connection material layer is patterned using a patterned mask layer to form a first connection member that contacts the first conductive layer, and the first connection member covers a first portion of the first conductive layer and does not cover a second portion of the first conductive layer.

[0135] For example, as Figure 9A shown, a patterned mask layer (which can be called a third mask layer) 637 is formed on the side of the connection material layer away from the substrate structure 110. For example, the material of the third mask layer is a photoresist.

[0136] Next, as Figure 9B shown, for example, by a wet etching process, the connection material layer 160 is patterned using the third mask layer 637 to form a first connection member 161. In addition, a second connection member 162 and a gate 163 etc. may also be formed in this process. During this wet etching process, the etching solution may etch a portion of the connection material layer below the edge of the third mask layer, so the formed first connection member is recessed inward.

[0137] In this way, the first connecting member is formed.

[0138] Returning to Figure 5 , in step S514, using a mask layer, the first insulating layer is etched by a self-alignment process to enlarge the first through hole, wherein another part of the active layer is exposed by the enlarged first through hole.

[0139] For example, as Figure 9C shown, using the patterned mask layer (i.e., the third mask layer) 637, the first insulating layer 130 is etched by a self-alignment process to enlarge the first through hole 141, wherein another part of the active layer 120 is exposed by the enlarged first through hole 141. For example, the etching is dry etching. Here, the entire surface of the first insulating layer is etched to form a gap between the first conductive layer and the gate insulating layer, i.e., the gap 301 described above.

[0140] Returning to Figure 5 , in step S516, a second conductorization process is performed on the other part of the active layer that is exposed.

[0141] For example, as Figure 9C shown, a second conductorization process is performed on the other part of the active layer 120 that is exposed. For example, a dry etching process can be used and He gas (helium gas) can be used to perform the second conductorization process. During this process, since there is the first conductive layer 151, the part of the active layer directly under the first conductive layer 151 can be protected from being etched.

[0142] Next, the third mask layer 637 is removed.

[0143] So far, a manufacturing method of an array substrate according to some embodiments of the present disclosure is provided. The manufacturing method includes: forming an active layer on a substrate structure; forming a patterned first insulating layer on a side of the active layer away from the substrate structure, the first insulating layer having a first through hole exposing a part of the active layer; performing a first conductorization process on the part of the active layer that is exposed; forming a first conductive layer in contact with the active layer in the first through hole; forming a connection material layer on a side of the first insulating layer away from the substrate structure by a deposition process; patterning the connection material layer using a patterned mask layer to form a first connecting member, the first connecting member being in contact with the first conductive layer, the first connecting member covering a first part of the first conductive layer and not covering a second part of the first conductive layer; using a mask layer to etch the first insulating layer by a self-alignment process to enlarge the first through hole, wherein another part of the active layer is exposed by the enlarged first through hole; and performing a second conductorization process on the other part of the active layer that is exposed. This manufacturing method can reduce the possibility of missing parts in the active layer, thereby improving the performance of the array substrate and the display device formed therefrom.

[0144] Furthermore, in the above manufacturing process, a negative photoresist is used for the second mask layer, so that the first mask plate described above can be used for exposure and development, without the need to fabricate an additional mask plate, thereby reducing the process complexity.

[0145] Figure 7 is a cross-sectional schematic view showing the structure at a stage in the manufacturing process of an array substrate according to another embodiment of the present disclosure. The Figure 7 shows a cross-sectional schematic view of the structure at a stage in the process of forming a first conductive layer according to some other embodiments.

[0146] For example, as Figure 7 shown, after forming the Figure 6E shown structure, through a deposition process, a first conductive layer 151 is formed on the patterned first mask layer 610 and in the first through hole 141 of the first insulating layer 130.

[0147] Next, through a lift-off process, the first mask layer 610 and the portion of the first conductive layer 151 on the first mask layer 610 are removed, and the portion of the first conductive layer 151 in the first through hole 141 is retained, thereby forming the Figure 6I shown structure.

[0148] In this embodiment, the lift-off process is adopted, without the need to add an additional mask process, further reducing the process complexity.

[0149] Figure 8 is a cross-sectional schematic view showing the structure at a stage in the manufacturing process of an array substrate according to another embodiment of the present disclosure. The Figure 8 shows a cross-sectional schematic view of the structure at a stage in the process of forming a first conductive layer according to some other embodiments.

[0150] For example, as Figure 8 shown, after forming the Figure 6F shown structure, using a patterned second mask plate 630 and adopting an evaporation process, a first conductive layer 151 is formed in the first through hole 141 of the first insulating layer 130, that is, the Figure 6I shown structure is formed. As Figure 8 shown, the second mask plate 630 has a through hole (which can be called the fourth through hole), and the opening is aligned with the first through hole 141. For example, the second mask plate is an FMM mask plate (Fine Metal Mask). In addition, Figure 8 also shows an evaporation source 635. The material of the evaporation source includes a transparent conductive material (such as ITO or IZO, etc.).

[0151] In this embodiment, the first conductive layer is formed by an evaporation process, which can reduce the process complexity.

[0152] Figures 10A to 10C FIG. is a cross-sectional schematic view showing the structures of several stages in the manufacturing process of an array substrate according to some other embodiments of the present disclosure. The following will be combined with Figures 10A to 10C and Figure 1 to describe in detail the manufacturing process of the array substrate according to some other embodiments of the present disclosure.

[0153] First, as Figure 10A shown, a substrate structure is provided. The step of providing the substrate structure includes the following steps.

[0154] For example, as Figure 10A shown, a light-shielding layer 112 is formed on the substrate 111 through a deposition and patterning process. In addition, a trace 115 is also formed.

[0155] Next, as Figure 10A shown, a third conductive layer 113 covering the light-shielding layer 112 is formed through a deposition and patterning process.

[0156] In some other embodiments, the third conductive layer 113 can also be first formed on the substrate 111 through a deposition and patterning process; then, the light-shielding layer 112 is formed on the third conductive layer 113 through a deposition and patterning process.

[0157] Next, as Figure 10A shown, a buffer layer 114 covering the third conductive layer 113 is formed through a deposition process.

[0158] So far, the substrate structure 110 is formed.

[0159] Next, as Figure 10B shown, the active layer 120, the first insulating layer 130, the first via 141, the first conductive layer 151, and the first connecting member 161 are formed by using the processes described above. Here, the second via 142, the third via 143, the second conductive layer 152, the second connecting member 162, and the gate 163 are also formed.

[0160] It should be noted that the second conductive layer 152 is formed together with the first conductive layer 151 using the same process, and the second connecting member 162 and the gate 163 are formed using the same lithography process as the first connecting member 161. Details are not described herein again.

[0161] It should also be noted that the second via 142 and the third via 143 can be formed simultaneously when the first via 141 is formed. The formation processes of the second via 142 and the third via 143 are similar to that of the first via 141, and details are not described herein again.

[0162] Next, as Figure 10B shown, a second insulating layer 171 covering the first connection member 161, the second connection member 162, and the gate 163 is formed through a deposition process.

[0163] Next, as Figure 10C shown, a planarization layer 172 is formed on a side of the second insulating layer 171 away from the substrate structure 110.

[0164] Next, as Figure 10C shown, a first electrode layer 181 electrically connected to the second connection member 162 is formed on a side of the planarization layer 172 away from the substrate structure 110.

[0165] Next, as Figure 10C shown, a pixel defining layer 174 is formed on a side of the planarization layer 172 away from the substrate structure 110. The pixel defining layer 174 has a first opening 1742 exposing at least a part of the first electrode layer 181.

[0166] Next, as Figure 1 shown, a light emitting layer 180 is formed at least in the first opening 1742.

[0167] Next, as Figure 1 shown, a second electrode layer 182 electrically connected to the light emitting layer 180 is formed through a deposition process.

[0168] So far, a manufacturing method of an array substrate according to some embodiments of the present disclosure has been provided. This manufacturing method can reduce the possibility of a missing part in the active layer, thereby improving the performance of the array substrate and the display device formed therefrom.

[0169] So far, the embodiments of the present disclosure have been described in detail. To avoid obscuring the concept of the present disclosure, some details well known in the art have not been described. Those skilled in the art can fully understand how to implement the technical solutions disclosed herein based on the above description.

[0170] Although some specific embodiments of the present disclosure have been described in detail by way of examples, those skilled in the art should understand that the above examples are only for illustration and not for limiting the scope of the present disclosure. Those skilled in the art should understand that the above embodiments can be modified or some technical features can be equivalently replaced without departing from the scope and spirit of the present disclosure. The scope of the present disclosure is defined by the appended claims.

Claims

1. An array substrate, comprising: A substrate structure; An active layer on the substrate structure; A patterned first insulating layer on a side of the active layer away from the substrate structure, the first insulating layer having a first through hole exposing a part of the active layer; A first conductive layer in the first through hole and in contact with the active layer, a positive projection of the first conductive layer on the substrate structure being located inside a positive projection of the active layer on the substrate structure; And A first connecting member on a side of the first insulating layer away from the substrate structure, the first connecting member being in contact with the first conductive layer, the first connecting member covering a first part of the first conductive layer and not covering a second part of the first conductive layer.

2. The array substrate according to claim 1, wherein: The first insulating layer further has a second through hole exposing another part of the active layer; The array substrate further comprises: A second conductive layer in the second through hole; A second connecting member electrically connected to the second conductive layer; and A gate located on a side of the first insulating layer away from the active layer; Wherein, the second connecting member and the gate are in the same layer, and both the first connecting member and the second connecting member are isolated from the gate.

3. The array substrate according to claim 2, wherein, The substrate structure comprises: A substrate substrate; A light-shielding layer and a third conductive layer on the substrate substrate, a positive projection of the light-shielding layer on the substrate substrate at least partially overlapping a positive projection of the active layer on the substrate substrate, wherein, the third conductive layer covers the light-shielding layer, or the light-shielding layer covers the third conductive layer; and A buffer layer between the third conductive layer and the active layer.

4. The array substrate according to claim 3, wherein, A positive projection of the first conductive layer on the substrate substrate at least partially overlaps a positive projection of the light-shielding layer on the substrate substrate.

5. The array substrate according to claim 3, wherein, The second through hole further exposes a part of the buffer layer; The second conductive layer comprises: a third part on a surface of the active layer and a fourth part on a surface of the buffer layer.

6. The array substrate according to claim 3, wherein Materials of the first conductive layer, the second conductive layer and the third conductive layer all comprise transparent conductive materials.

7. The array substrate according to claim 3, wherein A thickness of the third conductive layer is greater than a thickness of the second conductive layer, and the thickness of the second conductive layer is equal to the thickness of the first conductive layer.

8. The array substrate according to claim 1, wherein, A thickness of the first conductive layer is greater than a thickness of the active layer.

9. The array substrate according to claim 2, wherein An area of an overlapping part of the first connecting member and the first conductive layer is smaller than an area of an overlapping part of the second connecting member and the second conductive layer.

10. The array substrate according to claim 3, wherein: The first insulating layer comprises a gate insulating layer under the gate; The active layer comprises: a first conductorized region electrically connected to the first connecting member, a second conductorized region electrically connected to the second connecting member, and a channel region between the first conductorized region and the second conductorized region, the channel region being flush with an edge of the gate insulating layer.

11. The array substrate according to claim 10, wherein, The width of the overlapping portion of the first connection member and the first conductive layer in the direction from the first connection member to the gate is less than the distance between the edge of the first conductive layer and the channel region.

12. The array substrate according to claim 1, wherein, The area of the first conductive layer is greater than the area of the overlapping portion of the first connection member and the first conductive layer.

13. The array substrate according to claim 10, wherein, The area of the first conductive layer is less than the area of the channel region.

14. The array substrate according to claim 2, wherein The width of the overlapping portion of the first conductive layer and the active layer in the direction from the first connection member to the gate is less than the width of the overlapping portion of the second conductive layer and the active layer in the direction from the first connection member to the gate.

15. The array substrate according to claim 2, wherein The distance between the first conductive layer and the gate is greater than the width of the overlapping portion of the first connection member and the first conductive layer in the direction from the first connection member to the gate, and the width of the overlapping portion of the first connection member and the first conductive layer in the direction from the first connection member to the gate is greater than the width of the second portion of the first conductive layer in the direction from the first connection member to the gate.

16. The array substrate according to claim 3, further comprising: A second insulating layer covering the first connection member, the second connection member, and the gate; A planarization layer on the side of the second insulating layer away from the substrate structure; A first electrode layer and a pixel defining layer on the side of the planarization layer away from the substrate structure, the first electrode layer being electrically connected to the second connection member, and the pixel defining layer having a first opening exposing at least a part of the first electrode layer; A light-emitting layer at least located in the first opening; And A second electrode layer electrically connected to the light-emitting layer.

17. The array substrate according to claim 16, wherein The width of the overlapping portion between the orthographic projection of the second conductive layer on the substrate and the orthographic projection of the third conductive layer on the substrate in the direction from the first connection member to the gate is less than the width of the overlapping portion between the orthographic projection of the second conductive layer on the substrate and the orthographic projection of the first electrode layer on the substrate in the direction from the first connection member to the gate.

18. The array substrate according to claim 16, wherein The width of the overlapping portion between the orthographic projection of the second conductive layer on the substrate and the orthographic projection of the third conductive layer on the substrate in the direction from the first connection member to the gate is less than the width of the overlapping portion between the orthographic projection of the third conductive layer on the substrate and the orthographic projection of the first electrode layer on the substrate in the direction from the first connection member to the gate.

19. An array substrate, comprising: A substrate structure; And A thin film transistor on the substrate structure, the thin film transistor comprising: An active layer on the substrate structure; A patterned first insulating layer on a side of the active layer away from the substrate structure, the first insulating layer having a first through hole exposing a part of the active layer; A first conductive layer in the first through hole and in contact with the active layer; and A first connecting member, a second connecting member, and a gate on a side of the first insulating layer away from the substrate structure, wherein the first connecting member is in contact with the first conductive layer, the first connecting member, the second connecting member, and the gate are in the same layer and isolated from each other, and the gate is located between the first connecting member and the second connecting member; Wherein, the active layer includes: a first conductive region electrically connected to the first connecting member, a second conductive region electrically connected to the second connecting member, and a channel region between the first conductive region and the second conductive region, the channel region being under the gate; The first conductive layer includes a first portion away from the gate and a second portion close to the gate, the first portion is completely covered by the first connecting member, the second portion is not covered by the first connecting member, and a positive projection of the first conductive layer on the substrate structure is located inside a positive projection of the active layer on the substrate structure.

20. The array substrate according to claim 19, wherein, The width of the second portion in a direction from the first connecting member to the gate is smaller than the width of the first portion in a direction from the first connecting member to the gate.

21. The array substrate according to claim 19, wherein, The width of the second portion in a direction from the first connecting member to the gate is smaller than the width of the channel region in a direction from the first connecting member to the gate.

22. The array substrate according to claim 19, wherein, The thickness of the second portion is smaller than the thickness of the first portion.

23. The array substrate according to claim 20, wherein The width of the first portion is 2 to 5 times the width of the second portion.

24. The array substrate according to claim 20, wherein: The active layer further includes a semiconductor region located on a side of the first conductive region away from the channel region; Wherein, the width of the second portion in a direction from the first connecting member to the gate is smaller than the width of the semiconductor region in a direction from the first connecting member to the gate.

25. A display device, comprising: The array substrate according to any one of claims 1 to 24.

26. A manufacturing method of an array substrate, including: Forming an active layer on a substrate structure; Forming a patterned first insulating layer on a side of the active layer away from the substrate structure, the first insulating layer having a first through hole exposing a part of the active layer; Performing a first conductivity treatment on the exposed part of the active layer; After the first conductivity treatment, forming a first conductive layer in the first through hole and in contact with the active layer, a positive projection of the first conductive layer on the substrate structure is located inside a positive projection of the active layer on the substrate structure; Forming a connection material layer on a side of the first insulating layer away from the substrate structure by a deposition process; The connection material layer is patterned using a patterned mask layer to form a first connection member that contacts the first conductive layer, where the first connection member covers a first portion of the first conductive layer and does not cover a second portion of the first conductive layer; Using the mask layer, the first insulating layer is etched through a self-alignment process to enlarge the first through hole, where another portion of the active layer is exposed after the enlargement of the first through hole; and A second conductorization process is performed on the exposed other portion of the active layer.

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