parallel-to-serial conversion circuit

Abstract

The application provides a parallel-serial conversion circuit, comprising an output clock generation circuit and an output circuit, the output clock generation circuit is used for outputting N output signals and N inverted output signals, the output signals and the inverted output signals are inverse signals of each other, the N output signals are sequentially delayed by one clock cycle, the N inverted output signals are sequentially delayed by one clock cycle, N is a natural number greater than 0, the output circuit is connected with the output clock generation circuit, used for receiving N parallel transmission transmission data, the N output signals and the N inverted output signals, sequentially outputting the N transmission data according to the N output signals and the N inverted output signals, so as to convert the N parallel transmission transmission data into N serial transmission transmission data, without a selector, reducing the number of flip-flop flips, thereby reducing power consumption and reducing the occupied area.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of parallel-serial conversion, and particularly relates to a parallel-serial conversion circuit. BACKGROUND

[0002] The traditional parallel-serial conversion circuit structure is usually based on flip-flops and selectors to realize the circuit function. The selectors are used for sampling the input parallel data, and the flip-flops are used as registers to realize the conversion of the data from the parallel input to the serial output by shifting the registers under the triggering of the clock. In the process of parallel-serial conversion, the multi-way selector is always in the sampling state, and the flip-flop flips many times, which results in large power consumption. In addition, the number of selectors is large, which occupies a large area in the integrated circuit.

[0003] Therefore, it is necessary to provide a novel parallel-serial conversion circuit to solve the above problems in the prior art. SUMMARY

[0004] The purpose of the present application is to provide a parallel-serial conversion circuit to reduce power consumption.

[0005] To achieve the above purpose, the parallel-serial conversion circuit comprises:

[0006] an output clock generation circuit, configured to output N output signals and N inverted output signals, wherein the output signals and the inverted output signals are mutually inverse signals, the N output signals are sequentially delayed by one clock period, the N inverted output signals are sequentially delayed by one clock period, and N is a natural number greater than 0; and

[0007] an output circuit, connected with the output clock generation circuit, configured to receive N parallel transmission data, the N output signals and the N inverted output signals, sequentially output the N transmission data according to the N output signals and the N inverted output signals, so as to convert the N parallel transmission data into N serial transmission data.

[0008] The parallel-serial conversion circuit has the beneficial effects that the output clock generation circuit is configured to output N output signals and N inverted output signals, wherein the output signals and the inverted output signals are mutually inverse signals, the N output signals are sequentially delayed by one clock period, the N inverted output signals are sequentially delayed by one clock period, the output circuit is connected with the output clock generation circuit, configured to receive N parallel transmission data, the N output signals and the N inverted output signals, sequentially output the N transmission data according to the N output signals and the N inverted output signals, so as to convert the N parallel transmission data into N serial transmission data. No selector is needed, the number of flip-flop flips is reduced, the power consumption is reduced, and the occupied area is reduced.

[0009] Optionally, the output clock generating circuit comprises N D flip-flops, the N D flip-flops are connected in cascade, a data input terminal of a first stage D flip-flop is connected with a control signal, a data input terminal of a next stage D flip-flop is connected with a non-inverted output terminal of a previous stage D flip-flop, and clock terminals of the N D flip-flops are all connected with a clock signal.

[0010] Optionally, the D flip-flop comprises a logic unit, a gating unit, a first transmission gate, a first inverter and a second inverter, an input terminal of the first inverter is connected with an output terminal of the second inverter, an output terminal of the first transmission gate and a second input terminal of the logic unit, as an inverted output terminal of the D flip-flop, an output terminal of the first inverter is connected with an input terminal of the second inverter, as a non-inverted output terminal of the D flip-flop, a first input terminal of the logic unit is as a data input terminal of the D flip-flop, the logic unit is used for performing or operation and and operation on the control signal and the inverted output signal to output or operation data and and operation data, the gating unit is connected with the logic unit, the gating unit is used for receiving the or operation data, the and operation data, the clock signal and an inverted signal of the clock signal to output a gating signal according to the or operation data, the and operation data, the clock signal and the inverted signal of the clock signal, and an input terminal of the first transmission gate is connected with an output terminal of the logic unit to receive the gating signal.

[0011] Optionally, the logic unit comprises an or gate and an and gate, a first input terminal of the or gate and a first input terminal of the and gate are connected, as a first input terminal of the logic unit, and a second input terminal of the or gate and a second input terminal of the and gate are connected, as a second input terminal of the logic unit.

[0012] Optionally, the gating unit comprises a first PMOS transistor, a second PMOS transistor, a first NMOS transistor and a second NMOS transistor, a source of the first PMOS transistor is connected with a power voltage, a gate of the first PMOS transistor is connected with an output terminal of the or gate, a drain of the first PMOS transistor is connected with a source of the second PMOS transistor, a gate of the second PMOS transistor is connected with the clock signal, a drain of the second PMOS transistor is connected with a drain of the first NMOS transistor, as an output terminal of the gating unit, a gate of the first NMOS transistor is connected with an inverted signal of the clock signal, a source of the first NMOS transistor is connected with a drain of the second NMOS transistor, a gate of the second NMOS transistor is connected with an output terminal of the and gate, and a source of the second NMOS transistor is connected with the ground.

[0013] Optionally, the first transmission gate comprises a third PMOS tube and a third NMOS tube, the drain of the third PMOS tube and the drain of the third NMOS tube are connected as the input end of the first transmission gate, the source of the third PMOS tube and the source of the third NMOS tube are connected as the output end of the first transmission gate, the gate of the third PMOS tube is connected with the inverted clock signal of the clock signal, and the gate of the third NMOS tube is connected with the clock signal.

[0014] Optionally, the output clock generating circuit further comprises N third inverters, and the input ends of the N third inverters are connected with the non-inverted output ends of the N D flip-flops respectively.

[0015] Optionally, the clock frequency of the clock signal is N times of the clock frequency of the control signal, the duty cycle of the clock signal is 1 / 2, and the duty cycle of the control signal is 1 / N.

[0016] Optionally, the output circuit comprises N second transmission gates, the first control ends of the N second transmission gates are connected with the N output signals respectively, the second control ends of the N second transmission gates are connected with the N inverted output signals respectively, the input ends of the N second transmission gates are connected with N transmission data transmitted in parallel respectively, and the output ends of the N second transmission gates output the N transmission data in sequence. The beneficial effects are that the output circuit is formed by the N second transmission gates, only one second transmission gate is turned on at each time, there is no direct current path, and the circuit area and power consumption are reduced.

[0017] Optionally, the second transmission gate comprises a fourth PMOS tube and a fourth NMOS tube, the drain of the fourth PMOS tube and the drain of the fourth NMOS tube are connected as the input end of the second transmission gate, the source of the fourth PMOS tube and the source of the fourth NMOS tube are connected as the output end of the second transmission gate, the gate of the fourth PMOS tube is connected as the second control end of the second transmission gate, and the gate of the fourth NMOS tube is connected as the first control end of the second transmission gate. BRIEF DESCRIPTION OF DRAWINGS

[0018] Figure 1 FIG. 1 is a block diagram of the serial-to-parallel conversion circuit of the present application;

[0019] Figure 2 FIG. 4 is a circuit diagram of the output clock generating circuit in some embodiments of the present application;

[0020] Figure 3 FIG. 6 is a circuit schematic diagram of the D flip-flop in some embodiments of the present application;

[0021] Figure 4 FIG. 8 is a circuit diagram of the output clock generating circuit in some other embodiments of the present application;

[0022] Figure 5 a circuit schematic diagram of an output circuit in some embodiments of the present application;

[0023] Figure 6 a timing diagram of a parallel-serial conversion circuit in some embodiments of the present application. DETAILED DESCRIPTION

[0024] In order to make the objects, technical solutions and advantages of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings of the present application. Obviously, the described embodiments are only some but not all of the embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts should fall into the scope of the present application. Unless otherwise defined, the technical terms or scientific terms used herein should be understood as the common meanings thereof by those of ordinary skill in the art to which the present application belongs. The words such as "comprise" and the like used herein mean that the elements or objects before the words encompass the elements or objects listed after the words and equivalents thereof, and do not exclude other elements or objects.

[0025] In view of the problems in the prior art, embodiments of the present application provide a parallel-serial conversion circuit. Referring to Figure 1 , the parallel-serial conversion circuit 100 comprises an output clock generation circuit 101 and an output circuit 102 connected to each other.

[0026] Referring to Figure 1 , the output clock generation circuit 101 is configured to output N output signals and N inverted output signals, wherein the output signals and the inverted output signals are mutually inverted signals, the N output signals are sequentially delayed by one clock period, the N inverted output signals are sequentially delayed by one clock period, and N is a natural number greater than 0.

[0027] Referring to Figure 1 , the output circuit 102 is configured to receive N parallel transmission data, the N output signals and the N inverted output signals, sequentially output the N transmission data according to the N output signals and the N inverted output signals, so as to convert the N parallel transmission data into N serial transmission data.

[0028] Figure 2 a circuit diagram of an output clock generation circuit in some embodiments of the present application. Referring to Figure 2The output clock generating circuit 101 comprises N D flip-flops 1011, the N D flip-flop stages 1011 are connected in series, the data input end of the first stage D flip-flop 1011 is connected with a control signal Control, the data input end of the next stage D flip-flop 1011 is connected with the non-inverted output end of the previous stage D flip-flop 1011, and the clock end of the N D flip-flops 1011 is connected with a clock signal CLK.

[0029] In some embodiments, the clock frequency of the clock signal is N times of the clock frequency of the control signal, and the duty cycle of the clock signal is 1 / 2, and the duty cycle of the control signal is 1 / N.

[0030] Referring to Figure 1 and 2 The N output signals comprise a first output signal C0, a second output signal C1, a third output signal C2, and an Nth output signal Cn-1 in sequence, the non-inverted output end of the first stage D flip-flop 1011 outputs the first output signal C0, the non-inverted output end of the second stage D flip-flop 1011 outputs the second output signal C1, the non-inverted output end of the third stage D flip-flop 1011 outputs the third output signal C2, and the non-inverted output end of the Nth stage D flip-flop 1011 outputs the Nth output signal Cn-1.

[0031] Referring to Figure 1 and Figure 2 The N inverted output signals comprise a first inverted output signal C0b, a second inverted output signal C1b, a third inverted output signal C2b, and an Nth inverted output signal Cn-1b in sequence, the inverted output end of the first stage D flip-flop 1011 outputs the first inverted output signal C0b, the inverted output end of the second stage D flip-flop 1011 outputs the second inverted output signal C1b, the inverted output end of the third stage D flip-flop 1011 outputs the third inverted output signal C2b, and the inverted output end of the Nth stage D flip-flop 1011 outputs the Nth inverted output signal Cn-1b.

[0032] Figure 3 It is a circuit schematic diagram of the D flip-flop in some embodiments of the present application. Referring to Figure 3The D flip-flop 1011 comprises a logic unit 10111, a gating unit 10112, a first transmission gate 10113, a first inverter 10114 and a second inverter 10115. An input end of the first inverter 10114 is connected with an output end of the second inverter 10115, an output end of the first transmission gate 10113 and a second input end of the logic unit 10111, serving as an inverting output end Qb of the D flip-flop 1011. An output end of the first inverter 10114 is connected with an input end of the second inverter 10115, serving as a non-inverting output end Q of the D flip-flop 1011. A first input end of the logic unit 10112 serves as a data input end D of the D flip-flop 1011. The logic unit 10111 is configured to perform OR operation and AND operation on the control signal and the second output signal, to output OR operation data and AND operation data. The gating unit 10112 is connected with the logic unit 10111. The gating unit 10112 is configured to receive the OR operation data, the AND operation data, the clock signal CLK and an inverting signal CLKB of the clock signal, to output a gating signal Db according to the OR operation data, the AND operation data, the clock signal CLK and the inverting signal CLKB of the clock signal. An input end of the first transmission gate 10113 is connected with an output end of the logic unit 10111, for receiving the gating signal Db.

[0033] With reference to Figure 3 The logic unit 10111 comprises an OR gate 101111 and an AND gate 101112. A first input end of the OR gate 101111 and a first input end of the AND gate 101112 are connected, serving as a first input end of the logic unit 10111. A second input end of the OR gate 101111 and a second input end of the AND gate 101112 are connected, serving as a second input end of the logic unit 10111.

[0034] With reference to Figure 3The gating unit 10112 includes a first PMOS transistor M1, a second PMOS transistor M2, a first NMOS transistor M3 and a second NMOS transistor M4. The source of the first PMOS transistor M1 is connected to a power supply voltage. The gate of the first PMOS transistor M1 is connected to the output of the OR gate 101111. The drain of the first PMOS transistor M1 is connected to the source of the second PMOS transistor M2. The gate of the second PMOS transistor M2 is connected to the clock signal CLK. The drain of the second PMOS transistor M2 is connected to the drain of the first NMOS transistor M3, which is the output of the gating unit 10112. The gate of the first NMOS transistor M1 is connected to the inverted clock signal CLKB. The source of the first NMOS transistor M3 is connected to the drain of the second NMOS transistor M4. The gate of the second NMOS transistor M4 is connected to the output of the AND gate 101112. The source of the second NMOS transistor M4 is connected to ground.

[0035] With reference to Figure 3 The first transmission gate 10113 includes a third PMOS transistor M5 and a third NMOS transistor M6. The drain of the third PMOS transistor M5 and the drain of the third NMOS transistor M6 are connected, which is the input of the first transmission gate 10113. The source of the third PMOS transistor M5 and the source of the third NMOS transistor M6 are connected, which is the output of the first transmission gate 10113. The gate of the third PMOS transistor M5 is connected to the inverted clock signal CLKB. The gate of the third NMOS transistor M6 is connected to the clock signal CLK.

[0036] With reference to Figure 3 When the clock signal CLK is at a low level, the control signal and the inverted output signal are both at a low level, the OR operation data is at a low level, and the first PMOS transistor and the second PMOS transistor are turned on. At this time, the gating signal Db is at a high level.

[0037] With reference to Figure 3 When the clock signal CLK is at a low level, the control signal and the inverted output signal are both at a high level, the AND operation data is at a high level, and the first NMOS transistor and the second NMOS transistor are turned on. At this time, the gating signal Db is at a low level.

[0038] With reference to Figure 3 When the rising edge of the clock signal CLK comes, the gating signal Db is output through the first transmission gate 10113.

[0039] With reference to Figure 4The D flip-flop 1011 only works normally when the current input and the last cycle input are flipped, otherwise the output result is kept unchanged, the flip of the D flip-flop is reduced, and the power consumption of the circuit is reduced.

[0040] Figure 4 The circuit diagram of the output clock generating circuit in some embodiments of the present application is shown in FIG. 10. Referring to FIG. 10, Figure 1 The output clock generating circuit 101 comprises N D flip-flops 1011 and N third inverters 1016, the N D flip-flops 1011 are connected in cascade, the data input end of the first stage D flip-flop 1011 is connected with the control signal Control, the data input end of the next stage D flip-flop 1011 is connected with the non-inverted output end of the last stage D flip-flop 1011, the clock end of the N D flip-flops 1011 is connected with the clock signal CLK, and the input end of the N third inverters is connected with the non-inverted output end of the N D flip-flops respectively.

[0041] Referring to Figure 1 and 4 The N output signals comprise a first output signal C0, a second output signal C1, a third output signal C2, and a Nth output signal Cn-1 in turn, the non-inverted output end of the first stage D flip-flop 1011 outputs the first output signal C0, the non-inverted output end of the second stage D flip-flop 1011 outputs the second output signal C1, the non-inverted output end of the third stage D flip-flop 1011 outputs the third output signal C2, and the non-inverted output end of the Nth stage D flip-flop 1011 outputs the Nth output signal Cn-1.

[0042] Referring to Figure 4 and Figure 5 The N inverted output signals comprise a first inverted output signal C0b, a second inverted output signal C1b, a third inverted output signal C2b, and a Nth inverted output signal Cn-1b in turn, the input end of the first third inverter 1016 is connected with the non-inverted output end of the first stage D flip-flop 1011 to output the first inverted output signal C0b, the input end of the second third inverter 1016 is connected with the non-inverted output end of the second stage D flip-flop 1011 to output the second inverted output signal C1b, the input end of the third third inverter 1016 is connected with the non-inverted output end of the third stage D flip-flop 1011 to output the third inverted output signal C2b, and the input end of the Nth third inverter 1016 is connected with the non-inverted output end of the Nth stage D flip-flop 1011 to output the Nth inverted output signal Cn-1b.

[0043] Figure 5 The circuit diagram of the output circuit in some embodiments of the present application is shown in FIG. 11. Referring to FIG. 11,Figure 5 The output circuit 102 comprises N second transmission gates 1021, the first control ends of the N second transmission gates 1021 are connected with N output signals respectively, the second control ends of the N second transmission gates 1021 are connected with N inverted output signals respectively, the input ends of the N second transmission gates 1021 are connected with N transmission data transmitted in parallel respectively, and the output ends of the N second transmission gates 1021 output N transmission data in turn. The output circuit 102 is formed by the N second transmission gates 1021, only one second transmission gate 1021 is turned on each time, and there is no direct current path, thereby reducing the circuit area and power consumption.

[0044] With reference to Figure 2 The second transmission gate 1021 comprises a fourth PMOS tube M7 and a fourth NMOS tube M8, the drain of the fourth PMOS tube M7 and the drain of the fourth NMOS tube M8 are connected, serving as the input end of the second transmission gate 1021, the source of the fourth PMOS tube M7 and the source of the fourth NMOS tube M8 are connected, serving as the output end of the second transmission gate 1021, the gate of the fourth PMOS tube M7 serves as the second control end of the second transmission gate 1021, and the gate of the fourth NMOS tube M8 serves as the first control end of the second transmission gate 1021.

[0045] With reference to Figure 5 and Figure 4 The gate of the fourth NMOS tube M8 in the first second transmission gate 1021 is connected with the non-inverted output end of the first stage D flip-flop 1011, and the gate of the fourth PMOS tube M7 in the first second transmission gate 1021 is connected with the inverted output end of the first stage D flip-flop 1011; the gate of the fourth NMOS tube M8 in the second second transmission gate 1021 is connected with the non-inverted output end of the second stage D flip-flop 1011, and the gate of the fourth PMOS tube M7 in the second second transmission gate 1021 is connected with the inverted output end of the second stage D flip-flop 1011; the gate of the fourth NMOS tube M8 in the third second transmission gate 1021 is connected with the non-inverted output end of the third stage D flip-flop 1011, and the gate of the fourth PMOS tube M7 in the third second transmission gate 1021 is connected with the inverted output end of the third stage D flip-flop 1011; and the gate of the fourth NMOS tube M8 in the Nth second transmission gate 1021 is connected with the non-inverted output end of the Nth stage D flip-flop 1011, and the gate of the fourth PMOS tube M7 in the Nth second transmission gate 1021 is connected with the inverted output end of the Nth stage D flip-flop 1011.

[0046] With reference to Figure 5 and Figure 1The gate of the fourth NMOS transistor M8 in the first second transmission gate 1021 is connected with the non-inverted output end of the first D flip-flop 1011, and the gate of the fourth PMOS transistor M7 in the first second transmission gate 1021 is connected with the output end of the first third inverter 1016; the gate of the fourth NMOS transistor M8 in the second second transmission gate 1021 is connected with the non-inverted output end of the second D flip-flop 1011, and the gate of the fourth PMOS transistor M7 in the second second transmission gate 1021 is connected with the output end of the second third inverter 1016; the gate of the fourth NMOS transistor M8 in the third second transmission gate 1021 is connected with the non-inverted output end of the third D flip-flop 1011, and the gate of the fourth PMOS transistor M7 in the third second transmission gate 1021 is connected with the output end of the third third inverter 1016; by analogy, the gate of the fourth NMOS transistor M8 in the Nth second transmission gate 1021 is connected with the non-inverted output end of the Nth D flip-flop 1011, and the gate of the fourth PMOS transistor M7 in the Nth second transmission gate 1021 is connected with the output end of the Nth third inverter 1016.

[0047] Referring to Figure 5 and Figure 5 , the N parallel transmission data includes first transmission data D0, second transmission data D1, third transmission data D2, and by analogy to the Nth transmission data Dn-1, the input end of the first transmission gate is connected with the first transmission data D0, the input end of the second transmission gate is connected with the first transmission data D1, the input end of the third transmission gate is connected with the first transmission data D2, and by analogy, the input end of the Nth transmission gate is connected with the first transmission data Dn-1.

[0048] Referring to Figure 6 , the output end of the first second transmission gate 1021, the output end of the second second transmission gate 1021, the output end of the third transmission gate, and by analogy to the output end of the Nth second transmission gate 1021 output N transmission data in turn.

[0049] Figure 6 is the timing diagram of the parallel-serial conversion circuit in some embodiments of the present application. Referring to ​When the rising edge of the clock signal CLK comes, the output clock generating circuit sequentially generates the first output signal C0, the second output signal C1, the third output signal C2, to the Nth output signal Cn-1 and the first inverted output signal C0b, the second inverted output signal C1b, the third inverted output signal C2b, to the Nth inverted output signal Cn-1b, and the second output signal C1 is delayed by one period of the clock period CLK relative to the first output signal C0, the third output signal C2 is delayed by one period of the clock period CLK relative to the second output signal C1, and so on, the Nth output signal Cn-1 is delayed by one period of the clock period CLK relative to the N-1th output signal Cn-2, when the first output signal C0, the second output signal C1, the third output signal C2, to the Nth output signal Cn-1 are high, the output circuit sequentially outputs D<0> to D <n-1>, and parallel-to-serial conversion is completed after N cycles of the clock period.

[0050] While the embodiments of the application have been illustrated and described in detail, it will be readily apparent to those skilled in the art that various modifications and changes can be made therein without departing from the spirit and scope of the application as defined by the appended claims. Moreover, the foregoing description is not intended to limit the scope of the application to the particular embodiments described.

Claims

1. A parallel-to-serial conversion circuit, characterized by comprising: The application relates to a clock signal output circuit and a data output circuit. The clock signal output circuit comprises an output clock generation circuit and an output circuit. The output clock generation circuit is used for outputting N output signals and N inverted output signals, wherein the output signals and the inverted output signals are inverse signals of each other, the N output signals are sequentially delayed by one clock period, the N inverted output signals are sequentially delayed by one clock period, and N is a natural number greater than 0; the output clock generation circuit comprises N D flip-flops, the N D flip-flops are connected in cascade, the data input end of the first-stage D flip-flop is connected with a control signal, the data input end of the next-stage D flip-flop is connected with the non-inverted output end of the previous-stage D flip-flop, and the clock end of the N D flip-flops is connected with a clock signal. The output circuit is connected with the output clock generation circuit, is used for receiving N parallel transmission data, the N output signals and the N inverted output signals, sequentially outputs the N transmission data according to the N output signals and the N inverted output signals, and converts the N parallel transmission data into N serial transmission data; the output circuit comprises N second transmission gates, the first control end of the N second transmission gates is respectively connected with the N output signals, the second control end of the N second transmission gates is respectively connected with the N inverted output signals, the input end of the N second transmission gates is respectively connected with the N parallel transmission data, and the output end of the N second transmission gates sequentially outputs the N transmission data.

2. The parallel-to-serial conversion circuit of claim 1, wherein, The D flip-flop comprises a logic unit, a gating unit, a first transmission gate, a first inverter and a second inverter, the input end of the first inverter is connected with the output end of the second inverter, the output end of the first transmission gate and the second input end of the logic unit, and serves as an inverted output end of the D flip-flop, the output end of the first inverter is connected with the input end of the second inverter, and serves as a non-inverted output end of the D flip-flop, the first input end of the logic unit serves as a data input end of the D flip-flop, the logic unit is used for performing or operation and and operation on the control signal and the inverted output signal to output or operation data and and operation data, the gating unit is connected with the logic unit, the gating unit is used for receiving the or operation data, the and operation data, the clock signal and an inverted clock signal of the clock signal to output a gating signal according to the or operation data, the and operation data, the clock signal and the inverted clock signal, and the input end of the first transmission gate is connected with the output end of the logic unit to receive the gating signal.

3. The parallel-to-serial conversion circuit of claim 2, wherein, The logic unit comprises an or gate and an and gate, the first input end of the or gate and the first input end of the and gate are connected, and serve as first input ends of the logic unit, and the second input end of the or gate and the second input end of the and gate are connected, and serve as second input ends of the logic unit.

4. The parallel-to-serial conversion circuit of claim 3, wherein, The gating unit comprises a first PMOS tube, a second PMOS tube, a first NMOS tube and a second NMOS tube, the source of the first PMOS tube is connected to a power voltage, the gate of the first PMOS tube is connected to the output of the OR gate, the drain of the first PMOS tube is connected to the source of the second PMOS tube, the gate of the second PMOS tube is connected to the clock signal, the drain of the second PMOS tube is connected to the drain of the first NMOS tube as the output of the gating unit, the gate of the first NMOS tube is connected to the inverse signal of the clock signal, the source of the first NMOS tube is connected to the drain of the second NMOS tube, the gate of the second NMOS tube is connected to the output of the AND gate, and the source of the second NMOS tube is connected to the ground.

5. The parallel-to-serial conversion circuit of claim 3, wherein, The first transmission gate comprises a third PMOS tube and a third NMOS tube, the drain of the third PMOS tube and the drain of the third NMOS tube are connected as the input of the first transmission gate, the source of the third PMOS tube and the source of the third NMOS tube are connected as the output of the first transmission gate, the gate of the third PMOS tube is connected to the inverse signal of the clock signal, and the gate of the third NMOS tube is connected to the clock signal.

6. The parallel-to-serial conversion circuit of claim 1, wherein, The output clock generation circuit further comprises N third inverters, and the input of each of the N third inverters is connected to the positive output of the corresponding one of the N D flip-flops.

7. The parallel-to-serial conversion circuit according to any one of claims 1 to 6, characterized by The clock frequency of the clock signal is N times of the clock frequency of the control signal, and the duty cycle of the clock signal is 1 / 2, and the duty cycle of the control signal is 1 / N.

8. The parallel-to-serial conversion circuit of claim 1, wherein, The second transmission gate comprises a fourth PMOS tube and a fourth NMOS tube, the drain of the fourth PMOS tube and the drain of the fourth NMOS tube are connected as the input of the second transmission gate, the source of the fourth PMOS tube and the source of the fourth NMOS tube are connected as the output of the second transmission gate, the gate of the fourth PMOS tube is the second control end of the second transmission gate, and the gate of the fourth NMOS tube is the first control end of the second transmission gate.

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