Polar code SCL decoder with low hardware resource consumption and decoding method thereof

Abstract

The present invention provides a polar code SCL decoder with low hardware resource consumption and a decoding method thereof, relating to the field of channel coding technology. The present invention proposes a polar code SCL decoder with low hardware resource consumption. The SCL decoder utilizes only an SC decoder designed according to a serial pipeline structure, wherein the SC decoder includes an LLR calculation module, a partial sum calculation module, a path metric value calculation module, a path metric value sorting and deletion module, and a pointer module. This structure enables the SCL decoder of the present application to perform serial pipeline decoding between paths and parallel calculation within paths during the decoding process. The SCL decoder of the present invention reduces resource consumption during the implementation of the receiver decoding portion, thereby reducing communication costs.

Description

Technical Field

[0001] The present invention relates to a channel coding technology, and in particular to a polar code SCL decoder with low hardware resource consumption and a decoding method thereof. Background Art

[0002] Polar codes are the first coding scheme rigorously proven to theoretically reach the Shannon limit. Their encoding process is essentially fixed and highly regular, while their decoding can be implemented through an iterative structure. This allows for efficient gain without excessive resource consumption, facilitating engineering implementation. Polar codes have garnered widespread attention and rapid development in both academia and industry. Because polar code encoding is essentially fixed, researchers are focusing on decoding algorithms with excellent performance and low implementation complexity.

[0003] Currently, the most commonly used polar code decoding algorithms in engineering applications are Successive Cancellation (SC) and Successive Cancellation List (SCL). However, the traditional SCL decoding algorithm requires the simultaneous use of L universal SC decoders, resulting in significant waiting time between modules during the decoding process. This undoubtedly reduces hardware resource reuse and even results in a waste of hardware resources. The high resource consumption during decoder implementation limits the broader application of polar codes.

[0004] In summary, while SCL parallel decoding technology is a commonly used polar code scheme in industry, its high hardware resource consumption and low hardware resource reuse limit its broader application. Therefore, designing a low-hardware resource-consuming polar code SCL decoder is crucial for reducing hardware resource consumption during polar code decoding, lowering the complexity of polar code encoding and decoding, and controlling communication costs. Summary of the Invention

[0005] (1) Technical problems solved

[0006] In response to the shortcomings of the existing technology, the present invention provides a polar code SCL decoder and a decoding method thereof with low hardware resource consumption, which solves the problems of large hardware resource consumption and low hardware resource reuse in the existing traditional SCL decoding technology.

[0007] (2) Technical solution

[0008] To achieve the above objectives, the present invention is implemented through the following technical solutions:

[0009] In the first aspect, the present invention first proposes a polar code SCL decoder with low hardware resource consumption.

[0010] The polar code SCL decoder uses only one SC decoder designed according to a serial pipeline structure. The SC decoder includes an LLR calculation module, a partial sum calculation module, a path metric calculation module, a path metric sorting and pruning module, and a pointer module. During decoding, the SC decoder performs serial pipeline decoding between paths and parallel calculation within a path.

[0011] Preferably, the path metric value sorting and deletion module includes multiple 4-choose-2 basic circuits.

[0012] Preferably, the pointer module includes pointer replication and ping-pong storage structures.

[0013] Preferably, when the SC decoder is decoding, the serial pipeline decoding between paths thereof includes:

[0014] The partial sum calculation module, the LLR value calculation module and the path metric value calculation module sequentially calculate the decision LLR values ​​and path metric values ​​PM of different paths.

[0015] In a second aspect, the present invention further provides a decoding method for the polar code SCL decoder with low hardware resource consumption as described above, the method comprising:

[0016] S1, parameter setting and decoding mode setting, including setting the SCL decoding algorithm list size L, code length N; the current calculated bit index is i, the current calculated path index is l, and the number of paths after the current l-th path is expanded is L l The decoding method includes one and only one SC decoder in the SCL decoder, which decodes in accordance with the serial pipeline decoding between paths and the parallel calculation within the path;

[0017] S2. Preprocess the received input signal to obtain an initial LLR value of the received signal;

[0018] S3. If the current i-th bit is not the first bit, calculate the partial sum of the l-th path of the i-th bit and execute S4; if the current i-th bit is the first bit, execute S4 directly;

[0019] S4, calculate the decision LLR value corresponding to the lth path of the current i-th bit and execute S5;

[0020] S5. After the LLR value of the decision of the lth path of the i-th bit is calculated, if the i-th bit is an information bit, path extension is performed and the path metric value is calculated, and then S6 is executed; if the i-th bit is a frozen bit, path extension is not performed, and the path metric value is calculated, and then S6 is executed;

[0021] S6. If the i-th bit is calculated to the l-th path and the number of paths after expansion is L l exceeds L, then execute S7; if the number of paths after expansion is L l When not exceeding L, it includes:

[0022] A. The number of paths after the current lth path is expanded L l does not exceed L, and the current l-th path is the last path of the current i-th bit, and the current i-th bit is the last bit, then execute S8;

[0023] B. The number of paths after the current lth path is expanded L l If the number of paths does not exceed L and the current path l is the last path of the current i-th bit, and the current i-th bit is not the last bit, then the next bit is calculated, the bit index is updated to i=i+1, the path index l is set to 1, and S3 is executed;

[0024] C. The number of paths after the current lth path is expanded L l If the number of paths does not exceed L and the current l-th path of the current i-th bit is decoded and the current l-th path is not the last path of the current i-th bit, then calculate the next path of the current i-th bit, set the path index l = l + 1, and execute S3;

[0025] S7, path screening; after path screening, execution includes:

[0026] D. If the current path l is not the last path, set the path index l = l + 1 and execute S3;

[0027] E. If the current path l is the last path and the current bit i is not the last bit, calculate the next bit, set bit index i = i + 1, set path index l to 1, and execute S3;

[0028] F. If the current lth path is the last path and the current i-th bit is the last bit, execute S8;

[0029] S8. Select the decision value corresponding to the path with the highest reliability according to the path metric value and output it as the decoding result.

[0030] Preferably, the step S2 preprocesses the received input signal to obtain an initial LLR value of the received signal, including:

[0031] The received signal is subjected to demodulation, sampling, and equalization operations to obtain the initial LLR value of the received signal.

[0032] Preferably, when the S4 calculates the decision LLR value corresponding to the current ith bit and the lth path, a serial pointer is used to copy and update the path, and a ping-pong form is used to copy the pointer.

[0033] Preferably, the path screening in S7 includes:

[0034] The L+2 paths are sorted according to the path metric values, and the two paths with the highest reliability are selected as surviving paths. The smaller the path metric value, the higher the path reliability.

[0035] Preferably, when sorting the L+2 paths according to the path metric values ​​and selecting the two paths with the highest reliability as surviving paths, four four-choose-two circuit structures are used instead of one ten-choose-two circuit structure as the sorting structure to complete the sorting.

[0036] Preferably, the calculating the path metric value includes:

[0037] If the current bit is a frozen bit, the path metric is calculated as follows:

[0038]

[0039]

[0040] in, LLR i,l With PM i,l are the decision bit, decision LLR value, and path metric value corresponding to the l-th path of the i-th bit respectively;

[0041] If the current bit is a valid information bit, path extension is performed. The calculation method of the extended path metric is:

[0042]

[0043]

[0044] in, and Represents the metrics of the two paths whose current bit decisions are 0 and 1 respectively.

[0045] (3) Beneficial effects

[0046] The present invention provides a polar code SCL decoder and decoding method with low hardware resource consumption. Compared with the existing technology, it has the following advantages:

[0047] 1. The present invention discloses a polar code SCL decoder with low hardware resource consumption. This decoder utilizes only one SC decoder designed according to a serial pipeline architecture. The SC decoder comprises an LLR calculation module, a partial sum calculation module, a path metric calculation module, a path metric sorting and pruning module, and a pointer module. During the decoding process, serial pipeline decoding is performed between paths, while parallel computation is performed within paths. Although the polar code SCL decoder proposed in this invention utilizes only one SC decoder designed according to a serial pipeline architecture, its rational deployment strategy reduces the timing waits between modules, compared to existing SCL decoders that require the simultaneous use of L SC decoders. This allows each circuit module to operate at full capacity, significantly reducing decoder hardware resource consumption and improving hardware resource reuse while minimizing time delay variations.

[0048] 2. The polar code SCL decoder of the present invention uses four 4-to-2 selectors to implement the function of a 10-to-2 selector, which reduces hardware resource consumption compared to the traditional 16-to-8 selector.

[0049] 3. The present invention uses pointer copying and updating to replace data copying and updating, reducing the number of data read and write times; using a ping-pong storage structure to copy and store pointers, avoiding overwriting and errors;

[0050] 4. The polar code SCL decoder of the present invention maintains the same functionality as a traditional SCL decoder and is applicable to a variety of polar code decoder structures based on the SCL decoding criterion. It has broad practical application value in communication systems using polar codes for encoding. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0052] Figure 1 1 is a timing diagram of the working process corresponding to the decoding allocation strategy of the polar code SCL decoder in an embodiment of the present invention when the size of the list L is 8;

[0053] Figure 2 Schematic diagram of the path expansion and deletion process in an embodiment of the present invention;

[0054] Figure 3 10-choose-2 sorting circuit structure diagram and 4-choose-2 basic circuit structure diagram in an embodiment of the present invention;

[0055] Figure 4 A diagram showing the pointer replication and ping-pong storage structure in an embodiment of the present invention;

[0056] Figure 5 FIG4 is a flowchart of a decoding method of a polar code SCL decoder with low hardware resource consumption in an embodiment of the present invention. DETAILED DESCRIPTION

[0057] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions in the embodiments of the present invention are clearly and completely described. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0058] The embodiments of the present application provide a polar code SCL decoder and decoding method with low hardware resource consumption, thereby solving the problems of high hardware resource consumption and low hardware resource reuse in existing traditional SCL decoding technologies. This reduces resource consumption during the decoding implementation of a receiver and lowers communication costs.

[0059] The technical solution in the embodiments of the present application is to solve the above technical problems, and the overall idea is as follows:

[0060] To address the high hardware resource consumption and low hardware resource reuse issues of traditional SCL decoding technology, the present invention proposes a polar code SCL decoder with low hardware resource consumption. This SCL decoder utilizes only a single SC decoder designed with a serial pipeline architecture, comprising an LLR calculation module, a partial sum calculation module, a path metric calculation module, a path metric sorting and deletion module, and a pointer module. This allows the SCL decoder to perform serial pipeline decoding between paths and parallel computation within paths during the decoding process. This SCL decoder reduces resource consumption during the decoding implementation of the receiver, lowering communication costs.

[0061] In order to better understand the above technical solution, the above technical solution will be described in detail below with reference to the accompanying drawings and specific implementation methods.

[0062] Example 1:

[0063] In the first aspect, the present invention first proposes a polar code SCL decoder with low hardware resource consumption.

[0064] The polar code SCL decoder includes: using only one SC decoder designed according to a serial pipeline structure, the SC decoder includes an LLR calculation module, a partial sum calculation module, a path metric value calculation module, a path metric value sorting and deletion module, and a pointer module;

[0065] When the SC decoder is decoding, the decoding is performed serially between the paths and the calculation is performed in parallel within the paths.

[0066] As can be seen, this embodiment provides a polar code SCL decoder with low hardware resource consumption, which uses only one SC decoder designed according to a serial pipeline structure. The SC decoder includes: an LLR calculation module, a partial sum calculation module, a path metric calculation module, a path metric sorting and pruning module, and a pointer module. During the decoding process, serial pipeline decoding is performed between paths, and parallel calculations are performed within paths. Although the polar code SCL decoder proposed in this invention only uses one SC decoder designed according to a serial pipeline structure, due to its rational deployment strategy, compared with existing SCL decoders that require the simultaneous use of L SC decoders, it reduces the timing waits between modules, allowing each circuit module to operate at full capacity. This significantly reduces decoder hardware resource consumption and improves hardware resource reuse, while maintaining minimal time delay variation.

[0067] The following is combined with Figure 1-4 The specific structure of the polar code SCL decoder in this embodiment is described in detail to explain the implementation process of a polar code SCL decoder with low hardware resource consumption in this embodiment.

[0068] To reduce hardware resource consumption, the polar code SCL decoder in this implementation uses only a single SC decoder designed with a serial pipeline architecture. This SC decoder includes an LLR calculation module, a partial sum calculation module, a path metric calculation module, a path metric sorting and pruning module, and a pointer module. During decoding, the SC decoder performs serial pipeline decoding between paths and parallel computation within paths.

[0069] Specifically, such as Figure 1As shown, during the calculation process, each path does not interfere with each other, and the calculation process adopts a serial method: the partial sum calculation module first calculates the partial sum corresponding to the first path, and then while the LLR calculation module calculates the decision LLR value of the first path, the partial sum calculation module starts to calculate the partial sum corresponding to the second path; the LLR calculation module first calculates the decision LLR value corresponding to the first path, and then while the path metric value calculation module calculates the path metric value PM of the first path, the LLR value calculation module starts to calculate the LLR value corresponding to the second path, and so on. The partial sum calculation module, the LLR value calculation module, and the path metric value calculation module sequentially calculate the decision LLR values ​​and path metric values ​​PM of different paths.

[0070] Also, see Figure 2 , which is a schematic diagram of the path expansion and deletion process in this embodiment. In this embodiment, the path metric value sorting and deletion module needs to select the two paths with the highest reliability from L+2 paths as surviving paths, that is, select the two smallest values ​​from L+2 values. In order to reduce the consumption of hardware resources, a preferred way is to use a certain number of 4-choose-2 circuit cascades to implement this process, thereby realizing the role of a 10-choose-2 selector, which reduces the consumption of hardware resources compared to the traditional 16-choose-8 selector. Specifically, Figure 3 As shown, Figure 3 This is the structure diagram of the 10-choose-2 sorting circuit and the basic circuit structure diagram of 4-choose-2.

[0071] In addition, in this embodiment, the LLR calculation module uses serial pointers during the path copying and updating process. The pointer storage method is L×log2(N) registers with a width of log2(N). In order to prevent the pointer content from being overwritten during pointer copying, the pointer copying is performed in a ping-pong manner. Figure 4 , represents the pointer replication and ping-pong storage structure in this embodiment. After calculating the metrics of the two paths derived from a single path expansion, they are first stored in a cache. When calculating the LLR values ​​for each path, the cached path is pre-read to copy the pointer. The pointer is updated during the LLR calculation process and stored after the update. In this embodiment, pointer replication and storage are performed using a ping-pong structure to achieve path replication and prevent data overwriting and errors when using pointers.

[0072] Example 2:

[0073] In a second aspect, the present invention further provides a decoding method for the polar code SCL decoder with low hardware resource consumption, see Figure 5 , the method comprising:

[0074] S1, parameter setting and decoding mode setting, including setting the SCL decoding algorithm list size L, code length N; the current calculated bit index is i, the current calculated path index is l, and the number of paths after the current l-th path is expanded is L l The decoding method includes one and only one SC decoder in the SCL decoder, which decodes in accordance with the serial pipeline decoding between paths and the parallel calculation within the path;

[0075] S2. Preprocess the received input signal to obtain an initial LLR value of the received signal;

[0076] S3. If the current i-th bit is not the first bit, calculate the partial sum of the l-th path of the i-th bit and execute S4; if the current i-th bit is the first bit, execute S4 directly;

[0077] S4, calculate the decision LLR value corresponding to the lth path of the current i-th bit and execute S5;

[0078] S5. After the LLR value of the decision of the lth path of the i-th bit is calculated, if the i-th bit is an information bit, path extension is performed and the path metric value is calculated, and then S6 is executed; if the i-th bit is a frozen bit, path extension is not performed, and the path metric value is calculated, and then S6 is executed;

[0079] S6. If the i-th bit is calculated to the l-th path and the number of paths after expansion is L l exceeds L, then execute S7; if the number of paths after expansion is L l When not exceeding L, it includes:

[0080] A. The number of paths after the current lth path is expanded L l does not exceed L, and the current l-th path is the last path of the current i-th bit, and the current i-th bit is the last bit, then execute S8;

[0081] B. The number of paths after the current lth path is expanded L l If the number of paths does not exceed L and the current path l is the last path of the current i-th bit, and the current i-th bit is not the last bit, then the next bit is calculated, the bit index is updated to i=i+1, the path index l is set to 1, and S3 is executed;

[0082] C. The number of paths after the current lth path is expanded L l If the number of paths does not exceed L and the current l-th path of the current i-th bit is decoded and the current l-th path is not the last path of the current i-th bit, then calculate the next path of the current i-th bit, set the path index l = l + 1, and execute S3;

[0083] S7, path screening; after path screening, execution includes:

[0084] D. If the current path l is not the last path, set the path index l = l + 1 and go to S3;

[0085] E. If the current path l is the last path and the current bit i is not the last bit, calculate the next bit, set bit index i = i + 1, set path index l to 1, and execute S3;

[0086] F. If the current lth path is the last path and the current i-th bit is the last bit, execute S8;

[0087] S8. Select the decision value corresponding to the path with the highest reliability according to the path metric value and output it as the decoding result.

[0088] The following is combined with Figure 1-5 The implementation process of an embodiment of the present invention is described in detail with explanations of the specific steps of steps S1-S8.

[0089] S1, parameter setting and decoding method. Including setting the SCL decoding algorithm list size L, code length N; the current calculated bit index is i, the current calculated path index is l, and the number of surviving paths after the current i-th bit is calculated is L i , the number of paths after the current l-th path is expanded is L l The decoding method includes that one and only one SC decoder in the SCL decoder decodes according to the serial pipeline decoding between paths and the parallel calculation within the path.

[0090] First, set the parameters, including setting the list size of the SCL decoding algorithm to L, where L represents the maximum number of paths in the decoding process. Set the bit index of the current calculation to i, the path index of the current calculation to l, and L i Represents the number of surviving paths after decoding to the i-th bit. The number of paths after the current l-th path is expanded is L l Among them, L i ≥1 and L i ≤L,L i The initial value of is set to 1. In this embodiment, the value of L is 8, and the calculation starts from the first path of the first bit, that is, let i=1, l=1.

[0091] Specifically, the partial sum calculation module first calculates the partial sum corresponding to the first path, and then while the LLR calculation module calculates the decision LLR value of the first path, the partial sum calculation module starts to calculate the partial sum corresponding to the second path; the LLR calculation module first calculates the decision LLR value corresponding to the first path, and then while the path metric value calculation module calculates the path metric value of the first path, the LLR value calculation module starts to calculate the decision LLR value corresponding to the second path.

[0092] S2. Preprocess the received input signal to obtain an initial LLR value of the received signal.

[0093] The input signal is stored in the cache module. The input data of the decoder is the log-likelihood ratio (LLR) of the received signal obtained by the receiving end after sampling, demodulation, equalization and other operations, that is, the initial LLR value, which is recorded as Where N is the polar code length.

[0094] In this embodiment, the transmission channel is set to an additive white Gaussian noise channel, the modulation mode is BPSK, and the initial LLR value is Where y is the received signal amplitude, σ 2 is the noise variance.

[0095] S3: If the current i-th bit is not the first bit (i.e., i>1), calculate the partial sum of the l-th path of the i-th bit and execute S4. If the current i-th bit is the first bit (i.e., i=1), execute S4 directly.

[0096] For details, see Figure 1 If the partial sum calculation module first calculates the partial sum corresponding to the first path, and then while the LLR calculation module calculates the decision LLR value of the first path, the partial sum calculation module starts to calculate the partial sum corresponding to the second path; if the LLR calculation module first calculates the decision LLR value corresponding to the first path, and then while the path metric value calculation module calculates the path metric value of the first path, the LLR value calculation module starts to calculate the decision LLR value corresponding to the second path.

[0097] S4. Calculate the decision LLR value corresponding to the lth path of the current i-th bit and execute S5.

[0098] Path copying and updating are performed using serial pointers. The pointer storage method is L×log2(N) registers with a width of log2(N). In order to prevent the pointer content from being overwritten when the pointer is copied, the pointer copying is performed in a ping-pong manner. The structure is as follows Figure 4After the metrics of the two paths obtained by expanding a path are calculated, they are first stored in a cache. When calculating the decision value LLR value, each path first pre-reads the cached path to copy the pointer, updates it during the decision value LLR calculation process, and stores it after the update is completed.

[0099] S5. After the LLR value of the decision of the lth path of the i-th bit is calculated, if the i-th bit is an information bit, path extension is performed, and the path metric value is calculated, and then S6 is executed; if the i-th bit is a frozen bit, path extension is not performed, and the path metric value is calculated, and then S6 is executed.

[0100] After the decision LLR value of the lth path of the i-th bit is calculated, when judging whether path extension is needed, if the current bit is a frozen bit, after calculating the decision LLR value of the current path, the path metric value penalty is applied to the wrong path, and path extension is not performed; if the current bit is an information bit, path extension is performed, and the decision LLR value is used to calculate the path metric value PM corresponding to the current surviving path after extension. The judgment condition for determining whether the path is to be expanded into two is whether the current bit is a frozen bit or an information bit. If it is an information bit, it will definitely be extended. If it is a frozen bit, it will definitely not be extended. If the current bit is a frozen bit, the condition for determining whether to impose a penalty is whether the current bit is judged to be 0 or 1. If the judgment is 1, a penalty is imposed, and if the judgment is 0, no penalty is imposed. If the current bit is an information bit, the condition for determining whether to impose a penalty is whether the current bit is judged to be 0 or 1. If the judgment is 1, a penalty is imposed, and if the judgment is 0, no penalty is imposed. If the current bit is an information bit, the condition for determining whether to impose a penalty is whether the positive or negative value of the decision value LLR value and whether the decision value is 0 or 1. Specifically:

[0101] When the current i-th bit After the LLR value of the lth path is calculated, it is determined whether path extension is required, that is, whether A i Is it equal to 1. Among them, A i is a sequence The i-th element in .

[0102] If A i If it is equal to 1, it means that the current bit is a frozen bit, then the path metric value of each path after the path expansion is calculated. When the judgment value When the path metric value of the path is set to the maximum value, the decision value When , the path metric value does not change, the path extension is not performed, the decision value of the current bit decoding path is directly set to 0, and the process goes to step S6.

[0103] If A i If it is not equal to 1, it means that the current bit is an information bit, then the path metric value of each path after the path expansion is calculated. When the judgment value And the judgment value When , the path metric of the path is penalized and the path is expanded to two. The decision value is and When , the path metric value is penalized, the path is expanded to two, and the process goes to step S6.

[0104] In this embodiment, the i-th bit There are two methods for calculating the path metric value of the lth path:

[0105] When the current bit is a frozen bit, the path metric is calculated as follows:

[0106]

[0107]

[0108] in, LLR i,l With PM i,l are the decision bit, decision LLR value and path metric value corresponding to the lth path of the i-th bit respectively;

[0109] When the current bit is a valid information bit, path extension is performed. The metric after extension is calculated as follows:

[0110]

[0111]

[0112] in, and Represents the metrics of the two paths whose current bit decisions are 0 and 1 respectively.

[0113] There are four combinations of LLR positive and negative and judgment of 0 and 1. Except for the two cases mentioned above, penalties are imposed, and the other two cases are not punished.

[0114] S6. If the i-th bit is calculated to the l-th path and the number of paths after expansion is L l Exceeds L (ie L l >L), S7 is executed for path screening (as long as the number of paths after expansion exceeds L, S7 must be entered for path screening regardless of any situation); and when the number of paths after expansion does not exceed L, there are three situations:

[0115] If the number of paths after the current lth path is expanded is L l When it does not exceed L (i.e. Ll≤L), and the current l-th path is the last path of the current i-th bit (i.e. l=L i-1) and if the current i-th bit is the last bit (i.e., i = N), it means that the serial calculation process has been completed, and then S8 is executed. Whether it is the last path is determined by the surviving path of the previous bit. For example, if there are 8 remaining paths after expansion and deletion of all paths of the previous bit, then this bit can calculate up to the 8th path starting from the 1st path.

[0116] If the number of paths L after the current l-th path is expanded l does not exceed L (i.e., Ll ≤ L), and at the same time the current l-th path is the last path of the current i-th bit (i.e., l = L i-1 ), and the current i-th bit is not the last bit (i.e., i < N), then calculate the next bit, update the bit index number to i = i + 1, set the list number l to 1, and execute S3.

[0117] If the number of paths L after the current l-th path is expanded l does not exceed L (i.e., Ll ≤ L), and at the same time the decoding of the current l-th path of the current i-th bit is completed and the current l-th path is not the last path of the current i-th bit, then calculate the next path of the current i-th bit, set the path index l = l + 1, and execute S3.

[0118] S7. Perform path screening.

[0119] First, perform path screening.

[0120] After the above serial calculation process, for valid information bits, every time a path is calculated, it will be expanded into two paths. When the calculated path sequence is L / 2 + 1, the number of expanded paths is L + 2, exceeding the decoding list upper limit, and path screening needs to be performed. For frozen bits, every time a path is calculated, no path expansion is performed, and the number of paths will not exceed the list upper limit, so no path screening is required. Each time, select the 2 paths with the highest reliability and retain them as the surviving paths. After that, every time a path is calculated, the number of expanded paths will reach L + 2. Whenever the number of expanded paths exceeds the decoding list upper limit, sort the path metric values and perform path screening. When all paths are calculated, L surviving paths can be obtained. As Figure 2 shown. It is a schematic diagram of the path expansion and deletion process in this embodiment.

[0121] This embodiment proposes a path metric value sorting structure, which selects the 2 paths with the highest reliability from L + 2 paths, that is, selects the 2 smallest values from L + 2 values. This sorting structure can use a certain number of 4-to-2 circuit cascades to implement this process to replace the 10-to-2 sorting structure. The path metric value sorting structure described above is as Figure 2 shown when L = 8, Figure 3 This is a demonstration of the implementation of the sorting algorithm proposed in the present invention on hardware.

[0122] Then, after the path screening is completed, the following situations need to be discussed:

[0123] If the current l-th path is not the last path (i.e., l < L i-1 ), then set the path index l = l + 1 and enter S3.

[0124] If the current l-th path is the last path (i.e., l = L i-1 ), and the current i-th bit is not the last bit (i.e., i < N), then calculate the next bit, set the bit index i = i + 1, set the path index l to 1, and execute S3.

[0125] If the current l-th path is the last path (i.e., l = L i-1 ), and the current i-th bit is the last bit (i.e., i = N), then execute S8.

[0126] S8. Select the decision value corresponding to the path with the highest reliability based on the path metric value as the decoding result and output it.

[0127] When i = N, it means that the calculation has reached the last bit. Then select the decision result corresponding to the path with the highest reliability (i.e., the smallest path metric value) from the surviving paths as the decoding result. The decoding of one frame of data is completed, and the decoding result is output.

[0128] So far, the entire process of the decoding method of the polar code SCL decoder with low hardware resource consumption in the present invention has been completed.

[0129] It can be understood that the decoding method of the polar code SCL decoder with low hardware resource consumption provided by the embodiments of the present invention corresponds to the above-mentioned decoding system of the polar code SCL decoder with low hardware resource consumption. For the explanations, examples, beneficial effects, etc. of the relevant content, reference can be made to the corresponding content in the decoding system of the polar code SCL decoder with low hardware resource consumption, which will not be elaborated here.

[0130] In summary, compared with the prior art, the following beneficial effects are achieved:

[0131] 1. The present invention discloses a polar code SCL decoder with low hardware resource consumption. This decoder utilizes only one SC decoder designed according to a serial pipeline architecture. The SC decoder comprises an LLR calculation module, a partial sum calculation module, a path metric calculation module, a path metric sorting and pruning module, and a pointer module. During the decoding process, serial pipeline decoding is performed between paths, while parallel computation is performed within paths. Although the polar code SCL decoder proposed in this invention utilizes only one SC decoder designed according to a serial pipeline architecture, its rational deployment strategy reduces the timing waits between modules, compared to existing SCL decoders that require the simultaneous use of L SC decoders. This allows each circuit module to operate at full capacity, significantly reducing decoder hardware resource consumption and improving hardware resource reuse while minimizing time delay variations.

[0132] 2. The polar code SCL decoder of the present invention uses four 4-to-2 selectors to implement the function of a 10-to-2 selector, which reduces hardware resource consumption compared to the traditional 16-to-8 selector.

[0133] 3. The present invention uses pointer copying and updating to replace data copying and updating, reducing the number of data read and write times; using a ping-pong storage structure to copy and store pointers, avoiding overwriting and errors;

[0134] 4. The polar code SCL decoder of the present invention maintains the same functionality as a traditional SCL decoder and is applicable to a variety of polar code decoder structures based on the SCL decoding criterion. It has broad practical application value in communication systems using polar codes for encoding.

[0135] It should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply the existence of any such actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or device comprising the element.

[0136] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present invention.

Claims

1. A decoding method for a polar code SCL decoder with low hardware resource consumption, characterized in that: The method comprises: S1. Parameter setting and decoding mode setting, including setting the SCL decoding algorithm list size L, the code length N; the currently calculated bit index is i, the currently calculated path index is l, and the number of paths after the current l-th path is expanded is Ll; the decoding mode includes the only SC decoder in the SCL decoder decoding according to the serial pipeline decoding between paths and the parallel calculation method within the path; S2. Preprocess the received input signal to obtain an initial LLR value of the received signal; S3. If the current i-th bit is not the first bit, calculate the partial sum of the l-th path of the i-th bit and execute S4; if the current i-th bit is the first bit, execute S4 directly; S4, calculate the decision LLR value corresponding to the lth path of the current i-th bit and execute S5; S5. After the LLR value of the decision of the lth path of the i-th bit is calculated, if the i-th bit is an information bit, path extension is performed and the path metric value is calculated, and then S6 is executed; if the i-th bit is a frozen bit, path extension is not performed, and the path metric value is calculated, and then S6 is executed; S6. If the i-th bit is calculated up to the l-th path and the number of paths after extension L1 exceeds L, then execute S7. If the number of paths after extension L1 does not exceed L, then execute S7: A. If the number of paths Ll after the current l-th path is expanded does not exceed L, and the current l-th path is the last path of the current i-th bit, and the current i-th bit is the last bit, then execute S8; B. If the number of paths Ll after the current l-th path is expanded does not exceed L, and the current l-th path is the last path of the current i-th bit, and the current i-th bit is not the last bit, then calculate the next bit, update the bit index to i=i+1, set the path index l to 1, and execute S3; C. If the number of paths Ll after the current l-th path is expanded does not exceed L, and the current l-th path of the current i-th bit is decoded and the current l-th path is not the last path of the current i-th bit, then calculate the next path of the current i-th bit, set the path index l=l+1, and execute S3; S7, path screening; after path screening, execution includes: D. If the current path l is not the last path, set the path index l = l + 1 and execute S3; E. If the current path l is the last path and the current i-th bit is not the last bit, calculate the next bit, set the bit index i = i + 1, set the path index l to 1, and execute S3; F. If the current lth path is the last path and the current i-th bit is the last bit, execute S8; S8. Select the decision value corresponding to the path with the highest reliability according to the path metric value and output it as the decoding result.

2. The method according to claim 1, wherein The step S2 pre-processes the received input signal to obtain an initial LLR value of the received signal, including: The received signal is subjected to demodulation, sampling, and equalization operations to obtain the initial LLR value of the received signal.

3. The method according to claim 1, wherein When the S4 calculates the decision LLR value corresponding to the current i-th bit and the l-th path, the serial pointer is used to copy and update the path, and the pointer copy is performed in a ping-pong manner.

4. The method according to claim 1, wherein The path screening in S7 includes: The L+2 paths are sorted according to the path metric values, and the two paths with the highest reliability are selected as surviving paths. The smaller the path metric value, the higher the path reliability.

5. The method according to claim 4, wherein When sorting the L+2 paths according to the path metric values ​​and selecting the two paths with the highest reliability as surviving paths, four four-choose-two circuit structures are used instead of one ten-choose-two circuit structure as the sorting structure to complete the sorting.

6. The method according to claim 1, wherein Calculating the path metric value includes: If the current bit is a frozen bit, the path metric is calculated as follows: in, 、 and are the decision bit, decision LLR value, and path metric value corresponding to the l-th path of the i-th bit respectively; for The corresponding function, A is a variable; If the current bit is a valid information bit, path extension is performed. The calculation method of the extended path metric is: in, and Represents the metrics of the two paths whose current bit decisions are 0 and 1 respectively.

7. A polar code SCL decoder with low hardware resource consumption, characterized in that: Used to execute the decoding method according to any one of claims 1 to 6, wherein the polar code SCL decoder uses only one SC decoder designed according to a serial pipeline structure, The SC decoder includes an LLR calculation module, a partial sum calculation module, a path metric value calculation module, a path metric value sorting and deletion module, and a pointer module; When decoding, the SC decoder performs serial pipeline decoding between paths and parallel calculation within the paths.

8. The polar code SCL decoder according to claim 7, wherein: The path metric value sorting and pruning module includes multiple 4-choose-2 basic circuits.

9. The polar code SCL decoder according to claim 7, wherein: The pointer module includes pointer replication and ping-pong storage structures.

10. The polar code SCL decoder according to claim 7, wherein: When the SC decoder is decoding, the serial pipeline decoding between its paths includes: The partial sum calculation module, the LLR value calculation module and the path metric value calculation module sequentially calculate the decision LLR values ​​and path metric values ​​PM of different paths.

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