Charge loss tracking in memory subsystems

Abstract

A system is disclosed comprising a memory device and a processing device operatively coupled to the memory device to perform operations including identifying a block family comprising a plurality of blocks of the memory device. The operations performed by the processing device further comprise associating the block family with a threshold voltage offset. The operations performed by the processing device further comprise calculating an adjustment value for the threshold voltage offset, wherein the adjustment value reflects a time period elapsed since a triggering event and the temperature of a memory component carrying one or more of the plurality of blocks.

Description

Technical Field

[0001] Embodiments of this disclosure generally relate to memory subsystems, and more specifically, to tracking charge loss in memory subsystems. Background Technology

[0002] The memory subsystem may include one or more memory devices for storing data. The memory devices may be, for example, non-volatile memory devices and volatile memory devices. Generally, a host system may utilize the memory subsystem to store data at the memory devices and retrieve data from the memory devices. Attached Figure Description

[0003] This disclosure will be more fully understood from the detailed description given below and the accompanying drawings, which illustrate various embodiments of the present disclosure. However, the drawings should not be construed as limiting the disclosure to the specific embodiments, but are for explanation and understanding only.

[0004] Figure 1 An example computing system including a memory subsystem is shown according to some embodiments of the present disclosure.

[0005] Figure 2 The illustration schematically depicts a time-voltage shift of a three-level memory cell, according to some embodiments of the present disclosure, capable of storing three data bits by programming the memory cell to eight charge states, the eight charge states being different from the amount of charge on the floating gate of the cell.

[0006] Figure 3 Instance graphs depicting the dependence of threshold voltage offset on time after programming (i.e., the time period elapsed since the block has been programmed) according to some embodiments of the present disclosure.

[0007] Figure 4 A set of predefined threshold voltage offset ranges is schematically illustrated according to embodiments of the present disclosure.

[0008] Figure 5 The block family management operation performed by the block family manager component of the memory subsystem is illustrated schematically according to embodiments of the present disclosure.

[0009] Figure 6 The illustration schematically shows instance metadata maintained by the memory subsystem controller according to embodiments of the present disclosure for associating blocks and / or partitions with block families.

[0010] Figure 7 This is a flowchart of an example method 700 for tracking charge loss implemented by a memory subsystem controller, according to some embodiments of the present disclosure.

[0011] Figure 8This is a flowchart of an example method 800 for tracking charge loss implemented by a memory subsystem controller according to some embodiments of the present disclosure.

[0012] Figure 9 This is a block diagram of an example computer system in which embodiments of the present disclosure may be operated. Detailed Implementation

[0013] Various aspects of this disclosure relate to tracking charge loss in a memory subsystem. The memory subsystem may be a storage device, a memory module, or a combination of both. The following is combined with… Figure 1 Describe examples of storage devices and memory modules. Generally, a host system may utilize a memory subsystem that includes one or more components, such as a memory device for storing data. The host system can provide data to be stored in the memory subsystem and can request data to be retrieved from the memory subsystem.

[0014] The memory subsystem may utilize one or more memory devices (including any combination of different types of non-volatile memory devices and / or volatile memory devices) to store data provided by the host system. An example of a non-volatile memory device is a NAND flash memory device. The following section combines... Figure 1 Other examples of non-volatile memory devices are described. A non-volatile memory device is a package of one or more dies. Each die may consist of one or more planes. For some types of non-volatile memory devices (e.g., NAND devices), each plane consists of a set of physical blocks. Each block consists of a set of pages. Each page consists of a set of memory cells (“cells”). A cell is electronic circuitry for storing information.

[0015] Data operations can be performed by the memory subsystem. Data operations can be operations initiated by the host. For example, the host system can initiate data operations on the memory subsystem (e.g., write, read, erase, etc.). The host system can access requests to the memory subsystem (e.g., write commands, read commands) to store data on a memory device at the memory subsystem and to read data from a memory device at the memory subsystem. The data to be read or written, as specified by the host request, is referred to hereinafter as "host data". The host request may contain logical address information (e.g., logical block address (LBA), namespace) for the host data, which is the location associated between the host system and the host data. The logical address information (e.g., LBA, namespace) may be part of the metadata of the host data. The metadata may also include error handling data (e.g., ECC codeword, parity check code), data version (e.g., expiration date used to distinguish the written data), validity bitmap (whose LBA or logical transfer unit contains valid data), etc.

[0016] A memory device comprises multiple memory cells capable of storing one or more bits of information, depending on the type of memory cell. A memory cell can be programmed (written into) by applying a voltage to it, causing a charge to be held by the memory cell, thereby determining the voltage signal V. CG The voltage signal V CG A control electrode must be applied to the cell to open it to inter-cell current between the source and drain electrodes. More specifically, for each individual memory cell (with a charge Q stored therein), a threshold control gate voltage V may exist. T (Also referred to in this paper as the “threshold voltage” or simply the “threshold”), such that for V CG <V T The source-drain current is low. Once the control gate voltage exceeds the threshold voltage, V CG >V T The current increases significantly. Because the actual geometry of the electrodes and gate varies between cells, the threshold voltage V... T Even cells implemented on the same die can be different. Therefore, a memory cell can be characterized as a distribution of threshold voltage P, P(Q,V). T )=dW / dV T , where dW represents the threshold voltage of any given cell in the interval [V] when charge Q is placed on the cell. T V T +dV T The probability within ] .

[0017] High-quality memory devices can have a narrow distribution P(Q,V) compared to the operating range of the control voltages allowed by the cells of the device. T Therefore, multiple non-overlapping distributions P(Q) k V T The valley line can be fitted to the operating range, allowing for the storage and reliable detection of multiple charge values ​​Q. k k = 1, 2, 3… The distribution (valley lines) is interspersed with voltage intervals (valley tolerances), in which the memory cells of the device have no (or very few) their threshold voltages. Therefore, such valley tolerances can be used to separate various charge states Q. k —The corresponding threshold voltage V of the unit can be detected during the read operation. T The logic state of a cell is determined by which two valley tolerances it exists between. This effectively allows a single memory cell to store multiple bits of information: a memory cell with 2N-1 well-defined valley tolerances and 2N valley operations can reliably store N bits of information. Specifically, this can be achieved by comparing the measured threshold voltage V exhibited by the memory cell. TA read operation is performed with one or more reference voltage levels corresponding to a known valley tolerance (e.g., the center of the tolerance) of the memory device.

[0018] Due to a phenomenon known as slow charge loss (SCL), the threshold voltage V of a memory cell decreases as the cell's charge diminishes. T This can vary over time, and the process is sometimes referred to as "time-to-voltage shift" (TVS). Since a typical cell stores negatively charged particles (electrons), the loss of electrons causes the voltage threshold to shift along the voltage axis towards a lower voltage threshold V. T Shift. The threshold voltage can initially change rapidly (immediately after the memory cell is programmed), while simultaneously slowing down over a longer period in a roughly power-law manner relative to the time t elapsed since the cell programming event, ΔV T (t)=-C*t b In some embodiments of this disclosure, the voltage offset ΔV to be used during a read operation can be correlated by tracking the time elapsed since the programming event and the environmental conditions of a particular memory partition (box, plane, etc.). T To mitigate TVS, the standard "basic read level" threshold voltage V T (Displayed by the cell immediately following the programming) Modified by voltage offset: V T →V T +ΔV T Although TVS is a continuous process and compensation corrects ΔV T (t) can be a continuous function of time, but in some embodiments, sufficient accuracy of the offset can be achieved using a discrete number of offset "intervals". Each interval can be associated with a "family" of blocks (or any other memory partitions) programmed within a specified time window and under similar environmental conditions (e.g., temperature). Since the time elapsed since programming and temperature conditions are among the major factors affecting the amount of TVS, it can be assumed that different partitions within a single block family exhibit a similar distribution of threshold voltages for their memory cells, and therefore the same voltage offset will need to be applied to the base read level for read operations.

[0019] Block families can be created asynchronously relative to block programming events. In an illustrative example, a new family can be created (“opened”) whenever a specified time period Δt (e.g., a predetermined number of minutes) has elapsed since the creation of the previous block family, or whenever the reference temperature of a memory cell has changed by more than a specified threshold ΔΘ (e.g., 10K, 5K, or any other value). Similarly, a family can be “closed” (and a new family can be created) after a time period Δt has elapsed since its creation, or when the reference temperature (in either direction) has changed by more than ΔΘ. The memory subsystem controller can maintain an identifier for the active block families, which is associated with one or more blocks when they are programmed.

[0020] The memory subsystem controller may periodically perform calibration operations to associate partitions of each family with one of the intervals. Each interval may in turn be associated with a set of voltage offsets to be applied for read operations. The association between partitions and families, and between families and intervals, is referred to herein as Auxiliary Read Metadata (ARM), which represents a portion of the broader state metrics of the memory device. State metrics may also include the number of discarded physical memory blocks (or other partitions), the number of times various physical blocks have been erased, the configuration type of cells in various memory partitions (e.g., single-level cells vs. multi-level cells), or any other type of information indicating the state of the memory device. ARM may be stored in a metadata table maintained by the memory subsystem controller.

[0021] According to embodiments of this disclosure, TVS can be selectively tracked for programmable partitions grouped into families. Based on partition-to-family grouping, an appropriate interval-specific read (voltage) offset is applied to a base read (voltage) level during a read operation. The base read level can also be stored in the metadata of the memory device. Upon receiving a read command, the memory subsystem controller can perform the following operations: (1) identify the family associated with the memory partition identified by the logical address specified in the read command; (2) identify the current interval associated with the identified family; (3) determine a set of read offsets for the identified intervals; (4) calculate a new read voltage by superimposing the read offsets associated with the identified intervals onto the base read level; and (5) perform the read voltage using the new read voltage, as described in more detail below.

[0022] However, various implementations may fail to adequately address the impact of time-voltage shifts or the resulting performance and power effects when the memory subsystem controller must frequently perform calibration operations, and may employ inefficient strategies to correlate block families with the voltage offset applied in data operations due to TVS.

[0023] Various aspects of this disclosure address the aforementioned and other drawbacks by implementing a memory subsystem controller that tracks charge loss in a block family by accumulating the effects of threshold voltage offsets associated with the block family, thereby minimizing the amount of calibration operations that the memory subsystem controller should perform. In some embodiments, the memory subsystem controller can account for charge loss in blocks of the memory device by introducing a threshold voltage offset to be applied to a read operation, such that the threshold voltage offset depends on the time elapsed since the last programming event and the environmental (e.g., temperature) conditions experienced by the relevant portion of the memory component. The memory subsystem controller can accumulate changes in the threshold voltage offset over a period of time. Once the accumulated threshold voltage offset reaches a threshold voltage criterion, the memory subsystem controller can perform one or more calibration operations to determine an updated new threshold voltage. Thus, calibration is triggered by the accumulated threshold voltage offset reaching a threshold voltage value, resulting in a reduced frequency of calibration operations.

[0024] Therefore, the advantages of this disclosure include, but are not limited to, improving the performance and power consumption of the memory subsystem by reducing the frequency of calibration operations.

[0025] Figure 1 An example computing system 100 including a memory subsystem 110 is illustrated according to some embodiments of the present disclosure. The memory subsystem 110 may include media, such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination of such devices.

[0026] The memory subsystem 110 may be a storage device, a memory module, or a combination of a storage device and a memory module. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash memory (UFS) drives, secure digital cards (SD cards), and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0027] The computing system 100 may be a computing device such as a desktop computer, a laptop computer, a web server, a mobile device, a vehicle (e.g., an airplane, drone, train, car or other means of transport), an Internet of Things (IoT) enabled device, an embedded computer (e.g., a computer contained in a vehicle, industrial equipment or a commercially available connected device), or such a computing device that includes memory and processing means (e.g., a processor).

[0028] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to multiple memory subsystems 110 of different types. Figure 1 An example of a host system 120 coupled to a memory subsystem 110 is shown. As used herein, “coupled to” or “coupled with” generally refers to a connection between components, which can be an indirect or direct communication connection (e.g., without an intermediate component), whether wired or wireless, including connections such as electrical, optical, magnetic, etc.

[0029] Host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). Host system 120 uses memory subsystem 110, for example, to write data to memory subsystem 110 and read data from memory subsystem 110.

[0030] Host system 120 can be coupled to memory subsystem 110 via a physical host interface. Examples of physical host interfaces include, but are not limited to, Serial Advanced Technology Attachment (SATA) interfaces, Peripheral Component Interconnect High Speed ​​(PCIe) interfaces, Universal Serial Bus (USB) interfaces, Fibre Channel, Serial Attached SCSI (SAS), Dual Data Rate (DDR) memory buses, Small Computer System Interface (SCSI), Dual In-line Memory Module (DIMM) interfaces (e.g., DIMM sockets supporting Dual Data Rate (DDR)), Open NAND Flash Interface (ONFI), Low Power Dual Data Rate (LPDDR), and so on. The physical host interface can be used to transfer data between host system 120 and memory subsystem 110. When memory subsystem 110 is coupled to host system 120 via a physical host interface (e.g., a PCIe bus), host system 120 can further utilize an NVM High Speed ​​(NVMe) interface to access components (e.g., memory device 130). The physical host interface provides an interface for transferring control, address, data, and other signals between memory subsystem 110 and host system 120. Figure 1 Memory subsystem 110 is shown as an example. Generally, host system 120 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0031] Memory devices 130 and 140 may comprise any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory device 140) may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0032] Some examples of non-volatile memory devices (e.g., memory device 130) include NAND flash memory and in-place write memory, such as three-dimensional cross-point (“3D cross-point”) memory devices, which are cross-point arrays of non-volatile memory cells. The cross-point array of non-volatile memory cells can be combined with a stackable cross-grid data access array for bit storage based on changes in volume resistance. Furthermore, in contrast to many flash-based memories, cross-point non-volatile memories allow for in-place write operations, where non-volatile memory cells can be programmed without prior erasing. NAND flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0033] Each of the memory devices 130 may include one or more arrays of memory cells. One type of memory cell, such as a single-level cell (SLC), may store one bit per cell. Other types of memory cells, such as multi-level cell (MLC), three-level cell (TLC), four-level cell (QLC), and five-level cell (PLC), may store multiple bits per cell. In some embodiments, each of the memory devices 130 may include one or more arrays of memory cells, such as SLC, MLC, TLC, QLC, PLC, or any combination of such arrays. In some embodiments, a particular memory device may include an SLC portion of memory cells, as well as an MLC portion, a TLC portion, a QLC portion, or a PLC portion. The memory cells of the memory device 130 may be grouped into pages that can refer to logical units of the memory device used for storing data. For some types of memory (e.g., NAND), pages may be grouped to form blocks.

[0034] Although a 3D cross-point array of non-volatile memory cells and a non-volatile memory component of NAND type flash memory (e.g., 2D NAND, 3D NAND) have been described, the memory device 130 may be based on any other type of non-volatile memory, such as read-only memory (ROM), phase-change memory (PCM), auto-select memory, other chalcogenide-based memory, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), NOR flash memory, or electrically erasable programmable read-only memory (EEPROM).

[0035] The memory subsystem controller 115 (or, for simplicity, controller 115) can communicate with the memory device 130 to perform operations, such as reading data, writing data, or erasing data at the memory device 130, and other such operations. The memory subsystem controller 115 may include hardware, such as one or more integrated circuits and / or discrete components, buffer memories, or combinations thereof. The hardware may include a digital circuit system having dedicated (i.e., hard-decoded) logic for performing the operations described herein. The memory subsystem controller 115 may be a microcontroller, a dedicated logic circuit system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or other suitable processor.

[0036] The memory subsystem controller 115 may include a processing means comprising one or more processors (e.g., processor 117) configured to execute instructions stored in local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes embedded memory configured to store instructions for performing various processes, operations, logical flows, and routines that control the operation of the memory subsystem 110, including handling communication between the memory subsystem 110 and the host system 120.

[0037] In some embodiments, local memory 119 may include memory registers storing memory pointers, retrieved data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Although Figure 1 The instance memory subsystem 110 in the present disclosure is described as including a memory subsystem controller 115, but in another embodiment of the present disclosure, the memory subsystem 110 does not include a memory subsystem controller 115 and may actually rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0038] Generally, the memory subsystem controller 115 can receive commands or operations from the host system 120 and can translate these commands or operations into instructions or appropriate commands to achieve the desired access to the memory device 130. The memory subsystem controller 115 may handle other operations such as wear leveling, garbage collection, error detection and error correction code (ECC) operations, encryption, caching, and address translation between logical addresses (e.g., logical block addresses, namespaces) and physical addresses (e.g., physical block addresses) associated with the memory device 130. The memory subsystem controller 115 may also include a host interface circuitry for communicating with the host system 120 via a physical host interface. The host interface circuitry can translate commands received from the host system into command instructions to access the memory device 130, and translate responses associated with the memory device 130 into information for the host system 120.

[0039] In some implementations, the memory subsystem 110 may use a striping scheme, in which each data payload (e.g., user data) utilizes multiple dies of the memory device 130 (e.g., a NAND-type flash memory device), such that the payload is distributed across a subset of the dies, while the remaining one or more dies are used to store error correction information (e.g., parity bits). Therefore, a set of blocks distributed across a set of dies of a memory device using a striping scheme is referred to herein as a “superblock”.

[0040] The memory subsystem 110 may also include additional circuitry or components not shown. In some embodiments, the memory subsystem 110 may include a cache or buffer (e.g., DRAM) and address circuitry (e.g., row decoder and column decoder) that can receive addresses from the memory subsystem controller 115 and decode the addresses to access the memory device 130.

[0041] In some embodiments, memory device 130 includes a local media controller 135 that operates in conjunction with memory subsystem controller 115 to perform operations on one or more memory cells of memory device 130. An external controller (e.g., memory subsystem controller 115) may externally manage memory device 130 (e.g., perform media management operations on memory device 130). In some embodiments, memory subsystem 110 is a managed memory device, which is the original memory device 130 having on-die control logic (e.g., local controller 132) and a controller (e.g., memory subsystem controller 115) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0042] According to embodiments of this disclosure, memory subsystem 110 includes block family manager component 113, which can be used to track charge loss in memory cells by the effects of threshold voltage offset accumulation time and temperature. In some embodiments, memory subsystem controller 115 includes at least a portion of block family manager component 113. In some embodiments, block family manager component 113 is part of host system 110, an application, or an operating system. In other embodiments, local media controller 135 includes at least a portion of block family manager component 113 and is configured to perform the functionality described herein. Block family manager component 113 can manage the accumulation of threshold voltage offset based on the time and temperature of blocks associated with memory device 130, as described in more detail below.

[0043] Figure 2 This schematically illustrates the ability, according to some embodiments of the present disclosure, to program memory cells into eight charge states Q. k The time-voltage shift (TVS) of a three-level memory cell (TLC) storing three data bits involves eight charge states that differ from the charge levels on the floating gate of the cell. The threshold voltage P(V) T Q k The distribution of ) and the 7 valley tolerance VM n Separate. Programmed as the k-th charge state (Q) k Each cell can store a specific combination of 3 bits. For example, the charge state Q k It can store binary combinations 101, as depicted. This charge state Q k Valley tolerance VM can be detected during readout operations. k Internal control gate voltage V CG Sufficient to open the cell to source-drain current while the previous valley line tolerance VM k-1 The control gate voltage is insufficient to open the cell to the source-drain current. Memory cells can be configured to store N=1 bits (SLC), N=2 bits (MLC), N=3 bits (TLC), N=4 bits (QLC), etc., depending on how much distribution can be fitted within the operating range of the control gate voltage (and with a sufficiently large valley tolerance). Even Figure 2 The TLC described herein can be applied to any N-bit memory cell.

[0044] Memory cells are typically joined by word lines (wires electrically connected to the cell's control gate) and programmed together as memory pages (e.g., 16KB or 32KB pages) in one configuration (by selecting consecutive bit lines connected to the cell's source and drain electrodes). After three programming passes, the word lines of a three-level cell can store up to three pages: the lower page (LP), the upper page (UP), and the extra page (XP). For example, after the first programming pass, the cell can be driven to one of the charge states Q1, Q2, Q3, Q4 (corresponding to LP bit value 1, e.g., ...). Figure 2 (As shown in the diagram) or one of charge states Q5, Q6, Q7, Q8 (corresponding to LP bit value 0). After the second path, when UP is programmed into the same word line, the charge state of the memory cell can be adjusted to further narrow the range of possible locations of the cell's threshold voltage. For example, a cell in one of charge states Q1, Q2, Q3, or Q4 (LP bit value 1) can be driven to only one of the two states Q1 or Q2 (corresponding to UP bit value 1) or to one of the two states Q3 or Q4 (corresponding to UP bit value 0). Similarly, after the third programming path, the charge state of the memory cell can be further fine-tuned. For example, a cell in logic state 10 (i.e., UP bit value 1 and LP bit value 0) and one of charge states Q7 or Q8 can be driven to state Q7 (corresponding to XP bit value 0) or to state Q8 (corresponding to XP bit value 1). Conversely, during a read operation, the memory controller 115 can determine the control gate voltage V applied within the sixth valley tolerance VM6. CG The control gate voltage within the seventh valley tolerance VM7 is sufficient to open the cell to the source-drain current, and is sufficient to open the cell. Therefore, the memory controller 115 can determine that the cell is in charge state Q7 corresponding to logic state 010 (i.e., XP:0, UP:1, LP:0).

[0045] use Figure 2 The solid line in the figure depicts the distribution of threshold voltages that the memory cell has immediately after programming. Over time, due to slow charge loss, the distribution shifts (typically towards V). T The lower values ​​(as shown by the shifted valley lines indicated by dashed lines) are thus shifted by a certain value ΔV. T The value may depend on the time elapsed since programming, environmental conditions (e.g., ambient temperature), etc. For optimal read operations, controller 115 (or SSC 113) can therefore use the corresponding offset V. R →V R+ΔV is used to adjust the base read level, and the corresponding offset is the same as (or approximately the same as) the time voltage shift. In one embodiment, the offset can be determined (or estimated) as the difference between the center of the valley tolerance immediately following programming (e.g., center 202 of VM7) and the center of the same—but shifted—valley tolerance at a later time (e.g., new center 204). Figure 2 The diagram schematically illustrates that TVS with different distributions (valley lines) and valley line tolerances can differ from each other. Figure 2 In the typical scenario described, TVS is large for larger charges Q and small for smaller charges.

[0046] like Figure 2 As shown, TVS in a memory device is a continuous process. However, in some embodiments, sufficient accuracy of the voltage offset can be achieved using a set of discrete intervals and a corresponding set of discrete voltage offsets ΔV. In such embodiments, TVS can be addressed by setting several discrete intervals (e.g., five, eight, twenty, etc.) associated with various memory partitions. The interval-related data can be stored in metadata table 210. The association between various memory partitions (grouped into families, as described in more detail below) and intervals can be stored in family-interval association 212; the family-interval association can change dynamically over time. For example, as memory cells continue to lose charge over time, the corresponding memory partition (grouped into families) can move continuously from a primary interval to a higher-level interval with a larger voltage offset. Interval-offset association 214 can also be stored in metadata table 210. In some embodiments, interval-offset association 214 can be static, while family-interval association 212 can be adjusted (based on memory partition calibration) to account for the actual charge loss of memory cells in the corresponding partition. In some embodiments, family-range association 212 may store the logical address of a memory partition, such as the LBA of the corresponding block, and the association between the LBA and the corresponding physical block address (PBA) may be stored outside the metadata table 210, for example, in a memory translation table separately stored in one of the local memory 119 or memory devices 130, 140. However, in some embodiments, family-range association 212 may additionally include LBA-to-PBA translations or store direct PBA-to-range associations. (See also...) Figure 2 The interval numbering, interval-offset association 214, and partition-interval association are schematically depicted using curved arrows. These can be based on the calibration of the memory device (or a similar type of memory device, for example, during design and manufacturing) to maximize performance and minimize read errors during read operations.

[0047] Figure 3A plot 300 depicts an example curve illustrating the dependence of the threshold voltage offset 310 on the time 320 since programming (i.e., the time period elapsed since the block was programmed). As shown by... Figure 3 The diagram schematically illustrates that the blocks of the memory device are grouped into block families 330A-330N, such that each block family contains one or more blocks that have been programmed within a specified time window and a specified temperature window. As mentioned above, since the time elapsed after programming and temperature are the main factors affecting the time voltage shift, it is assumed that all blocks and / or partitions within a single block family 310 exhibit similar threshold voltage distributions in the memory cells, and therefore read operations will require the same voltage offset.

[0048] Block families can be created asynchronously relative to block programming events. In an illustrative example, a block family is created whenever a specified time period (e.g., a predetermined number of minutes) has elapsed since the creation of the previous block family, or whenever the reference temperature of a memory cell updated at specified time intervals since the creation of the current block family has changed by more than a specified threshold. Figure 1 The memory subsystem controller 115 can create new block families.

[0049] The newly created block family can be associated with interval 0. Then, the memory subsystem controller can periodically perform a calibration operation to ensure that each die in each block family is offset from a predefined threshold voltage interval (within...). Figure 3 In illustrative examples, this is associated with one of the intervals 0-7, which in turn is associated with a voltage offset to be applied for a read operation. The association between blocks and block families, as well as between block families and dies, and the threshold voltage offset interval can be stored in a corresponding metadata table maintained by the memory subsystem controller. In various embodiments of this disclosure, the block family manager component 113 can track the accumulation of threshold voltage offsets associated with any block family 330A-330N and perform a calibration operation after the threshold voltage offset reaches a threshold voltage criterion.

[0050] Figure 4 A set of predefined threshold voltage offset intervals (intervals 0 to 9) are schematically illustrated according to embodiments of the present disclosure. Figure 4 As schematically shown, the threshold voltage offset curve can be subdivided into multiple threshold voltage offset intervals, such that each interval corresponds to a predetermined range of threshold voltage offset. Although Figure 4 The illustrative example defines ten intervals, but in other embodiments, various other numbers of intervals may be used (e.g., 64 intervals). Based on the calibration operation performed, the memory subsystem controller associates each die of each block family with a threshold voltage offset interval, which defines a set of threshold voltage offsets to be applied to the base voltage read level to perform a read operation, as described in more detail below.

[0051] Figure 5The illustration schematically depicts block family management operations performed by the block family manager component of the memory subsystem controller, according to embodiments of the present disclosure. For example... Figure 5 As illustrated, the block family manager 510 may maintain an identifier 520 for the active block family in a memory variable, the identifier being associated with one or more blocks of the cursor 530A-530K when the cursors are programmed. "Cursor" will be used broadly herein to refer to the location on the memory device to which data is written.

[0052] The memory subsystem controller can use a power-on minute (POM) clock to track the creation time of the block family. In some implementations, in addition to the POM clock, a less accurate clock that continues to operate while the controller is in various low-power states can be used, so that the POM clock is updated immediately based on the less accurate clock after the controller wakes up from a low-power state.

[0053] Therefore, after initializing each block family, the current time 540 is stored in a memory variable as the block family start time 550. When a block is programmed, the current time 540 is compared with the block family start time 550. In response to detecting that the difference between the current time 540 and the block family start time 550 is greater than or equal to a specified time period (e.g., a predetermined number of minutes), the memory variable storing the active block family identifier 520 is updated to store the next block family number (e.g., the next sequential integer number), and the memory variable storing the block family start time 550 is updated to store the current time 540. The block family manager 510 can also use the current time 540 to track charge loss associated with the block family by accumulating the time effect on the threshold voltage offset.

[0054] The block family manager 510 may also maintain a set of memory variables for storing, for example, the high and low reference temperatures of selected dies in each memory device, and various temperatures of the selected dies in each memory device during a certain time period. After initializing each block family, the high temperature 560 and low temperature 570 variables store the current temperature values ​​of the selected dies in the memory device. In operation, while the active block family identifier 520 remains the same, temperature measurements are periodically obtained and compared with the correspondingly updated stored high temperature 560 and low temperature 570 values: if a temperature measurement is found to be greater than or equal to the value stored by the high temperature variable 560, the value stored by the high temperature variable 560 is updated to store the temperature measurement; conversely, if a temperature measurement is found to have dropped below the value stored by the low temperature variable 570, the value stored by the low temperature variable 570 is updated to store the temperature measurement.

[0055] The block family manager 510 can further periodically calculate the difference between the high temperature 560 and the low temperature 570. In response to determining that the difference between the high temperature 560 and the low temperature 570 is greater than or equal to a specified temperature threshold, the block family manager 510 can create a new active block family: the memory variable storing the active block family identifier 520 is updated to store the next block family number (e.g., the next sequential integer number), the memory variable storing the block family start time 550 is updated to store the current time 540, and the high temperature 560 and low temperature 570 variables are updated to store the current temperature value of the selected die of the memory device.

[0056] The block family manager 510 can also calculate the average temperature over an elapsed time period by using the stored temperature values ​​of a given die during a specific time period. The average temperature over the elapsed time period can, for example, be used to calculate an adjustment value for the threshold voltage offset, as referenced below. Figure 7 To describe in more detail.

[0057] When programming a block, the memory subsystem controller associates the block with the currently active block family. The association of each block with its corresponding block family is reflected in the block family metadata 580, as referenced below. Figure 6 To describe in more detail.

[0058] As mentioned above, based on a calibration operation triggered by accumulated threshold voltage offsets reaching a threshold voltage criterion, the memory subsystem controller associates each die in each block family with a threshold voltage offset interval, which defines a set of threshold voltage offsets to be applied to the base voltage read level to perform a read operation. The calibration operation involves performing read operations with different threshold voltage offsets relative to a specified number of randomly selected blocks within the block family being calibrated, and selecting the threshold voltage offset that minimizes the error rate of the read operation.

[0059] Figure 6 The illustration schematically depicts instance metadata maintained by the memory subsystem controller according to embodiments of the present disclosure for associating blocks and / or partitions with block families. (As provided by...) Figure 6 As schematically shown, the memory subsystem controller can maintain a superblock table 610, a family table 620, an offset table 630, and an accumulated threshold voltage offset table 640.

[0060] Each record in the superblock table 610 specifies a block family associated with a specified superblock and partition combination. In some implementations, the superblock table record may further include time and temperature values ​​associated with the specified superblock and partition combination.

[0061] Family table 620 is indexed by block family numbers, such that each record in family table 620 specifies a set of threshold voltage offset intervals associated with the corresponding die of the block family referenced by the record's index. In other words, each record in family table 620 contains a vector, each element of which specifies a threshold voltage offset interval associated with the die referenced by the index of the vector element. The threshold voltage offset interval to be associated with the block family die can be determined through a calibration process, as described in more detail above.

[0062] Offset table 630 is indexed by interval number. Each record in offset table 630 specifies a set of threshold voltage offsets (e.g., for TLC, MLC and / or SLC) associated with a threshold voltage offset interval.

[0063] Finally, the accumulated threshold voltage offset table 640 is indexed by the block family number, such that each record of the accumulated threshold voltage offset table 640 specifies the threshold voltage offset associated with the corresponding die of the block family referenced by the record's index, as well as the accumulated threshold offset voltage calculated based on the effects of time and temperature.

[0064] Metadata tables 610-630 can be stored Figure 1 On one or more memory devices 130. In some embodiments, at least a portion of the metadata table may be cached. Figure 1 The memory subsystem controller 115 is located in the local memory 119.

[0065] In operation, upon receiving a read command, the memory subsystem controller determines the physical address corresponding to the logical block address (LBA) specified in the read command. For example, components of the physical address of the physical block number and the die identifier are used to perform a metadata table traversal: First, the superblock table 610 is used to identify the block family identifier corresponding to the physical block number; then, the block family identifier is used as an index to the family table 620 to determine the threshold voltage offset interval associated with the block family and the die; the identified threshold voltage offset interval is used as an index to the offset table 630 to determine the threshold voltage offset corresponding to the interval; finally, the accumulated threshold voltage offset table 640 is used to determine whether a calibration operation should be performed to determine the threshold voltage offset based on whether the accumulated threshold voltage offset meets a threshold voltage criterion. The memory subsystem controller can then apply the identified threshold voltage offsets cumulatively to the base voltage read level to perform the requested read operation.

[0066] Figure 7This is a flowchart of an example method 700 for tracking charge loss implemented by a memory subsystem controller according to some embodiments of the present disclosure. Method 700 may be executed by processing logic, which may include hardware (e.g., processing device, circuit system, dedicated logic, programmable logic, microcode, device hardware, integrated circuit, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, method 700 is performed by… Figure 1 The block family manager component 113 executes. Although shown in a specific order or sequence, the order of processes can be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes can be executed in different orders, and some processes can be executed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0067] At operation 710, the processing logic identifies block families. A block family may include multiple blocks of the memory device. In an illustrative example, identifying a block family may include randomly selecting a block family from multiple blocks of the memory device.

[0068] At operation 715, the processing logic associates the block family with the threshold voltage offset. In the illustrative example, the processing logic utilizes... Figure 6 The block family table 620 is used to determine the interval identifier corresponding to the combination of the block family identifier and the die identifier. The processing logic then utilizes... Figure 6 The offset table 630 is used to determine the threshold voltage offset of the identified threshold voltage offset range.

[0069] At operation 720, the processing logic determines the elapsed time period since the triggering event. The triggering event can be, for example, a programming or calibration operation relative to one or more blocks of a block family identified by operation 710. In an illustrative example, the processing logic may utilize block family manager 510 and the current time 540 to determine the elapsed time period since the triggering event. For instance, block family manager 510 may calculate the difference between the current time 540 and the block family start time 550 to obtain the elapsed time period since the triggering event.

[0070] At operation 725, the processing logic receives a temperature measurement at a selected die of the identified block family. The temperature measurement may be the average temperature over a time period since the triggering event, as calculated by the block family manager 510, as explained in more detail herein.

[0071] At operation 730, the processing logic calculates an adjustment value for the threshold voltage offset. In some embodiments, the adjustment value may be calculated based on an elapsed time period determined by the processing logic at operation 720 and a temperature measurement received by the processing logic at operation 725. The adjustment value may be represented by a time function multiplied by a power of a first coefficient and multiplied by a second coefficient. The time function may reflect the elapsed time period determined by the processing logic at operation 720. At least one of the first and second coefficients may reflect the temperature of the memory component, such as a temperature measurement received by the processing logic at operation 725. The adjustment value may be cumulatively accumulated until the adjustment value meets a threshold voltage criterion. In response to a first trigger event, cumulatively accumulating the adjustment value may include storing the first adjustment value as the accumulated threshold voltage offset. In response to a second trigger event, a second adjustment value may be calculated as described above. The second adjustment value may be cumulatively applied to the accumulated threshold voltage offset. As mentioned above, metadata reflecting the temperature measurement, the elapsed time period, the adjustment value, and the accumulated threshold voltage offset may be maintained in a storage location. Figure 1 In one or more metadata tables 610-630 on one or more memory devices 130.

[0072] At operation 735, the processing logic determines whether the adjustment value meets a threshold voltage criterion. In some embodiments, the adjustment value may reflect the accumulated threshold voltage offset, as described above. The threshold voltage criterion may be one or more reference voltage levels, for example, corresponding to a known valley tolerance (e.g., the center of the tolerance) of the memory device, as described above. In response to determining that the calculated adjustment value meets the threshold voltage criterion, the processing continues at operation 740; otherwise, the processing loops back to operation 715.

[0073] At operation 740, the processing logic performs one or more calibration operations on the identified block families to associate each die in the identified block family with one of a predefined threshold voltage offset interval, which in turn is associated with a voltage offset to be applied for the read operation. The associations between blocks and block families, as well as between block families and dies and the threshold voltage offset intervals, can be stored in [the relevant storage / database]. Figure 1 In one or more metadata tables 610-630 on one or more memory devices 130.

[0074] At operation 745, the processing logic updates the threshold voltage offset associated with the block family based on the calculated adjustment value. The updated threshold voltage offset can then be used by the memory subsystem controller for performing read operations relative to one or more blocks of the block family.

[0075] Figure 8This is a flowchart of an example method 800 for tracking charge loss implemented by a memory subsystem controller according to some embodiments of the present disclosure. Method 800 may be executed by processing logic, which may include hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, device hardware, integrated circuits, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, method 800 is performed by… Figure 1 The block family manager component 113 executes. Although shown in a specific order or sequence, the order of processes can be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes can be executed in different orders, and some processes can be executed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0076] At operation 810, the processing logic identifies block families. A block family may include multiple blocks of the memory device. In an illustrative example, identifying a block family may include randomly selecting a block family from multiple blocks of the memory device.

[0077] At operation 815, the processing logic associates the block family with the threshold voltage offset. In an illustrative example, the processing device utilizes... Figure 6 The block family table 620 is used to determine the interval identifier corresponding to the combination of the block family identifier and the die identifier. The processing device then utilizes... Figure 6 The offset table 630 is used to determine the threshold voltage offset of the identified threshold voltage offset range.

[0078] At operation 820, the processing logic determines the elapsed time period since the triggering event. The triggering event can be, for example, a programming or calibration operation relative to one or more blocks of a block family identified by operation 810. In an illustrative example, the processing logic may utilize block family manager 510 and the current time 540 to determine the elapsed time period since the triggering event. For instance, block family manager 510 may calculate the difference between the current time 540 and the block family start time 550 to obtain the elapsed time period since the triggering event.

[0079] At operation 825, the processing logic determines the average temperature measurement over the time period elapsed since the trigger event at the selected die of the identified block family. The temperature measurement can be calculated via the block family manager 510, as mentioned above.

[0080] At operation 830, the processing logic calculates an adjustment value for the threshold voltage offset. In some embodiments, the adjustment value may be calculated based on an elapsed time period determined by the processing logic at operation 820 and a temperature measurement received by the processing logic at operation 825. The adjustment value may be represented by a time function multiplied by a power of a first coefficient and then by a second coefficient. The time function may reflect the elapsed time period determined by the processing logic at operation 820. At least one of the first and second coefficients may reflect the temperature of the memory component, such as a temperature measurement received by the processing logic at operation 825. The adjustment value may be cumulatively accumulated until the adjustment value meets a threshold voltage criterion. In response to a first trigger event, cumulatively accumulating the adjustment value may include storing the first adjustment value as the accumulated threshold voltage offset. In response to a second trigger event, a second adjustment value may be calculated as described above. The second adjustment value may be cumulatively applied to the accumulated threshold voltage offset. As mentioned above, metadata reflecting the temperature measurement, the elapsed time period, the adjustment value, and the accumulated threshold voltage offset may be maintained in a storage location. Figure 1 In one or more metadata tables 610-630 on one or more memory devices 130.

[0081] At operation 835, the processing logic determines whether the adjustment value meets a threshold voltage criterion. In some embodiments, the adjustment value may reflect the accumulated threshold voltage offset, as described above. The threshold voltage criterion may be one or more reference voltage levels, for example, corresponding to a known valley tolerance (e.g., the center of the tolerance) of the memory device, as described above. In response to determining that the calculated adjustment value is equal to the threshold voltage criterion voltage, the processing logic continues at operation 840; otherwise, the processing logic loops back to operation 815.

[0082] At operation 840, the processing logic performs one or more calibration operations on the identified block family to associate each die in the identified block family with one of a predefined threshold voltage offset interval, which in turn is associated with a voltage offset to be applied for the read operation. The associations between blocks and block families, as well as between block families and dies and the threshold voltage offset intervals, can be stored in [the relevant storage / database]. Figure 1 In one or more metadata tables 610-630 on one or more memory devices 130.

[0083] At operation 845, the processing logic determines whether to update the threshold voltage offset associated with the identified block family based on the adjustment value. In an illustrative example, the processing logic determines whether the adjustment value meets the threshold voltage criterion, as described above. The processing logic then performs one or more calibration operations on the identified block family, as described above. During the calibration operation, the memory subsystem controller associates each die of each block family with a threshold voltage offset interval. The threshold voltage offset interval defines a set of threshold voltage offsets to be applied to the base voltage read level to perform a read operation. Therefore, in some embodiments, the processing logic may update the threshold voltage offset based on the threshold voltage offset interval associated with each die of the block family after the calibration operation. The updated threshold voltage offset may be used by the memory subsystem controller to perform a read operation relative to one or more blocks of the block family. For example, the updated threshold voltage offset may be applied additively to the "base read level" threshold voltage to obtain a new read voltage for the identified block family.

[0084] Figure 9 An example machine is shown as a computer system 900, within which a set of instructions is executable to cause the machine to perform any or more of the methods discussed herein. In some embodiments, computer system 900 corresponds to a host system (e.g., Figure 1 The host system 120 includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 The memory subsystem 110) or can be used to perform controller operations (e.g., to execute the operating system to perform operations corresponding to...). Figure 1 (Operation of the block family manager component 113). In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a LAN, intranet, extranet, and / or the Internet. The machine may operate as a peer machine in a peer-to-peer (or distributed) network environment or as a server or client machine in a cloud computing infrastructure or environment, or within the capacity of a server or client machine in a client-server network environment.

[0085] The machine may be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), cellular phone, network device, server, network router, switch, or bridge, or any machine capable of executing (sequentially or otherwise) a set of instructions specifying actions to be taken by the machine. Furthermore, although a single machine is described, the term "machine" should be understood to include any collection of machines that individually or collectively execute a set (or more) of instructions to perform any or more of the methods discussed herein.

[0086] The example computer system 900 includes a processing device 902, a main memory 904 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM) or RDRAM), a static memory 906 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 918, which communicate with each other via a bus 930.

[0087] Processing device 902 represents one or more general-purpose processing devices, such as microprocessors, central processing units, etc. More specifically, the processing device may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processor implementing other instruction sets, or a processor implementing a combination of instruction sets. Processing device 902 may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, etc. Processing device 902 is configured to execute instructions 926 for performing the operations and steps discussed herein. Computer system 900 may further include a network interface device 908 for communication via network 920.

[0088] The data storage system 918 may include a machine-readable storage medium 924 (also referred to as a computer-readable medium) storing one or more sets of instructions 926 or software embodying any or more of the methods or functions described herein. The instructions 926 may also reside wholly or at least partially in main memory 904 and / or processing device 902 during execution by computer system 900, the main memory 904 and processing device 902 also constituting machine-readable storage media. The machine-readable storage medium 924, the data storage system 918, and / or main memory 904 may correspond to... Figure 1 The memory subsystem 110.

[0089] In one embodiment, instruction 926 includes instructions for implementing a component corresponding to a block family manager (e.g., Figure 1 The block family manager component 113) provides functional instructions. Although the machine-readable storage medium 924 is shown as a single medium in the exemplary embodiment, the term "machine-readable storage medium" should be considered to include a single medium storing a set of instructions or multiple media storing multiple sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding a set of instructions executable by a machine and causing the machine to perform any one or more of the methods of this disclosure. Therefore, the term "machine-readable storage medium" should be considered to include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0090] Some parts of the previously described in detail have been presented based on the algorithms and symbolic representations of operations on data bits within computer memory. These algorithmic descriptions and representations are the means by which those skilled in the art of data processing most effectively communicate the essence of their work to others skilled in the art. The algorithms in this paper generally refer to a self-consistent sequence of operations that produce a desired result. An operation is one that requires physical control over a physical quantity. These quantities are usually, but not necessarily, in the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. Primarily for general reasons, it has proven convenient to sometimes refer to these signals as bits, values, elements, symbols, characters, terms, numbers, etc.

[0091] However, it should be remembered that all these and similar terms should be associated with appropriate physical quantities and are merely convenient labels for application to those quantities. This disclosure can refer to the actions and processes of a computer system or similar electronic computing device that manipulate and transform data represented as physical (electronic) quantities in the registers and memories of a computer system, or other data similarly represented as physical quantities in the computer system's memory or registers or other such information storage systems.

[0092] This disclosure also relates to apparatus for performing the operations described herein. Such apparatus may be specifically constructed for the desired purpose, or may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in a computer. Such computer programs may be stored in computer-readable storage media, such as, but not limited to, any type of disk, including floppy disks, optical disks, CD-ROMs and magneto-optical disks, read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic cards or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

[0093] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general-purpose systems may be used with the programs taught herein, or it may be convenient to construct more specialized devices to perform the methods. Structures for various such systems will be presented as described below. Furthermore, this disclosure is described without reference to any particular programming language. It will be understood that the teachings of this disclosure as described herein can be implemented using various programming languages.

[0094] This disclosure can be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon that can be used to program a computer system (or other electronic device) to perform processes according to this disclosure. The machine-readable medium includes any mechanism for storing information in a machine-readable (e.g., computer-readable) form. In some embodiments, the machine-readable (e.g., computer-readable) medium includes machine-readable storage media, such as read-only memory (“ROM”), random access memory (“RAM”), disk storage media, optical storage media, flash memory components, etc.

[0095] In the foregoing description, embodiments of this disclosure have been described with reference to specific examples thereof. It will be apparent that various modifications can be made to the invention without departing from the broader spirit and scope of the embodiments set forth in the appended claims. Therefore, the description and drawings should be considered illustrative rather than restrictive.

Claims

1. A memory system comprising: Memory devices; and A processing device operatively coupled to the memory device to perform operations including: Identify a block family that includes multiple blocks of the memory device; Associate the block family with the threshold voltage offset; Calculate an adjustment value for the threshold voltage offset, wherein the adjustment value reflects the time period that has elapsed since the triggering event and the temperature of the memory component carrying one or more of the plurality of blocks; The adjustment value is determined to meet a threshold voltage standard, wherein the threshold voltage standard includes a reference voltage level corresponding to a known valley tolerance of the memory device; and In response to determining that the adjustment value meets the threshold voltage criterion, the threshold voltage offset is updated.

2. The memory system of claim 1, wherein the operation further comprises: In response to determining that the adjustment value meets the threshold voltage criterion, the block family is scanned.

3. The memory system of claim 1, wherein the triggering event is a memory cell programming event associated with the block family.

4. The memory system of claim 1, wherein the adjustment value is represented by a time function multiplied by a power of a first coefficient and a second coefficient, wherein at least one of the first coefficient and the second coefficient reflects the temperature of the memory component.

5. The memory system of claim 1, wherein the operation further comprises: Metadata reflecting the adjustment value and the threshold voltage offset is stored on the memory device.

6. The memory system of claim 1, wherein the adjustment value for calculating the threshold voltage offset is performed by a hardware accelerator.

7. The memory system of claim 1, wherein the block family comprising the plurality of blocks of the memory device is randomly identified from the plurality of blocks of the memory device.

8. A method for tracking charge loss, comprising: A block family comprising multiple blocks of a memory device is identified by a processing device, wherein the block family is associated with a threshold voltage offset; The processing device determines the average temperature of the memory assembly carrying one or more of the plurality of blocks. Calculate an adjustment value for the threshold voltage offset, wherein the adjustment value reflects the time period that has elapsed since the trigger event and the average temperature of the memory component; The adjustment value is determined to meet a threshold voltage standard, wherein the threshold voltage standard includes a reference voltage level corresponding to a known valley tolerance of the memory device; In response to determining that the adjustment value meets the threshold voltage criterion, one or more blocks of the block family are scanned; and The threshold voltage offset associated with the block family is updated based on the adjustment value.

9. The method of claim 8, further comprising: In response to determining that the adjustment value meets the threshold voltage criterion, the block family is scanned.

10. The method of claim 8, wherein the triggering event includes a memory cell programming event associated with the block family.

11. The method of claim 8, wherein the adjustment value is represented by a time function multiplied by a power of a first coefficient and a second coefficient, wherein at least one of the first coefficient and the second coefficient reflects the temperature of the memory component.

12. The method of claim 8, further comprising storing metadata reflecting the adjustment value and the threshold voltage offset at the memory device.

13. The method of claim 8, wherein the adjustment value for calculating the threshold voltage offset is performed by a hardware accelerator.

14. The method of claim 8, wherein the block family comprising the plurality of blocks of the memory device is randomly identified from the plurality of blocks of the memory device.

15. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing means, cause the processing means to perform operations including: Identify block families that include multiple blocks of a memory device; Associate the block family with the threshold voltage offset; Calculate an adjustment value for the threshold voltage offset, wherein the adjustment value reflects the time period that has elapsed since the triggering event and the temperature of the memory component carrying one or more of the plurality of blocks; The adjustment value is determined to meet a threshold voltage standard, wherein the threshold voltage standard includes a reference voltage level corresponding to a known valley tolerance of the memory device; and In response to determining that the adjustment value meets the threshold voltage criterion, the threshold voltage offset is updated.

16. The non-transitory computer-readable storage medium of claim 15, further comprising: In response to determining that the adjustment value meets the threshold voltage criterion, the block family is scanned.

17. The non-transitory computer-readable storage medium of claim 15, wherein the triggering event includes a memory cell programming event associated with the block family.

18. The non-transitory computer-readable storage medium of claim 15, wherein the adjustment value is represented by a time function multiplied by a power of a first coefficient and a second coefficient, wherein at least one of the first coefficient and the second coefficient reflects the temperature of the memory component.

19. The non-transitory computer-readable storage medium of claim 15, further comprising storing metadata reflecting the adjustment value and the threshold voltage offset at the memory device.

20. The non-transitory computer-readable storage medium of claim 15, wherein the adjustment value for calculating the threshold voltage offset is performed by a hardware accelerator.

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