Voltage supply circuit and semiconductor memory device

Abstract

To provide a voltage supply circuit that can reduce the ripple in the output voltage of a charge pump circuit by suppressing the effect of changes in the power supply voltage on the voltage supplied to the charge pump circuit. [Solution] The voltage supply circuit according to the embodiment includes: a first LDO amplifier circuit that receives a power supply voltage from a power source and outputs a first control voltage from a first output unit according to a preset reference voltage; a second LDO amplifier circuit that receives a power supply voltage from a power source and outputs a second control voltage from a second output unit according to a reference voltage; an oscillation circuit; a first charge pump circuit that outputs a first output voltage generated from the first control voltage to a first output terminal; a second charge pump circuit that outputs a second output voltage generated from the second control voltage to a second output terminal; and a control circuit that controls the operation of the first LDO amplifier circuit and the second LDO amplifier circuit.

Description

Technical Field

[0001] This embodiment relates to a voltage supply circuit.

Background Art

[0002] Conventionally, there has been a voltage supply circuit provided with a charge pump circuit that supplies a boosted voltage for each operation of a semiconductor memory device such as a flash memory.

[0003] In such a voltage supply circuit, when the range of the voltage supplied to the charge pump circuit is wide, the ripple of the output voltage of the charge pump circuit may become a problem.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] One embodiment aims to provide a voltage supply circuit capable of suppressing the influence of changes in the power supply voltage on the voltage supplied to the charge pump circuit and reducing the ripple of the output voltage of the charge pump circuit.

Means for Solving the Problems

[0006] A voltage supply circuit according to one embodiment a first LDO (Low Drop Out) amplifier circuit that is supplied with a power supply voltage from a power supply and outputs a first control voltage from a first output unit according to a preset reference voltage; a second LDO amplifier circuit that is supplied with the power supply voltage from the power supply and outputs a second control voltage from a second output unit according to the reference voltage; an oscillation circuit that generates and outputs a clock signal; A first charge pump circuit is supplied with the first control voltage, operates based on the clock signal, and outputs a first output voltage generated from the first control voltage to a first output terminal; A second charge pump circuit is supplied with the second control voltage and operates based on the clock signal to output a second output voltage generated from the second control voltage to a second output terminal. The system includes a control circuit for controlling the operation of the first LDO amplifier circuit and the second LDO amplifier circuit. It is characterized by the following: [Brief explanation of the drawing]

[0007] [Figure 1] Figure 1 shows an example of the configuration of a voltage supply circuit according to the first embodiment. [Figure 2] Figure 2 is a diagram illustrating the load response characteristics of the first and second LDO circuits according to the first embodiment. [Figure 3] Figure 3 shows an example of the simulation results of the characteristics of the first output voltage VO1 during writing and erasing. [Figure 4] Figure 4 shows an example of the simulation results of the characteristics of the second output voltage VO2 during writing and erasing. [Figure 5] Figure 5 shows an example of the simulation results of the characteristics of the second output voltage VO2 during readout. [Figure 6] Figure 6 shows an example of the configuration of a semiconductor memory device according to the third embodiment. [Figure 7] Figure 7 shows an example of the configuration of a voltage supply circuit according to the second embodiment. [Figure 8A] Figure 8A is a diagram illustrating the load response characteristics of the second LDO circuit according to the second embodiment. [Figure 8B] Figure 8B is a diagram illustrating the load response characteristics of the third LDO circuit according to the second embodiment. [Figure 9]Figure 9 shows an example of the simulation results of the characteristics of the second output voltage VO2 during readout. [Modes for carrying out the invention]

[0008] The voltage supply circuit according to the embodiment will be described in detail below with reference to the attached drawings. However, the present invention is not limited to these embodiments. (First Embodiment) Figure 1 shows an example of the configuration of a voltage supply circuit according to the first embodiment. Figure 2 is a diagram illustrating the load response characteristics of the first and second LDO circuits according to the first embodiment. [Voltage supply circuit]

[0009] The voltage supply circuit 100 according to the first embodiment is a circuit for supplying a predetermined voltage to the memory section M of the semiconductor memory device 1000 shown in Figure 6.

[0010] As shown in Figure 1, for example, this voltage supply circuit 100 includes a first LDO (Low Drop Out) amplifier circuit LDO1, a second LDO amplifier circuit LDO2, an oscillator circuit OSC, a first charge pump circuit P1, a second charge pump circuit P2, a control circuit CNT, a first LDO voltage divider circuit R1, a second LDO voltage divider circuit R2, a first output voltage divider circuit RO1, a second output voltage divider circuit RO2, a first comparator CMP1, and a second comparator CMP2.

[0011] The following details the configuration of the voltage supply circuit 100.

[0012] [First LDO voltage divider resistor] The first LDO voltage divider circuit R1 is connected between the first output section X1 of the first LDO amplifier circuit LDO1 and the ground potential VGND, as shown in Figure 1, for example.

[0013] This first LDO voltage division circuit R1, for example, as shown in FIG. 1, outputs a first LDO divided voltage VR1 obtained by dividing the voltage between the first output section X1 of the first LDO amplifier circuit LDO1 and the ground potential VGND at the first LDO division ratio from the first LDO output divided voltage terminal TR1.

[0014] This first LDO voltage division circuit R1 includes, for example, as shown in FIG. 1, a first LDO voltage division resistor R1a and a second LDO voltage division resistor R1b.

[0015] The first LDO voltage division resistor R1a has, for example, as shown in FIG. 1, one end connected to the output section X1 of the first LDO amplifier circuit LDO1 and the other end connected to the first LDO output divided voltage terminal TR1.

[0016] The second LDO voltage division resistor R1b has, for example, as shown in FIG. 1, one end connected to the first LDO output divided voltage terminal TR1 and the other end connected to the ground potential VGND.

[0017] [Second LDO Voltage Division Circuit] The second LDO voltage division circuit R2 is connected, for example, as shown in FIG. 1, between the second output section X2 of the second LDO amplifier circuit LDO2 and the ground potential VGND.

[0018] This second LDO voltage division circuit R2 outputs, for example, as shown in FIG. 1, a second LDO divided voltage VR2 obtained by dividing the voltage between the second output section X2 of the second LDO amplifier circuit LDO2 and the ground potential VGND at the second LDO division ratio from the second LDO output divided voltage terminal TR2.

[0019] This second LDO voltage division circuit R2 includes, for example, as shown in FIG. 1, a third LDO voltage division resistor R2a and a fourth LDO voltage division resistor R2b.

[0020] The third LDO voltage division resistor R2a has one end connected to the second output section X2 of the second LDO amplifier circuit LDO2 and the other end connected to the second LDO output divided voltage terminal TR2.

[0021] Furthermore, the fourth LDO voltage divider resistor R2b has one end connected to the second LDO output voltage divider terminal TR2 and the other end connected to the ground potential VGND.

[0022] [First LDO Amplifier Circuit] The first LDO amplifier circuit LDO1, as shown in Figure 1 for example, is supplied with a power supply voltage VCC from a power supply S, and outputs a first control voltage VLDO1 from the first output unit X1 according to a preset reference voltage VREF and the first LDO voltage divider voltage VR1 described above.

[0023] In particular, the first LDO amplifier circuit LDO1 controls the first control voltage VLDO1 such that the first LDO divided voltage VR1, obtained by dividing the first control voltage VLDO1 by the first LDO voltage divider circuit R1 at a first voltage division ratio, approaches the reference voltage VREF.

[0024] [Second LDO Amplifier Circuit] The second LDO amplifier circuit LDO2, as shown in Figure 1 for example, is supplied with a power supply voltage VCC from a power supply S, and outputs a second control voltage VLDO2 from the second output unit X2 in accordance with the reference voltage VREF and the second LDO voltage divider voltage VR2 described above.

[0025] In particular, the second LDO amplifier circuit LDO2 controls the second control voltage VLDO2 such that the second LDO divided voltage VR2, obtained by dividing the second control voltage VLDO2 by the second LDO voltage divider circuit R2 at the second voltage division ratio, approaches the reference voltage VREF.

[0026] Thus, the first and second LDO amplifier circuits LDO1 and LDO2 are provided corresponding to the first and second charge pump circuits P1 and P2, respectively. As a result, the load currents I1 and I2 output by the first and second LDO amplifier circuits LDO1 and LDO2 do not interfere with each other, and capacitance is not required in the first and second output sections X1 and X2 to suppress the overshoot of the first and second control voltages VLDO1 and VLDO2.

[0027] Furthermore, as shown in Figure 2 described above, the first and second LDO amplifier circuits LDO1 and LDO2 are configured to have a slow load response characteristic.

[0028] Furthermore, the load response of the first LDO amplifier circuit LDO1 and the second LDO amplifier circuit LDO2 can be controlled to be slower by setting the drive currents that drive the first LDO amplifier circuit LDO1 and the second LDO amplifier circuit LDO2 to small values, respectively.

[0029] [Oscillator circuit] The oscillator circuit OSC is supplied with the first control voltage VLDO1 output by the first LDO amplifier circuit LDO1.

[0030] The oscillator circuit OSC generates a clock signal CLK to set the boost operation and outputs it to the first charge pump circuit P1 and the second charge pump circuit P2.

[0031] [First output voltage divider circuit] The first output voltage divider circuit RO1 is connected between the first output terminal TO1 and the ground potential VGND, for example, as shown in Figure 1.

[0032] This first output voltage divider circuit RO1 outputs a first output voltage divider voltage VRO1 from the first output voltage divider terminal TRO1, which is obtained by dividing the voltage between the first output terminal TO1 and the ground potential VGND by the first output voltage divider ratio.

[0033] The first output voltage divider circuit RO1 includes, for example, a first output voltage divider resistor RO1a and a second output voltage divider resistor RO1b, as shown in Figure 1.

[0034] The first output voltage divider resistor RO1a has one end connected to the first output terminal TO1 and the other end connected to the first output voltage divider terminal TRO1.

[0035] Furthermore, the second output voltage divider resistor RO1b has one end connected to the first output voltage divider terminal TRO1 and the other end connected to the ground potential VGND.

[0036] [Second output voltage divider circuit] The second output voltage divider circuit RO2 is connected between the second output terminal TO2 and the power supply S, for example, as shown in Figure 1.

[0037] This second output voltage divider circuit RO2 outputs a second output voltage divider voltage VRO2 from the second output voltage divider terminal TRO2, which is obtained by dividing the voltage between the second output terminal TO2 and the power supply S by the second output voltage divider ratio.

[0038] This second output voltage divider circuit RO2 includes, for example, a third output voltage divider resistor RO2a and a fourth output voltage divider resistor RO2b, as shown in Figure 1.

[0039] The third output voltage divider resistor RO2b has one end connected to the second output terminal TO2 and the other end connected to the second output voltage divider terminal TRO2.

[0040] Furthermore, the fourth output voltage divider resistor RO2a has one end connected to the second output voltage divider terminal TRO2 and the other end connected to the power supply S.

[0041] [First comparator] The first comparator CMP1 outputs a first feedback signal S1 to the first charge pump circuit P1, which corresponds to the result of comparing the first reference voltage Vref1 with the first output voltage divider VRO1.

[0042] [Second Comparator] The second comparator CMP2 outputs a second feedback signal S2 to the second charge pump circuit P2, which corresponds to the result of comparing the second reference voltage Vref2 with the second output voltage divider VRO2.

[0043] [First charge pump circuit] The first charge pump circuit P1 is supplied with a first control voltage VLDO1 and operates based on the clock signal CLK and the first feedback signal S1 (boosting the voltage to the positive side), outputting a first output voltage VO1 generated from the first control voltage VLDO1 to the first output terminal TO1.

[0044] In other words, the first output voltage VO1 is a positive voltage higher than the ground potential VGND.

[0045] Here, the first charge pump circuit P1 adjusts the first output voltage VO1 based on the first feedback signal S1 so that the first output voltage divider voltage VRO1 approaches the first reference voltage Vref1.

[0046] For example, the first charge pump circuit P1 is configured to boost the voltage to the positive side and increase the first output voltage VO1 when the first feedback signal S1 indicates that the first output voltage divider voltage VRO1 is less than the first reference voltage Vref1.

[0047] On the other hand, the first charge pump circuit P1 is configured to stop its boost operation if the first feedback signal S1 indicates that the first output voltage divider voltage VRO1 is greater than or equal to the first reference voltage Vref1.

[0048] [Second charge pump circuit] The second charge pump circuit P2 is supplied with a second control voltage VLDO2 and operates based on the clock signal CLK and the second feedback signal S2 (by boosting the voltage to the negative side), outputting a second output voltage VO2 generated from the second control voltage VLDO2 to the second output terminal TO2.

[0049] In other words, the second output voltage VO2 is a negative voltage lower than the ground potential VGND.

[0050] Here, the second charge pump circuit P2 adjusts the second output voltage VO2 based on the second feedback signal S2 so that the second output voltage divider voltage VRO2 approaches the second reference voltage Vref2.

[0051] For example, the second charge pump circuit P2 is configured to boost the voltage to the negative side and lower the second output voltage VO2 when the second feedback signal S2 indicates that the second output voltage divider voltage VRO2 is greater than or equal to the second reference voltage Vref2.

[0052] On the other hand, the second charge pump circuit P2 is configured to stop boosting operation if the second feedback signal S2 indicates that the second output voltage divider voltage VRO2 is less than the second reference voltage Vref2.

[0053] [control circuit] The control circuit CNT controls the operation of the first LDO amplifier circuit LDO1, the second LDO amplifier circuit LDO2, the oscillator circuit OSC, the first charge pump circuit P1, and the second charge pump circuit P2.

[0054] For example, in a preset first mode, the control circuit CNT is configured to cause the first LDO amplifier circuit LDO1 to output a first control voltage VLDO1 from the first output unit X1 according to the reference voltage VREF.

[0055] Furthermore, in the first mode, the control circuit CNT is configured to cause the second LDO amplifier circuit LDO2 to output a second control voltage VLDO2 from the second output section X2.

[0056] On the other hand, in a preset second mode different from the first mode, the control circuit CNT is configured to forcibly bypass the power supply voltage VCC supplied from the power supply S to the first LDO amplifier circuit LDO1, regardless of the reference voltage VREF, and output it as the first control voltage VLDO1 from the first output unit X1.

[0057] Furthermore, in the second mode, the control circuit CNT bypasses the power supply voltage VCC supplied from the power supply S to the second LDO amplifier circuit LDO2 and outputs it as the second control voltage VLDO2 from the second output section X2.

[0058] Furthermore, the control circuit CNT may be configured to control the load response of the first LDO amplifier circuit LDO1 and the second LDO amplifier circuit LDO2 in the first mode so that it is slower than the load response of the first LDO amplifier circuit LDO1 and the second LDO amplifier circuit LDO2 in the second mode.

[0059] For example, in the first mode, the control circuit CNT controls the load response of the first LDO amplifier circuit LDO1 and the second LDO amplifier circuit LDO2 to be slowed down by reducing the drive currents that drive the first LDO amplifier circuit LDO1 and the second LDO amplifier circuit LDO2, respectively.

[0060] On the other hand, in the second mode, the control circuit CNT controls the load response of the first LDO amplifier circuit LDO1 and the second LDO amplifier circuit LDO2 to be faster by increasing the drive current that drives the first LDO amplifier circuit LDO1 and the second LDO amplifier circuit LDO2, respectively.

[0061] This first mode is, for example, a mode in which the memory section M of the semiconductor memory device 1000 shown in Figure 6 (described later) performs a write operation or an erase operation.

[0062] On the other hand, the second mode is, for example, a mode in which the memory section M of the semiconductor memory device 1000, shown in Figure 6 below, performs a read operation.

[0063] Here, the load capacity of the semiconductor storage device 1000 when the memory section M of the semiconductor storage device 1000 is performing a read operation is greater than the load capacity of the semiconductor storage device 1000 when the memory section M of the semiconductor storage device 1000 is performing a write operation or an erase operation.

[0064] In other words, the load capacity of the memory section M of the semiconductor storage device 1000 connected to the first output terminal TO1 and the second output terminal TO2 in the second mode is set to be larger than the load capacity of the memory section M of the semiconductor storage device 1000 connected to the first output terminal TO1 and the second output terminal TO2 in the first mode.

[0065] The control circuit CNT controls the first reference voltage Vref1 so that the value of the first output voltage VO1 output by the first charge pump circuit P1 is set to a target value defined for each of the first and second modes, respectively.

[0066] Furthermore, the control circuit CNT controls the second reference voltage Vref2 so that the value of the second output voltage VO2 output by the second charge pump circuit P2 is set to a target value defined for each of the first and second modes, respectively.

[0067] [Operating characteristics of the voltage supply circuit] Next, the operating characteristics of the voltage supply circuit 100 having the above configuration will be described.

[0068] As previously described, in the first mode, the control circuit CNT causes the first LDO amplifier circuit LDO1 to output a first control voltage VLDO1 from the first output unit X1 in accordance with the reference voltage VREF.

[0069] Furthermore, in the first mode, the control circuit CNT causes the second LDO amplifier circuit LDO2 to output a second control voltage VLDO2 from the second output section X2.

[0070] On the other hand, in the second mode, the control circuit CNT forcibly bypasses the power supply voltage VCC supplied from the power supply S to the first LDO amplifier circuit LDO1, regardless of the reference voltage VREF, and outputs it as the first control voltage VLDO1 from the first output unit X1.

[0071] Furthermore, in the second mode, the control circuit CNT bypasses the power supply voltage VCC supplied from the power supply S to the second LDO amplifier circuit LDO2 and outputs it as the second control voltage VLDO2 from the second output section X2.

[0072] Furthermore, as previously mentioned, the first and second LDO amplifier circuits LDO1 and LDO2 are configured to have a slow load response characteristic.

[0073] As previously described, the first charge pump circuit P1 is supplied with a first control voltage VLDO1 and operates based on the clock signal CLK and the first feedback signal S1, outputting a first output voltage VO1 generated from the first control voltage VLDO1 to the first output terminal TO1.

[0074] Furthermore, as previously described, the second charge pump circuit P2 is supplied with a second control voltage VLDO2 and operates based on the clock signal CLK and the second feedback signal S2, outputting a second output voltage VO2 generated from the second control voltage VLDO2 to the second output terminal TO2.

[0075] As a result of the operation of the voltage supply circuit 100 as described above, predetermined first and second output voltages VO1 and VO2 are output in the first mode and the second mode.

[0076] Here, Figure 3 shows an example of the simulation results of the characteristics of the first output voltage VO1 during writing and erasing. Figure 4 shows an example of the simulation results of the characteristics of the second output voltage VO2 during writing and erasing. Figure 5 shows an example of the simulation results of the characteristics of the second output voltage VO2 during reading.

[0077] Figure 3 shows the relationship between the maximum value of the first output voltage VO1 and the conditions for each write and erase operation. Figure 4 shows the relationship between the minimum value of the second output voltage VO2 and the conditions for each write and erase operation.

[0078] As shown in Figures 3 and 4, simulation results of the characteristics of the first and second output voltages VO1 and VO2 during writing and erasing confirmed that, in the voltage supply circuit 100 according to the first embodiment, the ripple of the first and second output voltages VO1 and VO2 can be reduced by providing the first and second LDO amplifier circuits LDO1 and LDO2 in the first and second charge pump circuits P1 and P2.

[0079] In other words, in the voltage supply circuit 100 according to the first embodiment, the ripple voltage can be reduced by using the first and second LDO amplifier circuits LDO1 and LDO2, which have a slow load response, during write and erase operations (first mode).

[0080] Furthermore, as shown in Figure 5, simulation results of the characteristics of the second output voltage VO2 during readout confirmed that, during readout operation (second mode), the power supply voltage VCC can be bypassed to the first and second output sections X1 and X2 of the first and second LDO amplifier circuits LDO1 and LDO2, respectively, to cope with sharp current changes. In addition, it was confirmed that, during readout operation (second mode), the ripple voltage of the second output voltage VO2 can be reduced because the load capacity of the memory section M of the semiconductor memory device 1000 is large.

[0081] In this way, during read operations, a mode is provided that bypasses the power supply voltage at the output of the LDO amplifier circuit, which is compatible with flash memory macro read operations and reduces the ripple voltage, thereby eliminating the need for capacitance at the output of the LDO amplifier circuit and the charge pump circuit.

[0082] In other words, in the voltage supply circuit 100 according to this first embodiment, the influence of changes in the power supply voltage on the voltage supplied to the charge pump circuit can be suppressed, thereby reducing the ripple of the output voltage of the charge pump circuit.

[0083] [Semiconductor memory devices] Here, Figure 6 shows an example of the configuration of a semiconductor memory device to which the voltage supply circuit 100 according to the first embodiment is applied.

[0084] The semiconductor memory device 1000 includes, for example, a memory section M and a voltage supply circuit 100, as shown in Figure 6. This semiconductor memory device 1000 is, for example, a flash memory such as a NOR-type flash memory.

[0085] The memory section M includes a memory cell array of flash memory.

[0086] Furthermore, the voltage supply circuit 100 is configured to supply a predetermined voltage to the memory section M of the semiconductor memory device 1000.

[0087] Thus, the voltage supply circuit 100 is provided in the semiconductor memory device 1000.

[0088] As previously described, the voltage supply circuit 100 supplies a first output voltage VO1 and a second output voltage VO2 from the first output terminal TO1 and the second output terminal TO2 shown in Figure 1 to the memory unit M, which performs data writing, erasing, and reading operations of the semiconductor memory device 1000.

[0089] As previously described, in the first mode, the control circuit CNT causes the first LDO amplifier circuit LDO1 to output a first control voltage VLDO1 from the first output unit X1 in accordance with the reference voltage VREF.

[0090] Furthermore, in the first mode, the control circuit CNT causes the second LDO amplifier circuit LDO2 to output a second control voltage VLDO2 from the second output section X2.

[0091] On the other hand, in the second mode, the control circuit CNT forcibly bypasses the power supply voltage VCC supplied from the power supply S to the first LDO amplifier circuit LDO1, regardless of the reference voltage VREF, and outputs it as the first control voltage VLDO1 from the first output unit X1.

[0092] Furthermore, in the second mode, the control circuit CNT bypasses the power supply voltage VCC supplied from the power supply S to the second LDO amplifier circuit LDO2 and outputs it as the second control voltage VLDO2 from the second output section X2.

[0093] The first mode is, for example, a mode in which the memory section M of the semiconductor memory device 1000, shown in Figure 6 below, performs a write operation or an erase operation.

[0094] On the other hand, the second mode is, for example, a mode in which the memory section M of the semiconductor memory device 1000 performs a read operation.

[0095] As previously described, the load capacity of the semiconductor storage device 1000 when the memory section M of the semiconductor storage device 1000 is performing a read operation is greater than the load capacity of the semiconductor storage device 1000 when the memory section M of the semiconductor storage device 1000 is performing a write operation or an erase operation.

[0096] In other words, the load capacity of the memory section M of the semiconductor storage device 1000 connected to the first output terminal TO1 and the second output terminal TO2 in the second mode is set to be larger than the load capacity of the memory section M of the semiconductor storage device 1000 connected to the first output terminal TO1 and the second output terminal in the first mode.

[0097] Therefore, as previously described, in the voltage supply circuit 100, during read operation (second mode), the power supply voltage VCC can be bypassed to the first and second output sections X1 and X2 of the first and second LDO amplifier circuits LDO1 and LDO2, thereby enabling response to rapid current changes. Furthermore, during read operation, the load capacity of the memory section M of the semiconductor memory device 1000 is large, which allows for a reduction in the ripple voltage of the second output voltage VO2.

[0098] In other words, with the semiconductor memory device 1000 to which the voltage supply circuit 100 according to the first embodiment is applied, the influence of changes in the power supply voltage on the voltage supplied to the charge pump circuit can be suppressed, thereby reducing the ripple of the output voltage of the charge pump circuit. As a result, write, erase, and read operations in the memory section M of the semiconductor memory device 1000 can be performed more appropriately.

[0099] (Second embodiment) In the first embodiment described above, an example of the configuration of a voltage supply circuit was explained. However, the configuration of this voltage supply circuit is not limited to this. Therefore, in this second embodiment, other examples of the configuration of a voltage supply circuit will be described.

[0100] In the following description of the voltage supply circuit according to the second embodiment, the configuration of the voltage supply circuit that is denoted by the same reference numerals as in the first embodiment will not be described.

[0101] Here, Figure 7 shows an example of the configuration of a voltage supply circuit according to the second embodiment. Figure 8A is a diagram illustrating the load response characteristics of the second LDO circuit according to the second embodiment. Figure 8B is a diagram illustrating the readout operation load response characteristics of the third LDO circuit according to the second embodiment.

[0102] Figure 8A shows the load response characteristics during write and erase operations. Figure 8B shows the load response characteristics during read operations.

[0103] [Voltage supply circuit] For example, as shown in Figure 7, the voltage supply circuit 200 according to the second embodiment further comprises a third LDO amplifier circuit LDO3 and a third LDO voltage divider circuit R3, compared to the configuration of the voltage supply circuit 100 according to the first embodiment shown in Figure 1.

[0104] [Third LDO voltage divider circuit] The third LDO voltage divider circuit R3 is connected, for example, between the third output section X3 of the third LDO amplifier circuit LDO3 and the ground potential VGND, as shown in Figure 7.

[0105] As shown in Figure 7, for example, this third LDO voltage divider circuit R3 outputs a third LDO divided voltage VR3, which is obtained by dividing the voltage between the third output section X3 of the third LDO amplifier circuit LDO3 and the ground potential VGND by the third LDO voltage division ratio, from the third LDO output voltage divider terminal TR3.

[0106] This third LDO voltage divider circuit R3 includes, for example, a fifth LDO voltage divider resistor R3a and a sixth LDO voltage divider resistor R3b, as shown in Figure 7.

[0107] The fifth LDO voltage divider resistor R3a has one end connected to the third output section X3 of the third LDO amplifier circuit LDO3, and the other end connected to the third LDO output voltage divider terminal TR3.

[0108] The sixth LDO voltage divider resistor R3b has one end connected to the third LDO output voltage divider terminal TR3 and the other end connected to the ground potential VGND.

[0109] [Third LDO Amplifier Circuit] The third LDO amplifier circuit LDO3 is supplied with a power supply voltage VCC from the power supply S, and outputs a third control voltage VLDO3 from the third output section X3 according to the reference voltage VREF.

[0110] In particular, the third LDO amplifier circuit LDO3 controls the third control voltage VLDO3 so that the third divided voltage VR3, obtained by dividing the third control voltage VLDO3 by the third LDO voltage divider circuit R3 according to the third voltage division ratio, approaches the reference voltage VREF.

[0111] In the voltage supply circuit 200 according to this second embodiment, the second charge pump circuit P2 is supplied with a second control voltage VLDO2 or a third control voltage VLDO3, operates based on a clock signal CLK, and outputs a second output voltage VO2 generated from the second control voltage VLDO2 or the third control voltage VLDO3 to the second output terminal TO2.

[0112] Furthermore, in this second embodiment, the circuit CNT controls the operation of the first LDO amplifier circuit LDO1, the second LDO amplifier circuit LDO2, and the third LDO amplifier circuit LDO3.

[0113] In a preset first mode, the control circuit CNT causes the first LDO amplifier circuit LDO1 to output a first control voltage VLDO1 from the first output unit X1, the second LDO amplifier circuit LDO2 to output a second control voltage VLDO2 from the second output unit X2, and the operation of the third LDO amplifier circuit LDO3 to stop, according to the reference voltage VREF.

[0114] On the other hand, in a preset second mode different from the first mode, the control circuit CNT causes the first LDO amplifier circuit LDO1 to output a first control voltage VLDO1 from the first output unit X1, the third LDO amplifier circuit LDO2 to output a third control voltage VLDO3 from the third output unit X3, and the operation of the second LDO amplifier circuit LDO2 to be stopped, in accordance with the reference voltage VREF.

[0115] Here, the load response (Figure 8A) of the second LDO amplifier circuit LDO2, which operates during write and erase operations (first mode) and outputs a second control voltage VLDO2, is set to be slower than the load response (Figure 8A) of the third LDO amplifier circuit LDO3, which operates during read operations (second mode) and outputs a third control voltage VLDO3.

[0116] Furthermore, the other configurations and operation of the voltage supply circuit 200 in this second embodiment are the same as those of the voltage supply circuit 100 in the first embodiment.

[0117] Figure 9 shows an example of the simulation results of the characteristics of the second output voltage VO2 during readout.

[0118] As shown in Figure 9, simulation results of the characteristics of the second output voltage VO2 during readout confirmed that, in the voltage supply circuit 200 according to this second embodiment, the fast load response of the third LDO amplifier circuit LDO3 during readout operation (second mode) can cope with sharp current changes. Furthermore, it was confirmed that the ripple voltage of the second output voltage VO2 can be reduced during readout operation (second mode) because the load capacity of the memory section M of the semiconductor memory device 1000 is large.

[0119] As described above, in the voltage supply circuit 200 according to this second embodiment, one of the second and third control voltages VLDO2 and VLDO3 output by the second and third LDO amplifier circuits LDO2 and LDO3 is applied to the second charge pump circuit P2. The control circuit CNT then switches between the third LDO amplifier circuit LDO3, which has a fast load response, and the second LDO amplifier circuit LDO2, which has a slow load response, depending on the current profile of the second charge pump circuit P2.

[0120] This enables the system to handle readout operations (second mode) that require a fast load response, and by reducing the ripple voltage, it eliminates the need for capacitance at the output of the LDO amplifier circuit and the charge pump circuit.

[0121] As described above, the voltage supply circuit according to this second embodiment suppresses the influence of changes in the power supply voltage on the voltage supplied to the charge pump circuit, thereby reducing the ripple in the output voltage of the charge pump circuit.

[0122] Furthermore, the voltage supply circuit 200 according to this second embodiment is also applied to the semiconductor memory device 1000 shown in Figure 6, as described above, similar to the voltage supply circuit 100 according to the first embodiment.

[0123] In other words, according to the semiconductor memory device 1000 to which the voltage supply circuit 200 according to the second embodiment is applied, the influence of changes in the power supply voltage on the voltage supplied to the charge pump circuit can be suppressed, thereby reducing the ripple of the output voltage of the charge pump circuit.

[0124] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of Symbols]

[0125] 100, 200V voltage supply circuit 1000 Semiconductor memory devices LDO1 First LDO Amplifier Circuit LDO2 Second LDO Amplifier Circuit OSC Oscillator Circuit P1 First charge pump circuit P2 Second charge pump circuit CNT control circuit R1 First LDO voltage divider circuit R2 Second LDO voltage divider circuit RO1 First Output Voltage Divider Circuit RO2 Second Output Voltage Divider Circuit CMP1 First Comparator CMP2 Second Comparator

Claims

1. A first LDO amplifier circuit receives a power supply voltage from a power source and outputs a first control voltage from a first output section according to a preset reference voltage, A second LDO amplifier circuit receives the power supply voltage from the power supply and outputs a second control voltage from the second output unit according to the reference voltage, An oscillator circuit that generates and outputs a clock signal, A first charge pump circuit is supplied with the first control voltage, operates based on the clock signal, and outputs a first output voltage generated from the first control voltage to a first output terminal. A second charge pump circuit is supplied with the second control voltage and operates based on the clock signal, outputting a second output voltage generated from the second control voltage to a second output terminal. The system comprises a control circuit that controls the operation of the first LDO amplifier circuit and the second LDO amplifier circuit, A voltage supply circuit characterized by the following features.

2. The aforementioned control circuit is In a preset first mode, the first LDO amplifier circuit is caused to output the first control voltage from the first output unit, and the second LDO amplifier circuit is caused to output the second control voltage from the second output unit, according to the reference voltage. On the other hand, in a preset second mode different from the first mode, regardless of the reference voltage, the power supply voltage supplied from the power supply is forcibly bypassed to the first LDO amplifier circuit and output as the first control voltage from the first output unit, and the power supply voltage supplied from the power supply is forcibly bypassed to the second LDO amplifier circuit and output as the second control voltage from the second output unit. The voltage supply circuit according to feature 1.

3. The aforementioned control circuit is The load response of the first LDO amplifier circuit and the second LDO amplifier circuit in the first mode is controlled to be slower than the load response of the first LDO amplifier circuit and the second LDO amplifier circuit in the second mode. The voltage supply circuit according to feature 2.

4. The aforementioned control circuit is In the first mode, the load response of the first LDO amplifier circuit and the second LDO amplifier circuit is controlled to be slowed down by reducing the drive current that drives the first LDO amplifier circuit and the second LDO amplifier circuit. On the other hand, in the second mode, the load response of the first LDO amplifier circuit and the second LDO amplifier circuit is controlled to be faster by increasing the drive current that drives the first LDO amplifier circuit and the second LDO amplifier circuit. The voltage supply circuit according to feature 3.

5. The voltage supply circuit is provided in the semiconductor memory device, The voltage supply circuit supplies the first output voltage and the second output voltage from the first output terminal and the second output terminal to the memory unit that performs data writing, erasing, and reading operations of the semiconductor memory device. The voltage supply circuit according to feature 1.

6. The first mode is a mode in which the memory portion of the semiconductor storage device performs a write operation or an erase operation. The second mode is a mode in which the memory portion of the semiconductor storage device performs a read operation. The voltage supply circuit according to claim 5.

7. In the second mode, the load capacity of the memory portion of the semiconductor storage device connected to the first and second output terminals is greater than the load capacity of the memory portion of the semiconductor storage device connected to the first and second output terminals in the first mode. The voltage supply circuit according to feature 6.

8. The power supply voltage is supplied from the power supply, and the circuit comprises a third LDO amplifier circuit that outputs a third control voltage from a third output unit according to the reference voltage, The second charge pump circuit is supplied with the second control voltage or the third control voltage and operates based on the clock signal, outputting a second output voltage generated from the second control voltage or the third control voltage to the second output terminal. The control circuit controls the operation of the first LDO amplifier circuit, the second LDO amplifier circuit, and the third LDO amplifier circuit. The voltage supply circuit according to feature 1.

9. The load response of the second LDO amplifier circuit is slower than the load response of the third LDO amplifier circuit. The voltage supply circuit according to feature 8.

10. The aforementioned control circuit is In a preset first mode, the first LDO amplifier circuit is made to output the first control voltage from the first output unit, the second LDO amplifier circuit is made to output the second control voltage from the second output unit, and the operation of the third LDO amplifier circuit is stopped, according to the reference voltage. On the other hand, in a preset second mode different from the first mode, the first LDO amplifier circuit is made to output the first control voltage from the first output unit, the third LDO amplifier circuit is made to output the third control voltage from the third output unit, and the operation of the second LDO amplifier circuit is stopped, according to the reference voltage. The voltage supply circuit according to feature 9.

11. The first output voltage is a positive voltage higher than the ground potential. The voltage supply circuit according to claim 1, characterized in that the second output voltage is a negative voltage lower than the ground potential.

12. A memory section including a memory cell array of flash memory, The memory unit is equipped with a voltage supply circuit that supplies voltage to the memory unit, The aforementioned voltage supply circuit is A first LDO amplifier circuit receives a power supply voltage from a power source and outputs a first control voltage from a first output section according to a preset reference voltage, A second LDO amplifier circuit receives the power supply voltage from the power supply and outputs a second control voltage from the second output unit according to the reference voltage, An oscillator circuit that generates and outputs a clock signal, A first charge pump circuit is supplied with the first control voltage, operates based on the clock signal, and outputs a first output voltage generated from the first control voltage to a first output terminal. A second charge pump circuit is supplied with the second control voltage and operates based on the clock signal, outputting a second output voltage generated from the second control voltage to a second output terminal. The system comprises a control circuit that controls the operation of the first LDO amplifier circuit and the second LDO amplifier circuit, A semiconductor memory device characterized by the following features.

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