Method and device for calibrating antenna array in wireless network node and network node

Abstract

A method for calibrating an antenna array in a wireless network node (100) is disclosed, the wireless network node comprising a plurality of antenna branches (110), each of the plurality of antenna branches comprising a corresponding antenna element (130). The method comprises repeatedly transmitting (508) slices of a fountain-coded sequence to the corresponding antenna element via the plurality of antenna branches, and for each of the plurality of antenna branches, selecting (516) the transmitted slice as a feedback signal via a return path (214) and determining (520) a signal quality of the feedback signal until the signal quality of the feedback signal for each antenna branch is greater than a threshold level. The method further comprises performing (512) antenna calibration based on the feedback signal for each antenna branch. Related apparatus, computer programs, and computer program products are disclosed.

Description

Technical Field

[0001] The present disclosure relates to wireless communication systems, and in particular, to antenna calibration systems / methods in multi-antenna communication devices. Background Art

[0002] The 5G wireless standard includes support for massive multiple-input, multiple-output (MIMO) antenna systems in wireless network nodes such as base stations and radios. Massive MIMO offers advantages for wireless communications due to improved spectral and energy efficiency.

[0003] Active Antenna Systems (AAS) are an implementation of massive MIMO that integrates RF transceivers and antennas to achieve compact size. AAS utilizes antenna arrays with beamforming to implement multi-user MIMO (MU-MIMO) to improve throughput or expand coverage. Beamforming is achieved by calculating complex weights and applying them to the signals radiated by multiple different antennas. The weights are selected to cause the signals transmitted by the different antennas to combine at a predetermined location or direction, resulting in selectively increased or decreased signal gain at the selected location or direction.

[0004] To obtain the full benefits of using AAS, for example to ensure that functions such as beam steering and / or sidelobe cancellation are being performed correctly by the system, it is best to carefully calibrate the antenna array and RF chain in the system. Due to manufacturing tolerances, it is difficult to determine the appropriate complex weights to use without proper knowledge of the channel conditions between the transmitter and the antenna. In addition, the channel conditions between the transmitter and the antenna can change over time, such as as a result of temperature changes or parameter drift over time.

[0005] The accuracy and robustness of antenna calibration directly affect the performance of the system using AAS. To this end, antenna calibration (AC) can be performed to enhance the effectiveness of AAS. Typically, AC includes both uplink AC and downlink AC. For downlink AC, the transmitter (TX) chain can be configured to transmit signals modulated in different domains such as time domain, frequency domain or code domain to the antenna interface transceiver (AI-TRX). Code domain multiplexing (CDM) is more popular than other methods because it requires fewer calibration resources (in terms of time and frequency) and can provide slightly better decoding gain. Summary of the Invention

[0006] Conventional antenna calibration systems / methods may suffer from a low signal-to-noise ratio in the calibration feedback signal, which may reduce the efficiency and / or effectiveness of the antenna calibration. In addition, the low SNR of the feedback signal may prompt the AC to restart, further reducing the efficiency of the AC.

[0007] Some embodiments described herein use fountain decoding sequences to generate calibration signals. In some embodiments, this approach can provide increased decoding gain, improved robustness to low SNRs, and / or enhanced calibration efficiency. Some embodiments can utilize low-complexity zero-forcing (ZF) or minimum mean square error (MMSE) decoding. Furthermore, some embodiments can achieve energy savings within AC accuracy constraints.

[0008] Some embodiments provide a method for calibrating an antenna array in a wireless network node (100), the wireless network node (100) comprising a plurality of antenna branches (110), each of the plurality of antenna branches comprising a corresponding antenna element (130). The method comprises repeatedly transmitting (508) slices of a fountain-coded sequence to the corresponding antenna element via the plurality of antenna branches, and for each of the plurality of antenna branches, selecting (516) the transmitted slice as a feedback signal via a return path (214) and determining (520) a signal quality of the feedback signal until the signal quality of the feedback signal for each antenna branch is greater than a threshold level. The method further comprises performing (512) antenna calibration based on the feedback signal for each antenna branch.

[0009] In some embodiments, transmitting the slices of the fountain coded sequence comprises transmitting consecutive slices of the fountain coded sequence until a matrix GG* formed by a generator matrix G is non-singular, wherein the generator matrix G comprises elements c n，m An N×M matrix, where N represents the number of antenna branches of the multiple antenna branches, M represents the number of received symbols of the fountain decoding sequence, and m represents the mth symbol of the fountain decoding sequence on the antenna branch n in the multiple antenna branches where the number of the multiple antenna branches is N.

[0010] In some embodiments, the method further includes generating a fountain coded sequence, slicing the fountain coded sequence to obtain slices of the fountain coded sequence, wherein the slices of the fountain coded sequence include at least one symbol of the fountain coded sequence, adding a cyclic prefix to the at least one symbol of the fountain coded sequence, and inserting the slices of the fountain coded symbols into a downlink signal for transmission.

[0011] In some embodiments, element c n，m including a spreading code, and wherein generating the fountain decoding sequence comprises using the spreading code c n，m to expand at least one symbol.

[0012] In some embodiments, generating a fountain coding sequence includes generating a symbol of length N and repeating the symbol to obtain a symbol of length N. seq >N sequence.

[0013] In some embodiments, generating the fountain decoding sequence includes generating a symbol for branch n according to the following equation:

[0014]

[0015] Where u and q represent the parameters of the Zadoff-Chu sequence.

[0016] In some embodiments, generating a fountain decoding sequence includes generating a length N according to the following equation seq Zadoff-Chu sequence:

[0017]

[0018] where u n is the root of the Zadoff-Chu sequence of branch n, and q represents the parameter of the Zadoff-Chu sequence.

[0019] In some embodiments, determining the signal quality of the feedback signal includes determining a signal-to-noise ratio (SNR) of the feedback signal.

[0020] In some embodiments, determining the signal-to-noise ratio of the feedback signal includes performing a blind SNR estimation.

[0021] In some embodiments, performing blind estimation includes determining the SNR according to the following formula:

[0022]

[0023] where ρ is the SNR, yes The jth element of is the estimated value of the symbol of the fountain decoding sequence at the nth antenna branch, and N fft is the size of the Fast Fourier Transform matrix used to generate the symbols.

[0024] In some embodiments, the method further includes estimating the fountain coding sequence from the feedback signal using a zero-forcing receiver or a minimum mean square error receiver.

[0025] In some embodiments, estimating the fountain coding sequence from the feedback signal using a zero-forcing receiver includes estimating the fountain coding sequence according to the following formula:

[0026]

[0027] where r m Represents the mth element of the received signal, G represents the element c n，mA generator matrix of a matrix where N represents the number of antenna branches of the plurality of antenna branches, M represents the number of received symbols of the fountain decoding sequence, m represents the mth symbol of the fountain decoding sequence on branch n of the plurality of antenna branches where the number of the plurality of antenna branches is N, and represents the estimated value of the mth symbol of the fountain decoding sequence on branch n.

[0028] In some embodiments, estimating the fountain decoding sequence from the feedback signal using a minimum mean square error receiver includes estimating the fountain decoding sequence according to the following formula:

[0029]

[0030] where r m Represents the mth element of the received signal, G represents the element c n，m A generator matrix of an N×M matrix, where N represents the number of antenna branches of the plurality of antenna branches, M represents the number of received symbols of the fountain decoding sequence, and m represents the mth symbol of the fountain decoding sequence on branch n of the plurality of antenna branches where the number of the plurality of antenna branches is N. denotes the estimated value of the mth symbol of the fountain coded sequence on branch n, and p is the signal-to-noise ratio (SNR).

[0031] In some embodiments, the fountain coded sequence includes a plurality of symbols generated by orthogonal frequency division multiplexing.

[0032] A network node (100) according to some embodiments includes a processor (106), a wireless transceiver (120) coupled to the processor, and a memory (108) coupled to the processor, the memory including machine-readable program instructions that, when executed by the processor, cause the network node to perform operations comprising repeatedly transmitting (508) slices of a fountain-decoded sequence to respective antenna elements via a plurality of antenna branches, and for each antenna branch of the plurality of antenna branches, selecting (516) the transmitted slice as a feedback signal via a return path (214) and determining (520) a signal quality of the feedback signal until the signal quality of the feedback signal for each antenna branch is greater than a threshold level, and performing (512) antenna calibration based on the feedback signal for each antenna branch.

[0033] A computer program includes program code to be executed by a processor (106) of a network node (100), the network node (100) being configured to operate in a communication network, whereby execution of the program code causes the network node (100) to perform operations comprising repeatedly transmitting (508) slices of a fountain decoded sequence to corresponding antenna elements via a plurality of antenna branches, and for each antenna branch of the plurality of antenna branches, selecting (516) the transmitted slice as a feedback signal via a return path (214) and determining (520) a signal quality of the feedback signal until the signal quality of the feedback signal for each antenna branch is greater than a threshold level, and performing (512) antenna calibration based on the feedback signal for each antenna branch.

[0034] A computer program product includes a non-transitory storage medium including program code to be executed by a processor (106) of a network node (100), the network node (100) being configured to operate in a communication network, whereby execution of the program code causes the network node (100) to perform operations comprising repeatedly transmitting (508) slices of a fountain decoded sequence to corresponding antenna elements via a plurality of antenna branches, and for each antenna branch of the plurality of antenna branches, selecting (516) the transmitted slice as a feedback signal via a return path (214) and determining (520) a signal quality of the feedback signal until the signal quality of the feedback signal for each antenna branch is greater than a threshold level, and performing (512) antenna calibration based on the feedback signal for each antenna branch.

[0035] Other systems, methods, and / or computer program products according to embodiments of the invention will be or become apparent to one skilled in the art upon reviewing the following figures and detailed description. It is intended that all such additional systems, methods, and / or computer program products be included within this description, be within the scope of the invention, and be protected by the accompanying claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1A is a block diagram of a network node of a wireless communication system.

[0037] Figure 1B is a block diagram illustrating a transceiver of a network node of a wireless communication system including an antenna array.

[0038] Figure 2 The transmission of a calibration sequence over multiple antenna branches of a transceiver of a network node of a wireless communication system is described.

[0039] Figure 3 Describes the format of the slices of the calibration sequence.

[0040] Figure 4 Describes the loss of calibration data in an antenna calibration system.

[0041] Figure 5A and 5B is a flow chart illustrating the operation of the system / method according to some embodiments.

[0042] Figure 6 and 7 is a graph illustrating simulation results according to some embodiments. DETAILED DESCRIPTION

[0043] The inventive concept will now be described more fully below with reference to the accompanying drawings, in which examples of embodiments of the inventive concept are shown. However, the inventive concept can be embodied in many different forms, and the inventive concept should not be interpreted as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that this disclosure will be exhaustive and complete and will fully convey the scope of the inventive concept to those skilled in the art. It should also be noted that these embodiments are not mutually exclusive. Components from one embodiment may be assumed by default to be present in / used in another embodiment.

[0044] The following description presents various embodiments of the disclosed subject matter. These embodiments are presented as teaching examples and should not be interpreted as limiting the scope of the disclosed subject matter. For example, some details of the described embodiments may be modified, omitted, or elaborated without departing from the scope of the described subject matter.

[0045] Antenna calibration (AC) is performed to enhance the coherence of active antenna systems. Downlink (DL) AC is performed by transmitting a calibration signal and feeding it back as a feedback signal for analysis. Typically, downlink AC is performed by transmitting the calibration signal during a normal downlink timeslot. Transmitting at other times, such as during a guard period (GP), may cause DL AC to not meet the 3GPP requirement of "TX OFF" during that time.

[0046] When transmitting the calibration signal in the normal DL timeslot, the DL AC must stop the DL traffic and insert the calibration signal sequence into the downlink signal. With appropriate scheduling in the baseband, the impact on the DL traffic can be reduced, but it cannot be completely removed. Although CDM is more efficient than other modulation techniques, typical CDM-based sequences do not have sufficient decoding gain to handle very low signal-to-noise ratios (SNRs). In addition, CDM-based sequences can be easily corrupted. That is, if the code does not contain a complete sequence, orthogonality may be lost and the calibration process may have to be restarted.

[0047] An incomplete calibration sequence can be indicated by a low SNR in the feedback signal. There are many functionalities in the AAS that can cause low SNR, such as link errors, loss of control words, erroneous TDD switching, or power fallback / shutdown at high temperatures. Restarting the AC may be undesirable because the system may have difficulty recovering from the error in a short period of time.

[0048] The SNR can be improved by changing the transmitter link budget. However, transmitter output power may be subject to strict constraints to avoid interference with adjacent infrastructure. Changing the AC link budget for a portion of the transmitted signal may be undesirable. Therefore, it is desirable for the calibration signal to have higher decoding gain and / or be more robust to low SNR. It is also desirable for the AC system to be able to adapt to dynamic traffic with flexible lengths. Furthermore, it is desirable for the AC system to have low complexity for ease of implementation.

[0049] Some embodiments described herein provide antenna calibration systems / methods that use fountain decoding sequences to generate calibration signals. First, a long CDM sequence is generated using fountain codes. Because fountain codes are used to generate the calibration signal, the decoding gain of the signal increases as more symbols are received. In addition, because fountain codes are used, the code can be decoded even if some slices are lost due to low SNR. Second, the sequence can be divided into several slices to accommodate null symbols. In some embodiments, the sequence can be extended to provide higher decoding gain. Finally, some embodiments utilize recursive decoding to reduce complexity.

[0050] Although the antenna calibration system / method is described herein in the context of downlink AC, the system / method described herein can also be applied to uplink AC, which is generally less complex than downlink AC.

[0051] Figure 1A is a block diagram of an exemplary network node 100 of a wireless communication system according to some embodiments, and Figure 1B is a block diagram illustrating an exemplary transceiver 120 of a network node 100 including an antenna array 150 according to some embodiments.

[0052] refer to Figure 1A , a network node 100 of a wireless communication system includes a wireless transceiver 120 configured to provide communication with other wireless devices over a communication network, a processor 106 coupled to the wireless transceiver 120, and a memory 108 coupled to the processor 106. The memory 108 may include computer-readable program code that, when executed by the processor 106, causes the processor 106 to perform operations according to the embodiments disclosed herein. In other embodiments, the processor 106 may be defined as including the memory, so that the memory 108 may not be provided separately.

[0053] The wireless transceiver 120 includes various subsystems that operate together to transmit / receive wireless signals over the air interface. Specifically, the wireless transceiver 120 includes a baseband processor 122, a transmit / receive circuit system 124, an analog front end (AFE) circuit system 126, an analog filter unit 128, and an antenna array 150.

[0054] refer to Figure 1B , which illustrates the elements of the wireless transceiver 120 in more detail. As shown therein, the antenna array 150 includes a plurality of antenna elements 130A-C, which are fed by a corresponding plurality of antenna branches 110A-C coupled between the antenna elements 130A-C and the baseband processor 122. Each antenna branch 110A-C includes a plurality of elements, including transmit / receive circuits 124A-C, analog front ends 126A-C, and analog filters 128A-C. Each of the antenna branches 110A-C forms a forward path from the baseband processor 122 to the corresponding antenna element 130A-C. Thus, the antenna calibration signals generated by the baseband processor 122 are transmitted to the antenna elements 130A-C on the forward path 212 via the corresponding antenna branches 110A-C. Although in Figure 1B Three antenna branches 110A-C and antenna elements 130A-C are illustrated in FIG, but it will be appreciated that a system according to some embodiments may include more than three antenna branches and associated antenna elements.

[0055] The wireless transceiver 120 further includes a return path 214 coupled to each of the antenna elements 130A-C via a corresponding coupler 140A-C and a combiner 145 that combines the signals from the couplers 140A-C. The antenna calibration signal received by the combiner 145 from the couplers 140A-C is passed to the baseband processor 122 via the TX / RX switch and the antenna interface transceiver 124D.

[0056] During the antenna calibration (AC) process, the calibration signals transmitted to the antenna elements 130A-C via the forward path are fed back to the baseband 122 as feedback signals via the return path 214. The baseband processor 122 analyzes the feedback signals to determine the channel characteristics of each of the antenna branches 110A-C. The channel characteristics of the antenna branches 110A-C are used by the baseband processor 122 to adjust the antenna weights applied to the signals transmitted on the antenna branches 110A-C to improve the performance of the active antenna system.

[0057] According to some embodiments, a fountain code is used to generate the calibration signal. Fountain codes (also known as rateless erasure codes) represent a class of erasure codes. Erasure codes are forward error correction (FEC) codes used in situations where bit erasures are more likely to occur than bit errors. In general, erasure codes transform a message of k symbols into a longer message (codeword) of n symbols, such that the original message can be recovered from a subset of the n symbols.

[0058] Fountain codes are capable of generating a potentially unlimited sequence of coded symbols from a given set of source symbols, such that the original source symbols can ideally be recovered from any subset of coded symbols of a size at least equal to the number of source symbols. The term "fountain" or "rateless" refers to the fact that, unlike typical erasure codes, fountain codes do not exhibit a fixed code rate.

[0059] Figure 2 CDM signal generation according to some embodiments is described, where s n (n=0, ..., N-1) represents an orthogonal frequency domain multiplexing (OFDM) symbol of antenna branch n, where N represents the number of antenna branches of the plurality of antenna branches. An OFDM symbol consists of N fft samples, which can be expressed as:

[0060] s n =F * S n [1]

[0061] Where F is a matrix with dimension N fft ×N fft The Fourier matrix of S n is a vector of branches n to collect all modulation symbols at active bins. The number of active bins is determined by the bandwidth and subcarrier spacing. For different branches (n≠n'), and therefore, S n and S n' The bins may be either different or the same. However, it would be better if mutually uncorrelated symbols were used for the different branches to reduce the peak-to-average ratio (PAR) of the combined signal. Without loss of generality, the values ​​of the active bins will be constant modulus sequences such as Zadoff-Chu or Gold sequences. This assumption facilitates the SNR estimation used at the receiver side.

[0062] To avoid inter-symbol interference (ISI) and force linear convolution to circular convolution, as Figure 2 As shown in the shaded box, the additional N cp samples are added to each OFDM symbol as a cyclic prefix (CP). The length of the CP should be greater than the length of Figure 1B The maximum delay introduced by filter 128A in the TX chain is shown in FIG.

[0063] As shown in Equation 2, the OFDM symbol is multiplied by the spreading code:

[0064] [x n，0 , x n，1 ,…,x n,m ]=[c n,0 s n , c n，1 s n ,...,c n,m s n ] [2]

[0065] where x n，m represents the mth symbol of branch n, and m≥N. c n，m Represents one chip (real or complex) of the m-th symbol of branch n.

[0066] In the expansion symbol x n，m After being transmitted to the antenna array 130, Figure 1B As shown in FIG, the signals are combined at combiner 145 and fed back to antenna interface transceiver (AI-TRX) 124D. The received signal is represented as shown in Equation 3:

[0067]

[0068] where w m is additive white Gaussian noise (AWGN), and h n is the channel response of branch n. The operator represents the circular convolution between the two vectors. Summing over all steps, the received signal can thus be expressed in equation [4]:

[0069] [r0, r1, ..., r m ]=[s′0,s′1…,s′ N-1 ]G+[w0,w1,…,w m ] [4]

[0070] where the generator matrix is ​​given by Equation 5 as:

[0071]

[0072] Signal s′ n It consists of a calibration signal and a channel response, namely:

[0073] s′ n =h n ☉s n [6].

[0074] The signal of branch n [x n，0 , xn，1 ,...,x n，m ] can be divided into several slices with different sizes. Figure 3 This illustrates inserting a slice into DL traffic data. The darker blocks indicate the margin between AC symbols and DL traffic data. The size of each slice depends on the number of null symbols available in the baseband. This approach facilitates baseband scheduling and provides increased flexibility for dynamic traffic.

[0075] Assuming that no symbols are dropped due to low SNR and the matrix G is full rank, the receiver can recover s using techniques such as zero forcing (ZF) or minimum mean square error (MMSE). n ZF reception can be performed according to Equation 7a and MMSE reception can be performed according to Equation 7b:

[0076]

[0077] in is s′ n is an estimate of , and ρ is the signal-to-noise ratio (SNR).

[0078] Note (GG * ) -1 or (GG * +1 / ρ) -1 The complexity is O(N 3 ), which may be prohibitive if N is large. Some embodiments provide a recursive algorithm for performing fast decoding. The exemplary recursive algorithm is described below with respect to ZF reception. However, it can be directly extended to MMSE.

[0079] Assume that G consists of two parts, namely G=[G A G B ], where G A represents the symbol received in the past, and G B is the newly received symbol, as in equation [8]:

[0080]

[0081] Since we have already calculated in the previous step and With very low dimensions (in the case of adding only one symbol, it could be a scalar division), the complexity of Equation 8 is only O(N 2 ). In addition, if G A is an orthogonal matrix, the calculation can be simplified to the form shown in equation [9]:

[0082]

[0083] If the spreading code includes a set of orthogonal sequences, the recursive algorithm can be started after the orthogonal sequences have been collected, thereby significantly reducing the complexity.

[0084] As mentioned above, fountain codes are rateless codes with potentially infinite code length. In this case, assume m = ∞. At each AC event, a new slice of fountain-coded symbols is added. As more symbols are received, the SNR at the receiver is increased. In addition to improving the SNR (or explicitly, better AC accuracy), the use of fountain codes also provides the ability to recover symbols even if some symbols are lost due to low SNR. Figure 4 An example of this situation is shown, where the symbol r is not received. i+2 and symbol r i+6 The use of fountain decoding sequences ensures that the AC can survive occasional data loss without having to be restarted.

[0085] The process of receiving calibration and processing calibration symbols at the baseband processor 122 can be described as follows.

[0086] First, if no new symbols are received at the antenna interface transceiver 124D, the baseband processor 122 will not update the SNR estimate and will wait for the next AC event.

[0087] Second, if the newly received symbol consists only of noise, the receiver will discard the new symbol and wait for the next AC event.

[0088] Once all antenna branches 110A-C have achieved a sufficiently good SNR to enable the operation of the AC algorithm, the process of transmitting and receiving calibration symbols is terminated, and the baseband processor 122 will continue to execute the AC algorithm based on the received calibration symbols.

[0089] SNR estimation is an important factor in determining when the AC algorithm can be successfully executed. Current SNR estimation requires delay / phase alignment, which is implemented in the AC algorithm. To avoid repeating the process in the AC algorithm, some embodiments perform blind SNR estimation. Considering that the modulation symbols at the active bin are constant modulus, and The kurtosis SNR estimate can be expressed as shown in Equation 10:

[0090]

[0091] in, and yes The jth element of .

[0092] Now about Figure 5A and 5BThe operation of the system / method according to some embodiments is described by using a flowchart of FIG. Figure 5A and 5B The described operation can be used by Figure 1A and 1B One or more devices of the device described in are executed.

[0093] Figure 5A Simplified operation of the system / method according to some embodiments is described in [ 5 ]. As shown therein, the operation includes repeatedly transmitting (block 508) slices of a fountain-coded sequence to corresponding antenna elements via a plurality of antenna branches, selecting (block 516) the transmitted slices as feedback signals via a return path for each of the plurality of antenna branches, and determining (block 520) the signal quality of the feedback signals. At block 525, the system / method checks to see if the last branch has been processed, and if not, the operation returns to block 516 to select the next feedback signal. The operations of blocks 516, 520, and 525 are repeated until the system / method determines at block 535 that the signal quality of the feedback signals for each antenna branch is greater than a threshold level. If so, the system / method performs (block 512) antenna calibration based on the feedback signals for each antenna branch.

[0094] exist Figure 5B The operation of the system / method according to some embodiments is described in more detail in the flowchart of FIG. Figure 5B Operation begins at block 502, where the baseband processor 122 initializes a target SNR threshold value SNR thr The method can also set the variables of each antenna branch to FALSE (such as doneReceiving n ), which indicates whether the system has received a calibration signal with a high enough SNR to perform antenna calibration on the nth branch. The method can also initialize variables for each branch (such as SNR max,n ) represents the maximum SNR of the feedback signal received on the n-th branch.

[0095] At block 504, the system / method generates a seq >>N fountain decoding sequence, where N represents the number of antenna branches of the plurality of antenna branches. The order of the operations of blocks 502 and 504 may be reversed.

[0096] After initialization and sequence generation, the operation checks to see if the baseband processor 122 has completed receiving the calibration signal with sufficient SNR on each antenna branch at block 506. If so, the receive operation terminates and the baseband processor 122 proceeds to the next step of the antenna calibration process at block 512, such as estimating the phase and amplitude of each branch based on the received calibration signal.

[0097] If the baseband processor 122 has not completed reception on all antenna branches, operation continues with a first loop including blocks 508, 509, and 510, where the baseband processor 122 transmits slices of the fountain-decoded sequence via the forward patch 212 (block 508) and receives the combined feedback signal via the return path 214 (block 509) until the baseband processor 122 determines at block 510 that the N×N matrix GG* is non-singular. Figure 1B , the transmitted signals are combined at the combiner 145 and the combined feedback signal is fed back to the baseband processor 122 via the return path 214 .

[0098] Reference again Figure 5B , operation then proceeds to block 514, where each of the received signals is processed by the baseband processor 122. At block 514, the system / method determines whether the last antenna branch has been processed, and if so, operation returns to block 506, which again determines whether the baseband processor 122 has completed receiving calibration signals with sufficient SNR on each antenna branch to continue the AC algorithm.

[0099] If the last antenna branch has not been processed, operation proceeds to block 516 where the baseband processor 122 selects a feedback signal for the next branch. The baseband processor 122 determines at block 518 whether processing of the selected branch has been completed. For example, the calibration signal for the selected branch may have exceeded the target SNR threshold (SNR ) based on reception of an earlier slice of the calibration signal. thr If so, operation returns to block 516 to select the next branch.

[0100] If processing of the selected finger has not yet completed, operation proceeds to block 520 where the baseband processor 122 determines whether the SNR of the selected finger is greater than a target SNR threshold SNR thr If so, the baseband processor 122 marks the processing of the selected branch as complete (e.g., by setting the variable doneReceiving for the selected branch to n is set equal to TRUE), and operation returns to block 514 to select the next branch.

[0101] If the baseband processor 122 determines at block 520 that the SNR of the selected branch has not exceeded the target SNR threshold, operation proceeds to block 524, where the baseband processor 122 determines whether the new SNR of the branch is greater than the previously determined maximum SNR (SNR ) of the selected branch. max,n If so, the operation returns to block 516 to select the next branch. Otherwise, the baseband processor 122 sets the maximum SNR (SNR) of the selected branch to max,n ) is set equal to the newly determined SNR of the branch, and operation returns to block 514 to select the next branch.

[0102] The following examples are provided for purposes of explanation, although the inventive concepts are not limited thereto.

[0103] Example Method 1:

[0104] In this example, the sequence for branch 0 is generated from a Zadoff-Chu sequence of length N. The matrix is ​​then copied to a length N seq , where N seq >> N. Specifically, the sequence of branch 0 is generated from the Zadoff-Chu sequence of length N according to the formula shown in Equation 11:

[0105]

[0106] where u and q represent the parameters of the Zadoff-Chu sequence. u should be a prime number of N.

[0107] According to Equation 12, the sequences of other branches are obtained by cyclic shift of the sequence of branch 0:

[0108] c n，i =c n-1,mod(i-1，N) , n=0,...,N-1

[12] .

[0109] Extend a sequence to N by repetition of the existing sequence seq , N seq >>N, that is:

[0110] c n,m =c n,mod(m,N) ,m=0,...,N seq -1

[13] .

[0111] Example Method 2:

[0112] In this example, there are N seq The Zadoff-Chu sequence generates the sequence of all branches, which can be expressed as shown in Equation 14:

[0113]

[0114] where u n is the root of the Zadoff-Chu sequence of branch n. n It should be a prime number of N. Because N seq is usually a power of 2, so the rule of thumb is that n Select an odd number.

[0115] Figure 6 The simulation results of the two methods described above for an AAS with 64 branches are compared in a scenario where some symbols are not received. The probability of a non-singular matrix (y-axis) is used as an indicator of the invertibility of GG*. The number of symbols is shown on the x-axis. The results of Example Method 1 are shown as curve 601, while the results of Example Method 2 are shown as curve 602.

[0116] As in Figure 6 As can be seen in , since method 1 uses copies of the first N vectors in the remaining vectors, example method 2 has a better convergence rate than example method 1. The threshold of p = 0.05 is also used as the threshold in Figure 6 This is shown as curve 603. Method 2 reaches the threshold at approximately 200 symbols, while method 1 reaches the threshold at approximately 300 symbols.

[0117] Figure 7 Simulation results comparing the SNR (y-axis) of the two methods as the number of received symbols (x-axis) increases. In this simulation, an AAS with 64 branches and 0dB SNR was assumed. This represents a poor SNR condition and is used to confirm that the techniques described in this article can handle a very large SNR dynamic range in a real-world environment. Method 1 can be decoded after the first 64 symbols are received. On the other hand, method 2 requires a few more symbols to start decoding. In addition, because the first 64 vectors of method 1 are orthogonal to each other, method 1 has a better SNR compared to method 2, which can provide more decoding gain. Figure 7 For each data point, the worst and best branches, as well as the average branch, are indicated. All branches can utilize decoding gain and achieve a good SNR. Whenever any branch exceeds the target SNR, it can be powered down to save energy. When all branches exceed the target SNR, the process can terminate and move on to the next AC algorithm.

[0118] definition

[0119] AAS Active Antenna System

[0120] AC Antenna Calibration

[0121] AWGN Additive White Gaussian Noise

[0122] CDM Code Division Multiplexing

[0123] CP Cyclic Prefix

[0124] DL Downlink

[0125] FDM Frequency Division Multiplexing

[0126] FEC Forward Error Correction

[0127] UL Uplink

[0128] MIMO Multiple Input Multiple Output

[0129] MMSE Minimum Mean Square Error

[0130] MU-MIMO Multi-User MIMO

[0131] OFDM Orthogonal Frequency Division Multiplexing

[0132] PAR Peak to Average Ratio

[0133] RX Receiver

[0134] SNR signal-to-noise ratio

[0135] TX transmitter

[0136] ZF forces zero.

[0137] Additional definitions and embodiments are discussed below.

[0138] As will be appreciated by those skilled in the art, the present invention may be embodied as a method, a data processing system, and / or a computer program product. Thus, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining all software and hardware aspects generally referred to herein as "circuits" or "modules." Furthermore, the present invention may take the form of a computer program product on a tangible computer-usable storage medium having computer program code embodied therein that can be executed by a computer. Any suitable tangible computer-readable medium may be utilized, including a hard disk, a CD ROM, an optical storage device, or a magnetic storage device.

[0139] The embodiments described herein provide useful physical machines and specially configured computer hardware arrangements of computing devices, servers, constrained devices, processors, memories, networks, such as generally referred to herein as "computing devices." Referring to the accompanying drawings, illustrative systems for implementing the described techniques include a general-purpose computing device in the form of a computer, such as a mobile computing device or a stationary computing device. Components of a computer may include, but are not limited to, a processing unit including processor circuitry such as a programmable microprocessor or microcontroller, a system memory, and a system bus that couples various system components, including the system memory, to the processing unit.

[0140] For unconstrained devices, the processor circuit can be a multi-core processor comprising two or more independent processing units. Each core among the cores in the processor circuit can support multi-threaded operation, that is, can have the ability to execute multiple processes or threads concurrently. In addition, the processor circuit can have an onboard memory cache. An example of a suitable multi-core, multi-threaded processor circuit is the Intel Core i7-7920HQ processor, which has four cores each supporting eight threads and has an 8MB onboard cache. Typically, the processor circuit can, for example, include any type of general-purpose microprocessor or microcontroller, a digital signal processing (DSP) processor, an integrated circuit, a field programmable gate array (FPGA), a reconfigurable processor, a programmable read-only memory (PROM), or any combination thereof. For constrained devices, the processor can, for example, include an 8-bit or 16-bit microprocessor or microcontroller with or without built-in memory.

[0141] The system bus may be any of several types of bus structures, including a memory bus or memory controller, a peripheral bus, and a local bus using any of a variety of bus architectures. By way of example and not limitation, such architectures include the Industry Standard Architecture (ISA) bus, the Micro Channel Architecture (MCA) bus, the Enhanced ISA (EISA) bus, the Video Electronics Standards Association (VESA) local bus, and the Peripheral Component Interconnect (PCI) bus (also known as a mezzanine bus).

[0142] Computing devices may include a variety of computer-readable media. Computer-readable media can be any available media that can be accessed by a computer and includes volatile and non-volatile media, removable and non-removable media. By way of example and not limitation, computer-readable media may include computer storage media and communication media. Computer storage media include both volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information such as computer-readable instructions, data structures, program modules, or other data. Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disks (DVDs) or other optical disk storage devices, cassettes, magnetic tape, magnetic disk storage devices or other magnetic storage devices, or any other medium that can be used to store desired information and can be accessed by a computer. Communication media typically contain computer-readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transmission mechanism and include any information delivery media. The term "modulated data signal" refers to a signal that has one or more of its characteristics set or changed in such a manner as to encode the information in the signal. By way of example, and not limitation, communication media includes wired media such as a wired network or direct-wired connection, and wireless media such as acoustic, RF, infrared and other wireless media. Combinations of any of the above should also be included within the scope of computer-readable media.

[0143] System memory includes computer storage media in the form of volatile and / or nonvolatile memory, such as read-only memory (ROM) and random access memory (RAM). The basic input / output system (BIOS), which contains basic routines that help transfer information between components within the computer, such as during startup, is typically stored in ROM. RAM typically contains data and / or program modules that are immediately accessible to and / or currently being operated on by the processing unit. System memory can store an operating system, application programs, other program modules, and program data.

[0144] The computing device may also include other removable / non-removable, volatile / non-volatile computer storage media. By way of example only, a computer may include a hard drive that reads from or writes to a non-removable, non-volatile magnetic medium, a magnetic disk drive that reads from or writes to a removable, non-volatile magnetic disk, and / or an optical disk drive that reads from or writes to a removable, non-volatile optical disk such as a CD ROM or other optical medium. Other removable / non-removable, volatile / non-volatile computer storage media that may be used in the illustrative operating environment include, but are not limited to, magnetic cassettes, flash memory cards, digital versatile disks, digital video tapes, solid-state RAM, solid-state ROM, and the like. The hard drive is typically connected to the system bus via a non-removable memory interface.

[0145] The drives discussed above and their associated computer storage media provide storage for computer-readable instructions, data structures, program modules, and other data for the computer. A user can enter commands and information into the computer through input devices such as a keyboard and a pointing device (commonly referred to as a mouse, trackball, or touchpad). Other input devices (not shown) may include a microphone, a joystick, a game controller, a satellite dish, a scanner, a touch screen, and the like. These and other input devices are often connected to the processing unit through a user input interface coupled to the system bus, but may be connected through other interfaces and bus structures such as a parallel port, a game port, or a universal serial bus (USB). A monitor or other type of display device is also connected to the system bus via an interface such as a video interface. In addition to a monitor, a computer may also include other peripheral output devices such as speakers and a printer that may be connected through an output peripheral interface.

[0146] Computing device can use the logical connection to one or more remote computers (such as remote computers) to operate in a networked environment.The remote computer can be a personal computer, server, router, network PC, peer device or other common network node and generally includes many or all elements in the element described above relative to the computer.Logical connection includes local area network (LAN) connection and wide area network (WAN) connection, but can also include other networks.Such networked environment is common in office, enterprise-wide computer network, intranet and the Internet.

[0147] When used in a LAN networking environment, the computing device can be connected to the LAN via a network interface or adapter. When used in a WAN networking environment, the computing device can include a modem or other components for establishing communications over the WAN. The modem, which can be internal or external, can be connected to the system bus via a user input interface or other appropriate mechanism.

[0148] Some embodiments of the present inventive concept are described herein with reference to flowchart illustrations and / or block diagrams of methods, systems, and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, as well as combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device to produce a machine such that instructions executed by the processor of the computer or other programmable data processing device create components for implementing the functions / actions specified in the flowchart and / or block diagram block or multiple flowchart and / or block diagram blocks.

[0149] These computer program instructions that can direct a computer or other programmable data processing device to operate in a specific manner may also be stored in a computer-readable memory, so that the instructions stored in the computer-readable memory produce an article of manufacture including instruction components that implement the functions / actions specified in the flowchart and / or block diagram block or multiple flowchart and / or block diagram blocks.

[0150] The computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process, such that the instructions executed on the computer or other programmable apparatus provide steps for implementing the functions / actions specified in the flowchart and / or block diagram block or multiple flowchart and / or block diagram blocks.

[0151] It is to be understood that the functions / actions annotated in the blocks may not occur in the order annotated in the operational instructions. For example, depending on the functionality / actions involved, two blocks shown in succession may actually be executed substantially simultaneously, or the blocks may sometimes be executed in the reverse order. Although some of the figures include arrows on communication paths to illustrate the primary direction of communication, it is to be understood that communication may occur in the opposite direction of the depicted arrows.

[0152] The computer program code for performing the operation of the present invention can be written with an object-oriented programming language such as Java or C++. However, the computer program code for performing the operation of the present invention can also be written with a conventional process programming language such as " C " or JavaScript programming language. The program code can be executed completely on the user's computer, partly on the user's computer, as an independent software package, partly on the user's computer and partly on a remote computer, or completely on the remote computer. In the latter scenario, the remote computer can be connected to the user's computer by a local area network (LAN) or a wide area network (WAN), or (for example, utilizing an Internet service provider to pass through the Internet) can be made to be connected to an external computer.

[0153] In the above description of the various embodiments of the present invention concept, it is to be understood that the terms used herein are only for the purpose of describing specific embodiments and are not specified as being limitations of the present invention concept. Unless otherwise defined, all terms used herein (including technical terms and scientific terms) have the same meanings as those generally understood by those of ordinary skill in the art to which the present invention concept belongs. It will be further understood that the terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of this specification and the relevant field, and unless clearly defined as such in this article, the terms such as those defined in commonly used dictionaries will not be interpreted in an idealized or overly formal sense.

[0154] When an element is referred to as being "connected" to, being "coupled" to, "responsive to" or its variant to another element, it can be directly connected to, directly coupled to or directly responsive to another element or there can be an intermediate element. On the contrary, when an element is referred to as being "directly connected" to, being "directly coupled" to, "directly responsive to" or its variant to another element, there is no intermediate element. Similar numbers refer to similar elements throughout the text. In addition, "coupled", "connected", "responsive" or its variants as used in this article may include wireless coupling, connection or response. Unless the context clearly indicates otherwise, as used in this article, the singular form "a", "an" and "the" are intended to also include plural forms. For the sake of brevity and / or clarity, well-known functions or structures may not be described in detail. The term "and / or" includes any and all combinations of one or more of the associated listed items.

[0155] It will be understood that although the terms first, second, third, etc. can be used to describe various elements / operations in this article, these elements / operations should not be limited by these terms. These terms are only used to distinguish one element / operation from another element / operation. Therefore, the first element / operation in some embodiments can be referred to as the second element / operation in other embodiments and can not deviate from the teaching of the present invention. Throughout this specification, identical reference numerals or identical reference designators represent identical or similar elements.

[0156] As used herein, the terms "comprise," "comprising," "comprises," "include," "including," "includes," "have," "has," "having," or variations thereof, are open ended and include one or more stated features, integers, elements, steps, components, or functions, but do not preclude the presence or addition of one or more other features, integers, elements, steps, components, functions, or groups thereof. Furthermore, as used herein, the common abbreviation "e.g.," derived from the Latin phrase "exempli gratia," may be used to introduce or designate one or more general examples of previously mentioned items and is not intended to be a limitation of such items. The common abbreviation "ie," derived from the Latin phrase "id est," may be used to designate a specific item from a more general statement.

[0157] Example embodiments are described herein with reference to block diagrams and / or flowchart illustrations of methods, devices (systems and / or apparatus) and / or computer program products implemented by a computer. Of course, the blocks of the block diagrams and / or flowchart illustrations and combinations of blocks in the block diagrams and / or flowchart illustrations can be implemented by computer program instructions executed by one or more computer circuits. These computer program instructions can be provided to a processor circuit of a general-purpose computer circuit, a special-purpose computer circuit and / or other programmable data processing circuit to produce a machine so that instructions executed by a processor of a computer and / or other programmable data processing device transform and control transistors, values ​​stored in storage locations and other hardware components within such circuit systems to implement the functions / actions specified in the block diagrams and / or flowchart blocks or multiple block diagrams and / or flowchart blocks and thereby create components (functionality) and / or structures for implementing the functions / actions specified in (one or more) block diagrams and / or flowchart blocks.

[0158] These computer program instructions that can direct a computer or other programmable data processing device to operate in a specific manner may also be stored in a tangible computer-readable medium, such that the instructions stored in the computer-readable medium produce an article of manufacture including instructions for implementing the functions / actions specified in the block diagram and / or flowchart block or multiple block diagrams and / or flowchart blocks. Thus, embodiments of the inventive concept may be embodied in hardware and / or in software (including firmware, resident software, microcode, etc.) running on a processor such as a digital signal processor, which may be collectively referred to as "circuitry," "module," or variations thereof.

[0159] It should also be noted that in some alternative implementations, the function / action annotated in the frame may not occur in the order annotated in the flow chart. For example, depending on the functionality / action involved, in fact, the two frames shown in succession may be performed substantially simultaneously or the frames may be performed in reverse order sometimes. In addition, the functionality of the given frame of a flow chart and / or block diagram may be divided into multiple frames and / or may at least partially integrate the functionality of two or more frames of a flow chart and / or block diagram. Finally, without departing from the scope of the inventive concept, other frames may be added / inserted between the frames of illustration, and / or frame / operation may be omitted. In addition, although some figures in the figure include arrows on the communication path to illustrate the main direction of communication, it will be appreciated that communication may occur in the direction opposite to the arrows depicted.

[0160] In the case of not departing substantially from the principles of the inventive concept, many changes and modifications may be made to the embodiments. All such changes and modifications are intended to be included within the scope of the inventive concept. Therefore, the subject matter disclosed above is to be considered illustrative, rather than restrictive, and the example of the embodiment is intended to cover all such modifications, enhancements, and other embodiments that belong to the spirit and scope of the inventive concept. Thus, to the maximum extent permitted by law, the scope of the inventive concept shall be determined by the broadest permissible interpretation of the present disclosure including the examples of the embodiments and their equivalents, and the scope of the inventive concept shall not be restricted or limited by the detailed description above.

[0161] Generally, they will be interpreted according to the ordinary meaning of all terms used in this article in the relevant technical field, unless different meanings are implied and / or clearly given from the context in which it is used. Unless otherwise clearly stated, all references to one / an / described element, device, assembly, part, step, etc. will be openly interpreted as referring to at least one instance of an element, device, assembly, part, step, etc. Unless a step is explicitly described as being after or before another step and / or wherein an implicit step must be after or before another step, it is not necessary to perform the steps of any method disclosed herein in the precise order disclosed. Where appropriate, any feature of any embodiment in the embodiments disclosed herein may be applied to any other embodiment. Similarly, any advantage of any embodiment in the embodiment may be applied to any other embodiment, and vice versa. From the description, other purposes, features and advantages of the attached embodiments will be apparent.

[0162] Many different embodiments have been disclosed herein in conjunction with the above description and figures. It will be understood that literally describing and illustrating every combination and subcombination of these embodiments would be unduly repetitive and obscure. Therefore, all embodiments may be combined in any manner and / or combination, and this specification, including the figures, should be construed to constitute a complete written description of all combinations and subcombinations of the embodiments described herein, as well as a complete written description of the manner and process of making and using them, and this specification, including the figures, should support claims to any such combination or subcombination.

[0163] In the drawings and specification, typical embodiments of the invention have been disclosed, and although specific terms are employed, they are used in a generic and descriptive sense only and not for purposes of limitation, the scope of the invention being set forth in the following claims.

Claims

1. A method for calibrating an antenna array in a wireless network node (100), the wireless network node (100) comprising a plurality of antenna branches (110), each antenna branch of the plurality of antenna branches comprising a respective antenna element (130), the method comprising: Repeat the following steps: transmitting (508) slices of the fountain-coded sequence to the corresponding antenna elements via the plurality of antenna branches; as well as For each antenna branch of the plurality of antenna branches: selecting (516) the transmitted slice as a feedback signal via the return path (214); as well as determining (520) a signal quality of the feedback signal; until the signal quality of the feedback signal of each antenna branch is greater than a threshold level; as well as Antenna calibration is performed (512) based on the feedback signal for each antenna branch.

2. The method according to claim 1, wherein Transmitting the slices of the fountain coded sequence comprises transmitting consecutive slices of the fountain coded sequence until a matrix GG* formed by a generator matrix G is non-singular, wherein the generator matrix G comprises an N×M matrix including elements c n，m , N represents the number of antenna branches of the multiple antenna branches, M represents the number of received symbols of the fountain decoding sequence, and m represents the mth symbol of the fountain decoding sequence on the antenna branch n in the branch where the number of the multiple antenna branches is N.

3. The method of claim 2, further comprising: generating the fountain decoding sequence; slicing the fountain decoding sequence to obtain the slice of the fountain decoding sequence, wherein the slice of the fountain decoding sequence includes at least one symbol of the fountain decoding sequence; adding a cyclic prefix to the at least one symbol of the fountain coded sequence; and The slice of the fountain coded sequence is inserted into a downlink signal for transmission.

4. The method according to claim 3, wherein: The element c n，m comprising a spreading code, and wherein generating the fountain decoding sequence comprises using the spreading code c n，m to expand the at least one symbol.

5. The method according to claim 4, wherein: Generating the fountain decoding sequence includes generating a symbol of length N and repeating the symbol to obtain a symbol of length N. seq >N sequence.

6. The method according to claim 5, wherein: Generating the fountain decoding sequence includes generating the symbol of branch n according to the following equation: Where u and q represent the parameters of the Zadoff-Chu sequence.

7. The method of claim 4, wherein: Generating the fountain decoding sequence includes generating a sequence of length N according to the following equation seq Zadoff-Chu sequence: Among them, u n is the root of the Zadoff-Chu sequence of branch n, and q represents the parameter of the Zadoff-Chu sequence.

8. The method of claim 1, wherein: Determining the signal quality of the feedback signal includes determining a signal-to-noise ratio (SNR) of the feedback signal.

9. The method of claim 8, wherein: Determining the signal-to-noise ratio of the feedback signal includes performing a blind SNR estimation.

10. The method of claim 9, wherein: Performing a blind estimation involves determining the SNR according to the following formula: where ρ is the SNR, yes The jth element of is an estimate of at least one symbol of the fountain-coded sequence at the nth antenna branch, and N fft is the size of the Fast Fourier Transform matrix used to generate the at least one symbol.

11. The method according to any one of claims 1 to 2, further comprising: The fountain coding sequence is estimated from the feedback signal using a zero-forcing receiver or a minimum mean square error receiver.

12. The method of claim 11, wherein: Estimating the fountain decoding sequence from the feedback signal using a zero-forcing receiver includes estimating the fountain decoding sequence according to the following formula: Among them, r m represents the mth element of the received signal, G represents a generator matrix including a matrix including elements c n， m, wherein N represents the number of antenna branches of the plurality of antenna branches, M represents the number of received symbols of the fountain decoding sequence, and m represents the mth symbol of the fountain decoding sequence on branch n of the plurality of antenna branches being N in number, and represents the estimated value of the mth symbol of the fountain decoding sequence on branch n.

13. The method of claim 11, wherein: Estimating the fountain decoding sequence from the feedback signal using a minimum mean square error receiver includes estimating the fountain decoding sequence according to the following formula: Among them, r m represents the mth element of the received signal, G represents a generator matrix including an N×M matrix including elements c n，m , N represents the number of antenna branches of the multiple antenna branches, M represents the number of received symbols of the fountain decoding sequence, m represents the mth symbol of the fountain decoding sequence on branch n of the multiple antenna branches where the number of branches is N, denotes the estimated value of the mth symbol of the fountain coded sequence on branch n, and p is the signal-to-noise ratio (SNR).

14. The method according to any one of claims 1 to 2, wherein: The fountain decoding sequence includes a plurality of symbols generated by orthogonal frequency division multiplexing.

15. A network node (100), comprising: Processor (106); a wireless transceiver (120) coupled to the processor; as well as A memory (108) coupled to the processor, the memory comprising machine-readable program instructions that, when executed by the processor, cause the network node to perform operations including the operations of the method according to any one of claims 1 to 14.

16. An apparatus for calibrating an antenna array in a wireless network node, the wireless network node comprising a plurality of antenna branches, each antenna branch of the plurality of antenna branches comprising a respective antenna element, the apparatus comprising means for performing the operations of the method according to any one of claims 1 to 14.

17. A non-transitory computer-readable storage medium comprising a computer program to be executed by a processor (106) of a network node (100), the network node (100) being configured to operate in a communications network, whereby execution of the computer program causes the network node (100) to perform the operations of the method according to any one of claims 1 to 14.

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