Method and apparatus for power conservation in universal serial bus repeaters / re-timers

Abstract

The present disclosure relates to methods and apparatus for power saving in a USB repeater / retimer. Disclosed are techniques for saving power in a universal serial bus (USB) repeater / retimer between a USB host and a peripheral device by intercepting packets received from the host to predict the direction of data traffic to selectively turn on / off circuitry for a peripheral port that receives packets from the peripheral device. If the host port determines that the host is sending a start of frame (SOF) packet, then the direction of data flow is from the host to the peripheral device, and the repeater can turn off the peripheral port, e.g., mute circuitry. If the host port determines that the host is sending a non-SOF packet, e.g., an address token before a host-to-peripheral data transfer or a peripheral-to-host data transfer, then the direction of data flow is predicted to be from the peripheral device to the host, and the repeater can re-enable the deactivation circuitry of the peripheral port.

Description

Technical Field

[0001] This disclosure generally relates to Universal Serial Bus (USB) systems, and more specifically to methods and systems for saving power in USB repeaters / retimers. Background Technology

[0002] Various electronic devices (e.g., smartphones, tablets, laptops, laptops, hubs, chargers, adapters, etc.) are configured to transmit data or power via a Universal Serial Bus (USB) connector system. Devices in a USB system can transmit data at various rates. In some applications, repeater / retimer devices in USB hubs are used to connect devices operating at different data rates to a host. A repeater / retimer device (or simply a repeater) can receive USB packets sent from the host at a higher data rate and can retransmit the USB packets to one or more downstream devices at the same or a lower data rate. Similarly, a repeater can receive USB packets sent from a downstream device at one data rate and can retransmit the USB packets to the host at the same or a higher data rate. As the demand for higher throughput drives increasingly higher data rates supported by USB systems, and as USB repeaters support more parallel data channels and are integrated into portable devices, low power consumption of USB repeaters has become an important design requirement.

[0003] One opportunity to minimize repeater power consumption without compromising data throughput is when the repeater is in an idle state, not transmitting data and waiting to receive packets. This is because keeping the receive circuitry on both ports of the repeater active while it's idle, ready to receive data on either port, consumes a significant amount of power. If a method exists to anticipate the timing of incoming packets or the idle state, there's an opportunity to disable the receive circuitry to save power. However, this can be difficult because when the repeater forwards packets from one port to another, it is unaware of the data transaction protocol between the host and the device. Requiring the repeater to intercept packets to determine the host / device data transaction protocol introduces significant overhead, potentially offsetting any power savings gained from disabling the receive circuitry. Therefore, there is a need to find a method to reduce power consumption with minimal complexity and cost when the repeater is idle. Summary of the Invention

[0004] This invention discloses an apparatus for relaying Universal Serial Bus (USB) packets exchanged between a host and a peripheral device, comprising: a host port configured to receive USB packets from the host; a peripheral port configured to receive USB packets from the peripheral device; and a processing system configured to: detect a USB packet received from the host by the host port; determine the type of the received USB packet; disable the peripheral port in response to the USB packet being determined to be a Start of Frame (SOF) packet; and enable the peripheral port in response to the USB packet being determined to be a non-SOF packet, so that the peripheral port is ready to receive USB packets from the peripheral device.

[0005] The present invention discloses a method comprising: detecting a Universal Serial Bus (USB) compliant repeater received from a host; determining the type of the received USB packet; disabling the receiving circuitry system of the USB compliant repeater for receiving USB packets from a peripheral device in response to the USB packet being determined to be a Start of Frame (SOF) packet; and enabling the receiving circuitry system in response to the USB packet being determined to be a non-SOF packet, such that the receiving circuitry system is prepared to receive USB packets from the peripheral device. Attached Figure Description

[0006] The described embodiments and their advantages can be best understood by referring to the following description taken in conjunction with the accompanying drawings. These drawings do not limit any formal or detailed changes that may be made to the described embodiments by those skilled in the art without departing from the spirit and scope of the described embodiments.

[0007] Figure 1 This is a block diagram illustrating a repeater device (or simply repeater) of a USB system according to one aspect of this disclosure for relaying data packets between an embedded USB2 (eUSB2) port and a USB2 port.

[0008] Figure 2 This illustrates one aspect of the disclosure. Figure 1 A block diagram of an eUSB repeater subsystem for relaying data packets between an embedded USB2 (eUSB2) host port and a USB2 peripheral port;

[0009] Figure 3 A block diagram of a USB repeater / retimer device, according to one aspect of this disclosure, is shown, which intercepts USB packets received from a host to predict the direction of the data flow and thereby control the operation of a peripheral receive port.

[0010] Figure 4One aspect of this disclosure is shown. Figure 3 Functional block diagram of a USB repeater / retimer device that operates to intercept USB packets received from the host, thereby controlling the peripheral receiving port to save power in idle mode;

[0011] Figure 5 A state machine is shown for a USB repeater / retimer device according to one aspect of this disclosure, which monitors a USB packet on the host receive port to control the operation of the peripheral receive port, thereby saving power in idle mode.

[0012] Figure 6 A timing diagram is shown of a host receive port in a first scenario of host and device data transactions, according to one aspect of this disclosure, where a USB repeater / retimer monitors USB packets from the host to disable the peripheral receive port when a Start of Frame (SOF) packet is received and to enable the peripheral receive port when a non-SOF packet is received.

[0013] Figure 7 A timing diagram is shown of a host receive port in a second scenario of host and device data transactions, according to one aspect of this disclosure, where a USB repeater / retimer monitors USB packets from the host to disable the peripheral receive port when a Start of Frame (SOF) packet is received and to enable the peripheral receive port when a non-SOF packet is received.

[0014] Figure 8 This is a flowchart of a method for a repeater / retimer to monitor USB packets received from a host in order to control the operation of a peripheral receive port, thereby saving power in idle mode, according to one aspect of this disclosure. Detailed Implementation

[0015] Examples of various aspects and variations of the subject matter are described herein and illustrated in the accompanying drawings. The following description is not intended to limit the invention to these embodiments, but rather to enable those skilled in the art to make and use the invention.

[0016] This document describes various aspects of a power-saving technique in a Universal Serial Bus (USB) repeater / retimer configured to exchange packets between a USB host and a peripheral device by intercepting packets received from the host to predict the direction of data flow when the repeater is in idle mode. In idle mode, there is no data transmission between the host and the peripheral device, and the repeater is waiting to receive data. The repeater's host port can intercept USB packets received from the host to predict the direction of data flow, thereby selectively turning off or on the receiver circuitry on the peripheral port. In one aspect, if the host port determines that the host is sending a Start of Frame (SOF) packet, the direction of data flow is from the host to the peripheral device, and the repeater can turn off the circuitry on the peripheral port used to receive and relay traffic from the peripheral device to save power. If the host port determines that the host is sending a non-SOF packet, such as an address token before sending data from the host to a peripheral device or before requesting data from a peripheral device, the direction of the data flow is expected to be from the peripheral device to the host, and the repeater can re-enable the deactivation circuitry of the peripheral port so that the repeater can receive handshake packets or data packets from the peripheral device.

[0017] Peripheral devices connected to a USB repeater may include, but are not limited to, personal computers (e.g., laptops, notebook computers, etc.), mobile computing devices (e.g., tablets, tablet computers, e-reader devices, etc.), mobile communication devices (e.g., smartphones, mobile phones, personal digital assistants, messaging devices, handheld computers, etc.), connection and charging devices (e.g., hubs, docking stations, adapters, chargers, etc.), audio / video / data recording and / or playback devices (e.g., camera devices, recorders, handheld scanners, monitors, etc.), and other similar electronic devices that can communicate and / or charge batteries using a USB connector (interface).

[0018] As used herein, an electronic device or system is referred to as "USB-enabled" or "USB-compliant" if it conforms to at least one release of the USB specification. Examples of such USB specifications include, but are not limited to, USB specification revision 2.0, the USB 3.0 specification, the USB 3.1 specification, and / or various supplements (e.g., On-The-Go or OTG), versions, and their errata. USB specifications typically define the characteristics of the differential serial bus required for designing and building standard communication systems and peripherals (e.g., attributes, protocol definitions, transaction types, bus management, programming interfaces, etc.).

[0019] For example, a USB-enabled peripheral electronic device can be attached to a USB-enabled host device via its USB port to form a USB-enabled system. The host device can embed a USB repeater to perform retiming and voltage level shifting between the serial bus on the host side, which operates at a lower core voltage on the host device, and the serial data on the peripheral side, which conforms to the USB specification. A USB 2.0 (or simply USB2) port may include a 5V power line (e.g., V...). BUS The USB 3.0 port also provides a differential pair for the data lines (e.g., which can be represented as D+ or DP and D- or DN) and a ground wire (e.g., GND) for power return. BUS The USB 3.0 port provides differential pairs for the transmitter data lines (SSTX+ and SSTX-), differential pairs for the receiver data lines (SSRX+ and SSRX-), a power line for power (e.g., DPWR), and a ground line for power return (e.g., DGND). The USB 3.1 port provides the same wiring as the USB 3.0 port for backward compatibility with USB 2.0 and USB 3.0 communication, but extends the performance of the SuperSpeed ​​bus through a series of features known as Enhanced SuperSpeed.

[0020] Various releases of the USB Type-C specification define updated technologies for USB connectors, referred to as USB Type-C. These technologies provide USB Type-C receptacles, plugs, and cables that can support USB communication and power delivery via newer USB Power Delivery protocols, such as those defined in one or more revisions of the USB Power Delivery (USB PD) specification. As used herein, "USB Type-C subsystem" can refer, for example, to a hardware circuitry controllable by firmware and / or software in an integrated circuit (IC) controller, configured and operable to perform functions and meet the requirements specified in at least one release of the USB Type-C specification.

[0021] Some electronic devices can use low-voltage USB 2.0 interfaces optimized for power consumption of the supplement to USB 2.0 (referred to as embedded USB (eUSB or eUSB2)) that conforms to the eUSB2 physical layer specification (e.g., revision 1.1 or later). eUSB uses 1.2V signaling to decouple external USB 2.0 and / or USB Type-C ports from the internal components of electronic devices manufactured using lower-technology nodes that operate at lower voltages. High-speed repeaters between USB-enabled host devices and USB-compliant electronic devices can switch between signaling using the eUSB and USB 2.0 standards.

[0022] USB-compliant electronic devices can be connected to USB-enabled host devices via one or more hubs to form a USB-enabled system. Devices can use USB 2.0 and / or USB Type-C ports through one or more hubs to exchange data packets with the host and receive power from the host. Hubs allow the host to connect to a mix of devices operating at different data rates. Repeaters in the hub can receive USB packets sent from the host at a higher data rate and can resend the USB packets to the device at the same or a lower data rate. Under USB 2.0, a USB-enabled system can operate at a maximum data rate of 480 megabits per second (Mb / s) at High Speed ​​(HS). If necessary, the device may fall back to the 12 Mb / s Full Speed ​​(FS) or 1.5 Mb / s Low Speed ​​(LS) rate of USB 1.0. USB 2.0 compliant repeaters can support retiming functions for High Speed, Full Speed, and Low Speed.

[0023] Figure 1 This is a block diagram illustrating a repeater 100 of a USB subsystem according to one aspect of this disclosure. Such a USB subsystem can be implemented as part of and / or within a USB-enabled system such as a USB 2.0 hub or USB 2.0 docking station. The repeater 100 can be embedded in an IC controller chip fabricated on an integrated circuit (IC) die, such as the IC controller chip of a USB hub. In another example, the repeater 100 can be a single-chip IC fabricated as a system-on-a-chip (SoC). The repeater 100 can be an eUSB / USB repeater that performs relay functionality between an embedded USB2 (eUSB2) port compliant with the eUSB2 physical layer specification 1.1, USB 2.0, and a USB2 port compliant with USB 2.0. In another example, the repeater 100 can perform relay functionality between two USB2 ports.

[0024] Among other components, repeater 100 may include a CPU subsystem 102, system interconnect 112, peripheral interconnect 114, system resources 116, various input / output (I / O) blocks (e.g., 118A to 118C), and an eUSB repeater subsystem 124. Additionally, repeater 100 may provide firmware and circuitry configured and operable to support multiple power states 122. CPU subsystem 102 may include one or more CPUs (Central Processing Units) 104 coupled to system interconnect 112, flash memory 106, SRAM (Static Random Access Memory) 108, and ROM (Read-Only Memory) 110. CPU 104 is a suitable processor that can operate in a system-on-a-chip device. In some embodiments, a large number of gated clocks may be used to optimize CPU 104 for low-power operation, and CPU 104 may include various internal controller circuitry that enables CPU 104 to operate in various power states.

[0025] For example, CPU 104 may include a wake-up interrupt controller configured to wake CPU 104 from a hibernation state, thereby enabling power to be “turned off” when repeater 100 is in a hibernation state. Flash memory 106 may be any type of program memory (e.g., NAND flash, NOR flash, etc.) configurable for storing data and / or programs. SRAM 108 may be any type of volatile or non-volatile memory suitable for storing data and firmware / software instructions accessed by CPU 104. ROM 110 may be any type of suitable storage device configurable for storing boot routines, configuration parameters, and other on-chip system firmware parameters and settings. System interconnect 112 is a system bus (e.g., a single-level or multi-level Advanced High-Performance Bus, or AHB) configured as an interface coupling the various components of CPU subsystem 102 to each other and as a data and control interface between the various components of CPU subsystem and peripheral interconnect 114.

[0026] Peripheral interconnect 114 is a peripheral bus (e.g., a single-level or multi-level AHB) that provides the primary data and control interface between CPU subsystem 102 and its peripherals and other resources, such as system resources 116, I / O blocks (e.g., 118A to 118C), and eUSB repeater subsystem 124. Peripheral interconnect 114 may include various controller circuitry (e.g., direct memory access or DMA controllers) that can be programmed to transfer data between peripheral blocks without burdening the CPU subsystem. In various embodiments, each component of CPU subsystem 102 and peripheral interconnect 114 may vary depending on the selection or type of the CPU, system bus, and / or peripheral bus.

[0027] System resource 116 may include various electronic circuits supporting the operation of repeater 100 in its various states and modes. For example, system resource 116 may include a power subsystem that provides the power resources required for each controller state / mode, such as voltage and / or current references, wake-up interrupt controller (WIC), power-on reset, etc. In some embodiments, the power subsystem of system resource 116 may also include circuitry that allows repeater 100 to draw power from and / or supply power to external sources at several different voltage and / or current levels. System resource 116 may also include a clock subsystem that provides various clocks used by repeater 100 and circuitry implementing various controller functions such as external reset.

[0028] In various implementations and methods, the IC controller, such as repeater 100, may include various different types of I / O blocks and subsystems. For example, in Figure 1 In the illustrated embodiment, repeater 100 may include a GPIO (General Purpose Input / Output) block 118A, a TCPWM (Timer / Counter / Pulse Width Modulation) block 118B, an SCB (Serial Communication Block) 118C, and an eUSB repeater subsystem 124. GPIO 118A includes circuitry configured to implement various functions such as pull-up, pull-down, input threshold selection, input and output buffer enable / disable, and multiplexed signals connected to the respective I / O pins. TCPWM 118B includes circuitry configured to implement timers, counters, pulse width modulators, decoders, and various other analog / mixed-signal elements configured to operate on input / output signals. SCB 118C includes circuitry configured to implement various serial communication interfaces such as I / O... 2 C. Circuits such as SPI (Serial Peripheral Interface) and UART (Universal Asynchronous Receiver / Transmitter).

[0029] In some implementations, the eUSB repeater subsystem 124 may be used according to the techniques described herein, and the eUSB repeater subsystem 124 may also support USB communication via the USB port, as well as other USB functions such as power delivery and battery charging. For example, the eUSB repeater subsystem 124 may be a USB-PD subsystem, a USB Type-C subsystem, or both (e.g., a USB Type-C subsystem supporting USB-PD functionality). The eUSB repeater subsystem 124 may include transceivers and physical layer logic (PHYs) 126, 128 for eUSB2 and USB 2.0, respectively, the transceivers and physical layer logic (PHYs) 126, 128 being configured to integrate baseband PHY circuitry to perform various digital encoding / decoding functions (e.g., biphase marker code-BMC encoding / decoding, cyclic redundancy check-CRC, etc.) and analog signal processing functions involved in physical layer transmission. The eUSB repeater subsystem 124 may be referred to as an eUSB retiming repeater. In various implementations, the repeater (e.g., such as eUSB repeater subsystem 124) can be implemented as hardware logic including various components such as logic gates, adders, multiplexers, latches, flip-flops, counters, registers, transistors, diodes, resistors, capacitors, and various circuits thereof. As will be discussed further below, eUSB repeater subsystem 124 may include circuitry for intercepting packets received from the host via eUSBPHY 126 to predict the direction of data traffic when eUSB repeater subsystem 124 is in idle mode. The predicted direction of data traffic can be used to selectively turn off or on the receiver circuitry in USB PHY 128 connected to peripheral devices to save power.

[0030] Figure 2 This illustrates one aspect of the disclosure. Figure 1 A block diagram of an eUSB repeater subsystem 124 for relaying data packets between an embedded USB2 (eUSB2) port and a USB2 port is provided. The eUSB repeater subsystem 124 may include: a serial repeater 134 configured to perform packet retiming and relay functions; a serial interface engine 132 configured to detect events on the eUSB2 and USB2 ports; and a repeater state machine configured to determine the state of the serial repeater 134 based on the detected events. The eUSB repeater subsystem 124 can be connected to the eUSB2 port and the USB2 port via an eUSB PHY 126 and a USB PHY 128, respectively.

[0031] The eUSB PHY 126 can connect to a host or intermediate hub / repeater to receive data packets sent from the host via differential data pairs DP and DM. The USB PHY 128 can connect to a peripheral device or intermediate hub / repeater to retransmit data packets to the peripheral device via a second differential data pair DP and DM at the same or lower data rate. For data from device to host, the USB PHY 128 can receive data packets sent by the device, and the eUSBPHY 126 can retransmit the data packets to the host at the same or lower data rate. High-speed, full-speed, or low-speed data rates can be supported. For high-speed data, the eUSB PHY 126 and USB PHY 128 can each include a transmission envelope detector (e.g., implemented as hardware logic) for performing clock and data recovery (CDR) functions to lock the SYNC bit of received high-speed data packets. If the voltage between the differential data pairs is less than 100 μV, the transmission envelope detector can generate a squelch signal to indicate that there is no data.

[0032] The serial interface engine 132 can monitor activity on the host port of the eUSB PHY 126 and the device port of the USB PHY 128 to decode bus events and trigger appropriate actions. The serial interface engine 132 can decode bus events to trigger the repeater state machine 130 and control the data path of packets via the serial repeater 134. For example, the serial interface engine 132 can determine the receiver speed (e.g., high speed, full speed, or low speed), detect the configuration of the eUSB2 port and USB2 port, monitor the status of the host or device's data lines, etc., to enable the repeater and retiming functions of the serial repeater 134.

[0033] In one aspect, the serial interface engine 132 can detect SOF packets received by the host port of the eUSB PHY 126 to disable the transmission envelope detector, which includes squelch detection circuitry, in the device port of the USB PHY 128, and disable the circuitry in the serial repeater 134 used for relaying and retiming data received from that device port. The host can send SOF packets (also known as SOF tokens) every millisecond in full-speed or low-speed USB to schedule access to the data bus, and these SOF packets serve as timing references for synchronizing isochronous and interrupt data transfers. SOF packets can contain an 11-bit incrementing frame number. In high-speed USB, millisecond frames are divided into eight 125μs-long microframes. The host can send a high-speed SOF packet for each microframe by relaying each frame number eight times within each millisecond frame. Detecting SOF packets provides a simple way to predict that the eUSB repeater subsystem 124 is in idle mode, where no data from the device is expected, thus allowing the circuitry associated with detecting, receiving, relaying, and retiming device data packets to save power. In one aspect, the serial interface engine 132 can shut down the clock in the squelch circuitry of the device port of the USB PHY 128, as well as the clock in the relay and retiming circuitry for data received from the device port in the serial repeater 134.

[0034] When the next packet following an SOF packet from the host is a non-SOF packet, the serial interface engine 132 can re-enable disabled circuitry to prepare it for receiving data from the device port. For example, if the next packet is an in-token requesting the device to send a data packet, the data flow direction will be from the device to the host. When the next packet is an out-token indicating the transmission of a data packet from the host to the device, the data flow direction can still be from the device to the host because the device responds to the data packet by sending a handshake packet indicating whether the data packet has been successfully received. The serial interface 132 can determine whether the packet from the host is an SOF packet or a non-SOF packet by decoding the packet's packet identifier (PID) byte. After re-enabling the transmission envelope detector in the device port of the USB PHY 128 and the relay and retiming circuitry in the serial repeater 134 for receiving device data, they can remain enabled until the next SOF packet is received.

[0035] The repeater state machine 130 can receive decoded bus events from the serial interface engine 132 and the internal state of the serial repeater 134 to control the operation of the serial repeater 134. The repeater state machine 130 can also control the state of the eUSB repeater subsystem 124 to achieve a state compliant with the eUSB specification.

[0036] Figure 3A block diagram is shown of a USB repeater / re-timer device 311, according to one aspect of this disclosure, that intercepts USB packets received from host 301 to predict the direction of data flow and thereby control the operation of peripheral receive port 325. Host 301 may have a transmit port 303 for sending USB packets to peripheral device 331 via repeater / re-timer 311 and a receive port 305 for receiving USB packets from peripheral device 331 via repeater / re-timer 311. Peripheral device 331 may have a receive port 333 for receiving USB packets from host 301 and a transmit port 335 for sending USB packets to host 301 via repeater / re-timer 311. Repeater / re-timer 311 may be... Figure 1 and Figure 2 The eUSB repeater subsystem 124, eUSB PHY 126, and USB PHY 128 are implemented, or they can be implemented as standalone repeaters.

[0037] The host Rx port 313 of the repeater / retimer 311 can receive USB packets transmitted by the host 301 via differential data pairs. The host Rx port 313 can support low-speed, full-speed, and high-speed data rates for USB 2.0, SuperSpeed ​​for USB 3.0, and Enhanced SuperSpeed ​​for USB 3.1. In one aspect, the host Rx port 313 can have a transmission envelope detector, squelch circuitry, or other receiving circuitry to detect activity on the data lines, for example, when the differential data lines exceed 100 μV at high speeds and when a SYNC bit mode indicating the presence of a packet from the host 301 is present. When a packet is detected, the repeater / retimer 311 can perform retiming and relay functions on the serial bits of the packet before forwarding it to the peripheral Tx port 323 for transmission to the peripheral device 331.

[0038] When a packet is detected from host 301, host Rx port 313 can forward the packet identifier (PID) byte 316, which follows the SYNC bit mode, to idle mode power-saving state machine 317 to determine whether the packet is an SOF packet. If the PID byte 316 indicates an SOF packet, the USB transaction protocol is considered to be in idle mode, in which no packets are expected from peripheral device 331. Idle mode power-saving state machine 317 can send a peripheral Rx port control signal 318 to peripheral Rx port 325 to put peripheral Rx port 325 into a power-saving state.

[0039] Similar to the host Rx port 313, the peripheral Rx port 325 may have a transmission envelope detector, squelch circuitry, or other receiving circuitry to detect activity on the data line from the peripheral device 331 when a SYNC bit mode indicating the presence of a packet from the peripheral device 331 is present. The peripheral Rx port 325 may disable its receiving circuitry when the Rx port control signal 318 is received in idle mode. In one aspect, the circuitry in the repeater / retimer 311 that performs retiming and relaying of serial bits of packets received from the peripheral device 331 may also be disabled.

[0040] The USB system is not in idle mode when the PID byte 316 of a packet from host 301 indicates a non-SOF packet. For example, the packet could be an in-to-toe token requesting peripheral device 331 to send a data packet to host 301, or an out-to-toe token request before transferring a data packet from host 301 to peripheral device 331. In both scenarios, peripheral Rx port 313 is expected to receive the requested data packet from peripheral device 331, or a handshake packet indicating whether a data packet sent by host 301 was successfully received. If the receive circuitry was previously disabled, the idle mode power-saving state machine 317 can send a peripheral Rx port control signal 318 to peripheral Rx port 325 to re-enable the receive circuitry. In one aspect, if the circuitry for retiming and relaying packets received from peripheral device 331 was previously disabled, that circuitry can also be re-enabled. When the peripheral Rx port 325 receives a packet from a peripheral device, the repeater / re-timer 311 can perform re-timing and relay functions on the serial bits of the packet before forwarding the packet to the host Tx port 315 for transmission to the host 301.

[0041] In one aspect, the repeater / retimer device 311 can relay USB packets between a host 301 and multiple peripheral devices 331 connected via corresponding peripheral Rx ports 325. The repeater / retimer 311 can intercept USB packets received from the host 301 to predict the direction of the data flow, thereby controlling the operation of each corresponding peripheral Rx port 325 among the peripheral devices 331. For example, when the host Rx port 313 receives an SOF packet from the host, the idle mode power-saving state machine 317 can send a peripheral Rx port control signal 318 to each corresponding peripheral Rx port 325 among the peripheral devices 331, causing all peripheral Rx ports 325 to enter a power-saving state. When the host Rx port 313 receives a non-SOF packet addressed to one of the peripheral devices 331 from the host, the idle mode power-saving state machine 317 can send a peripheral Rx port control signal 318 to enable the peripheral Rx port 325 corresponding to the addressed peripheral device 331 and keep the peripheral Rx port 325 corresponding to the unaddressed peripheral device 331 in a power-saving state.

[0042] Figure 4 One aspect of this disclosure is shown. Figure 3 The functional block diagram describes a USB repeater / retimer device 311 that operates to intercept USB packets received from the host 511, thereby controlling the peripheral receive port to save power in idle mode. The host Rx port 313 has a host Rx squelch circuit 501 for detecting the absence of squelch indicating activity on the data line from the host and for detecting the start of a valid packet. The host Rx squelch circuit 501 can extract the PID byte 316 of the detected packet and forward it to the idle mode power-saving state machine 317.

[0043] The PID detection module 503 in the idle mode power-saving state machine 317 can receive the PID byte 316 of a detected packet from the host to determine whether the packet is an SOF packet or a non-SOF packet. If the packet is an SOF packet, the PID detection module 503 can send the SOF PID signal 513 to the peripheral Rx port control switching circuit 505 to generate a peripheral Rx port control signal 318 that causes the peripheral Rx port 325 to enter the power-saving state. If the packet is a non-SOF packet, the PID detection module 503 can send the non-SOF PID signal 515 to the peripheral Rx port control switching circuit 505 to generate a peripheral Rx port control signal 318 that causes the peripheral Rx port 325 to exit the power-saving state. Therefore, the peripheral Rx port control signal 318 can switch between the two states based on whether the detected packet from the host is an SOF packet.

[0044] The peripheral Rx port 325 may have a peripheral Rx squelch circuit 507, which includes circuitry such as a transmission envelope detector, squelch circuitry, or other circuitry configured to receive packets 517 from peripheral device 331 to generate peripheral Rx packets 519. The peripheral Rx serial repeater circuit 509 may be configured to perform retiming and relay functions on the serial bits of the peripheral Rx packets 517. When a peripheral Rx port control signal 318 is received commanding peripheral Rx port 325 to enter or remain in a power-saving state, the peripheral Rx squelch circuit 507 and the peripheral Rx serial repeater circuit 509 may be disabled or remain disabled. In one aspect, the clock to the peripheral Rx squelch circuit 507 and the peripheral Rx serial repeater circuit 509 may be turned off. On the other hand, when the peripheral Rx port 325 receives the peripheral Rx port control signal 318 commanding it to exit power-saving mode or remain active, the peripheral Rx squelch circuit 507 and the peripheral Rx serial repeater circuit 509 can be enabled or remain enabled to prepare to receive and process packets from peripheral devices. The peripheral Rx squelch circuit 507 can receive packets 517 from peripheral devices to generate peripheral Rx packets 519. The peripheral Rx serial repeater circuit 509 can process the peripheral Rx packets 519 to generate peripheral Rx retiming packets 521 for transmission to the host.

[0045] Figure 5 A state machine 500 is shown that monitors a USB packet on the Rx port of a USB repeater / retimer device according to one aspect of this disclosure to control the operation of the peripheral Rx port, thereby saving power in idle mode. The state machine 500 can be... Figure 3 Implemented by the host Rx port 313 and the idle mode power-saving state machine 317, or by Figure 4 The main unit Rx noise reduction circuit 501, PID detection module 503, and peripheral Rx port control switching circuit 505 are used to implement this.

[0046] At operation 501, state machine 500 monitors the squelch signal on the host Rx port. In one aspect, for example, when the differential data line voltage exceeds 100 μV at high speeds or other data rates, the transmission envelope detector can detect activity on the data lines from the host. If a squelch signal is detected, indicating that the differential data line voltage is less than 100 μV, operation 501 continues to monitor the squelch signal. Otherwise, if no squelch signal is detected, indicating activity on the data lines, state machine 500 can detect the SYNC bit mode indicating the start of an incoming packet from the host to transition to operation 503.

[0047] At operation 503, state machine 500 monitors the PID byte following the SYNC bit mode to determine if the packet is an SOF (Single Message Forward) packet. If the PID byte indicates an SOF packet, the USB transaction protocol is considered to be in idle mode and the data flow direction is from the host to the peripheral device. State machine 500 transitions to operation 505 to shut down the squelch circuitry and receiver in the peripheral Rx port to save power. In another aspect, the circuitry performing retiming and relay functions for data received by the peripheral Rx port can also be shut down. The state machine can then return to operation 501 to monitor the squelch signal on the host Rx port to look for the next packet from the host.

[0048] At operation 503, if the PID byte indicates a non-SOF packet, it is assumed that the USB transaction protocol is no longer in idle mode and the direction of data flow can be from the peripheral device to the host. State machine 500 transitions to operation 507 to enable the squelch circuitry and receiver in the peripheral Rx port, preparing it to receive packets from the peripheral device. In one aspect, circuitry performing retiming and relay functions on data received from the peripheral Rx port can also be enabled. The state machine can then return to operation 501 to monitor the squelch signal on the host Rx port for the next packet from the host.

[0049] Figure 6 A timing diagram is shown of a repeater / retimer monitoring a host Rx port in a first scenario of host and device data transactions, according to one aspect of this disclosure, to disable the peripheral Rx port when a Start of Frame (SOF) packet is received and to enable the peripheral Rx port when a non-SOF packet is received.

[0050] The host Rx port monitors bus activity on the data lines from the host to detect the presence of USB packets. If a packet is detected, the host Rx port determines whether the packet is an SOF packet by decoding the PID byte. Initially, the peripheral Rx port can be enabled to prepare for receiving packets from peripheral devices. When the host Rx port detects the first SOF packet 601, it disables the peripheral Rx port by toggling the peripheral Rx port enable signal, thus putting the peripheral Rx port into a power-saving state. In one aspect, the peripheral Rx port enable signal can be... Figure 4 or Figure 5 The peripheral Rx port control signal 318. In the frame following the first SOF packet 601, the host does not send any other packets. When the host Rx port detects the second SOF packet 603, the peripheral Rx port remains in a power-saving state. In one aspect, the frame duration between SOF packets can be one millisecond in full-speed or low-speed USB, a 125 μs microframe duration in high-speed USB, or a frame period interval of other USB specifications.

[0051] When the host Rx port receives the first data packet 605 from the host, the host Rx port re-enables the peripheral Rx port by switching the peripheral Rx port enable signal to command the peripheral Rx port to exit the power-saving state. In one aspect, data packet 601 may include an outgoing address token packet indicating host-to-device data transmission, followed by a data packet containing data for the peripheral device. In another aspect, an incoming address token packet may be present requesting device-to-host data transmission from the peripheral device. In either scenario, the peripheral Rx port is enabled and thus ready to receive the second data packet 607. When the first data packet 601 is a host-to-device data transmission, the second data packet 607 may be a handshake packet returned from the peripheral device to the host, indicating whether the peripheral device successfully received the data packet. In one aspect, when the host sends an incoming address token packet, the second data packet 607 may be the requested device-to-host data packet. A repeater / retimer performs relay and retiming functions on the serial bits of the second data packet 607 for transmission to the host.

[0052] When the host Rx port detects the third SOF packet 609, it disables the peripheral Rx port by switching the peripheral Rx port enable signal, returning the peripheral Rx port to a power-saving state. The host does not send any other packets in frames following the third SOF packet 609. When the host Rx port detects the fourth SOF packet 611, the peripheral Rx port remains in power-saving state.

[0053] Figure 7 A timing diagram is shown of a repeater / retimer monitoring a host Rx port in a second scenario of host and device data transactions, according to one aspect of this disclosure, to disable the peripheral Rx port when a Start of Frame (SOF) packet is received and to enable the peripheral Rx port when a non-SOF packet is received.

[0054] Similar to Figure 6 The host Rx port detects the first SOF packet 701 to disable the peripheral Rx port by switching the peripheral Rx port enable signal, thus putting the peripheral Rx port into a power-saving state. The host Rx port then maintains the power-saving state of the peripheral Rx port upon detecting the second SOF packet 703. Similarly... Figure 6 The host Rx port receives the first data packet 705 to re-enable the peripheral Rx port by switching the peripheral Rx port enable signal, thereby commanding the peripheral Rx port to exit power-saving mode. The first data packet 701 may be a host-to-device data transfer or a device-to-host data transfer request from the peripheral device. However, due to a bus error, the peripheral device does not respond to the first data packet 705 by sending a data packet back to the host within the frame duration of the second SOF packet 703.

[0055] If the host does not receive a data packet from the peripheral device in response to the first data packet 705, the host may time out when the frame duration of the second SOF packet 703 expires. When the host Rx port receives the third SOF packet 707, the host Rx port toggles the peripheral Rx port enable signal to return the peripheral Rx port to a power-saving state. During the frame duration of the third SOF packet 707, the host sends a second data packet 709 to re-initiate host-to-device data transmission. In one aspect, the host may resend the address token packet requesting device-to-host data transmission from the peripheral device.

[0056] When the host Rx port receives the second data packet 709 from the host, the host Rx port toggles the peripheral Rx port enable signal to command the peripheral Rx port to exit power-saving mode. During the frame duration of the third SOF packet 707, the peripheral device generates the third data packet 711 in response to the second data packet 709. The peripheral Rx port receives the third data packet 711, and the repeater / retimer performs forwarding and retiming functions on the serial bits of the third data packet 711 for transmission to the host. When the host Rx port detects the fourth SOF packet 713, the host Rx port disables the peripheral Rx port by toggling the peripheral Rx port enable signal to return the peripheral Rx port to power-saving mode.

[0057] Figure 8 This is a flowchart of a method 800 for a repeater / resetter to monitor USB packets received from a host to control the operation of a peripheral receive port, thereby saving power in idle mode, according to one aspect of this disclosure. In one embodiment, method 800 may be... Figure 1 eUSB / USB repeater 100 Figure 2 The eUSB repeater subsystem 124, eUSBPHY 126, and USB PHY 128, Figure 3 Repeater / retimer, Figure 4 The host Rx port 313 and idle mode power-saving state machine 317 or Figure 5 The state machine 500 is used for execution. In one aspect, method 800 can be executed using a combination of hardware logic or programmable registers that store configuration values.

[0058] At operation 801, the repeater / retimer detects the start of a USB packet from the host. In one aspect, the repeater / retimer can monitor the squelch signal on the data line at high speeds or other data rates from the host. If no squelch signal is present, indicating activity on the data line, the repeater / retimer can detect the SYNC bit mode to indicate the start of a USB packet from the host.

[0059] At operation 803, the repeater / re-timer detects the PID of the USB packet to determine the packet type. The PID can be bytes following the SYNC bit pattern to indicate whether the USB packet is a token packet, data packet, handshake packet, or special packet. Operation 803 can detect the PID to predict the direction of data flow. For example, when the repeater / re-timer detects a token packet such as an SOF packet, the direction of data flow is from the host to the peripheral device. When the repeater / re-timer detects a token packet such as an address token preceding a host-to-peripheral data transfer or a peripheral-to-host data transfer, the direction of data flow is predicted to be from the peripheral device to the host, including handshake packets generated in response to host-to-peripheral data transfers or data packets requested by the requested peripheral-to-host data transfer.

[0060] At operation 805, the repeater / retimer determines whether the PID indicates an SOF packet. If the PID indicates an SOF packet, the transaction protocol between the host and the peripheral device is considered to be in idle mode, and it is expected that the peripheral device will not transmit packets to the host.

[0061] At operation 807, if the PID indicates an SOF packet, the repeater / retimer disables the receiving circuitry of the repeater / retimer's peripheral Rx port to save power. In one aspect, the repeater / retimer can disable the transmission envelope detector, including the squelch detection circuitry and other receiving circuitry in the peripheral Rx port, and can disable the circuitry used for relaying and retiming data received from peripheral devices. In another aspect, the clock for the receiving, relaying, and retiming circuitry used to receive and process data from peripheral devices can be turned off.

[0062] Otherwise, at operation 809, if the PID indicates a non-SOF packet, the repeater / retimer enables the receive circuitry of the repeater / retimer's peripheral Rx port to prepare the peripheral Rx port for receiving packets from the peripheral device. In one aspect, if the circuitry is off, the repeater / retimer can turn on the transmission envelope detector, including the squelch detection circuitry and other receive circuitry in the peripheral Rx port. In one aspect, if the circuitry used for relaying and retiming data received from the peripheral device was previously off, the repeater / retimer can enable that circuitry. In one aspect, if the clock of the receive, relay, and retiming circuitry used for receiving and processing data from the peripheral device is off, it can be turned on again.

[0063] At operation 811, the repeater / retimer detects the end of a USB packet from the host. In one aspect, the repeater / retimer can detect packet end patterns corresponding to various data rates. The repeater / retimer then returns to operation 801 to detect the start of the next USB packet from the host.

[0064] The various implementations of the USB repeater subsystem described herein for intercepting host packets to predict the direction of data flow and thereby disabling inactive circuitry on peripheral ports may include a variety of operations. These operations may be performed and / or controlled by hardware components, digital hardware and / or firmware / programmable registers (e.g., as implemented in a computer-readable medium) and / or combinations thereof. The methods and illustrative examples described herein are not inherently related to any particular computer or other device. Various systems (e.g., such as USB hubs and docking stations) may be used in accordance with the teachings described herein, or it may prove convenient to construct more specialized devices to perform the required method steps. The required structures for various systems in these systems will emerge as set forth in the description above.

[0065] Computer-readable media used to implement the operations of various aspects of this disclosure may be non-transitory computer-readable storage media, which may include, but are not limited to, electromagnetic storage media, magneto-optical storage media, read-only memory (ROM), random access memory (RAM), erasable programmable memory (e.g., EPROM and EEPROM), flash memory, or other media of a non-transitory type now known or hereafter developed that are suitable for storing configuration information.

[0066] The above description is intended to be illustrative and not restrictive. Although this disclosure has been described with reference to specific illustrative examples, it will be appreciated that this disclosure is not limited to the described examples. The scope of this disclosure should be determined by referring to the appended claims and the full scope of their equivalents.

[0067] As used herein, unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “the” are intended to also include the plural forms. It will also be understood that the terms “comprise,” “comprising,” “include,” and / or “including,” as used herein, specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. Therefore, the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting.

[0068] It should also be noted that in some alternative implementations, the functions / actions may not occur in the order shown in the figures. For example, depending on the functions / actions involved, the two figures shown consecutively may actually be executed substantially simultaneously or sometimes in reverse order.

[0069] Although the method operations are described in a specific order, it should be understood that other operations may be performed between the described operations, the described operations may be adjusted so that they occur at slightly different times, or the described operations may be distributed across a system that allows processing operations to occur at various intervals associated with processing. For example, some operations may be performed at least partially in reverse order, concurrently with and / or in parallel with other operations.

[0070] Various units, circuits, or other components may be described or claimed as being "configured to" or "configurable to" perform one or more tasks. In such a context, the phrase "configured to" or "configurable to" is used to indicate a structure by indicating that the unit / circuit / component includes a structure (e.g., a circuit system) that performs one or more tasks during operation. Thus, even if a specified unit / circuit / component is currently inoperable (e.g., not switched on), it can be said that the unit / circuit / component is configured to perform a task or can be configured to perform a task. Units / circuit / components used with the language "configured to" or "configurable to" include hardware such as circuits, memory storing program instructions executable to perform operations, etc. The statement that a unit / circuit / component is "configured to" or "configurable to" perform one or more tasks is expressly not intended to invoke paragraph 6 of 35 U.S.SC112 against that unit / circuit / component.

[0071] Additionally, "configured to" or "configurable to" can include general-purpose structures (e.g., general-purpose circuit systems) manipulated by firmware (e.g., FPGAs) to operate in a manner capable of performing the tasks in question. "Configured to" can also include adapting a manufacturing process (e.g., a semiconductor manufacturing facility) to manufacture devices (e.g., integrated circuits) suitable for implementing or performing one or more tasks. It is explicitly stated that "configurable to" is not intended to apply to blank media, unprogrammed processors, or unprogrammed programmable logic devices, programmable gate arrays, or other unprogrammed devices, unless accompanied by programmed media that endows the unprogrammed device with the ability to be configured to perform the disclosed functions.

[0072] For illustrative purposes, the foregoing description has been described with reference to specific embodiments. However, the above illustrative discussion is not intended to be exhaustive or to limit the invention to the precise forms disclosed. Many modifications and variations are possible in light of the foregoing teachings. Embodiments were chosen and described to best illustrate the principles of these embodiments and their practical application, thereby enabling those skilled in the art to best utilize these embodiments and various modifications that may be suitable for the particular purpose contemplated. Therefore, these embodiments are to be considered illustrative rather than restrictive, and the invention is not limited to the details given herein, but modifications to these details may be made within the scope of the appended claims and their equivalents.

Claims

1. An apparatus for relaying Universal Serial Bus packets exchanged between a host and peripheral devices, comprising: A host port, configured to receive Universal Serial Bus packets from the host; A peripheral port, configured to receive Universal Serial Bus packets from the peripheral device; The processing system is configured as follows: Detect Universal Serial Bus packets received from the host via the host port; Determine the type of the received Universal Serial Bus (USB) packet; In response to the Universal Serial Bus packet being determined to be a Start of Frame packet, the peripheral port is disabled to prevent the peripheral port from receiving Universal Serial Bus packets from the peripheral device. as well as In response to the Universal Serial Bus (USB) packet being determined to be a non-start-of-frame packet, the peripheral port is enabled to prepare it for receiving USB packets from the peripheral device. The non-frame start packet includes an address token that instructs the host to prepare to transmit a data packet to the peripheral device or requests the peripheral device to transmit a data packet to the host.

2. The apparatus according to claim 1, wherein, In order to detect the Universal Serial Bus packets received from the host by the host port, the processing system is configured to: Detect the start of the Universal Serial Bus packet; as well as Detect the packet identifier of the Universal Serial Bus packet.

3. The apparatus according to claim 2, wherein, In order to detect the start of the Universal Serial Bus packet, the processing system is configured to: When the host port is configured to receive high-speed data packets from the host using the Universal Serial Bus, the absence of a squelch signal is detected. as well as Detect the synchronization mode of the Universal Serial Bus packet.

4. The apparatus according to claim 1, wherein, To determine the type of the received Universal Serial Bus (USB) packet, the processing system is configured to: Detect the packet identifier of the Universal Serial Bus packet; as well as The type of the Universal Serial Bus packet is determined based on the packet identifier.

5. The apparatus according to claim 1, wherein, The frame start packet includes a periodic packet sent by the host to the peripheral device as a timing reference for synchronizing the Universal Serial Bus packets exchanged between the host and the peripheral device.

6. The apparatus according to claim 1, wherein, When the received Universal Serial Bus packet is identified as the Start of Frame packet, the direction of the data flow is predicted to be from the host to the peripheral device, and the processing system is configured to disable the peripheral port to save power.

7. The apparatus according to claim 1, wherein, The apparatus further includes a relay circuit system configured to relay the Universal Serial Bus (USB) packets for the host received from the peripheral device by the peripheral port, and wherein, in response to the USB packet being identified as the start of a frame packet, the processing system is further configured to disable the relay circuit system.

8. The apparatus according to claim 1, wherein, When the received Universal Serial Bus packet is determined to be the non-start-of-frame packet, the direction of the data flow is predicted to be from the peripheral device to the host, and wherein the processing system is configured to enable the peripheral port to receive data packets transmitted by the peripheral device or handshake packets generated by the peripheral device in response to the non-start-of-frame packet.

9. The apparatus according to claim 1, wherein, It provides a plurality of peripheral ports including the aforementioned peripheral ports and a plurality of peripheral devices including the aforementioned peripheral devices, wherein, In response to the Universal Serial Bus (USB) packet being determined as the start of a frame packet, all peripheral ports among the plurality of peripheral ports are disabled to prevent the device from receiving USB packets from all peripheral devices among the plurality of peripheral devices; and In response to the Universal Serial Bus (USB) packet being determined to be the non-start-of-frame packet, one of the plurality of peripheral ports is enabled to prepare the enabled peripheral port to receive USB packets from a corresponding peripheral device among the plurality of peripheral devices.

10. A method for relaying Universal Serial Bus packets exchanged between a host and peripheral devices, comprising: Universal Serial Bus (USB) packets received from the host are detected by a repeater that conforms to the Universal Serial Bus protocol. Determine the type of the received Universal Serial Bus (USB) packet; In response to the Universal Serial Bus (USB) packet being determined to be a Start of Frame packet, the receiving circuitry of the repeater of the USB compliant device used to receive USB packets from the peripheral device is disabled to prevent the receiving circuitry from receiving USB packets from the peripheral device. as well as In response to the Universal Serial Bus (USB) packet being determined to be a non-start-of-frame packet, the receive circuitry is activated to prepare the receive circuitry to receive USB packets from the peripheral device. The non-frame start packet includes an address token that instructs the host to prepare to transmit a data packet to the peripheral device or requests the peripheral device to transmit a data packet to the host.

11. The method according to claim 10, wherein, Detecting the Universal Serial Bus packets received from the host includes: Detecting the start of the Universal Serial Bus packet; and Detect the packet identifier of the Universal Serial Bus packet.

12. The method according to claim 11, wherein, The start of detecting the Universal Serial Bus packet includes: When the Universal Serial Bus (USB) compliant repeater receives a USB high-speed data packet from the host, it detects the absence of a squelch signal; and Detect the synchronization mode of the Universal Serial Bus packet.

13. The method according to claim 10, wherein, Determining the type of the received Universal Serial Bus (USB) packet includes: Detect the packet identifier of the Universal Serial Bus packet; and The type of the Universal Serial Bus packet is determined based on the packet identifier.

14. The method of claim 10, wherein, The start-of-frame packet includes a periodic packet sent by the host to the peripheral device as a timing reference for synchronizing Universal Serial Bus packets exchanged between the host and the peripheral device.

15. The method according to claim 10, wherein, When the received Universal Serial Bus (USB) packet is identified as the start of a frame packet, the direction of the data flow is expected to be from the host to the peripheral device, and wherein disabling the receiving circuitry system saves power to the USB compliant repeater.

16. The method of claim 10, further comprising: In response to identifying the Universal Serial Bus (USB) packet as the start of frame packet, the relay circuitry system of the USB compliant repeater for relaying the USB packets received from the peripheral device for the host is disabled.

17. The method according to claim 10, wherein, When a received Universal Serial Bus packet is determined to be the non-start-of-frame packet, the direction of the data flow is predicted to be from the peripheral device to the host, and wherein enabling the receive circuitry system includes enabling the receive circuitry system to receive data packets transmitted by the peripheral device or handshake packets generated by the peripheral device in response to the non-start-of-frame packet.

18. The method according to claim 10, wherein, A plurality of receiving circuit systems including the aforementioned receiving circuit system and a plurality of peripheral devices including the aforementioned peripheral devices are provided, wherein, In response to identifying the Universal Serial Bus (USB) packet as the start of frame packet, disable all receiver circuit systems in the plurality of receiver circuit systems to prevent the USB-compliant repeater from receiving USB packets from all peripheral devices in the plurality of peripheral devices; and In response to identifying the Universal Serial Bus (USB) packet as the non-start-of-frame packet, one of the plurality of receiver circuit systems is enabled to prepare the enabled receiver circuit system to receive the USB packet from a corresponding peripheral device among the plurality of peripheral devices.

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