Display panel and display device

Abstract

This application provides a display panel and a display device. The display panel includes a substrate, multiple scan lines, multiple data lines, multiple display sub-pixels, and at least one test sub-pixel. The display sub-pixel includes a display transistor, a pixel electrode, and a common electrode. The first drain of the display transistor is electrically connected to the pixel electrode, and at least two common electrodes are electrically connected. The test sub-pixel includes a test transistor, a first electrode, and a second electrode. The second gate and second source of the test transistor are electrically connected to the first gate and first source of at least one display transistor, respectively. The first electrode is located on the side of the second electrode away from the film layer where the test transistor is located, and the second drain is electrically connected to the first electrode, so that the test transistor and at least one display transistor are in the same working environment. By detecting the electrical characteristics of the test transistor, the problem of not being able to test the electrical characteristics of the display transistor can be solved.

Description

[Technical Field]

[0001] This application relates to the field of display technology, and in particular to a display panel and display device. [Background Technology]

[0002] Currently, display devices typically use thin-film transistor (TFT) array substrates. TFTs are crucial components in existing flat-panel display devices, and their characteristics directly impact display quality. Therefore, accurately analyzing TFT defects in the display area allows for effective mitigation of these defects, leading to improvement solutions that enable the TFTs in the display device to meet higher requirements and ultimately achieve high-quality display.

[0003] In the existing technology, the testing of TFT characteristics in display devices is generally divided into two types: one is to design some TFT characteristic testing element groups in the blank area of ​​the motherboard of the display panel, but these TFT characteristic testing element groups will disappear with the cutting process of the motherboard, so the time period for testing the characteristics of TFT is limited; the other is to design one or more TFT characteristic testing element groups at the step of the daughterboard of the display panel, but in practical applications, this method is not accurate enough for testing the characteristics of TFT in the display panel.

[0004] [Application Content]

[0005] In view of this, embodiments of this application provide a display panel and a display device.

[0006] In a first aspect, this application provides a display panel, including a substrate and a plurality of scan lines and a plurality of data lines disposed on the substrate, the display panel further comprising:

[0007] Multiple display sub-pixels include display transistors, pixel electrodes, and common electrodes; the display transistors include a first gate, a first source, a first drain, and a first semiconductor layer, wherein the first gate is electrically connected to the scan line, the first source is electrically connected to the data line, and the first drain is electrically connected to the pixel electrode; the common electrodes of at least two of the display sub-pixels are electrically connected.

[0008] At least one test sub-pixel includes a test transistor, a first electrode, and a second electrode; the test transistor includes a second gate, a second source, a second drain, and a second semiconductor layer, wherein the second gate and the second source are electrically connected to the first gate and the first source of at least one of the display transistors, respectively;

[0009] The first electrode is located on the side of the second electrode away from the substrate, and the second drain of the test transistor is electrically connected to the first electrode.

[0010] In one implementation of the first aspect, the common electrode is located on the side of the pixel electrode away from the substrate, and the first electrode and the common electrode are disposed on the same layer.

[0011] In one implementation of the first aspect, the second electrode in the test sub-pixel is electrically connected to the common electrode.

[0012] In one implementation of the first aspect, the overlap area between the first electrode and the second electrode in the test sub-pixel is S1, and the overlap area between the pixel electrode and the common electrode in the display sub-pixel is S2, where S1 = S2.

[0013] In one implementation of the first aspect, the pixel electrode and the common electrode, the one disposed in the same layer as the first electrode, includes a plurality of slits; the first electrode is a continuous structure covering the entire surface.

[0014] In one implementation of the first aspect, the first electrode serves as a first test pin.

[0015] In one implementation of the first aspect, the first electrode is electrically connected to the first test pin.

[0016] In one implementation of the first aspect, the second gate and the second source are electrically connected to the first gate and the first source of at least one of the display transistors, respectively, comprising:

[0017] The second gate and the first gate of at least one of the display transistors are both electrically connected to the same scan line, and the second source and the first source of the at least one of the display transistors are both electrically connected to the same data line.

[0018] In one implementation of the first aspect, the scan line, which is electrically connected to both the second gate of the test transistor and the first gate of the display transistor, is electrically connected to a second test pin; and the data line, which is electrically connected to both the second source of the test transistor and the first source of the display transistor, is electrically connected to a third test pin.

[0019] In one implementation of the first aspect, the display panel further includes a plurality of dummy sub-pixels, wherein the test sub-pixels are arranged in the same row or column as the dummy sub-pixels.

[0020] Secondly, this application provides a display device, including a display panel as provided in the first aspect.

[0021] The display panel and display device provided in this application embodiment, by setting the connection method of each pole of the test transistor in the test sub-pixel, make the test transistor and the display transistor have the same working environment. Thus, by detecting the electrical characteristics of the test transistor, the electrical characteristics of the display transistor can be detected. When the display transistor in the display panel malfunctions, the malfunction can be analyzed and processed according to the electrical characteristics of the display transistor, thereby enabling the display panel to achieve high-quality display. [Attached Image Description]

[0022] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 This is a schematic diagram of a planar structure of a display panel provided in an embodiment of the present invention;

[0024] Figure 2 for Figure 1 A cross-sectional diagram of subpixels is displayed in the image.

[0025] Figure 3 for Figure 1 The diagram shows another cross-sectional view using sub-pixels;

[0026] Figure 4 for Figure 1 A cross-sectional schematic diagram of a sub-pixel used in testing;

[0027] Figure 5 for Figure 1 A cross-sectional view of the central display panel;

[0028] Figure 6 for Figure 1 Another cross-sectional view of the central display panel;

[0029] Figure 7 for Figure 1 Another cross-sectional view of the central display panel;

[0030] Figure 8 This is a schematic diagram of the projection of a test sub-pixel and a display sub-pixel in a display panel, provided by an embodiment of the present invention.

[0031] Figure 9 This is a schematic diagram of a planar structure of a display panel provided in an embodiment of the present invention;

[0032] Figure 10 A schematic diagram of another planar structure of a display panel provided in an embodiment of the present invention;

[0033] Figure 11 This is a schematic diagram of a display device provided in an embodiment of the present invention.

Detailed Implementation Methods

[0034] To better understand the technical solution of this application, the embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0035] It should be understood that the described embodiments are merely some, not all, of the embodiments in this application. All other embodiments obtained by those skilled in the art based on the embodiments in this application without inventive effort are within the scope of protection of this application.

[0036] The terminology used in the embodiments of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of this application. The singular forms “a,” “the,” and “the” used in the embodiments of this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0037] It should be understood that the term "and / or" used in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0038] In the description of this specification, it should be understood that the terms "substantially", "approximately", "about", "about", "generally", "largely" used in the claims and embodiments of this application refer to values ​​that can be generally agreed upon within a reasonable range of process operations or tolerances, rather than a precise value.

[0039] It should be understood that although terms such as first, second, third, etc., may be used to describe electrodes in the embodiments of this application, these directions, etc., should not be limited to these terms. These terms are only used to distinguish directions, etc., from one another. For example, without departing from the scope of the embodiments of this application, a first electrode may also be referred to as a second electrode, and similarly, a second electrode may also be referred to as a first electrode.

[0040] Through meticulous and in-depth research, the applicant in this case has provided a solution to the problems existing in the prior art.

[0041] Figure 1 This is a schematic diagram of a planar structure of a display panel provided in an embodiment of the present invention. Figure 2 for Figure 1A cross-sectional diagram showing the subpixels.

[0042] like Figure 1 and Figure 2 As shown, the display panel 100 provided in this embodiment of the invention includes a display area AA and a non-display area NA. Furthermore, the display panel 100 includes a first substrate 101 and a substrate 102 disposed opposite to each other, and a liquid crystal layer 103 disposed between the first substrate 101 and the substrate 102. A plurality of scan lines 41 and a plurality of data lines 42 are disposed on the substrate 102, and the mutually insulated scan lines 41 and data lines 42 intersect to define a plurality of display sub-pixels 10. The display panel 100 also includes at least one test sub-pixel 20. The display sub-pixels 10 are located in the display area AA, and the test sub-pixels 20 may be located in the non-display area NA or at the edge of the display area AA.

[0043] Figure 3 for Figure 1 The diagram shows another cross-sectional structure using sub-pixels.

[0044] like Figure 2 and Figure 3 As shown, the display sub-pixel 10 includes a display transistor 44, a pixel electrode 13, a common electrode 14, a color resist 18, and a black matrix 19.

[0045] In this design, the black matrix 19 is disposed in the area surrounding the color resist 18, and the color resist 18 disposed in the display sub-pixel 10 is used to realize the display function of the display sub-pixel 10. Additionally, in this technical solution, the pixel electrode 13 can be disposed on the side of the common electrode 14 away from the substrate 102, or it can be disposed on the side of the common electrode 14 closer to the substrate 102. For example, as... Figure 2 As shown, the pixel electrode 13 in the sub-pixel 10 is disposed on the side of the common electrode 14 away from the substrate 102. For example, as Figure 3 As shown, the pixel electrode 13 in the sub-pixel 10 is disposed on the side of the common electrode 14 near the substrate 102.

[0046] refer to Figures 1-3The display transistor 44 includes a first gate g1, a first source s1, a first drain d1, and a first semiconductor layer 16. The first gate g1 of the display transistor 44 is electrically connected to a scan line 41, and the signal on the scan line 41 controls the switching state of the display transistor 44. The first source s1 of the display transistor 44 is electrically connected to a data line 42 and is used to receive data signals from the data line 42. The first drain d1 of the display transistor 44 is electrically connected to a pixel electrode 13 and is used to transmit the data signals received at the first source s1 to the pixel electrode 13 through the first drain d1. In operation, the display transistor 44 is turned on under the control of the scan line 41, providing the data signals from the data line 42 to its corresponding pixel electrode 13, thus controlling the display of the sub-pixel 10.

[0047] Furthermore, when setting the common electrode 14, the common electrodes 14 in at least two display sub-pixels 10 are electrically connected, meaning that the common voltage received by the common electrodes 14 in the at least two display sub-pixels 10 is the same. Therefore, by controlling the magnitude of the data signal received by the pixel electrodes 13 in the at least two display sub-pixels 10, the at least two display sub-pixels 10 can emit light of their respective corresponding brightness.

[0048] Furthermore, the common electrodes 14 in all display sub-pixels 10 can be connected together. Alternatively, the common electrodes 14 in some display sub-pixels 10 can be connected together to serve as touch electrodes.

[0049] Figure 4 for Figure 1 A cross-sectional schematic diagram of a sub-pixel used in testing.

[0050] like Figure 4 As shown, at least one test sub-pixel 20 includes a test transistor 45, a first electrode 11, and a second electrode 12. The test transistor 45 includes a second gate g2, a second source s2, a second drain d2, and a second semiconductor layer 17. The structures of the first electrode 11 and the second electrode 12 are not specifically limited here. Since the test sub-pixel 20 does not need to have a display function, the area where the test sub-pixel 20 is located can be as follows: Figure 4 The color stop 18 and black matrix 19 are not set as shown. Alternatively, the area where the test sub-pixel 20 is located can be completely covered by black matrix 19. There are no specific limitations here.

[0051] Combination Figure 1 and Figure 4The second gate g2 and the second source s2 of the test transistor 45 are electrically connected to the first gate g1 and the first source s1 of at least one display transistor 44, respectively, so that the test transistor 45 can be in the same working environment as the at least one display transistor 44, that is, the test transistor 45 and the at least one display transistor 44 have the same switching state and the same data signal received by the source s.

[0052] The first electrode 11 is located on the side of the second electrode 12 away from the substrate, and the second drain d2 of the test transistor 45 is electrically connected to the first electrode 11. Specifically, the electrical connection can be achieved through the via 15, which is used to transmit the signal received by the second drain d2 to the first electrode 11.

[0053] The display transistor 44 is an important component in the display panel 100, and its characteristics have a direct impact on the display quality of the display panel 100. Therefore, when the display transistor 44 in the display panel 100 malfunctions, if the electrical characteristics of the display transistor 44 can be accurately tested, the malfunction can be quickly and accurately analyzed, and improvement solutions can be proposed to improve the display yield of the display panel 100.

[0054] In this technical solution, the second gate g2 and second source s2 of the test transistor 45 are electrically connected to the first gate g1 and first source s1 of at least one display transistor 44, respectively. This means that the test transistor 45 and the at least one display transistor 44 have the same switching state and receive the same data signal at their sources s1 and s2, placing them in the same operating environment. Therefore, when a malfunction occurs in the display transistor 44 of the display panel 100, the malfunction can be analyzed and addressed more accurately.

[0055] Furthermore, in this embodiment, the first electrode 11 is located on the side of the second electrode 12 away from the substrate 102. Thus, the first electrode 11 is located above the film layer of the second electrode 12, and the first electrode is electrically connected to the second drain d2 of the test transistor 45. In this case, the signal of the second drain d2 of the test transistor 45 is transmitted to the first electrode 11 near the top layer on the substrate 102, which facilitates the probe to detect the signal on the second drain d2 of the test transistor 45.

[0056] Figure 5 for Figure 1 A cross-sectional structural diagram of a display panel. Figure 6 for Figure 1 Another cross-sectional view of the display panel is shown in the diagram. Figure 7 for Figure 1 Another cross-sectional structural diagram of the display panel.

[0057] refer to Figures 5-7 In the test sub-pixel 20, one of the first electrode 11 and the second electrode 12 can be set in the same layer as the pixel electrode 13 in the display sub-pixel 10, and the other can be set in the same layer as the common electrode 14 in the display sub-pixel 10.

[0058] like Figure 5 and Figure 6 As shown, in one embodiment of this application, the common electrode 14 of the display panel 100 provided by the present invention is located on the side of the pixel electrode 13 away from the substrate 102, and the first electrode 11 of the test sub-pixel 20 is disposed on the same layer as the common electrode 14.

[0059] In this embodiment, as Figure 5 and Figure 6 As shown, the common electrode 14 of the display sub-pixels 10 in the display panel 100 is located on the side of the pixel electrode 13 away from the substrate 102, that is, the film layer where the common electrode 14 is located is located above the film layer where the pixel electrode 13 is located. The second drain d2 of the test transistor 45 is electrically connected to the first electrode 11, and the signal received by the second drain d2 can be transmitted to the first electrode 11, that is, the signal of the second drain d2 of the test transistor 45 is led to the conductive film layer located at the top in the display panel.

[0060] Through analysis of the display panel 100 and its working process, the inventors discovered that the edge field driving display panel 100, in a film layer architecture where the common electrode is located above the pixel electrode (TOP COM), achieves edge field driving in a manner similar to... Figure 3 In the case shown, the probe cannot reach the second drain d2 of the test transistor 45, so it is impossible to analyze the malfunction of the display transistor 44 in the display panel 100.

[0061] Based on the above problems and the analysis of their causes, in this technical solution, the first electrode 11 of the test sub-pixel 20 in the display panel 100 is located on the side of the second electrode 12 away from the substrate 102, that is, the first electrode 11 is located above the second electrode 12. Thus, when the signal received by the second drain d2 of the test transistor 45 is transmitted to the first electrode 11, the performance of the test transistor 45 is obtained by analyzing the signal received by the first electrode 11, thereby determining the performance of the display transistor 44. This solves the problem that the electrical signal of the second drain d2 of the test transistor 45 cannot be measured under the film layer architecture where the common electrode of the display panel 100 is located above the pixel electrode (TOP COM).

[0062] In one technical solution corresponding to this embodiment, such as Figure 5 and Figure 6As shown, the second electrode 12 is electrically connected to the common electrode 14. Specifically, the electrical connection can be achieved through a via 15. That is, the voltage received by the second electrode 12 in the test sub-pixel 20 is the same as the common voltage received by the common electrode 14 in the display sub-pixel 10. Therefore, during the display process of the display panel, the voltage difference between the first electrode 11 and the second electrode 12 is the same as the voltage difference between the pixel electrode 13 and the common electrode 14. This avoids the generation of a bias electric field between the test sub-pixel 20 and the display sub-pixel 10, which could lead to abnormal bright lines on the display panel 100.

[0063] Furthermore, to ensure normal display of the sub-pixels 10, the common electrode 14 located on the side of the pixel electrode 13 away from the substrate 102 needs to be configured as a multi-slit structure. However, as Figure 6 As shown, the first electrode 11 can be a continuous structure, in which case the first electrode 11 can be directly used as a probe pad, that is, the probe can be directly attached to the first electrode 11.

[0064] In one embodiment of this application, such as Figure 7 As shown, in this embodiment of the invention, the pixel electrode 13 of the display panel 100 is located on the side of the common electrode 14 that is away from the substrate 102, and the first electrode 11 of the test sub-pixel 20 is disposed on the same layer as the pixel electrode 13. In this embodiment, the second electrode 12 can be disposed on the same layer as the common electrode 14, and the second electrode 12 can be a structure continuous with the common electrode 14, except that the two are located in the area where the test sub-pixel 20 is located and the area where the display sub-pixel 10 is located, respectively.

[0065] Figure 8 This is a schematic diagram of the projection of a test sub-pixel and a display sub-pixel in a display panel, provided as an embodiment of this application.

[0066] In one embodiment of this application, such as Figure 8 As shown, the overlap area between the first electrode 11 and the second electrode 12 in the test sub-pixel 20 of the display panel 100 is S1, and the overlap area between the pixel electrode 13 and the common electrode 14 in the display sub-pixel 10 is S2, where S1 = S2. It should be noted that due to the influence of process precision, S1 = S2 means that the overlap area between the first electrode 11 and the second electrode 12 in the test sub-pixel 20 of the display panel 100 is approximately equal to the overlap area between the pixel electrode 13 and the common electrode 14 in the display sub-pixel 10, or in other words, the overlap area between the first electrode 11 and the second electrode 12 in the test sub-pixel 20 of the display panel 100 is approximately equal to the overlap area between the pixel electrode 13 and the common electrode 14 in the display sub-pixel 10.

[0067] In this embodiment, the overlap area between the first electrode 11 and the second electrode 12 in the test sub-pixel 20 is set to be substantially the same as the overlap area between the pixel electrode 13 and the common electrode 14 in the display sub-pixel 10. Therefore, the storage capacitance formed by the overlap of the first electrode 11 and the second electrode 12 is the same as the storage capacitance formed by the overlap of the pixel electrode 13 and the common electrode 14. This makes the total capacitance of the test sub-pixel 20 substantially the same as the total capacitance of the display sub-pixel 10. When the total capacitance of the test sub-pixel 20 is the same as the total capacitance of the display sub-pixel 10, the problem of abnormal bright lines appearing on the display panel due to the bias electric field generated between the two pixels can be mitigated.

[0068] In one implementation of this embodiment, please refer to... Figure 8 and Figure 6 , Figure 7 As shown, the pixel electrode 13 and the common electrode 14 of the display panel 100, which are disposed on the same layer as the first electrode 11, may include multiple slits and the first electrode 11 is a continuous structure on the entire surface.

[0069] The upper one of the pixel electrode 13 and the common electrode 14 of the display sub-pixel 10 needs to have multiple slits. However, since the area occupied by the test sub-pixel 20 is usually smaller than that occupied by the display sub-pixel 10, the area occupied by each electrode in the test sub-pixel 20 is also smaller than that occupied by each electrode in the display sub-pixel 10. Therefore, by setting the first electrode 11 as a continuous structure over an entire surface, this application can achieve a capacitance between the first electrode 11 and the second electrode 12 that is substantially the same as the capacitance in the pixel electrode 13 and the common electrode 14 within a smaller area.

[0070] For example, please combine Figure 8 and Figure 7 The first electrode 11 has a continuous structure across the entire surface, and the pixel electrode 13, which is disposed on the same layer as the first electrode 11, includes multiple slits.

[0071] For example, please combine Figure 8 With Figure 6 The first electrode 11 has a continuous structure, and the common electrode 14, which is disposed in the same layer as the first electrode 11, includes multiple slits.

[0072] Figure 9 This is a schematic diagram of a planar structure of a display panel provided in an embodiment of the present invention. Figure 10 This is a schematic diagram of another planar structure of a display panel provided in an embodiment of the present invention.

[0073] In this embodiment, the second gate g2 and the second source s2 of the test transistor 45 are electrically connected to the scan line 41 and the data line 42, respectively. Test pins can then be led out from the scan line 41 and the data line 42, which are electrically connected to the second gate g2 and the second source s2, respectively. That is, the test pin corresponding to the second gate g2 of the test transistor 45 is electrically connected to the second gate g2 through the scan line 41, and the test pin corresponding to the second source s2 of the test transistor 45 is electrically connected to the second source s2 through the data line 42.

[0074] For example, the scan line 41 electrically connected to the second gate g2 can lead to the second test pin A2, and the data line 42 electrically connected to the second source s2 can lead to the third test pin A3. Then, the second test pin A2 and the third test pin A3 can respectively contact different probes to transmit corresponding test signals.

[0075] In one technical solution of this embodiment, such as Figure 9 As shown, the first electrode 11 can serve as the first test pin A1, that is, the test pin corresponding to the second drain d2 of the test transistor 45 directly reuses the first electrode 11. Then, the first electrode 11 can contact the probe to transmit the corresponding test signal.

[0076] In one technical solution of this embodiment, such as Figure 10 As shown, the first electrode 11 of the test transistor 45 is electrically connected to the first test pin A1. That is, the test pin corresponding to the second drain d2 of the test transistor 45 is electrically connected to the second drain d2 of the test transistor 45 through the first electrode 11. Then, the first test pin A1 contacts the probe to receive or transmit the signal on the second drain d2 of the test transistor 45.

[0077] like Figure 1 and Figure 9 , Figure 10 As shown, an embodiment of the present invention provides a display panel 100, wherein the second gate g2 and the second source s2 of the test transistor 45 in the display panel 100 are electrically connected to the first gate g1 and the first source s1 of at least one display transistor 44, respectively.

[0078] In one embodiment of this application, such as Figure 1As shown, the second gate g2 of the test transistor 45 and the first gate g1 of at least one display transistor 44 are both electrically connected to the same scan line 41, so that the signal on the scan line 41 can simultaneously control the switching state of the test transistor 45 and the at least one display transistor 44, that is, the switching states of the test transistor 45 and the at least one display transistor 44 are the same. The second source s2 of the test transistor 45 and the first source s1 of the at least one display transistor 44 are both electrically connected to the same data line 42, so that the second source s2 of the test transistor 45 and the first source s1 of the at least one display transistor 44 receive the same signal. That is, in this embodiment, the gate and source signals of the test transistor 45 and the at least one display transistor 44 are always the same.

[0079] In this embodiment, the second gate g2 of the test transistor 45 and the first gate g1 of at least one display transistor 44 are both electrically connected to the same scan line 41, and the second source s2 of the test transistor 45 and the first source s1 of the at least one display transistor 44 are both electrically connected to the same data line 42, so that the test transistor 45 and the at least one display transistor 44 are in the same working environment. That is, the electrical signals on the first gate g1, first source s1, and first drain d1 of a test transistor 45 are the same as the electrical signals on the second gate g2, second source s2, and second drain d2 of at least one display transistor 44.

[0080] In the technical solution of this embodiment, such as Figure 8 and 9 As shown, the scan line 41, which is electrically connected to the second gate g2 of the test transistor 45 and the first gate g1 of the display transistor 44, is electrically connected to the second test pin A2, and the data line 42, which is electrically connected to the second source s2 of the test transistor 45 and the first source s1 of the display transistor 44, is electrically connected to the third test pin A3.

[0081] At this time, the signal on the second gate g2 of the test transistor 45 can be obtained by testing the signal on the second test pin A2, or the second gate g2 of the test transistor 45 can be made to receive a probe signal by outputting a probe signal to the second test pin A2. Similarly, the signal on the second source s2 of the test transistor 45 can be obtained by testing the signal on the third test pin A3, or the second source s2 of the test transistor 45 can be made to receive a probe signal by outputting a probe signal to the third test pin A3.

[0082] like Figure 1 , Figure 9 and Figure 10As shown, the display panel 100 provided in this embodiment of the invention further includes a plurality of dummy sub-pixels 30. The gate of the transistor in the dummy sub-pixel 30 is electrically connected to the dummy scan line G-dummy, and / or, the source is electrically connected to the dummy data line S-dummy. The test sub-pixel 20 is arranged in the same row or column as the dummy sub-pixels 30, but the gate of the test sub-pixel 20 is electrically connected to the scan line 41 and the source is electrically connected to the data line 42.

[0083] In this technical solution, the connection method of the transistors in the partially dummy sub-pixel 30 is adjusted so that the gate and source of the transistors in the partially dummy sub-pixel 30 are connected to the same signal line as the gate and source of the transistors in a display sub-pixel 10. Then, the partially dummy sub-pixel 30 is reused as the test sub-pixel 20 in the embodiment of this application.

[0084] Figure 11 This is a schematic diagram of a display device provided in an embodiment of the present invention.

[0085] like Figure 11 As shown, this application embodiment also provides a display device, including the display panel 100 provided in any of the above embodiments and a housing, wherein the housing forms an accommodating space for accommodating the display panel. The housing can be rigid or flexible, and the present invention does not impose specific limitations on it. It is understood that the display device provided in the embodiments of the present invention can be other display devices with display functions, such as computers, televisions, and vehicle-mounted display devices, and the present invention does not impose specific limitations on it.

[0086] The display device provided in this application embodiment, by configuring the connection method of each electrode of the test transistor 45 in the test sub-pixel 20, allows the test transistor 45 to have the same operating environment as the display transistor 44. Therefore, the detection of the test transistor 45 in the test sub-pixel 20 can effectively resolve defects in the display transistor 44 in the display sub-pixel 10. Furthermore, the signal from the second drain d2 of the test transistor 45 is transmitted to the first electrode 11 disposed on the substrate 102 near the top layer, facilitating the probe to detect the signal on the second drain d2 of the test transistor 45.

[0087] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A display panel, characterized in that, The display panel includes a substrate and multiple scan lines and multiple data lines disposed on the substrate. Multiple display sub-pixels include display transistors, pixel electrodes, and common electrodes; the display transistors include a first gate, a first source, a first drain, and a first semiconductor layer, wherein the first gate is electrically connected to the scan line, the first source is electrically connected to the data line, and the first drain is electrically connected to the pixel electrode; the common electrodes of at least two of the display sub-pixels are electrically connected. At least one test sub-pixel includes a test transistor, a first electrode, and a second electrode; the test transistor includes a second gate, a second source, a second drain, and a second semiconductor layer, wherein the second gate and the second source are electrically connected to the first gate and the first source of at least one of the display transistors, respectively; Wherein, the first electrode is located on the side of the second electrode away from the substrate, and the second drain of the test transistor is electrically connected to the first electrode; The common electrode is located on the side of the pixel electrode away from the substrate, and the first electrode is disposed on the same layer as the common electrode.

2. The display panel according to claim 1, characterized in that, The second electrode in the test sub-pixel is electrically connected to the common electrode.

3. The display panel according to claim 1, characterized in that, The overlap area between the first electrode and the second electrode in the test sub-pixel is S1, and the overlap area between the pixel electrode and the common electrode in the display sub-pixel is S2, where S1 = S2.

4. The display panel according to claim 3, characterized in that, Of the pixel electrode and the common electrode, the one disposed in the same layer as the first electrode includes multiple slits; the first electrode is a continuous structure covering the entire surface.

5. The display panel according to claim 1, characterized in that, The first electrode serves as the first test pin.

6. The display panel according to claim 1, characterized in that, The first electrode is electrically connected to the first test pin.

7. The display panel according to claim 1, characterized in that, The second gate and the second source are respectively electrically connected to the first gate and the first source of at least one of the display transistors, including: The second gate and the first gate of at least one of the display transistors are both electrically connected to the same scan line, and the second source and the first source of the at least one of the display transistors are both electrically connected to the same data line.

8. The display panel according to claim 7, characterized in that, The scan line, which is electrically connected to the second gate of the test transistor and the first gate of the display transistor, is electrically connected to the second test pin; the data line, which is electrically connected to the second source of the test transistor and the first source of the display transistor, is electrically connected to the third test pin.

9. The display panel according to claim 1, characterized in that, The display panel also includes multiple dummy sub-pixels, and the test sub-pixels are arranged in the same row or column as the dummy sub-pixels.

10. A display device, characterized in that, Includes the display panel as described in any one of claims 1-9.

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