A method for preparing a P-type silicon solar cell

Abstract

The embodiment of the present invention provides a method for preparing a P-type silicon solar cell, which belongs to the technical field of silicon wafer batteries, and comprises: cleaning and texturing a substrate layer of a P-type silicon material; performing phosphorus diffusion on the lower end surface of the substrate layer after cleaning and texturing; after the phosphorus diffusion, removing the PSG formed in the phosphorus diffusion process; after removing the PSG, performing surface passivation treatment on the upper end surface of the substrate layer and the lower end surface of the diffusion layer to form a passivation layer; forming an N-type amorphous silicon layer; forming a P-type amorphous silicon layer; depositing an anti-reflection layer outside the N-type amorphous silicon layer and the P-type amorphous silicon layer; printing to form a metal electrode; after printing the metal electrode, performing high-temperature sintering on the semi-finished battery so that the metal electrode and silicon form a metal silicide; and converting the N-type amorphous silicon layer and the P-type amorphous silicon layer into a poly-Si(n) layer and a poly-Si(p) layer; achieving the technical effect of reducing battery cost and avoiding the use of a boron diffusion process.

Description

Technical Field

[0001] The invention relates to the technical field of silicon wafer batteries, and in particular to a method for preparing a P-type silicon solar cell. Background Art

[0002] The existing N-type TOPCon (Tunnel Oxide Passivated Contact) cells rely on the "tunnel effect" to achieve rear surface passivation and collect electrons, and the PN junction formed by boron diffusion is located on the incident light side. The rear surface structure of the existing TOPCon cell is semiconductor substrate, tunneling layer, doped conductive layer, and rear surface anti-reflection layer from the inside to the outside. The N-type silicon wafer used in the N-type TOPCon cell is more expensive than the P-type silicon wafer, and the N-type TOPCon cell involves a high-temperature boron diffusion process with high process difficulty.

[0003] Therefore, the technical problems of the prior art are that the N-type TOPCon battery is costly and requires a boron diffusion process. Summary of the invention

[0004] The embodiment of the present application provides a method for preparing a P-type silicon solar cell, which solves the technical problems of high battery cost and the need for a boron diffusion process in the prior art of N-type TOPCon batteries, thereby achieving the technical effect of reducing battery cost and avoiding the use of a boron diffusion process.

[0005] The present application provides a method for preparing a P-type silicon solar cell, the method comprising: cleaning and texturing a substrate layer of P-type silicon material; performing phosphorus diffusion on the lower end surface of the cleaned and texturized substrate layer to form a diffusion layer; forming a PN junction between the diffusion layer and the substrate layer, and the PN junction is arranged on the back side of the substrate layer, away from incident light; after the phosphorus diffusion, removing the PSG formed in the phosphorus diffusion process; after removing the PSG, performing surface passivation treatment on the upper end surface of the substrate layer and the lower end surface of the diffusion layer to form a passivation layer; performing in-situ doping deposition on the passivation layer located on the lower side of the substrate layer to form an N-type amorphous silicon layer; performing i on the passivation layer located on the upper side of the substrate layer; n-situ doping deposition is performed to form a P-type amorphous silicon layer; an anti-reflection layer is deposited outside the N-type amorphous silicon layer and the P-type amorphous silicon layer; a metal electrode is printed on the anti-reflection layer outside the N-type amorphous silicon layer and the P-type amorphous silicon layer; after printing the metal electrode, the semi-finished battery is subjected to high-temperature sintering so that the metal electrode and silicon form a metal silicide; and the N-type amorphous silicon layer and the P-type amorphous silicon layer are converted into an N-type polycrystalline silicon layer and a P-type polycrystalline silicon layer.

[0006] Preferably, the preparation method comprises: when performing in-situ doped silicon deposition on the passivation layer located on the lower side of the substrate layer, placing the semi-finished battery after passivation in parallel on the electrode of a flat-plate PECVD device or a furnace-tube PECVD device, so that the passivation layer on the lower side of the substrate layer is exposed; and when performing in-situ doped silicon deposition on the passivation layer located on the upper side of the substrate layer, placing the semi-finished battery after passivation in parallel on the electrode of a flat-plate PECVD device or a furnace-tube PECVD device, so that the passivation layer on the upper side of the substrate layer is exposed.

[0007] Preferably, the N-type amorphous silicon layer is an electron collection layer, and the deposition thickness of the N-type amorphous silicon layer is Preferably, the thickness of the P-type amorphous silicon layer is less than

[0008] Preferably, the steps of forming the N-type amorphous silicon layer and the steps of forming the P-type amorphous silicon layer are interchanged in order.

[0009] Preferably, the resistivity of the substrate layer is greater than 2.0 Ω.cm, and the substrate layer is doped with gallium, and the doping concentration of gallium is less than 7.1x10 15 cm-3.

[0010] Preferably, the resistivity of the substrate layer is greater than 2.0 Ω.cm, and the substrate layer is doped with boron.

[0011] A method for preparing a P-type silicon solar cell, the method comprising: cleaning and texturing a substrate layer of P-type silicon material; diffusing phosphorus on the lower end surface of the cleaned and texturized substrate layer to form a diffusion layer; forming a PN junction between the diffusion layer and the substrate layer, and the PN junction is arranged on the back side of the substrate layer, away from incident light; after phosphorus diffusion, removing PSG formed during the phosphorus diffusion process; after removing PSG, performing surface passivation treatment on the upper end surface of the substrate layer and the lower end surface of the diffusion layer to form a passivation layer; depositing on the passivation layer located on the upper side of the substrate layer to form an Al2O3 layer; depositing an anti-reflection layer outside the N-type amorphous silicon layer and the Al2O3 layer; printing a metal electrode on the anti-reflection layer outside the N-type amorphous silicon layer and the Al2O3 layer; after printing the metal electrode, sintering the semi-finished battery at a high temperature so that the metal electrode and silicon form a metal silicide; and converting the N-type amorphous silicon layer into an N-type polycrystalline silicon layer.

[0012] Preferably, the thickness of the Al2O3 layer is less than and the thickness of the passivation layer is less than Based on the thickness of the Al2O3 layer and the passivation layer, the silver paste printed on the anti-reflection layer as the metal electrode material is diffused and extended into the substrate layer through high-temperature sintering.

[0013] Preferably, the resistivity of the substrate layer is greater than 2.0Ω.cm, and the substrate layer is doped with gallium or boron.

[0014] The above one or more technical solutions in the embodiments of the present application have at least one or more of the following technical effects:

[0015] 1. In the embodiment of the present application, P-type silicon is used as the substrate layer so that the diffusion layer can be made into an N-type diffusion layer by a phosphorus diffusion process. First, the boron diffusion process is avoided, and the process temperature requirement is reduced from 1000°C to 850-900°C, which reduces the requirement for the process temperature; second, the formation of BO bonds is avoided, and the power attenuation of the battery cell is avoided; the technical problem that the N-type TOPCon battery in the prior art is high in battery cost and requires a boron diffusion process is solved; the technical effect of reducing battery cost and avoiding the use of a boron diffusion process is achieved.

[0016] 2. In the embodiment of the present application, the PN junction is placed on the back side, away from the incident light, which reduces the influence of the space charge region on the photogenerated carriers and increases the collection of carriers; and because a P-type silicon substrate is used, Al2O3 can be used as a hole collection layer on the light incident surface to reduce light absorption; the influence of high temperature diffusion or annealing on the silicon substrate caused by using P-type polysilicon as a hole collection layer is avoided, and specifically, oxygen can be prevented from entering the substrate layer.

[0017] 3. In the embodiment of the present application, the gallium doping concentration of the substrate layer is limited (boron doping is also acceptable) to ensure the integrity of the material; similarly, the resistivity of the substrate layer is limited to control the integrity of the material; based on the integrity of the substrate layer material, the minority carrier lifetime is improved, thereby ensuring the minority carriers' ability to pass through the substrate layer and improving the battery efficiency of the battery. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 This is a schematic diagram of the main view structure of a P-type silicon solar cell in an embodiment of the present application;

[0019] Figure 2 This is a schematic diagram of the main view structure of another P-type silicon solar cell in an embodiment of the present application.

[0020] Figure numerals: 1, substrate layer; 2, diffusion layer; 3, passivation layer; 4, electron collection layer; 5, hole collection layer; 6, anti-reflection layer; 7, metal electrode. DETAILED DESCRIPTION

[0021] The serial numbers assigned to the components herein, such as "first", "second", etc., are only used to distinguish the objects described and do not have any order or technical meaning. The "connection" and "coupling" mentioned in this application, unless otherwise specified, include direct and indirect connections (couplings). In the description of this application, it should be understood that the terms "upper", "lower", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on this application.

[0022] In the present application, unless otherwise clearly specified and limited, a first feature being "on" or "under" a second feature may mean that the first and second features are in direct contact, or that the first and second features are in indirect contact through an intermediate medium. Moreover, a first feature being "above", "above" and "above" a second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. A first feature being "under", "below" and "below" a second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.

[0023] In order to better understand the above technical solution, the above technical solution will be described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0024] A method for preparing a P-type silicon solar cell, the method comprising:

[0025] S1, cleaning and texturing the substrate layer 1 of P-type silicon material; the purpose of texturing is to form a velvet surface on the surface of the substrate layer 1 to reduce the reflectivity of the battery cell. The uneven velvet surface can increase secondary reflection and change the optical path and the incident mode. Usually, a pyramid-shaped velvet surface can be obtained by treating a single crystal with alkali; a wormhole-shaped irregular velvet surface can be obtained by treating a polycrystalline with acid.

[0026] Specifically, after texturing, the upper and lower end surfaces of the substrate layer 1 are respectively rough texture structures. The specific rough texture structure can be a wave-like pattern, a pyramid or an inverted pyramid pattern to increase the surface area and reduce the reflection of the incident light.

[0027] S2, phosphorus diffusion is performed on the lower end surface of the cleaned and textured substrate layer 1 to form a diffusion layer 2; a PN junction is formed between the diffusion layer 2 and the substrate layer 1, and the PN junction is arranged on the lower side of the substrate layer 1; the phosphorus diffusion process is carried out at a temperature of 850-900°C, so that the lower part of the substrate layer 1 forms a diffusion layer 2 due to diffusion, and a PN junction is constructed based on the P-type substrate layer 1 and the N-type diffusion layer 2.

[0028] Regarding phosphorus diffusion, POCl3 is specifically used. POCl3 is a liquid phosphorus source. Liquid phosphorus source diffusion has the advantages of high production efficiency, good stability, uniform and flat PN junction, and good surface of the diffusion layer 2.

[0029] S3, after phosphorus diffusion, remove PSG (phosphosilicate glass) formed during the phosphorus diffusion process; after removing PSG, perform a cleaning operation.

[0030] The formation process of PSG is as follows: After using POCl3, POCl3 decomposes to generate phosphorus pentachloride (PCl5) and phosphorus pentoxide (P2O5) under the condition of more than 600℃. PCl5 has a corrosive effect on the surface of silicon wafers. When there is oxygen O2, PC l5 will decompose into P2O5 and release chlorine, so a certain flow of oxygen is introduced while diffusing nitrogen. P2O5 reacts with silicon at the diffusion temperature to generate silicon dioxide and phosphorus atoms. The generated P2O5 is deposited on the surface of silicon wafers and continues to react with silicon to generate SiO2 and phosphorus atoms, and forms phosphorus-silicon glass (PSG) on the surface of silicon wafers.

[0031] S4, after removing PSG, the upper end surface of the substrate layer 1 and the lower end surface of the diffusion layer 2 are subjected to surface passivation treatment to form a passivation layer 3. The passivation layer 3 is specifically a first passivation layer and a second passivation layer, which are respectively arranged on the upper end surface of the substrate layer 1 and the lower end surface of the diffusion layer 2 under the substrate layer 1. Based on research, the optimal thickness value of the first passivation layer is less than the optimal thickness value of the second passivation layer, but when the surface passivation of both end surfaces is performed at the same time, it is difficult to achieve the purpose of differential growth of the two passivation layers 3, and generally the thickness of the first passivation layer and the second passivation layer are prepared to be consistent.

[0032] S5, performing in-situ doping deposition on the passivation layer 3 located at the lower side of the substrate layer 1 to form an N-type amorphous silicon layer; of course, it is also feasible to first deposit intrinsic silicon and then perform phosphorus diffusion process / ion implantation.

[0033] The specific N-type amorphous silicon layer processing technology can be to use PECVD equipment, add silane and doping source (phosphorus), the concentration of phosphine in the reaction gas is about 1-2%, and form an N-type amorphous silicon layer; it should be noted that the N-type amorphous silicon layer can be subsequently annealed at high temperature to be converted into an N-type polycrystalline silicon layer.

[0034] S6, performing in-situ doping deposition on the passivation layer 3 located on the upper side of the substrate layer 1 to form a P-type amorphous silicon layer; of course, it is also feasible to first deposit intrinsic silicon and then perform a boron diffusion process / ion implantation; the specific processing method is the same as that in S5, the difference being whether phosphorus or boron is used.

[0035] Regarding the formation of the N-type amorphous silicon layer / P-type amorphous silicon layer, a flat-plate PECVD device or a furnace-tube PECVD device can be used. In the specific operation, the semi-finished battery after passivation is placed parallel to the electrode of the device to form the N-type amorphous silicon layer on one side / the P-type amorphous silicon layer on one side. In addition, LPCVD is used to form the double-sided first, and then the amorphous silicon layer on the unnecessary side is removed by etching / corrosion.

[0036] It should be noted that there is no specific order for S5 and S6. You can do S5 first and then S6; or you can do S6 first and then S5.

[0037] S7, depositing an anti-reflection layer 6 outside the N-type amorphous silicon layer and the P-type amorphous silicon layer, the anti-reflection layer 6 can be a SixNy film. Specifically, the reflection loss rate of sunlight on the silicon surface is as high as about 35%. The anti-reflection film can improve the absorption of sunlight by the cell, reduce the reflection of sunlight, help to increase the photocurrent, and thus improve the conversion efficiency: on the other hand, the passivation of the battery surface by hydrogen in the film reduces the surface recombination rate of the emitter junction, reduces the dark current, increases the open circuit voltage, and improves the photoelectric conversion efficiency. H can react with defects or impurities in silicon, thereby transferring the energy band in the forbidden band into the valence band or conduction band.

[0038] The specific processing method of SixNy film can be to place the semi-finished battery cell into a PECVD graphite boat, and deposit the N-type amorphous silicon layer and the P-type amorphous silicon layer by conducting the graphite boat in a vacuum environment and at a temperature of 400 degrees Celsius.

[0039] Regarding the sequence of steps S5, S6 and S7: S7 can be performed after S5 to form the anti-reflection layer 6 on the outside of the N-type amorphous silicon layer; then S6 is performed, and finally S7 is performed once to form the anti-reflection layer 6 on the outside of the P-type amorphous silicon layer. Similarly, the order of S5 and S6 can be reversed and S7 can be performed twice. Of course, the best solution is to perform S5 and S6 and then perform S7 at once to form two layers of anti-reflection layers 6.

[0040] S8, forming a metal electrode 7 by printing on the anti-reflection layer 6 outside the N-type amorphous silicon layer and the P-type amorphous silicon layer.

[0041] S9, after printing the metal electrode 7, the semi-finished battery is subjected to high temperature sintering to solidify the metal electrode 7 and convert the N-type amorphous silicon layer and the P-type amorphous silicon layer into an N-type polysilicon layer and a P-type polysilicon layer.

[0042] High temperature sintering is to sinter the metal electrode 7 printed on the surface of the cell at high temperature, so that the metal electrode 7 and the silicon chip itself form an ohmic contact, improve the open circuit voltage and fill factor of the cell, and make the contact of the metal electrode 7 have ohmic characteristics to achieve high conversion efficiency. While the metal electrode 7 is sintered at high temperature, the N-type amorphous silicon layer and the P-type amorphous silicon layer will be transformed from amorphous silicon to polycrystalline silicon to form the electron collection layer 4 and the hole collection layer 5.

[0043] In another embodiment, the hole collection layer 5 is optimized from a poly-Si(p) layer to an Al2O3 layer to avoid the poly-Si(p) layer from absorbing sunlight and to increase the concentration of photogenerated carriers on the incident surface. Specifically, step S6 is modified to:

[0044] S6, depositing on the passivation layer 3 located on the upper side of the substrate layer 1 to form an Al2O3 layer; the deposition technology of the Al2O3 layer can adopt PECVD, high-speed space ALD technology and reactive sputtering technology.

[0045] In addition, since the hole collection layer 5 is optimized from a poly-Si(p) layer to an Al2O3 layer, in step S8-9, the metal electrode 7 on the upper side is connected to the silicon substrate, and through high-temperature sintering, the metal electrode 7 and the silicon substrate form an ohmic junction contact, and the N-type amorphous silicon layer is converted into a poly-Si(n) layer.

[0046] In addition to the above-mentioned materials, the first passivation layer can also be made of aluminum oxide, and the passivation method using aluminum oxide is electric field passivation; and when both the first passivation layer and the hole collection layer 5 can be set to aluminum oxide, the steps of the specific preparation scheme can be further simplified, and the passivation layer 3 of S4 and the Al2O3 layer of S6 can be more optimally combined, that is, firstly single-sided passivation is performed on the lower end face of the diffusion layer 2 in S4; and then the Al2O3 layer is prepared on the upper end face of the substrate layer 1 in S6; such a preparation method has the advantage that the thickness of the first passivation layer and the thickness of the second passivation layer on both sides of the PN junction can be independently controlled, so that the thickness of the first passivation layer and the thickness of the second passivation layer can be prepared to their respective optimal thicknesses, achieving the optimal solution that the thickness of the first passivation layer is less than the thickness of the second passivation layer.

[0047] Based on the above preparation method, a solar cell with a novel structure can be prepared, as follows:

[0048] A P-type silicon solar cell, see the attached manual Figure 1 and2 The solar cell comprises: a substrate layer 1, a diffusion layer 2, a passivation layer 3, an electron collection layer 4, a hole collection layer 5, an anti-reflection layer 6 and a metal electrode 7; wherein the diffusion layer 2 is arranged on the lower end surface of the substrate layer 1 (i.e., the back side of the battery) to form a PN junction, the passivation layer 3 is divided into two layers and is respectively arranged on the upper and lower end surfaces of the PN junction, the electron collection layer 4 is arranged on the lower passivation layer 3, and the hole collection layer 5 is arranged on the upper passivation layer 3, the metal electrode 7 is divided into two groups of positive and negative metal electrodes 7 respectively connected to the two sides of the PN junction, and an anti-reflection layer 6 for reducing the reflection of incident light is arranged on the electron collection layer 4 and the hole collection layer 5.

[0049] Substrate layer 1, specifically a P-type silicon substrate doped with gallium. In the present application, the PN junction is at the back (i.e., the diffusion layer 2 is formed on the lower end surface of the substrate layer 1), and the photogenerated carrier concentration on the incident light side is the highest. The corresponding minority carriers are electrons, which need to diffuse a longer distance (the distance from the incident light side to the PN junction) to be collected. Therefore, the battery structure in the present application requires a higher minority carrier lifetime. In order to ensure the minority carrier lifetime, it is preferred to improve the material integrity of the substrate layer 1 and limit the gallium doping concentration to less than 7.1x10 15 cm- 3 At the same time, the resistivity of the substrate layer 1 needs to be greater than 2.0Ω.cm; further, the doping concentration of gallium is less than 4.6x1 0 15 cm- 3 , the resistivity of the substrate layer 1 needs to be greater than 3.0Ω.cm.

[0050] Regarding the minority carrier lifetime of the substrate layer 1, in the prior art, since the PN junction is in the front (i.e., the diffusion layer 2 is formed on the upper end surface of the substrate layer 1), light is incident from the PN junction, and the generated carriers corresponding to the minority carriers are more easily collected, so the minority carrier lifetime requirement of the substrate layer 1 is low. For example, PERC uses a P-type silicon wafer, and light is incident from the PN junction. There are more photogenerated carriers near the PN junction, and electrons are minority carriers, so the diffusion distance is short and they are easier to collect.

[0051] The diffusion layer 2 is an N-type silicon layer prepared by a phosphorus diffusion process; the diffusion layer 2 is arranged on the lower end surface of the substrate layer 1, and the diffusion layer 2 and the substrate layer 1 form a PN junction; when the PN junction is acted upon by light, an electromotive force is generated on the P-type substrate layer 1 and the N-type diffusion layer 2 based on the photovoltaic effect, and carriers are output to the outside through the metal electrodes 7 at the upper and lower ends to form a current.

[0052] P-type silicon wafers are used as the core material of the battery, and a phosphorus diffusion process is performed on the substrate layer 1 to construct a diffusion layer 2, avoiding the difficult boron diffusion process when preparing the battery; the specific boron diffusion process needs to be carried out in a high temperature environment of 1000°C, while the phosphorus diffusion process used in this application only requires a diffusion temperature of 850-900°C. In addition, the advantages of the phosphorus diffusion process also include no light attenuation problem; if the boron diffusion process is used, there is boron in the PN junction, and light or current injection will cause boron and oxygen to form a boron-oxygen (BO) complex. The boron-oxygen complex is a metastable defect that forms a recombination center, thereby reducing the minority carrier lifetime and causing power attenuation in solar cells and components during illumination.

[0053] Passivation layer 3, the passivation layer 3 is arranged on the upper and lower end surfaces of the PN junction, that is, the passivation layer 3 is arranged with two layers, the first passivation layer is arranged on the upper end surface of the substrate layer 1, and the second passivation layer is arranged on the lower end surface of the diffusion layer 2; the material of the passivation layer 3 is specifically silicon nitride, silicon oxide, silicon oxynitride or a composite of two or more of the above materials. Exemplarily, the material of the passivation layer 3 in the present application is silicon oxide, and the thickness of the passivation layer 3 is less than In addition, in addition to the above materials, the first passivation layer can also be made of aluminum oxide. When aluminum oxide is used, both the first passivation layer and the hole collection layer 5 can be set to aluminum oxide, and the steps of the specific preparation scheme can be further simplified. The preparation of the first passivation layer and the preparation of the hole collection layer 5 can be combined in one step, thereby shortening the steps required for preparation and optimizing the structure of the battery.

[0054] The electron collection layer 4 is disposed on the lower side of the passivation layer 3 below the PN junction; the electron collection layer 4 is specifically a poly-Si(n) layer. The thickness of the electron collection layer 4 is

[0055] The hole collection layer 5 is arranged on the upper side of the passivation layer 3 above the PN junction; the hole collection layer 5 is specifically a poly-Si(p) layer or an Al2O3 layer; when the hole collection layer 5 is a poly-Si(p) layer, refer to the appendix of the specification Figure 1 , the thickness of the hole collection layer 5 is less than The positive metal electrode 7 located on the upper side of the PN junction is connected to the hole collection layer 5; or, when the hole collection layer 5 is an Al2O3 layer, refer to the appendix of the specification. Figure 2 , the thickness of the hole collection layer 5 is less than It is an ultra-thin film, and the positive metal electrode 7 located on the upper side of the PN junction is sintered at a high temperature to diffuse and extend and connect to the substrate layer 1.

[0056] Regarding the similarities and differences between the poly-Si(p) layer and the Al2O3 layer, the poly-Si(p) layer provides negatively charged ions (generated after boron doping), and the Al2O3 layer provides negatively charged defects. Both have the same effect on the photogenerated holes in the single-crystalline silicon layer, collecting holes. The disadvantage of using the poly-Si(p) layer is that it absorbs part of the incident light, but the advantage is that the process equipment does not need to introduce Al2O3 preparation equipment, reducing the demand for preparation equipment, such as no need for ALD equipment.

[0057] The metal electrode 7 is used to transmit current to the outside. The metal electrode 7 is provided with two groups, upper and lower, to serve as a positive metal electrode and a negative metal electrode. The negative metal electrode located at the lower side of the PN junction is connected to the electron collection layer 4. When the hole collection layer 5 is a poly-Si(p) layer, the positive metal electrode located at the upper side of the PN junction is connected to the hole collection layer 5; or, when the hole collection layer 5 is an Al2O3 layer, the positive metal electrode located at the upper side of the PN junction is connected to the substrate layer 1 through diffusion extension after high-temperature sintering. The metal electrode 7 is specifically a metal or alloy made of gold, silver, copper, aluminum or titanium. The metal electrode 7 is formed by printing and high-temperature sintering during specific manufacturing.

[0058] The anti-reflection layer 6 is used to reduce the reflection of the incident light and increase the incident light. In the present application, the anti-reflection layer 6 is arranged outside the electron collection layer 4 and the hole collection layer 5; the material of the anti-reflection layer 6 is specifically silicon nitride, silicon oxide, silicon oxynitride or a transparent material with a refractive index lower than 2.5. In one embodiment, the first anti-reflection layer can be arranged in a wavy shape to reduce the reflection of the incident light.

[0059] Technical effects:

[0060] 1. In the embodiment of the present application, P-type silicon is used as the substrate layer 1, so that the diffusion layer 2 can be made into the N-type diffusion layer 2 by the phosphorus diffusion process. First, the boron diffusion process is avoided, and the process temperature requirement is reduced from 1000°C to 850-900°C, which reduces the requirement for the process temperature; second, the formation of BO bonds is avoided, and the power attenuation of the battery cell is avoided; the technical problem that the N-type TOPCon battery in the prior art is high in battery cost and requires a boron diffusion process is solved; the technical effect of reducing battery cost and avoiding the use of a boron diffusion process is achieved.

[0061] 2. In the embodiment of the present application, the PN junction is placed on the back side, away from the incident light, which reduces the influence of the space charge region on the photogenerated carriers and increases the collection of carriers; and because a P-type silicon substrate is used, Al2O3 can be used as the hole collection layer 5 on the light incident surface to reduce light absorption; the influence of high temperature diffusion or annealing on the silicon substrate caused by using P-type polysilicon as the hole collection layer 5 is avoided, and specifically, oxygen can be prevented from entering the substrate layer 1.

[0062] 3. In the embodiment of the present application, the gallium doping concentration of the substrate layer 1 is limited (boron doping is also acceptable) to ensure the integrity of the material; similarly, the resistivity of the substrate layer 1 is limited to control the integrity of the material; based on the integrity of the substrate layer 1 material, the minority carrier lifetime is improved, thereby ensuring the minority carriers' ability to pass through the substrate layer 1 and improving the battery efficiency of the battery.

[0063] Although the preferred embodiments of the present invention have been described, those skilled in the art may make other changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0064] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims

1. A method for preparing a P-type silicon solar cell, characterized in that: The preparation method comprises: Cleaning and texturing of P-type silicon substrate layer; Phosphorus diffusion is performed on the lower end surface of the cleaned and textured substrate layer to form a diffusion layer; a PN junction is formed between the diffusion layer and the substrate layer, and the PN junction is arranged on the back side of the substrate layer, away from incident light; After phosphorus diffusion, PSG formed during phosphorus diffusion is removed; After removing the PSG, the upper end surface of the substrate layer and the lower end surface of the diffusion layer are subjected to surface passivation treatment to form a passivation layer; in-situ doping deposition is performed on the passivation layer located at the lower side of the substrate layer to form an N-type amorphous silicon layer; Performing in-situ doping deposition on the passivation layer located on the upper side of the substrate layer to form a P-type amorphous silicon layer; Depositing an anti-reflection layer outside the N-type amorphous silicon layer and the P-type amorphous silicon layer; Printing and forming metal electrodes on the anti-reflection layer outside the N-type amorphous silicon layer and the P-type amorphous silicon layer; After printing the metal electrode, the semi-finished battery is sintered at high temperature so that the metal electrode and silicon form metal silicide; and the N-type amorphous silicon layer and the P-type amorphous silicon layer are converted into N-type polycrystalline silicon layer and P-type polycrystalline silicon layer.

2. The preparation method according to claim 1, characterized in that The preparation method comprises: when performing in-situ doped silicon deposition on the passivation layer located at the bottom of the substrate layer, placing the semi-finished battery after passivation in parallel on the electrode of the flat-plate PECVD device or the furnace tube PECVD device, so that the passivation layer at the bottom of the substrate layer is in an exposed state; When the passivation layer on the upper side of the substrate layer is deposited with in-situ doped silicon, the passivated semi-finished battery is placed in parallel on the electrode of a flat-plate PECVD device or a furnace tube PECVD device, so that the passivation layer on the upper side of the substrate layer is exposed.

3. The preparation method according to claim 1, characterized in that: The N-type amorphous silicon layer is an electron collection layer, and the deposition thickness of the N-type amorphous silicon layer is 4. The preparation method according to claim 1, characterized in that: The thickness of the P-type amorphous silicon layer is less than 5. The preparation method according to claim 1, characterized in that: The steps of forming the N-type amorphous silicon layer and the steps of forming the P-type amorphous silicon layer are interchanged in order.

6. The preparation method according to claim 1, characterized in that: The resistivity of the substrate layer is greater than 2.0 Ω.cm, and the substrate layer is doped with gallium, and the doping concentration of gallium is less than 7.1x10 15 cm -3 .

7. The preparation method according to claim 1, characterized in that: The resistivity of the substrate layer is greater than 2.0 Ω.cm, and the substrate layer is doped with boron.

8. A method for preparing a P-type silicon solar cell, characterized in that: The preparation method comprises: Cleaning and texturing of P-type silicon substrate layer; Phosphorus diffusion is performed on the lower end surface of the cleaned and textured substrate layer to form a diffusion layer; a PN junction is formed between the diffusion layer and the substrate layer, and the PN junction is arranged on the back side of the substrate layer, away from incident light; After phosphorus diffusion, PSG formed during phosphorus diffusion is removed; After removing the PSG, the upper end surface of the substrate layer and the lower end surface of the diffusion layer are subjected to surface passivation treatment to form a passivation layer; Depositing on the passivation layer located on the upper side of the substrate layer to form an Al2O3 layer; Depositing on the passivation layer located at the lower side of the substrate layer to form an N-type amorphous silicon layer; Depositing an anti-reflection layer outside the N-type amorphous silicon layer and the Al2O3 layer; Printing a metal electrode on the anti-reflection layer outside the N-type amorphous silicon layer and the Al2O3 layer; After printing the metal electrode, the semi-finished battery is sintered at high temperature so that the metal electrode and silicon form metal silicide; and the N-type amorphous silicon layer is converted into an N-type polycrystalline silicon layer.

9. The preparation method according to claim 8, characterized in that: The thickness of the Al2O3 layer is less than And the thickness of the passivation layer is less than Based on the thickness of the Al2O3 layer and the passivation layer, the silver paste printed on the anti-reflection layer as the metal electrode material is diffused and extended into the substrate layer through high-temperature sintering.

10. The preparation method according to claim 8, characterized in that: The resistivity of the substrate layer is greater than 2.0Ω.cm, and the substrate layer is doped with gallium or boron.

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