Display panel, driving method and display device

Abstract

A display panel, a driving method and a display device. The display panel includes a plurality of rows and columns of pixel circuits, a plurality of rows of gate lines, a plurality of rows of reset control lines and a plurality of columns of data lines; the same row of pixel circuits corresponds to two rows of gate lines, one of the two rows of gate lines is used to provide a corresponding gate drive signal for an odd-numbered column of pixel circuits in the row of pixel circuits; the other of the two rows of gate lines is used to provide a corresponding gate drive signal for an even-numbered column of pixel circuits in the row of pixel circuits; the same column of pixel circuits corresponds to two columns of data lines, one of the two columns of data lines provides a corresponding data voltage for an odd-numbered row of pixel circuits in the column of pixel circuits; the other of the two columns of data lines provides a corresponding data voltage for an even-numbered row of pixel circuits in the column of pixel circuits. The display panel can improve the compensation time, ensure the display effect, and achieve a higher data refresh rate.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display panel, a driving method and a display device. Background Art

[0002] Currently, VR (Virtual Reality) displays and gaming phones, which are in great demand in the market, require display panels to increase their refresh rates. When the refresh rate of the display panel increases to a predetermined rate, the traditional driving method has the problem of insufficient threshold voltage compensation capability, which will cause uneven display of the display panel. Summary of the invention

[0003] The main purpose of the present invention is to provide a display panel, a driving method and a display device to solve the problem that when the refresh speed of the existing display panel reaches a predetermined speed, the traditional driving method has insufficient threshold voltage compensation capability, which will cause uneven display of the display panel.

[0004] In one aspect, an embodiment of the present invention provides a display panel including a plurality of rows and columns of pixel circuits, a plurality of rows of gate lines, a plurality of rows of reset control lines, and a plurality of columns of data lines;

[0005] The same row of pixel circuits corresponds to two rows of gate lines, one of the two rows of gate lines is electrically connected to the odd-numbered column pixel circuits in the row of pixel circuits, and is used to provide corresponding gate drive signals for the odd-numbered column pixel circuits in the row of pixel circuits; the other row of gate lines is electrically connected to the even-numbered column pixel circuits in the row of pixel circuits, and is used to provide corresponding gate drive signals for the even-numbered column pixel circuits in the row of pixel circuits;

[0006] The same row of pixel circuits corresponds to a row of reset control lines, and the reset control lines provide corresponding reset control signals for the corresponding row of pixel circuits;

[0007] The same column of pixel circuits corresponds to two columns of data lines, and one of the two columns of data lines is electrically connected to the odd-numbered rows of pixel circuits in the column of pixel circuits, for providing corresponding data voltages to the odd-numbered rows of pixel circuits in the column of pixel circuits;

[0008] The other column of the two columns of data lines is electrically connected to the even-numbered rows of pixel circuits in the column of pixel circuits, and is used to provide corresponding data voltages for the even-numbered rows of pixel circuits in the column of pixel circuits.

[0009] Optionally, the gate driving signal on the gate line is delayed by H / 2 compared with the gate driving signal on the adjacent previous row of gate lines, where H is a row period.

[0010] Optionally, the display panel described in the embodiment of the present invention further includes a plurality of multiplexing circuits;

[0011] The multiplexing circuit is used to control the data voltage provided by the pth data input terminal to be input to the four columns of data lines in a time-sharing manner under the control of the multiplexing control signal provided by the multiplexing control line; p is a positive integer.

[0012] Optionally, the multiplexing control line includes a first multiplexing control line, a second multiplexing control line, a first column gating control line, and a second column gating control line; the pth multiplexing circuit includes a pth row multiplexing sub-circuit and a pth column multiplexing sub-circuit;

[0013] The p-th column multiplexing subcircuit is electrically connected to the p-th data input terminal, the first column selection control line, the second column selection control line, the 2p-1th write node and the 2p write node respectively, and is used for controlling the connection between the p-th data input terminal and the 2p-1th write node to be turned on or off, and controlling the connection between the p-th data input terminal and the 2p write node to be turned on or off, under the control of a first column selection control signal provided by the first column selection control line and a second column selection control signal provided by the second column selection control line;

[0014] The p-th row multiplexing sub-circuit is electrically connected to the 2p-1th write node, the 2p write node, the first multiplexing control line, the second multiplexing control line, the first column data line, the second column data line, the third column data line and the fourth column data line, respectively, and is used to control the connection between the 2p-1th write node and the first column data line or the second column data line, and to control the connection between the 2p write node and the third column data line or the fourth column data line under the control of a first multiplexing control signal provided by the first multiplexing control line and a second multiplexing control signal provided by the second multiplexing control line.

[0015] Optionally, the p-th column multiplexing subcircuit includes a p-th first column multiplexing transistor and a p-th second column multiplexing transistor, wherein:

[0016] The control electrode of the pth first column multiplexing transistor is electrically connected to the first column selection control line, the first electrode of the pth first column multiplexing transistor is electrically connected to the pth data input terminal, and the second electrode of the pth first column multiplexing transistor is electrically connected to the 2p-1th write node;

[0017] The control electrode of the pth second column multiplexing transistor is electrically connected to the second column selection control line, the first electrode of the pth second column multiplexing transistor is electrically connected to the pth data input terminal, and the second electrode of the pth second column multiplexing transistor is electrically connected to the 2pth write node.

[0018] Optionally, the p-th row multiplexing subcircuit includes a p-th first row multiplexing transistor, a p-th second row multiplexing transistor, a p-th third row multiplexing transistor and a p-th fourth row multiplexing transistor;

[0019] The control electrode of the pth first-row multiplexing transistor is electrically connected to the first multiplexing control line, the first electrode of the pth first-row multiplexing transistor is electrically connected to the 2p-1th write node, and the second electrode of the pth first-row multiplexing transistor is electrically connected to the first column data line;

[0020] The control electrode of the pth second-row multiplexing transistor is electrically connected to the second multiplexing control line, the first electrode of the pth second-row multiplexing transistor is electrically connected to the 2p-1th write node, and the second electrode of the pth second-row multiplexing transistor is electrically connected to the second column data line;

[0021] The control electrode of the pth third-row multiplexing transistor is electrically connected to the second multiplexing control line, the first electrode of the pth third-row multiplexing transistor is electrically connected to the 2pth write node, and the second electrode of the pth third-row multiplexing transistor is electrically connected to the third column data line;

[0022] The control electrode of the pth fourth row multiplexing transistor is electrically connected to the first multiplexing control line, the first electrode of the pth fourth row multiplexing transistor is electrically connected to the 2pth write node, and the second electrode of the pth fourth row multiplexing transistor is electrically connected to the fourth column data line.

[0023] Optionally, the multiplexing control line includes a first multiplexing control line, a second multiplexing control line, a third multiplexing control line and a fourth multiplexing control line, and the pth multiplexing circuit includes a pth first multiplexing sub-circuit, a pth second multiplexing sub-circuit, a pth third multiplexing sub-circuit and a pth fourth multiplexing sub-circuit, wherein,

[0024] The pth first multiplexing subcircuit is electrically connected to the first multiplexing control line, the pth data input terminal and the first column data line respectively, and is used to switch on or off the connection between the pth data input terminal and the first column data line under the control of the first multiplexing control signal provided by the first multiplexing control line;

[0025] The pth second multiplexing subcircuit is electrically connected to the third multiplexing control line, the pth data input terminal and the second column data line respectively, and is used to switch on or off the connection between the pth data input terminal and the second column data line under the control of a third multiplexing control signal provided by the third multiplexing control line;

[0026] The pth third multiplexing sub-circuit is electrically connected to the fourth multiplexing control line, the pth data input terminal and the third column data line respectively, and is used to turn on or off the connection between the pth data input terminal and the third column data line under the control of a fourth multiplexing control signal provided by the fourth multiplexing control line;

[0027] The pth fourth multiplexing sub-circuit is electrically connected to the second multiplexing control line, the pth data input terminal and the fourth column data line respectively, and is used to turn on or off the connection between the pth data input terminal and the fourth column data line under the control of a second multiplexing control signal provided by the second multiplexing control line.

[0028] Optionally, the pth first multiplexing subcircuit includes a pth first multiplexing transistor, the pth second multiplexing subcircuit includes a pth second multiplexing transistor, the pth third multiplexing subcircuit includes a pth third multiplexing transistor, and the pth fourth multiplexing subcircuit includes a pth fourth multiplexing transistor;

[0029] The control electrode of the pth first multiplexing transistor is electrically connected to the first multiplexing control line, the first electrode of the pth first multiplexing transistor is electrically connected to the pth data input terminal, and the second electrode of the pth first multiplexing transistor is electrically connected to the first column data line;

[0030] The control electrode of the pth second multiplexing transistor is electrically connected to the third multiplexing control line, the first electrode of the pth second multiplexing transistor is electrically connected to the pth data input terminal, and the second electrode of the pth second multiplexing transistor is electrically connected to the second column data line;

[0031] The control electrode of the pth third multiplexing transistor is electrically connected to the fourth multiplexing control line, the first electrode of the pth third multiplexing transistor is electrically connected to the pth data input terminal, and the second electrode of the pth third multiplexing transistor is electrically connected to the third column data line;

[0032] The control electrode of the pth fourth multiplexing transistor is electrically connected to the second multiplexing control line, the first electrode of the pth fourth multiplexing transistor is electrically connected to the pth data input terminal, and the second electrode of the pth fourth multiplexing transistor is electrically connected to the fourth column data line.

[0033] Optionally, the display panel described in at least one embodiment of the present invention further includes a plurality of rows of light emitting control lines;

[0034] The pixel circuits in the same row are electrically connected to the reset control line and the light emitting control line in the same row respectively. The reset control line in the same row is used to provide a reset control signal for the pixel circuits in the same row, and the light emitting control line in the same row is used to provide a light emitting control signal for the pixel circuits in the same row.

[0035] In a second aspect, an embodiment of the present invention further provides a method for driving a display panel, which is applied to the above-mentioned display panel. The method for driving a display panel includes:

[0036] The reset control line of the same row provides a reset control signal for the pixel circuits of the same row;

[0037] One of the two rows of gate lines corresponding to the same row of pixel circuits provides corresponding gate drive signals for the odd-numbered column pixel circuits in the same row of pixel circuits, and the other of the two rows of gate lines provides corresponding gate drive signals for the even-numbered column pixel circuits in the same row of pixel circuits;

[0038] One of the two data lines corresponding to the same column of pixel circuits provides corresponding data voltages for odd-numbered pixel circuits in the same column of pixel circuits, and the other of the two data lines provides corresponding data voltages for even-numbered pixel circuits in the same column of pixel circuits;

[0039] The gate driving signal on the gate line is delayed by H / 2 compared with the gate driving signal on the adjacent previous row of gate lines, where H is the row period.

[0040] Optionally, the display panel further includes a plurality of rows of light emitting control lines; and the method for driving the display panel further includes:

[0041] The light emitting control lines in the same row provide light emitting control signals for the pixel circuits in the same row.

[0042] Optionally, the nth row display phase includes an nth reset time period, an nth data writing time period and an nth light emitting control time period which are sequentially arranged; n is a positive integer;

[0043] In the nth reset time period, the nth row reset control line provides a valid nth row reset control signal;

[0044] In the 2n-1th row writing time period included in the nth data writing time period, the 2n-1th row gate line provides a valid gate driving signal;

[0045] In the 2nth row writing time period included in the nth data writing time period, the 2nth row gate line provides a valid gate driving signal;

[0046] In the nth light emitting control period, the nth row of light emitting control lines provides a valid light emitting control signal;

[0047] The 2nth row writing period is delayed by H / 2 from the 2n-1th row writing period.

[0048] Optionally, the display panel further includes a plurality of multiplexing circuits; and the driving method of the display panel further includes:

[0049] The multiplexing circuit controls the data voltage provided by the data input terminal to be input to the four column data lines in a time-sharing manner under the control of the multiplexing control signal provided by the multiplexing control line.

[0050] Optionally, the multiplexing control line includes a first multiplexing control line, a second multiplexing control line, a first column gating control line and a second column gating control line; the p-th multiplexing circuit includes a p-th row multiplexing subcircuit and a p-th column multiplexing subcircuit; the data providing cycle includes a first data providing phase, a second data providing phase, a third data providing phase and a fourth data providing phase which are arranged in sequence; p is a positive integer;

[0051] The multiplexing circuit, under the control of the multiplexing control signal provided by the multiplexing control line, controls the data voltage provided by the data input terminal to be input to the four column data lines in a time-sharing manner, including:

[0052] In the first data providing stage and the third data providing stage, the p-th column multiplexing subcircuit controls the connection between the p-th data input terminal and the 2p-1-th write node to be turned on, and controls the connection between the p-th data input terminal and the 2p-1-th write node to be turned off, under the control of the first column enabling control signal provided by the first column enabling control line and the second column enabling control signal provided by the second column enabling control line;

[0053] In the second data providing stage and the fourth data providing stage, the p-th column multiplexing subcircuit controls, under the control of the first column selection control signal and the second column selection control signal, to disconnect the connection between the p-th data input terminal and the 2p-1th write node, and controls to connect the connection between the p-th data input terminal and the 2p-1th write node;

[0054] In the first data providing stage and the second data providing stage, the p-th row multiplexing subcircuit controls the connection between the 2p-1th write node and the first column data line, and controls the connection between the 2p write node and the fourth column data line, under the control of the first multiplexing control signal provided by the first multiplexing control line and the second multiplexing control signal provided by the second multiplexing control line;

[0055] In the third data providing stage and the fourth data providing stage, the p-th row multiplexing sub-circuit controls the connection between the 2p-1th write node and the second column data line, and controls the connection between the 2p write node and the third column data line under the control of the first multiplexing control signal and the second multiplexing control signal.

[0056] Optionally, the multiplexing control line includes a first multiplexing control line, a second multiplexing control line, a third multiplexing control line and a fourth multiplexing control line; the p-th multiplexing circuit includes a p-th first multiplexing sub-circuit, a p-th second multiplexing sub-circuit, a p-th third multiplexing sub-circuit and a p-th fourth multiplexing sub-circuit; the data providing cycle includes a first data providing phase, a second data providing phase, a third data providing phase and a fourth data providing phase which are arranged in sequence; p is a positive integer;

[0057] The multiplexing circuit, under the control of the multiplexing control signal provided by the multiplexing control line, controls the data voltage provided by the data input terminal to be input to the four column data lines in a time-sharing manner, including:

[0058] In the first data providing stage, the pth first multiplexing subcircuit, under the control of the first multiplexing control signal provided by the first multiplexing control line, conducts the connection between the pth data input terminal and the first column data line;

[0059] In the second data providing stage, the pth fourth multiplexing subcircuit, under the control of the second multiplexing control signal provided by the second multiplexing control line, conducts the connection between the pth data input terminal and the fourth column data line;

[0060] In the third data providing stage, the pth second multiplexing subcircuit, under the control of the third multiplexing control signal provided by the third multiplexing control line, conducts the connection between the pth data input terminal and the second column data line;

[0061] In the fourth data providing stage, the pth third multiplexing sub-circuit, under the control of a fourth multiplexing control signal provided by a fourth multiplexing control line, turns on the connection between the pth data input terminal and the third column data line.

[0062] In a third aspect, an embodiment of the present invention further provides a display device, comprising the above-mentioned display panel.

[0063] Optionally, the display device described in at least one embodiment of the present invention further includes a first gate driving circuit, a second gate driving circuit, a third gate driving circuit and a fourth gate driving circuit;

[0064] The first gate driving circuit is used to provide a first row of gate driving signals for a first row of gate lines;

[0065] The second gate driving circuit is used for providing a second row of gate driving signals for the second row of gate lines;

[0066] The third gate driving circuit is used to provide a third row of gate driving signals for the third row of gate lines;

[0067] The fourth gate driving circuit is used for providing a fourth row of gate driving signals for a fourth row of gate lines.

[0068] Optionally, the first gate driving circuit includes a multi-stage first shift register unit;

[0069] The gate drive signal output terminal of the a-th first shift register unit is electrically connected to the first row gate line, and the input terminal of the a+1-th first shift register unit is electrically connected to the first row gate line; the gate drive signal output terminal of the a+1-th first shift register unit is electrically connected to the fifth row gate line; the reset terminal of the a-th first shift register unit is electrically connected to the fifth row gate line;

[0070] The second gate driving circuit includes a multi-stage second shift register unit;

[0071] The gate drive signal output terminal of the a-th second shift register unit is electrically connected to the second row gate line, and the input terminal of the a+1-th second shift register unit is electrically connected to the second row gate line; the gate drive signal output terminal of the a+1-th second shift register unit is electrically connected to the sixth row gate line; the reset terminal of the a-th second shift register unit is electrically connected to the sixth row gate line;

[0072] The third gate driving circuit includes a multi-stage third shift register unit;

[0073] The gate drive signal output terminal of the third shift register unit of the ath level is electrically connected to the third row gate line, and the input terminal of the second shift register unit of the a+1th level is electrically connected to the third row gate line; the gate drive signal output terminal of the third shift register unit of the a+1th level is electrically connected to the seventh row gate line; the reset terminal of the third shift register unit of the ath level is electrically connected to the seventh row gate line;

[0074] The fourth gate driving circuit includes a multi-stage fourth shift register unit;

[0075] The gate drive signal output end of the fourth shift register unit of the ath level is electrically connected to the fourth row gate line, and the input end of the fourth shift register unit of the a+1th level is electrically connected to the fourth row gate line; the gate drive signal output end of the fourth shift register unit of the a+1th level is electrically connected to the eighth row gate line; the reset end of the fourth shift register unit of the ath level is electrically connected to the eighth row gate line.

[0076] Optionally, the display panel further includes a plurality of rows of reset control lines; the display device further includes a reset control signal generating circuit, and the reset control signal generating circuit is used to provide a corresponding reset control signal for each row of reset control lines.

[0077] Optionally, the display panel further includes a plurality of rows of light-emitting control lines; the display device further includes a light-emitting control signal generating circuit; the light-emitting control signal generating circuit is used to provide corresponding light-emitting control signals for each row of light-emitting control lines.

[0078] Compared with the prior art, the display panel, driving method and display device described in the present invention achieve a compensation time of twice the row cycle by electrically connecting a row of pixel circuits to two rows of gate lines and a column of pixel circuits to two columns of data lines. This allows for sufficient time to compensate for the threshold voltage of the driving transistor in the pixel circuit, thereby ensuring the display effect and achieving a higher data refresh speed. BRIEF DESCRIPTION OF THE DRAWINGS

[0079] Figure 1 is a schematic structural diagram of a display panel according to at least one embodiment of the present invention, comprising four rows and four columns of pixel circuits, eight rows of gate lines, and eight columns of data lines;

[0080] Figure 2 is a waveform diagram of gate driving signals on four rows of gate lines of a display panel according to at least one embodiment of the present invention;

[0081] Figure 3 is a structural diagram of a display panel according to at least one embodiment of the present invention;

[0082] Figure 4 is a structural diagram of a display panel according to at least one embodiment of the present invention;

[0083] Figure 5 is a circuit diagram of a display panel according to at least one embodiment of the present invention;

[0084] Fig. 6A The present invention is Figure 5 An operation timing diagram of at least one embodiment of the display panel shown;

[0085] Figure 6B The present invention is Figure 5 An operation timing diagram of at least one embodiment of the display panel shown;

[0086] Fig. 7A The present invention is Figure 5 An operation timing diagram of at least one embodiment of the display panel shown;

[0087] Figure 7B The present invention is Figure 5 An operation timing diagram of at least one embodiment of the display panel shown;

[0088] Fig. 8A The present invention is Figure 5 An operation timing diagram of at least one embodiment of the display panel shown;

[0089] Figure 8B The present invention is Figure 5 An operation timing diagram of at least one embodiment of the display panel shown;

[0090] Fig. 9 is a structural diagram of a display panel according to at least one embodiment of the present invention;

[0091] Fig.10 is a circuit diagram of a display panel according to at least one embodiment of the present invention;

[0092] Fig.11A The present invention is Fig.10 An operation timing diagram of at least one embodiment of the display panel shown;

[0093] Fig. 11B The present invention is Fig.10 An operation timing diagram of at least one embodiment of the display panel shown;

[0094] Fig.12 is a structural diagram of a display panel according to at least one embodiment of the present invention;

[0095] Fig.13 and Fig.14 is based on Fig.12 A structural diagram of a display panel according to at least one embodiment of the present invention;

[0096] Fig.15 is a structural diagram of a display panel according to at least one embodiment of the present invention;

[0097] Fig.16 and Fig.17 is based on Fig.15 A structural diagram of a display panel according to at least one embodiment of the present invention;

[0098] Fig.18 is a structural diagram of a first gate driving circuit in a display device according to at least one embodiment of the present invention;

[0099] Fig.19 is a structural diagram of a second gate driving circuit in a display device according to at least one embodiment of the present invention;

[0100] Fig. 20 is a structural diagram of a third gate driving circuit in a display device according to at least one embodiment of the present invention;

[0101] Fig.21 is a structural diagram of a fourth gate driving circuit in a display device according to at least one embodiment of the present invention. DETAILED DESCRIPTION

[0102] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0103] The transistors used in all embodiments of the present invention may be triodes, thin film transistors, field effect transistors or other devices with the same characteristics. In the embodiments of the present invention, in order to distinguish the two electrodes of the transistor except the control electrode, one of the electrodes is called the first electrode and the other is called the second electrode.

[0104] In actual operation, when the transistor is a triode, the control electrode may be a base, the first electrode may be a collector, and the second electrode may be an emitter; or, the control electrode may be a base, the first electrode may be an emitter, and the second electrode may be a collector.

[0105] In actual operation, when the transistor is a thin film transistor or a field effect transistor, the control electrode can be a gate, the first electrode can be a drain, and the second electrode can be a source; or, the control electrode can be a gate, the first electrode can be a source, and the second electrode can be a drain.

[0106] The display panel described in at least one embodiment of the present invention comprises a plurality of rows and columns of pixel circuits, a plurality of rows of gate lines, a plurality of rows of reset control lines and a plurality of columns of data lines;

[0107] The same row of pixel circuits corresponds to two rows of gate lines, and one of the two rows of gate lines is electrically connected to the odd-numbered columns of pixel circuits in the row of pixel circuits, for providing corresponding gate drive signals to the odd-numbered columns of pixel circuits in the row of pixel circuits;

[0108] Another row of the two rows of gate lines is electrically connected to the even-numbered columns of pixel circuits in the row of pixel circuits, and is used to provide corresponding gate drive signals to the even-numbered columns of pixel circuits in the row of pixel circuits;

[0109] The same row of pixel circuits corresponds to a row of reset control lines, and the reset control lines provide corresponding reset control signals for the corresponding row of pixel circuits;

[0110] The same column of pixel circuits corresponds to two columns of data lines, and one of the two columns of data lines is electrically connected to the odd-numbered rows of pixel circuits in the column of pixel circuits, for providing corresponding data voltages to the odd-numbered rows of pixel circuits in the column of pixel circuits;

[0111] The other column of the two columns of data lines is electrically connected to the even-numbered rows of pixel circuits in the column of pixel circuits, and is used to provide corresponding data voltages for the even-numbered rows of pixel circuits in the column of pixel circuits.

[0112] The display panel described in at least one embodiment of the present invention realizes a compensation time of twice the row period by electrically connecting one row of pixel circuits to two rows of gate lines and one column of pixel circuits to two columns of data lines. This allows for sufficient time to compensate for the threshold voltage of the driving transistor in the pixel circuit, thereby ensuring the display effect and achieving a relatively high data refresh speed.

[0113] In at least one embodiment of the present invention, each row of pixel circuits corresponds to a row of reset control lines, and instead of multiplexing adjacent row gate drive signals to provide reset control signals for a row of pixel circuits, a reset control signal is provided separately for each row of reset control lines.

[0114] Optionally, the gate driving signal on the gate line is delayed by H / 2 compared with the gate driving signal on the adjacent previous row of gate lines, where H is a row period.

[0115] In at least one embodiment of the present invention, the row period refers to the data writing time of each row of pixel circuits, but is not limited thereto.

[0116] In at least one embodiment of the present invention, the display panel may include a regular area and a special-shaped area.

[0117] The irregular area may include: an edge area, an irregular area, a camera area, and an area around the camera; wherein the area around the camera may be displayed, and for the design of the under-screen camera, in order to improve the transmittance of the area around the camera, the area around the camera may not be displayed. In a specific implementation, the camera area may be a circular area, and the area around the camera may generally be an annular area surrounding the camera area. In the area around the camera, the signal lines on the left and right sides of the camera area (the signal lines may be, for example, gate lines, light-emitting control lines, and reset control lines, but not limited thereto) may be connected by winding.

[0118] In a specific implementation, in the special-shaped area, a normal frequency solution may be adopted, or a high frequency solution in at least one embodiment of the present invention may be adopted.

[0119] In at least one embodiment of the present invention, in a regular area, a driving circuit (the driving circuit may include, for example, a gate driving circuit, a light emitting control signal generating circuit, and a reset control signal generating circuit) is arranged on both sides of the AA area (effective display area), and the driving circuit is mirrored on the left and right sides of the AA area, but is not limited to this.

[0120] Figure 1 The display panel according to at least one embodiment of the present invention includes four rows and four columns of pixel circuits, eight rows of gate lines and eight columns of data lines;

[0121] exist Figure 1 , the display panel includes a first row and a first column pixel circuit P11, a first row and a second column pixel circuit P12, a first row and a third column pixel circuit P13, a first row and a fourth column pixel circuit P14, a second row and a first column pixel circuit P21, a second row and a second column pixel circuit P22, a second row and a third column pixel circuit P23, a second row and a fourth column pixel circuit P24, a third row and a first column pixel circuit P31, a third row and a second column pixel circuit P32, a third row and a third column pixel circuit P33, a third row and a fourth column pixel circuit P34, a fourth row and a first column pixel circuit P41, a fourth row and a second column pixel circuit P42, a fourth row and a third column pixel circuit P43, and a fourth row and a fourth column pixel circuit P44;

[0122] The display panel includes a first row of gate lines G11, a second row of gate lines G12, a third row of gate lines G21, a fourth row of gate lines G22, a fifth row of gate lines G31, a sixth row of gate lines G32, a seventh row of gate lines G41, an eighth row of gate lines G42, a first column of data lines D11, a second column of data lines D12, a third column of data lines D21, a fourth column of data lines D22, a fifth column of data lines D31, a sixth column of data lines D32, a seventh column of data lines D41 and an eighth column of data lines D42, wherein:

[0123] G11 is electrically connected to P11 and P13, and G12 is electrically connected to P12 and P14;

[0124] G21 is electrically connected to P21 and P23, and G22 is electrically connected to P22 and P24;

[0125] G31 is electrically connected to P31 and P33, and G32 is electrically connected to P32 and P34;

[0126] G41 is electrically connected to P41 and P43, and G42 is electrically connected to P42 and P44;

[0127] D11 is electrically connected to P11 and P31, and D12 is electrically connected to P21 and P41;

[0128] D21 is electrically connected to P22 and P42, and D22 is electrically connected to P12 and P32;

[0129] D31 is electrically connected to P13 and P33, and D32 is electrically connected to P23 and P43;

[0130] D41 is electrically connected to P24 and P44, and D42 is electrically connected to P14 and P34.

[0131] In at least one embodiment of the present invention, the display panel may include a plurality of rows of gate lines, a plurality of columns of data lines, and a plurality of rows and columns of pixel circuits. Figure 1 Only part of the pixel circuits, part of the gate lines and part of the data lines included in the display panel are shown.

[0132] The present invention Figure 1 At least one embodiment of the display panel shown in FIG. Figure 2 As shown, G11, G12, G21, G22, G31, G32, G41 and G42 are changed from the closed state to the open state in sequence, and the second row gate drive signal provided by G12 is delayed by H / 2 (H is the row period) than the first row gate drive signal provided by G11, the third row gate drive signal provided by G21 is delayed by H / 2 than the second row gate drive signal provided by G12, the fourth row gate drive signal provided by G22 is delayed by H / 2 than the third row gate drive signal provided by G21, the fifth row gate drive signal provided by G31 is delayed by H / 2 than the fourth row gate drive signal provided by G22, the sixth row gate drive signal provided by G32 is delayed by H / 2 than the fifth row gate drive signal provided by G31, the seventh row gate drive signal provided by G41 is delayed by H / 2 than the sixth row gate drive signal provided by G32, and the eighth row gate drive signal provided by G42 is delayed by H / 2 than the seventh row gate drive signal provided by G41;

[0133] like Figure 2 As shown, the present invention is Figure 1 When at least one embodiment of the display panel shown is in operation, during the period when G11 is turned on (i.e., the period when G11 outputs a low voltage), the data writing transistor and the compensation transistor in the pixel circuit of the first row and odd columns are turned on;

[0134] During the period when G12 is turned on (i.e., the period when G12 outputs a low voltage), the data writing transistor and the compensation transistor in the pixel circuit of the first row and even column are turned on;

[0135] During the period when G21 is turned on (i.e., the period when G21 outputs a low voltage), the data writing transistor and the compensation transistor in the pixel circuit of the second row and odd column are turned on;

[0136] During the period when G22 is turned on (i.e., the period when G22 outputs a low voltage), the data writing transistor and the compensation transistor in the pixel circuit of the second row and even column are turned on;

[0137] That is, even if there are overlapping time periods between the time periods when G11 is turned on, the time periods when G12 is turned on, the time periods when G21 is turned on, and the time periods when G22 is turned on, it will not affect the charging and compensation of each pixel circuit (the compensation refers to the compensation for the threshold voltage of the driving transistor in the pixel circuit). Therefore, the compensation time can be increased (the compensation time can be the time when a row of gate lines is continuously turned on) and the compensation time can be increased to twice the row cycle.

[0138] In a specific implementation, the display panel described in at least one embodiment of the present invention further includes a plurality of multiplexing circuits;

[0139] The multiplexing circuit is used to control the data voltage provided by the data input terminal to be input to the four column data lines in a time-sharing manner under the control of the multiplexing control signal provided by the multiplexing control line.

[0140] The display panel described in at least one embodiment of the present invention uses a multiplexing circuit to provide data voltages to four columns of data lines through a data input terminal in a time-sharing manner, thereby reducing the number of channels of the data driver IC (Integrated Circuit) required and reducing the cost of the display panel.

[0141] like Figure 3 As shown, in Figure 1 Based on at least one embodiment of the display panel shown, the display panel according to at least one embodiment of the present invention further includes a first multiplexing circuit 31 and a second multiplexing circuit 32;

[0142] The first multiplexing circuit 31 is electrically connected to the multiplexing control line M0, the first data input terminal I1, the first column data line D11, the second column data line D12, the third column data line D21 and the fourth column data line D22 respectively, and is used to control the data voltage provided by the first data input terminal I1 to be provided to D11, D12, D21 and D22 in a time-sharing manner under the control of the multiplexing control signal provided by the multiplexing control line M0;

[0143] The second multiplexing circuit 32 is electrically connected to the multiplexing control line M0, the second data input terminal I2, the fifth column data line D31, the sixth column data line D32, the seventh column data line D41 and the eighth column data line D42, respectively, and is used to control the data voltage provided by the second data input terminal I2 to be provided to D31, D32, D41 and D42 in a time-sharing manner under the control of the multiplexing control signal provided by the multiplexing control line M0.

[0144] According to a specific implementation, the multiplexing control line includes a first multiplexing control line, a second multiplexing control line, a first column gating control line and a second column gating control line; the pth multiplexing circuit includes a pth row multiplexing subcircuit and a pth column multiplexing subcircuit; p is a positive integer;

[0145] The p-th column multiplexing subcircuit is electrically connected to the p-th data input terminal, the first column selection control line, the second column selection control line, the 2p-1th write node and the 2p write node respectively, and is used for controlling the connection between the p-th data input terminal and the 2p-1th write node to be turned on or off, and controlling the connection between the p-th data input terminal and the 2p write node to be turned on or off, under the control of a first column selection control signal provided by the first column selection control line and a second column selection control signal provided by the second column selection control line;

[0146] The p-th row multiplexing sub-circuit is electrically connected to the 2p-1th write node, the 2p write node, the first multiplexing control line, the second multiplexing control line, the 4p-3th column data line, the 4p-2th column data line, the 4p-1th column data line and the 4p column data line, respectively, and is used to control the connection between the 2p-1th write node and the 4p-3th column data line or the 4p-2th column data line, and to control the connection between the 2p write node and the 4p-1th column data line or the 4p column data line under the control of a first multiplexing control signal provided by the first multiplexing control line and a second multiplexing control signal provided by the second multiplexing control line.

[0147] In a specific implementation, the multiplexing control line may include a first multiplexing control line, a second multiplexing control line, a first column selection control line and a second column selection control line; the pth multiplexing circuit includes a pth row multiplexing sub-circuit and a pth column multiplexing sub-circuit, the pth column multiplexing sub-circuit is used to control the connection between the pth data input terminal and the 2p-1th write node or the 2pth write node, the pth row multiplexing sub-circuit controls the connection between the 2p-1th write node and the 4p-3th column data line or the 4p-2th column data line, and controls the connection between the 2p write node and the 4p-1th column data line or the 4p column data line, so as to realize the time-sharing provision of the data voltage provided by the pth data input terminal to the 4p-3th column data line, the 4p-2th column data line, the 4p-1th column data line and the 4p column data line.

[0148] like Figure 4 As shown, in Figure 3 On the basis of at least one embodiment of the display panel shown, the multiplexing control line includes a first multiplexing control line M1, a second multiplexing control line M2, a first column gating control line S1 and a second column gating control line S2; the first multiplexing circuit includes a first row multiplexing sub-circuit 311 and a first column multiplexing sub-circuit 312; the second multiplexing circuit includes a second row multiplexing sub-circuit 321 and a second column multiplexing sub-circuit 322;

[0149] The first column multiplexing sub-circuit 312 is electrically connected to the first data input terminal I1, the first column selection control line S1, the second column selection control line S2, the first write node W1 and the second write node W2, respectively, and is used to control the connection between the first data input terminal I1 and the first write node W1 and the connection between the first data input terminal I1 and the second write node W2 to be turned on or off under the control of a first column selection control signal provided by the first column selection control line S1 and a second column selection control signal provided by the second column selection control line S2;

[0150] The first row multiplexing sub-circuit 311 is electrically connected to the first write node W1, the second write node W2, the first multiplexing control line M1, the second multiplexing control line M2, the first column data line D11, the second column data line D12, the third column data line D21 and the fourth column data line D22, respectively, and is used to control the first write node W1 to be connected to the first column data line D11 or the second column data line D12, and to control the second write node W2 to be connected to the third column data line D21 or the fourth column data line D22 under the control of a first multiplexing control signal provided by the first multiplexing control line M1 and a second multiplexing control signal provided by the second multiplexing control line M2;

[0151] The second column multiplexing sub-circuit 322 is electrically connected to the second data input terminal I2, the first column selection control line S1, the second column selection control line S2, the third write node W3 and the fourth write node W4 respectively, and is used to control the connection between the second data input terminal I2 and the third write node W3 to be turned on or off, and the connection between the second data input terminal I2 and the fourth write node W4 to be turned on or off, under the control of the first column selection control signal provided by the first column selection control line S1 and the second column selection control signal provided by the second column selection control line S2;

[0152] The second row multiplexing sub-circuit 321 is electrically connected to the third write node W3, the fourth write node W4, the first multiplexing control line M1, the second multiplexing control line M2, the fifth column data line D31, the sixth column data line D32, the seventh column data line D41 and the eighth column data line D42, respectively, and is used to control the connection between the third write node W1 and the fifth column data line D31 or the sixth column data line D32, and to control the connection between the fourth write node W4 and the seventh column data line D41 or the eighth column data line D42 under the control of a first multiplexing control signal provided by the first multiplexing control line M1 and a second multiplexing control signal provided by the second multiplexing control line M2.

[0153] In a specific implementation, the multiplexing control line may include a first multiplexing control line M1, a second multiplexing control line M2, a first column selection control line S1, and a second column selection control line S2; the first multiplexing circuit includes a first row multiplexing sub-circuit 311 and a first column multiplexing sub-circuit 312, the first column multiplexing sub-circuit 312 is used to control the connection between the first data input terminal I1 and the first write node W1 or the second write node W2, the first row multiplexing sub-circuit 311 controls the connection between the first write node W1 and the first column data line D11 or the second column data line D12, and controls the connection between the second write node W2 and the third column data line D21 or the fourth column data line D22, so as to realize that the data voltage provided by the first data input terminal I1 is provided to the first column data line D11, the second column data line D12, the third column data line D21, and the fourth column data line D22 in a time-sharing manner;

[0154] The second multiplexing circuit includes a second row multiplexing sub-circuit 321 and a second column multiplexing sub-circuit 322. The second column multiplexing sub-circuit 322 is used to control the connection between the second data input terminal I2 and the third write node W3 or the fourth write node W4. The second row multiplexing sub-circuit 321 controls the connection between the third write node W3 and the fifth column data line D31 or the sixth column data line D32, and controls the connection between the fourth write node W4 and the seventh column data line D41 or the eighth column data line D42, so as to realize the time-sharing provision of the data voltage provided by the second data input terminal I2 to the fifth column data line D31, the sixth column data line D32, the seventh column data line D41 and the eighth column data line D42.

[0155] Optionally, the p-th column multiplexing subcircuit includes a p-th first column multiplexing transistor and a p-th second column multiplexing transistor, wherein:

[0156] The control electrode of the pth first column multiplexing transistor is electrically connected to the first column selection control line, the first electrode of the pth first column multiplexing transistor is electrically connected to the pth data input terminal, and the second electrode of the pth first column multiplexing transistor is electrically connected to the 2p-1th write node;

[0157] The control electrode of the pth second column multiplexing transistor is electrically connected to the second column selection control line, the first electrode of the pth second column multiplexing transistor is electrically connected to the pth data input terminal, and the second electrode of the pth second column multiplexing transistor is electrically connected to the 2pth write node.

[0158] Optionally, the p-th row multiplexing subcircuit includes a p-th first row multiplexing transistor, a p-th second row multiplexing transistor, a p-th third row multiplexing transistor and a p-th fourth row multiplexing transistor;

[0159] The control electrode of the pth first-row multiplexing transistor is electrically connected to the first multiplexing control line, the first electrode of the pth first-row multiplexing transistor is electrically connected to the 2p-1th write node, and the second electrode of the pth first-row multiplexing transistor is electrically connected to the 4p-3th column data line;

[0160] The control electrode of the p-th second-row multiplexing transistor is electrically connected to the second multiplexing control line, the first electrode of the p-th second-row multiplexing transistor is electrically connected to the 2p-1th write node, and the second electrode of the p-th second-row multiplexing transistor is electrically connected to the 4p-2th column data line;

[0161] The control electrode of the p-th third-row multiplexing transistor is electrically connected to the second multiplexing control line, the first electrode of the p-th third-row multiplexing transistor is electrically connected to the 2p-th write node, and the second electrode of the p-th third-row multiplexing transistor is electrically connected to the 4p-1-th column data line;

[0162] The control electrode of the pth fourth row multiplexing transistor is electrically connected to the first multiplexing control line, the first electrode of the pth fourth row multiplexing transistor is electrically connected to the 2pth write node, and the second electrode of the pth fourth row multiplexing transistor is electrically connected to the 4p column data line.

[0163] like Figure 5 As shown, in Figure 4 Based on at least one embodiment of the display panel shown, the first column multiplexing sub-circuit 312 includes a first first column multiplexing transistor T11 and a first second column multiplexing transistor T12, wherein:

[0164] The gate of the first first column multiplexing transistor T11 is electrically connected to the first column selection control line S1, the source of the first first column multiplexing transistor T11 is electrically connected to the first data input terminal I1, and the drain of the first first column multiplexing transistor T11 is electrically connected to the first write node W1;

[0165] The gate of the first second column multiplexing transistor T12 is electrically connected to the second column selection control line S2, the source of the first second column multiplexing transistor T12 is electrically connected to the first data input terminal I1, and the drain of the first second column multiplexing transistor T12 is electrically connected to the second write node W2;

[0166] The first row multiplexing sub-circuit 311 includes a first first row multiplexing transistor T21, a first second row multiplexing transistor T22, a first third row multiplexing transistor T23 and a first fourth row multiplexing transistor T24;

[0167] The gate of the first first-row multiplexing transistor T21 is electrically connected to the first multiplexing control line M1, the source of the first first-row multiplexing transistor T21 is electrically connected to the first write node W1, and the drain of the first first-row multiplexing transistor T21 is electrically connected to the first column data line D11;

[0168] The gate of the first second row multiplexing transistor T22 is electrically connected to the second multiplexing control line M2, the source of the first second row multiplexing transistor T22 is electrically connected to the first write node W1, and the drain of the first second row multiplexing transistor T22 is electrically connected to the second column data line D12;

[0169] The gate of the first third-row multiplexing transistor T23 is electrically connected to the second multiplexing control line M2, the source of the first third-row multiplexing transistor T23 is electrically connected to the second write node W2, and the drain of the first third-row multiplexing transistor T23 is electrically connected to the third column data line D21;

[0170] The gate of the first fourth-row multiplexing transistor T24 is electrically connected to the first multiplexing control line M1, the source of the first fourth-row multiplexing transistor T24 is electrically connected to the second write node W2, and the drain of the first fourth-row multiplexing transistor T24 is electrically connected to the fourth column data line D22;

[0171] The second column multiplexing sub-circuit 322 includes a second first column multiplexing transistor T31 and a second second column multiplexing transistor T32, wherein:

[0172] The gate of the second first column multiplexing transistor T31 is electrically connected to the first column selection control line S1, the source of the second first column multiplexing transistor T31 is electrically connected to the second data input terminal I2, and the drain of the second first column multiplexing transistor T31 is electrically connected to the third write node W3;

[0173] The gate of the second second column multiplexing transistor T32 is electrically connected to the second column selection control line S2, the source of the second second column multiplexing transistor T32 is electrically connected to the second data input terminal I2, and the drain of the second second column multiplexing transistor T32 is electrically connected to the fourth write node W4;

[0174] The second row multiplexing sub-circuit 321 includes a second first row multiplexing transistor T41, a second second row multiplexing transistor T42, a second third row multiplexing transistor T43 and a second fourth row multiplexing transistor T44;

[0175] The gate of the second first-row multiplexing transistor T41 is electrically connected to the first multiplexing control line M1, the source of the second first-row multiplexing transistor T41 is electrically connected to the third write node W3, and the drain of the second first-row multiplexing transistor T41 is electrically connected to the fifth column data line D31;

[0176] The gate of the second second-row multiplexing transistor T42 is electrically connected to the second multiplexing control line M2, the source of the second second-row multiplexing transistor T42 is electrically connected to the third write node W3, and the drain of the second second-row multiplexing transistor T42 is electrically connected to the sixth column data line D32;

[0177] The gate of the second third row multiplexing transistor T43 is electrically connected to the second multiplexing control line M2, the source of the second third row multiplexing transistor T43 is electrically connected to the fourth write node W4, and the drain of the second third row multiplexing transistor T43 is electrically connected to the seventh column data line D41;

[0178] The gate of the second fourth-row multiplexing transistor T44 is electrically connected to the first multiplexing control line M1, the source of the second fourth-row multiplexing transistor T44 is electrically connected to the fourth write node W4, and the drain of the first fourth-row multiplexing transistor T44 is electrically connected to the eighth column data line D42;

[0179] exist Figure 5 In at least one embodiment of the display panel shown, all transistors are p-type thin film transistors, but the present invention is not limited thereto.

[0180] like Fig. 6A As shown, the present invention is Figure 5 When at least one embodiment of the display panel shown is in operation, the data providing cycle includes a first data providing phase t1, a second data providing phase t2, a third data providing phase t3, a fourth data providing phase t4, a fifth data providing phase t5, a sixth data providing phase t6, a seventh data providing phase t7 and an eighth data providing phase t8 which are arranged in sequence;

[0181] In the first data providing stage t1, S1 provides a low voltage, S2 provides a high voltage, M1 provides a low voltage, M2 provides a high voltage, T11 is turned on, T12 is turned off, T31 is turned on, T32 is turned off, T21 and T24 are turned on, T22 and T23 are turned off, T41 and T44 are turned on, T42 and T43 are turned off, I1 is connected to W1, W1 is connected to D11, and I1 provides a data voltage to D11; I2 is connected to W3, W3 is connected to D31, and I2 provides a data voltage to D31;

[0182] In the second data providing phase t2, S1 provides a high voltage, S2 provides a low voltage, M1 provides a low voltage, M2 provides a high voltage, T11 is turned off, T12 is turned on, T31 is turned off, T32 is turned on, T21 and T24 are turned on, T22 and T23 are turned off, T41 and T44 are turned on, T42 and T43 are turned off, I1 is connected to W2, W2 is connected to D22, I1 provides a data voltage to D22; I2 is connected to W4, W4 is connected to D42, and I2 provides a data voltage to D42;

[0183] In the third data providing phase t3, S1 provides a low voltage, S2 provides a high voltage, M1 provides a high voltage, M2 provides a low voltage, T11 is turned on, T12 is turned off, T31 is turned on, T32 is turned off, T21 and T24 are turned off, T22 and T23 are turned on, T41 and T44 are turned off, T42 and T43 are turned on, I1 is connected to W1, W1 is connected to D12, I1 provides a data voltage to D12, I2 is connected to W3, W3 is connected to D32, and I2 provides a data voltage to D32;

[0184] In the fourth data providing stage t4, S1 provides a high voltage, S2 provides a low voltage, M1 provides a high voltage, M2 provides a low voltage, T11 is turned off, T12 is turned on, T31 is turned off, T32 is turned on, T21 and T24 are turned off, T22 and T23 are turned on, T41 and T44 are turned off, T42 and T43 are turned on, I1 is connected to W2, W2 is connected to D21, and I1 provides a data voltage to D21; I2 is connected to W4, W4 is connected to D41, and I2 provides a data voltage to D41;

[0185] In the fifth data providing stage t5, S1 provides a low voltage, S2 provides a high voltage, M1 provides a low voltage, M2 provides a high voltage, T11 is turned on, T12 is turned off, T31 is turned on, T32 is turned off, T21 and T24 are turned on, T22 and T23 are turned off, T41 and T44 are turned on, T42 and T43 are turned off, I1 is connected to W1, W1 is connected to D11, I1 provides a data voltage to D11; I2 is connected to W3, W3 is connected to D31, and I2 provides a data voltage to D31;

[0186] In the sixth data providing phase t6, S1 provides a high voltage, S2 provides a low voltage, M1 provides a low voltage, M2 provides a high voltage, T11 is turned off, T12 is turned on, T31 is turned off, T32 is turned on, T21 and T24 are turned on, T22 and T23 are turned off, T41 and T44 are turned on, T42 and T43 are turned off, I1 is connected to W2, W2 is connected to D22, I1 provides a data voltage to D22; I2 is connected to W4, W4 is connected to D42, and I2 provides a data voltage to D42;

[0187] In the seventh data providing phase t7, S1 provides a low voltage, S2 provides a high voltage, M1 provides a high voltage, M2 provides a low voltage, T11 is turned on, T12 is turned off, T31 is turned on, T32 is turned off, T21 and T24 are turned off, T22 and T23 are turned on, T41 and T44 are turned off, T42 and T43 are turned on, I1 is connected to W1, W1 is connected to D12, I1 provides a data voltage to D12, I2 is connected to W3, W3 is connected to D32, and I2 provides a data voltage to D32;

[0188] In the eighth data providing stage t8, S1 provides a high voltage, S2 provides a low voltage, M1 provides a high voltage, M2 provides a low voltage, T11 is turned off, T12 is turned on, T31 is turned off, T32 is turned on, T21 and T24 are turned off, T22 and T23 are turned on, T41 and T44 are turned off, T42 and T43 are turned on, I1 is connected to W2, W2 is connected to D21, and I1 provides a data voltage to D21; I2 is connected to W4, W4 is connected to D41, and I2 provides a data voltage to D41.

[0189] like Fig. 6A As shown, at t1, t2, t3 and t4, G11 provides a low voltage and G11 is turned on;

[0190] At t2, t3, t4 and t5, G12 provides a low voltage and G12 is turned on;

[0191] At t3, t4, t5, and t6, G21 provides a low voltage and G21 is turned on;

[0192] At t4, t5, t6 and t7, G22 provides a low voltage and G22 is turned on.

[0193] like Fig. 6A As shown, the second row gate drive signal provided by G12 is delayed by H / 2 compared with the first row gate drive signal provided by G11, the third row gate drive signal provided by G21 is delayed by H / 2 compared with the second row gate drive signal provided by G12, and the fourth row gate drive signal provided by G22 is delayed by H / 2 compared with the first row gate drive signal provided by G21.

[0194] The present invention Figure 5 At least one embodiment of the display panel shown in FIG. Fig. 6A As shown,

[0195] At t1, I1 provides a data voltage to D11, I2 provides a data voltage to D31, and G11 is turned on, so that the data voltage provided by each data writing terminal can be written into the pixel circuit of the odd-numbered column of the first row;

[0196] At t2, I1 provides a data voltage to D22, I2 provides a data voltage to D42, and G12 is turned on, so that the data voltage provided by each data writing terminal can be written into the pixel circuit of the first row and even column;

[0197] At t3, I1 provides a data voltage to D12, I2 provides a data voltage to D32, and G13 is turned on, so that the data voltage provided by each data writing terminal can be written into the pixel circuit of the second row and odd column;

[0198] At t4, I1 provides a data voltage to D21, I2 provides a data voltage to D41, and G14 is turned on, so that the data voltage provided by each data writing terminal can be written into the pixel circuit of the second row and even column.

[0199] Since the present invention Figure 5 At least one embodiment of the display panel shown adopts a multiplexing circuit to provide data voltages to four data lines in a time-sharing manner through a data writing terminal, and a row of pixel circuits corresponds to two rows of gate lines, and a column of pixel circuits corresponds to two columns of data lines. Therefore, in order to provide corresponding data voltages to odd-row odd-column pixel circuits, odd-row even-column pixel circuits, even-row odd-column pixel circuits, and even-row even-column pixel circuits, respectively, the gate drive signals on adjacent row gate lines need to be set to be spaced H / 2 apart from each other.

[0200] In a specific implementation, the first-level light emitting control signal generating unit in the light emitting control signal generating circuit can provide light emitting control signals to two rows of pixel circuits through two rows of light emitting control lines. Figure 5 In at least one embodiment shown, a first-stage light-emitting control signal generating circuit may provide light-emitting control signals for E1 and E2, and a second-stage light-emitting control signal generating circuit may provide light-emitting control signals for E3 and E4.

[0201] Figure 6B yes Figure 5 Another working timing diagram of at least one embodiment of the display panel shown, Figure 6B and Fig. 6A The difference is that the light-emitting control signal on E1 is the same as the light-emitting control signal on E2.

[0202] like Fig. 7A As shown, the present invention is Figure 5 When at least one embodiment of the display panel shown is in operation, the first row display phase S01 may include a first reset time period S011, a first data writing time period S012 and a first light emission control time period S013 which are sequentially arranged;

[0203] In the first reset period S011, the first row reset control line R1 provides a valid first row reset control signal;

[0204] In the first row writing period S71 included in the first data writing period S012, the first row gate line G11 provides a valid gate driving signal;

[0205] In the second row writing period S72 included in the first data writing period S012, the second row gate line G12 provides a valid gate driving signal;

[0206] In the first light emitting control period S013, the first row light emitting control line E1 provides a valid light emitting control signal;

[0207] The second row writing period S72 is delayed by H / 2 compared to the first row writing period S71.

[0208] Figure 7B yes Figure 5 Another working timing diagram of at least one embodiment of the display panel shown, Figure 7B and Fig. 7A The difference is that the light-emitting control signal on E1 is the same as the light-emitting control signal on E2.

[0209] like Fig. 8A As shown, the present invention is Figure 5 When at least one embodiment of the display panel shown is in operation, the second row display phase S02 may include a second reset time period S021, a second data writing time period S022, and a second light emission control time period S023 which are sequentially arranged;

[0210] In the second reset period S021, the second row reset control line R2 provides a valid second row reset control signal;

[0211] In the third row writing period S81 included in the second data writing period S022, the third row gate line G21 provides a valid gate driving signal;

[0212] In the fourth row writing period S82 included in the second data writing period S022, the fourth row gate line G22 provides a valid gate driving signal;

[0213] In the second light emitting control period S023, the second row light emitting control line E2 provides a valid light emitting control signal;

[0214] The fourth row writing period S82 is delayed by H / 2 compared to the third row writing period S81.

[0215] Figure 8B yes Figure 5 Another working timing diagram of at least one embodiment of the display panel shown, Figure 8B and Fig. 8A The difference is that the light-emitting control signal on E1 is the same as the light-emitting control signal on E2.

[0216] According to another specific implementation, the multiplexing control line includes a first multiplexing control line, a second multiplexing control line, a third multiplexing control line and a fourth multiplexing control line, and the pth multiplexing circuit includes a pth first multiplexing sub-circuit, a pth second multiplexing sub-circuit, a pth third multiplexing sub-circuit and a pth fourth multiplexing sub-circuit, wherein,

[0217] The pth first multiplexing subcircuit is electrically connected to the first multiplexing control line, the pth data input terminal and the 4p-3th column data line respectively, and is used to switch on or off the connection between the pth data input terminal and the 4p-3th column data line under the control of the first multiplexing control signal provided by the first multiplexing control line;

[0218] The p-th second multiplexing subcircuit is electrically connected to the third multiplexing control line, the p-th data input terminal and the 4p-2 column data line respectively, and is used to turn on or off the connection between the p-th data input terminal and the 4p-2 column data line under the control of a third multiplexing control signal provided by the third multiplexing control line;

[0219] The pth third multiplexing subcircuit is electrically connected to the fourth multiplexing control line, the pth data input terminal and the 4p-1th column data line respectively, and is used to turn on or off the connection between the pth data input terminal and the 4p-1th column data line under the control of a fourth multiplexing control signal provided by the fourth multiplexing control line;

[0220] The pth fourth multiplexing sub-circuit is electrically connected to the second multiplexing control line, the pth data input terminal and the 4pth column data line respectively, and is used to turn on or off the connection between the pth data input terminal and the 4pth column data line under the control of a second multiplexing control signal provided by the second multiplexing control line.

[0221] In a specific implementation, the multiplexing control line may include a first multiplexing control line, a second multiplexing control line, a third multiplexing control line and a fourth multiplexing control line, the pth multiplexing circuit may include a pth first multiplexing sub-circuit, a pth second multiplexing sub-circuit, a pth third multiplexing sub-circuit and a pth fourth multiplexing sub-circuit, the pth first multiplexing sub-circuit, the pth second multiplexing sub-circuit, the pth third multiplexing sub-circuit and the pth fourth multiplexing sub-circuit control the pth data input terminal to provide data voltage to the 4p-3 column data line, the 4p-2 column data line, the 4p-1 column data line and the 4p column data line in a time-sharing manner.

[0222] like Fig. 9 As shown, in Figure 3Based on at least one embodiment of the display panel shown, the multiplexing control line includes a first multiplexing control line M1, a second multiplexing control line M2, a third multiplexing control line M3 and a fourth multiplexing control line M4, and the first multiplexing circuit includes a first first multiplexing sub-circuit 711, a first second multiplexing sub-circuit 712, a first third multiplexing sub-circuit 713 and a first fourth multiplexing sub-circuit 714, wherein,

[0223] The first first multiplexing sub-circuit 711 is electrically connected to the first multiplexing control line M1, the first data input terminal I1 and the first column data line D11 respectively, and is used to switch on or off the connection between the first data input terminal I1 and the first column data line D11 under the control of the first multiplexing control signal provided by the first multiplexing control line M1;

[0224] The first second multiplexing sub-circuit 712 is electrically connected to the third multiplexing control line M3, the first data input terminal I1 and the second column data line D12 respectively, and is used to turn on or off the connection between the first data input terminal I1 and the second column data line D12 under the control of the third multiplexing control signal provided by the third multiplexing control line M3;

[0225] The first third multiplexing sub-circuit 713 is electrically connected to the fourth multiplexing control line M4, the first data input terminal I1 and the third column data line D21 respectively, and is used to turn on or off the connection between the first data input terminal I1 and the third column data line D21 under the control of the fourth multiplexing control signal provided by the fourth multiplexing control line M4;

[0226] The first fourth multiplexing sub-circuit 714 is electrically connected to the second multiplexing control line M2, the first data input terminal I1 and the fourth column data line D22 respectively, and is used to turn on or off the connection between the first data input terminal I1 and the fourth column data line D22 under the control of the second multiplexing control signal provided by the second multiplexing control line M2;

[0227] The second multiplexing circuit includes a second first multiplexing sub-circuit 721, a second second multiplexing sub-circuit 722, a second third multiplexing sub-circuit 723 and a second fourth multiplexing sub-circuit 724, wherein:

[0228] The second first multiplexing sub-circuit 721 is electrically connected to the first multiplexing control line M1, the second data input terminal I2 and the fifth column data line D31 respectively, and is used to turn on or off the connection between the second data input terminal I2 and the fifth column data line D31 under the control of the first multiplexing control signal provided by the first multiplexing control line M1;

[0229] The second second multiplexing sub-circuit 722 is electrically connected to the third multiplexing control line M3, the second data input terminal I2 and the sixth column data line D32 respectively, and is used to turn on or off the connection between the second data input terminal I2 and the sixth column data line D32 under the control of the third multiplexing control signal provided by the third multiplexing control line M3;

[0230] The second third multiplexing sub-circuit 723 is electrically connected to the fourth multiplexing control line M4, the second data input terminal I2 and the seventh column data line D41 respectively, and is used to turn on or off the connection between the second data input terminal I2 and the seventh column data line D41 under the control of the fourth multiplexing control signal provided by the fourth multiplexing control line M4;

[0231] The second fourth multiplexing sub-circuit 724 is electrically connected to the second multiplexing control line M2, the second data input terminal I2 and the eighth column data line D42, respectively, and is used to turn on or off the connection between the second data input terminal I2 and the eighth column data line D42 under the control of the second multiplexing control signal provided by the second multiplexing control line M2.

[0232] In a specific implementation, the multiplexing control line may include a first multiplexing control line M1, a second multiplexing control line M2, a third multiplexing control line M3 and a fourth multiplexing control line M4, and the first multiplexing circuit may include a first first multiplexing sub-circuit 711, a first second multiplexing sub-circuit 712, a first third multiplexing sub-circuit 713 and a first fourth multiplexing sub-circuit 714, and the first first multiplexing sub-circuit 711, the first second multiplexing sub-circuit 712, the first third multiplexing sub-circuit 713 and the first fourth multiplexing sub-circuit 714 control the first data input The input terminal I1 provides data voltage to D11, D12, D21 and D22 in time sharing; the second multiplexing circuit may include a second first multiplexing sub-circuit 721, a second second multiplexing sub-circuit 722, a second third multiplexing sub-circuit 723 and a second fourth multiplexing sub-circuit 724, and the second first multiplexing sub-circuit 721, the second second multiplexing sub-circuit 722, the second third multiplexing sub-circuit 723 and the second fourth multiplexing sub-circuit 724 control the second data input terminal I2 to provide data voltage to D31, D32, D41 and D42 in time sharing.

[0233] Optionally, the pth first multiplexing subcircuit includes a pth first multiplexing transistor, the pth second multiplexing subcircuit includes a pth second multiplexing transistor, the pth third multiplexing subcircuit includes a pth third multiplexing transistor, and the pth fourth multiplexing subcircuit includes a pth fourth multiplexing transistor;

[0234] The control electrode of the pth first multiplexing transistor is electrically connected to the first multiplexing control line, the first electrode of the pth first multiplexing transistor is electrically connected to the pth data input terminal, and the second electrode of the pth first multiplexing transistor is electrically connected to the 4p-3th column data line;

[0235] The control electrode of the pth second multiplexing transistor is electrically connected to the third multiplexing control line, the first electrode of the pth second multiplexing transistor is electrically connected to the pth data input terminal, and the second electrode of the pth second multiplexing transistor is electrically connected to the 4p-2th column data line;

[0236] The control electrode of the pth third multiplexing transistor is electrically connected to the fourth multiplexing control line, the first electrode of the pth third multiplexing transistor is electrically connected to the pth data input terminal, and the second electrode of the pth third multiplexing transistor is electrically connected to the 4p-1th column data line;

[0237] The control electrode of the pth fourth multiplexing transistor is electrically connected to the second multiplexing control line, the first electrode of the pth fourth multiplexing transistor is electrically connected to the pth data input terminal, and the second electrode of the pth fourth multiplexing transistor is electrically connected to the 4pth column data line.

[0238] like Fig.10 As shown, in Fig. 9 Based on at least one embodiment of the display panel shown,

[0239] The first first multiplexing sub-circuit 711 includes a first first multiplexing transistor T71, the first second multiplexing sub-circuit 712 includes a first second multiplexing transistor T72, the first third multiplexing sub-circuit 713 includes a first third multiplexing transistor T73, and the first fourth multiplexing sub-circuit 714 includes a first fourth multiplexing transistor T74;

[0240] The gate of the first first multiplexing transistor T71 is electrically connected to the first multiplexing control line M1, the source of the first first multiplexing transistor T71 is electrically connected to the first data input terminal I1, and the drain of the first first multiplexing transistor T71 is electrically connected to the first column data line D11;

[0241] The gate of the first second multiplexing transistor T72 is electrically connected to the third multiplexing control line M3, the source of the first second multiplexing transistor T72 is electrically connected to the first data input terminal I1, and the drain of the first second multiplexing transistor T72 is electrically connected to the second column data line D12;

[0242] The gate of the first third multiplexing transistor T73 is electrically connected to the fourth multiplexing control line M4, the source of the first third multiplexing transistor T73 is electrically connected to the first data input terminal I1, and the drain of the first third multiplexing transistor T73 is electrically connected to the third column data line D21;

[0243] The gate of the first fourth multiplexing transistor T74 is electrically connected to the second multiplexing control line M2, the source of the first fourth multiplexing transistor T74 is electrically connected to the first data input terminal I1, and the drain of the first fourth multiplexing transistor T74 is electrically connected to the fourth column data line D22;

[0244] The second first multiplexing sub-circuit 721 includes a second first multiplexing transistor T81, the second second multiplexing sub-circuit 722 includes a second second multiplexing transistor T82, the second third multiplexing sub-circuit 723 includes a second third multiplexing transistor T83, and the second fourth multiplexing sub-circuit 724 includes a second fourth multiplexing transistor T84;

[0245] The gate of the second first multiplexing transistor T81 is electrically connected to the first multiplexing control line M1, the source of the second first multiplexing transistor T81 is electrically connected to the second data input terminal I2, and the drain of the second first multiplexing transistor T81 is electrically connected to the fifth column data line D31;

[0246] The gate of the second second multiplexing transistor T82 is electrically connected to the third multiplexing control line M3, the source of the second second multiplexing transistor T82 is electrically connected to the second data input terminal I2, and the drain of the second second multiplexing transistor T82 is electrically connected to the sixth column data line D32;

[0247] The gate of the second third multiplexing transistor T83 is electrically connected to the fourth multiplexing control line M4, the source of the second third multiplexing transistor T83 is electrically connected to the second data input terminal I2, and the drain of the second third multiplexing transistor T83 is electrically connected to the seventh column data line D41;

[0248] The gate of the second fourth multiplexing transistor T84 is electrically connected to the second multiplexing control line M2, the source of the second fourth multiplexing transistor T84 is electrically connected to the second data input terminal I2, and the drain of the second fourth multiplexing transistor T84 is electrically connected to the eighth column data line D42.

[0249] exist Fig.10 In at least one embodiment shown, all transistors are p-type thin film transistors, but the present invention is not limited thereto.

[0250] like Fig.11A As shown, Fig.10 When at least one embodiment of the display panel shown is in operation, the data providing cycle includes a first data providing phase t1, a second data providing phase t2, a third data providing phase t3 and a fourth data providing phase t4 which are arranged in sequence;

[0251] In the first data providing stage t1, M1 provides a low voltage, M2, M3 and M4 all provide a high voltage, T71 is turned on, T72, T73 and T74 are all turned off, the first data input terminal I1 is electrically connected to the first column data line D11, and I1 provides a data voltage to D11; T81 is turned on, T82, T83 and T84 are all turned off, the second data input terminal I2 is electrically connected to the fifth column data line D31, and I2 provides a data voltage to D31;

[0252] In the second data providing stage t2, M2 provides a low voltage, M1, M3 and M4 all provide a high voltage, T74 is turned on, T71, T72 and T73 are all turned off, the first data input terminal I1 is electrically connected to the fourth column data line D22, and I1 provides a data voltage to D22; T84 is turned on, T81, T82 and T83 are all turned off, the second data input terminal I2 is electrically connected to the eighth column data line D42, and I2 provides a data voltage to D42;

[0253] In the third data providing phase t3, M3 provides a low voltage, M1, M2 and M4 all provide a high voltage, T72 is turned on, T71, T73 and T74 are all turned off, the first data input terminal I1 is electrically connected to the second column data line D12, and I1 provides a data voltage to D12; T82 is turned on, T81, T83 and T84 are all turned off, the second data input terminal I2 is electrically connected to the sixth column data line D32, and I2 provides a data voltage to D32;

[0254] In the fourth data providing stage t4, M4 provides a low voltage, M1, M2 and M3 all provide a high voltage, T73 is turned on, T71, T72 and T74 are all turned off, the first data input terminal I1 is electrically connected to the third column data line D21, and I1 provides a data voltage to D21; T83 is turned on, T81, T82 and T84 are all turned off, the second data input terminal I2 is electrically connected to the seventh column data line D41, and I2 provides a data voltage to D41;

[0255] In a specific implementation, the display panel described in at least one embodiment of the present invention further includes a plurality of rows of reset control lines and a plurality of rows of light emitting control lines;

[0256] The pixel circuits in the same row are electrically connected to the reset control line and the light emitting control line in the same row respectively. The reset control line in the same row is used to provide a reset control signal for the pixel circuits in the same row, and the light emitting control line in the same row is used to provide a light emitting control signal for the pixel circuits in the same row.

[0257] In at least one embodiment of the present invention, the display panel further includes a plurality of rows of reset control lines and a plurality of rows of light emitting control lines, and each row of pixel circuits is electrically connected to a corresponding row of reset control lines and a corresponding row of light emitting control lines.

[0258] like Figure 1 As shown, the display panel according to at least one embodiment of the present invention further includes a first row of reset control lines R1, a second row of reset control lines R2, a third row of reset control lines R3, a fourth row of reset control lines R4, a first row of light-emitting control lines E1, a second row of light-emitting control lines E2, a third row of light-emitting control lines E3 and a fourth row of light-emitting control lines E4;

[0259] P11, P12, P13 and P14 are all electrically connected to R1, and P11, P12, P13 and P14 are all electrically connected to E1;

[0260] P21, P22, P23 and P24 are all electrically connected to R2, and P21, P22, P23 and P24 are all electrically connected to E2;

[0261] P31, P32, P33 and P34 are all electrically connected to R3, and P31, P32, P33 and P34 are all electrically connected to E3;

[0262] P41, P42, P43 and P44 are all electrically connected to R4, and P41, P42, P43 and P44 are all electrically connected to E4;

[0263] E1 provides a first row light-emitting control signal for P11, P12, P13 and P14, and R1 provides a first row reset control signal for P11, P12, P13 and P14;

[0264] E2 provides a second row light-emitting control signal for P21, P22, P23 and P24, and R2 provides a second row reset control signal for P11, P12, P13 and P14;

[0265] E3 provides a third row light-emitting control signal for P31, P32, P33 and P34, and R3 provides a third row reset control signal for P31, P32, P33 and P34;

[0266] E4 provides a fourth-row light-emitting control signal for P41, P42, P43 and P44, and R4 provides a fourth-row reset control signal for P41, P42, P43 and P44.

[0267] exist Fig. 6A and Fig.11A In the figure, the line labeled R1 is the reset control line of the first row, the line labeled E1 is the light-emitting control line of the first row, the line labeled R2 is the reset control line of the second row, and the line labeled E2 is the light-emitting control line of the second row.

[0268] In at least one embodiment of the display panel of the present invention, four gate driving circuits may provide gate driving signals for multiple rows of pixel circuits in the display panel; wherein:

[0269] The first gate driving circuit is used to provide a 4a-3 row gate driving signal for the 4a-3 row gate line;

[0270] The second gate driving circuit is used to provide a 4a-2 row gate driving signal for the 4a-2 row gate line;

[0271] The third gate driving circuit is used to provide the 4a-1 row gate driving signal for the 4a-1 row gate line;

[0272] The fourth gate driving circuit is used for providing a 4a row gate driving signal for the 4a row gate line;

[0273] a is a positive integer, 4a is less than or equal to 2N; N is a positive integer.

[0274] like Fig.11A As shown, the pulse width of the first row gate drive signal provided by G11, the pulse width of the second row gate drive signal provided by G12, the pulse width of the third row gate drive signal provided by G21 and the pulse width of the fourth row gate drive signal provided by G22 are all Th, and the phase difference between adjacent row gate drive signals is Th / 4. However, the phase difference between the gate drive signals output by adjacent row shift register units included in the same gate drive circuit is Th. Therefore, at least one embodiment of the present invention can use four gate drive circuits to provide gate drive signals for multiple rows of pixel circuits in the display panel.

[0275] In at least one embodiment of the present invention, the pulse width Th of each row of gate driving signals may be 2H, where H is a row period, and the phase difference between adjacent row gate driving signals may be H / 2.

[0276] In at least one embodiment of the present invention, if the reset control signal is provided by the gate driving circuit, since one row of pixel circuits corresponds to two rows of gate driving signals, there are also two reset control signals provided for one row of pixel circuits. In order to save the wiring space of the display panel, one row of pixel circuits only corresponds to one row of reset control lines. Therefore, in at least one embodiment of the present invention, a separate reset control signal generating circuit is used to provide corresponding reset control signals for each row of reset control lines, instead of the gate driving circuit providing the reset control signal.

[0277] In at least one embodiment of the present invention, a light emitting control signal generating circuit may provide corresponding light emitting control signals to multiple rows of pixel circuits respectively.

[0278] In a specific implementation, the first-level light emitting control signal generating unit in the light emitting control signal generating circuit can provide light emitting control signals to two rows of pixel circuits through two rows of light emitting control lines. Fig.10 In at least one embodiment shown, a first-stage light-emitting control signal generating circuit may provide light-emitting control signals for E1 and E2, and a second-stage light-emitting control signal generating circuit may provide light-emitting control signals for E3 and E4. Fig. 11B yes Fig.10 Another working timing diagram of at least one embodiment of the display panel shown in FIG. Fig. 11B As shown, the light-emitting control signal on E1 is the same as the light-emitting control signal on E2.

[0279] like Fig.12 As shown, in Figure 5 Based on at least one embodiment of the display panel shown, the display device according to at least one embodiment of the present invention further includes a first left gate driving circuit 101, a second left gate driving circuit 102, a third left gate driving circuit 103 and a fourth left gate driving circuit 104, a left reset control signal generating circuit 110 and a left light emission control signal generating circuit 120;

[0280] The first left gate driving circuit 101 is electrically connected to G11 and G31 respectively, and is used to provide corresponding gate driving signals to G11 and G31 respectively;

[0281] The second left gate driving circuit 102 is electrically connected to G12 and G32 respectively, and is used to provide corresponding gate driving signals to G12 and G32 respectively;

[0282] The third left gate driving circuit 103 is electrically connected to G21 and G41 respectively, and is used to provide corresponding gate driving signals to G21 and G41 respectively;

[0283] The fourth left gate driving circuit 104 is electrically connected to G22 and G42 respectively, and is used to provide corresponding gate driving signals to G22 and G42 respectively;

[0284] The left reset control signal generating circuit 110 is electrically connected to the first row reset control line R1, the second row reset control line R2, the third row reset control line R3 and the fourth row reset control line R4, respectively, for providing corresponding reset control signals to the first row reset control line R1, the second row reset control line R2, the third row reset control line R3 and the fourth row reset control line R4;

[0285] The left-side light-emitting control signal generating circuit 120 is electrically connected to the first row of light-emitting control lines E1, the second row of light-emitting control lines E2, the third row of light-emitting control lines E3 and the fourth row of light-emitting control lines E4, respectively, and is used to provide corresponding light-emitting control signals to the first row of light-emitting control lines E1, the second row of light-emitting control lines E2, the third row of light-emitting control lines E3 and the fourth row of light-emitting control lines E4, respectively.

[0286] Fig.13 is based on Fig.12 The overall structure diagram of the Fig.13 As shown, a gate driving circuit, a reset control signal generating circuit and a light emitting control signal generating circuit may be respectively arranged on the left and right sides of the pixel circuit.

[0287] like Fig.13 As shown, the display panel includes a plurality of rows and columns of pixel circuits P0;

[0288] The first row of pixel circuits is electrically connected to the first row of gate lines G11 and the second row of gate lines G12;

[0289] The second row of pixel circuits is electrically connected to the third row of gate lines G21 and the fourth row of gate lines G22;

[0290] The third row of pixel circuits is electrically connected to the fifth row of gate lines G31 and the sixth row of gate lines G32;

[0291] The fourth row of pixel circuits is electrically connected to the seventh row of gate line G41 and the eighth row of gate line G42;

[0292] The pixel circuit of the N-3th row is electrically connected to the gate line G011 of the 2N-7th row and the gate line G012 of the 2N-6th row;

[0293] The pixel circuit of the N-2th row is electrically connected to the gate line G021 of the 2N-5th row and the gate line G022 of the 2N-4th row;

[0294] The pixel circuit of the N-1th row is electrically connected to the gate line G031 of the 2N-3th row and the gate line G032 of the 2N-2th row;

[0295] The pixel circuit of the Nth row is electrically connected to the gate line G041 of the 2N-1th row and the gate line G042 of the 2Nth row.

[0296] The first column pixel circuit is electrically connected to the first column data line D11 and the second column data line D12;

[0297] The second column pixel circuit is electrically connected to the third column data line D21 and the fourth column data line D22;

[0298] The third column pixel circuit is electrically connected to the fifth column data line D31 and the sixth column data line D32;

[0299] The fourth column pixel circuit is electrically connected to the seventh column data line D41 and the eighth column data line D42;

[0300] The pixel circuit in the M-3 column is electrically connected to the data line D011 in the 2M-7 column and the data line D012 in the 2M-6 column;

[0301] The pixel circuit in the M-2 column is electrically connected to the data line D021 in the 2M-5 column and the data line D022 in the 2M-4 column;

[0302] The pixel circuit in the M-1th column is electrically connected to the data line D031 in the 2M-3th column and the data line D032 in the 2M-2nd column;

[0303] The pixel circuit in the Mth column is electrically connected to the data line D041 in the 2M-1th column and the data line D042 in the 2Mth column;

[0304] The first row of pixel circuits are electrically connected to the first row of reset control lines R1 and the first row of light emitting control lines E1 respectively;

[0305] The second row of pixel circuits are electrically connected to the second row of reset control lines R2 and the second row of light emitting control lines E2 respectively;

[0306] The third row of pixel circuits are electrically connected to the third row of reset control lines R3 and the third row of light emitting control lines E3 respectively;

[0307] The fourth row of pixel circuits are electrically connected to the fourth row of reset control lines R4 and the fourth row of light emitting control lines E4 respectively;

[0308] The pixel circuits in the N-3rd row are electrically connected to the reset control line R01 in the N-3rd row and the light emission control line E01 in the N-3rd row respectively;

[0309] The pixel circuits in the N-2th row are electrically connected to the reset control line R02 in the N-2th row and the light emission control line E02 in the N-2th row respectively;

[0310] The pixel circuits in the N-1th row are electrically connected to the reset control line R03 in the N-1th row and the light emission control line E03 in the N-1th row;

[0311] The pixel circuits in the Nth row are electrically connected to the reset control line R04 in the Nth row and the light emission control line E04 in the Nth row respectively;

[0312] The display device described in at least one embodiment of the present invention further includes a first left-side gate driving circuit, a second left-side gate driving circuit, a third left-side gate driving circuit, a fourth left-side gate driving circuit, a first right-side gate driving circuit, a second right-side gate driving circuit, a third right-side gate driving circuit, a fourth right-side gate driving circuit, a left-side reset control signal generating circuit, a right-side reset control signal generating circuit, a left-side light-emitting control signal generating circuit, and a right-side light-emitting control signal generating circuit;

[0313] A first-stage left-side shift register unit L11 included in the first left-side gate driving circuit, a second-stage left-side shift register unit L12 included in the first left-side gate driving circuit, a third-stage left-side shift register unit L13 included in the first left-side gate driving circuit, and a fourth-stage left-side shift register unit L14 included in the first left-side gate driving circuit are electrically connected to G11, G31, G011, and G031, respectively, and are used to provide corresponding gate driving signals to G11, G31, G011, and G031, respectively;

[0314] A first-stage right-side shift register unit L21 included in the first right-side gate driving circuit, a second-stage right-side shift register unit L22 included in the first right-side gate driving circuit, a third-stage right-side shift register unit L23 included in the first right-side gate driving circuit, and a fourth-stage right-side shift register unit L24 included in the first right-side gate driving circuit are electrically connected to G11, G31, G011, and G031, respectively, and are used to provide corresponding gate driving signals to G11, G31, G011, and G031, respectively;

[0315] A first-stage left-side shift register unit L31 included in the second left-side gate driving circuit, a second-stage left-side shift register unit L32 included in the second left-side gate driving circuit, a third-stage left-side shift register unit L33 included in the second left-side gate driving circuit, and a fourth-stage left-side shift register unit L34 included in the second left-side gate driving circuit are electrically connected to G12, G32, G012, and G032, respectively, and are used to provide corresponding gate driving signals to G12, G32, G012, and G032, respectively;

[0316] The first-stage right shift register unit L41 included in the second right gate driving circuit, the second-stage right shift register unit L42 included in the second right gate driving circuit, the third-stage right shift register unit L43 included in the second right gate driving circuit, and the fourth-stage right shift register unit L44 included in the second right gate driving circuit are electrically connected to G12, G32, G012 and G032 respectively, and are used to provide corresponding gate driving signals to G12, G32, G012 and G032 respectively;

[0317] A first-stage left-side shift register unit L51 included in the third left-side gate driving circuit, a second-stage left-side shift register unit L52 included in the third left-side gate driving circuit, a third-stage left-side shift register unit L53 included in the third left-side gate driving circuit, and a fourth-stage left-side shift register unit L54 included in the third left-side gate driving circuit are electrically connected to G21, G41, G021, and G041, respectively, and are used to provide corresponding gate driving signals to G21, G41, G021, and G041, respectively;

[0318] A first-stage right-side shift register unit L61 included in the third right-side gate driving circuit, a second-stage right-side shift register unit L62 included in the third right-side gate driving circuit, a third-stage right-side shift register unit L63 included in the third right-side gate driving circuit, and a fourth-stage right-side shift register unit L64 included in the third right-side gate driving circuit are electrically connected to G21, G41, G021, and G041, respectively, for providing corresponding gate driving signals to G21, G41, G021, and G041, respectively;

[0319] A first-stage left-side shift register unit L71 included in the fourth left-side gate driving circuit, a second-stage left-side shift register unit L72 included in the fourth left-side gate driving circuit, a third-stage left-side shift register unit L73 included in the fourth left-side gate driving circuit, and a fourth-stage left-side shift register unit L74 included in the fourth left-side gate driving circuit are electrically connected to G22, G42, G022, and G042, respectively, and are used to provide corresponding gate driving signals to G22, G42, G022, and G042, respectively;

[0320] The first-stage right shift register unit L81 included in the fourth right gate driving circuit, the second-stage right shift register unit L82 included in the fourth right gate driving circuit, the third-stage right shift register unit L83 included in the fourth right gate driving circuit, and the fourth-stage right shift register unit L84 included in the fourth right gate driving circuit are electrically connected to G22, G42, G022 and G042 respectively, and are used to provide corresponding gate driving signals to G22, G42, G022 and G042 respectively;

[0321] The left-side reset control signal generating circuit includes a first-level left-side reset control signal generating unit R11, a second-level left-side reset control signal generating unit R12, a third-level left-side reset control signal generating unit R13, a fourth-level left-side reset control signal generating unit R14, an N-3th-level left-side reset control signal generating unit R011, an N-2th-level left-side reset control signal generating unit R012, and an N-1th-level left-side reset control signal generating unit R013. 013. The left reset control signal generating circuit includes an N-th level left reset control signal generating unit R014 which is electrically connected to the first row reset control line R1, the second row reset control line R2, the third row reset control line R3, the fourth row reset control line R4, the N-3rd row reset control line R01, the N-2nd row reset control line R02, the N-1st row reset control line R03 and the N-row reset control line R04, respectively, and is used to provide corresponding reset control signals to the first row reset control line R1, the second row reset control line R2, the third row reset control line R3, the fourth row reset control line R4, the N-3rd row reset control line R01, the N-2nd row reset control line R02, the N-1st row reset control line R03 and the N-row reset control line R04, respectively;

[0322] The right reset control signal generating circuit includes a first-level right reset control signal generating unit R21, a second-level right reset control signal generating unit R22, a third-level right reset control signal generating unit R23, a fourth-level right reset control signal generating unit R24, an N-3-th right reset control signal generating unit R021, an N-2-th right reset control signal generating unit R022, and an N-1-th right reset control signal generating unit R023. 023. The right reset control signal generating circuit includes an N-th level right reset control signal generating unit R024 which is electrically connected to the first row reset control line R1, the second row reset control line R2, the third row reset control line R3, the fourth row reset control line R4, the N-3rd row reset control line R01, the N-2nd row reset control line R02, the N-1st row reset control line R03 and the N-row reset control line R04, respectively, and is used to provide corresponding reset control signals to the first row reset control line R1, the second row reset control line R2, the third row reset control line R3, the fourth row reset control line R4, the N-3rd row reset control line R01, the N-2nd row reset control line R02, the N-1st row reset control line R03 and the N-row reset control line R04, respectively;

[0323] The left-side light emitting control signal generating circuit includes a first-level left-side light emitting control signal generating unit E11, a second-level left-side light emitting control signal generating unit E12, a third-level left-side light emitting control signal generating unit E13, a fourth-level left-side light emitting control signal generating unit E14, an N-3th-level left-side light emitting control signal generating unit E011, an N-2th-level left-side light emitting control signal generating unit E012, and an N-1th-level left-side light emitting control signal generating unit E15. 013. The left-side light-emitting control signal generating circuit includes an N-th level left-side light-emitting control signal generating unit E014 which is electrically connected to the first-row light-emitting control line E1, the second-row light-emitting control line E2, the third-row light-emitting control line E3, the fourth-row light-emitting control line E4, the N-3-th-row light-emitting control line E01, the N-2-th-row light-emitting control line E02, the N-1-th-row light-emitting control line E03 and the N-th-row light-emitting control line E04, respectively, and is used to provide corresponding light-emitting control signals to the first-row light-emitting control line E1, the second-row light-emitting control line E2, the third-row light-emitting control line E3, the fourth-row light-emitting control line E4, the N-3-th-row light-emitting control line E01, the N-2-th-row light-emitting control line E02, the N-1-th-row light-emitting control line E03 and the N-th-row light-emitting control line E04, respectively;

[0324] The right side light emitting control signal generating circuit includes a first level right side light emitting control signal generating unit E21, a second level right side light emitting control signal generating unit E22, a third level right side light emitting control signal generating unit E23, a fourth level right side light emitting control signal generating unit E24, an N-3 level right side light emitting control signal generating unit E021, an N-2 level right side light emitting control signal generating unit E022, and an N-1 level right side light emitting control signal generating unit E023. 023. The right-side light-emitting control signal generating circuit includes an N-th right-side light-emitting control signal generating unit E024 which is electrically connected to the first-row light-emitting control line E1, the second-row light-emitting control line E2, the third-row light-emitting control line E3, the fourth-row light-emitting control line E4, the N-3-th-row light-emitting control line E01, the N-2-th-row light-emitting control line E02, the N-1-th-row light-emitting control line E03 and the N-th-row light-emitting control line E04, respectively, and is used to provide corresponding light-emitting control signals to the first-row light-emitting control line E1, the second-row light-emitting control line E2, the third-row light-emitting control line E3, the fourth-row light-emitting control line E4, the N-3-th-row light-emitting control line E01, the N-2-th-row light-emitting control line E02, the N-1-th-row light-emitting control line E03 and the N-th-row light-emitting control line E04, respectively;

[0325] like Fig.13 As shown, the multiplexing control line includes a first multiplexing control line M1, a second multiplexing control line M2, a first column gate control line S1 and a second column gate control line S2;

[0326] exist Fig.13 , the terminal labeled I1 is the first data writing terminal, the terminal labeled I2 is the second data writing terminal, the terminal labeled I01 is the P-1th data writing terminal, and the terminal labeled I02 is the Pth data writing terminal; P is an integer greater than 3;

[0327] exist Fig.13In the figure, the transistor labeled T11 is the first multiplexing transistor of the first column, the transistor labeled T12 is the first multiplexing transistor of the second column; the transistor labeled T21 is the first multiplexing transistor of the first row, the transistor labeled T22 is the first multiplexing transistor of the second row, the transistor labeled T23 is the first multiplexing transistor of the third row, and the transistor labeled T24 is the first multiplexing transistor of the fourth row; the transistor labeled T31 is the second multiplexing transistor of the first column, and the transistor labeled T32 is the second multiplexing transistor of the second column; the transistor labeled T41 is the second multiplexing transistor of the first row, the transistor labeled T42 is the second multiplexing transistor of the second row, the transistor labeled T43 is the second multiplexing transistor of the third row, and the transistor labeled T44 is the second multiplexing transistor of the fourth row;

[0328] exist Fig.13 , the transistor labeled T011 is the P-1th first column multiplexing transistor, the transistor labeled T012 is the P-1th second column multiplexing transistor; the transistor labeled T021 is the P-1th first row multiplexing transistor, the transistor labeled T022 is the P-1th second row multiplexing transistor, the transistor labeled T023 is the P-1th third row multiplexing transistor, and the transistor labeled T024 is the P-1th fourth row multiplexing transistor; the transistor labeled T031 is the Pth first column multiplexing transistor, the transistor labeled T032 is the Pth second column multiplexing transistor; the transistor labeled T041 is the Pth first row multiplexing transistor, the transistor labeled T042 is the Pth second row multiplexing transistor, the transistor labeled T043 is the Pth third row multiplexing transistor, and the transistor labeled T044 is the Pth fourth row multiplexing transistor;

[0329] The left light emitting control signal generating circuit and the right light emitting control signal generating circuit are connected to the first light emitting control clock signal and the second light emitting control clock signal;

[0330] The left reset control signal generating circuit and the right reset control signal generating circuit are connected to the first reset control clock signal and the second reset control clock signal;

[0331] The first left gate driving circuit and the first right gate driving circuit are connected to the first clock signal and the second clock signal;

[0332] The second left gate driving circuit and the second right gate driving circuit are connected to the third clock signal and the fourth clock signal;

[0333] The third left gate driving circuit and the third right gate driving circuit are connected to the fifth clock signal and the sixth clock signal;

[0334] The fourth left-side gate driving circuit and the fourth right-side gate driving circuit are connected to the seventh clock signal and the eighth clock signal.

[0335] like Fig.13As shown, the first left gate driving circuit, the second left gate driving circuit, the third left gate driving circuit, the fourth left gate driving circuit, the left reset control signal generating circuit and the left light emission control signal generating circuit are arranged on the left side of the display panel;

[0336] The first right side gate driving circuit, the second right side gate driving circuit, the third right side gate driving circuit, the fourth right side gate driving circuit, the right side reset control signal generating circuit, and the right side light emitting control signal generating circuit are arranged on the right side of the display panel.

[0337] Fig.14 is based on Fig.12 In the specific implementation, such as Fig.14 As shown, a gate driving circuit, a reset control signal generating circuit and a light emitting control signal generating circuit may be respectively arranged on the left and right sides of the pixel circuit.

[0338] like Fig.14 As shown, the display panel includes a plurality of rows and columns of pixel circuits P0;

[0339] The first row of pixel circuits is electrically connected to the first row of gate lines G11 and the second row of gate lines G12;

[0340] The second row of pixel circuits is electrically connected to the third row of gate lines G21 and the fourth row of gate lines G22;

[0341] The third row of pixel circuits is electrically connected to the fifth row of gate lines G31 and the sixth row of gate lines G32;

[0342] The fourth row of pixel circuits is electrically connected to the seventh row of gate line G41 and the eighth row of gate line G42;

[0343] The pixel circuit of the N-3th row is electrically connected to the gate line G011 of the 2N-7th row and the gate line G012 of the 2N-6th row;

[0344] The pixel circuit of the N-2th row is electrically connected to the gate line G021 of the 2N-5th row and the gate line G022 of the 2N-4th row;

[0345] The pixel circuit of the N-1th row is electrically connected to the gate line G031 of the 2N-3th row and the gate line G032 of the 2N-2th row;

[0346] The pixel circuit of the Nth row is electrically connected to the gate line G041 of the 2N-1th row and the gate line G042 of the 2Nth row.

[0347] The first column pixel circuit is electrically connected to the first column data line D11 and the second column data line D12;

[0348] The second column pixel circuit is electrically connected to the third column data line D21 and the fourth column data line D22;

[0349] The third column pixel circuit is electrically connected to the fifth column data line D31 and the sixth column data line D32;

[0350] The fourth column pixel circuit is electrically connected to the seventh column data line D41 and the eighth column data line D42;

[0351] The pixel circuit in the M-3 column is electrically connected to the data line D011 in the 2M-7 column and the data line D012 in the 2M-6 column;

[0352] The pixel circuit in the M-2 column is electrically connected to the data line D021 in the 2M-5 column and the data line D022 in the 2M-4 column;

[0353] The pixel circuit in the M-1th column is electrically connected to the data line D031 in the 2M-3th column and the data line D032 in the 2M-2nd column;

[0354] The pixel circuit in the Mth column is electrically connected to the data line D041 in the 2M-1th column and the data line D042 in the 2Mth column;

[0355] The first row of pixel circuits are electrically connected to the first row of reset control lines R1 and the first row of light emitting control lines E1 respectively;

[0356] The second row of pixel circuits are electrically connected to the second row of reset control lines R2 and the second row of light emitting control lines E2 respectively;

[0357] The third row of pixel circuits are electrically connected to the third row of reset control lines R3 and the third row of light emitting control lines E3 respectively;

[0358] The fourth row of pixel circuits are electrically connected to the fourth row of reset control lines R4 and the fourth row of light emitting control lines E4 respectively;

[0359] The pixel circuits in the N-3rd row are electrically connected to the reset control line R01 in the N-3rd row and the light emission control line E01 in the N-3rd row respectively;

[0360] The pixel circuits in the N-2th row are electrically connected to the reset control line R02 in the N-2th row and the light emission control line E02 in the N-2th row respectively;

[0361] The pixel circuits in the N-1th row are electrically connected to the reset control line R03 in the N-1th row and the light emission control line E03 in the N-1th row;

[0362] The pixel circuits in the Nth row are electrically connected to the reset control line R04 in the Nth row and the light emission control line E04 in the Nth row respectively;

[0363] The display device described in at least one embodiment of the present invention further includes a first left-side gate driving circuit, a second left-side gate driving circuit, a third left-side gate driving circuit, a fourth left-side gate driving circuit, a first right-side gate driving circuit, a second right-side gate driving circuit, a third right-side gate driving circuit, a fourth right-side gate driving circuit, a left-side reset control signal generating circuit, a right-side reset control signal generating circuit, a left-side light-emitting control signal generating circuit, and a right-side light-emitting control signal generating circuit;

[0364] A first-stage left-side shift register unit L11 included in the first left-side gate driving circuit, a second-stage left-side shift register unit L12 included in the first left-side gate driving circuit, a third-stage left-side shift register unit L13 included in the first left-side gate driving circuit, and a fourth-stage left-side shift register unit L14 included in the first left-side gate driving circuit are electrically connected to G11, G31, G011, and G031, respectively, and are used to provide corresponding gate driving signals to G11, G31, G011, and G031, respectively;

[0365] A first-stage right-side shift register unit L21 included in the first right-side gate driving circuit, a second-stage right-side shift register unit L22 included in the first right-side gate driving circuit, a third-stage right-side shift register unit L23 included in the first right-side gate driving circuit, and a fourth-stage right-side shift register unit L24 included in the first right-side gate driving circuit are electrically connected to G11, G31, G011, and G031, respectively, and are used to provide corresponding gate driving signals to G11, G31, G011, and G031, respectively;

[0366] A first-stage left-side shift register unit L31 included in the second left-side gate driving circuit, a second-stage left-side shift register unit L32 included in the second left-side gate driving circuit, a third-stage left-side shift register unit L33 included in the second left-side gate driving circuit, and a fourth-stage left-side shift register unit L34 included in the second left-side gate driving circuit are electrically connected to G12, G32, G012, and G032, respectively, and are used to provide corresponding gate driving signals to G12, G32, G012, and G032, respectively;

[0367] The first-stage right shift register unit L41 included in the second right gate driving circuit, the second-stage right shift register unit L42 included in the second right gate driving circuit, the third-stage right shift register unit L43 included in the second right gate driving circuit, and the fourth-stage right shift register unit L44 included in the second right gate driving circuit are electrically connected to G12, G32, G012 and G032 respectively, and are used to provide corresponding gate driving signals to G12, G32, G012 and G032 respectively;

[0368] A first-stage left-side shift register unit L51 included in the third left-side gate driving circuit, a second-stage left-side shift register unit L52 included in the third left-side gate driving circuit, a third-stage left-side shift register unit L53 included in the third left-side gate driving circuit, and a fourth-stage left-side shift register unit L54 included in the third left-side gate driving circuit are electrically connected to G21, G41, G021, and G041, respectively, and are used to provide corresponding gate driving signals to G21, G41, G021, and G041, respectively;

[0369] A first-stage right-side shift register unit L61 included in the third right-side gate driving circuit, a second-stage right-side shift register unit L62 included in the third right-side gate driving circuit, a third-stage right-side shift register unit L63 included in the third right-side gate driving circuit, and a fourth-stage right-side shift register unit L64 included in the third right-side gate driving circuit are electrically connected to G21, G41, G021, and G041, respectively, for providing corresponding gate driving signals to G21, G41, G021, and G041, respectively;

[0370] A first-stage left-side shift register unit L71 included in the fourth left-side gate driving circuit, a second-stage left-side shift register unit L72 included in the fourth left-side gate driving circuit, a third-stage left-side shift register unit L73 included in the fourth left-side gate driving circuit, and a fourth-stage left-side shift register unit L74 included in the fourth left-side gate driving circuit are electrically connected to G22, G42, G022, and G042, respectively, and are used to provide corresponding gate driving signals to G22, G42, G022, and G042, respectively;

[0371] The first-stage right shift register unit L81 included in the fourth right gate driving circuit, the second-stage right shift register unit L82 included in the fourth right gate driving circuit, the third-stage right shift register unit L83 included in the fourth right gate driving circuit, and the fourth-stage right shift register unit L84 included in the fourth right gate driving circuit are electrically connected to G22, G42, G022 and G042 respectively, and are used to provide corresponding gate driving signals to G22, G42, G022 and G042 respectively;

[0372] The left-side reset control signal generating circuit includes a first-level left-side reset control signal generating unit R11, a second-level left-side reset control signal generating unit R12, a third-level left-side reset control signal generating unit R13, a fourth-level left-side reset control signal generating unit R14, an N-3th-level left-side reset control signal generating unit R011, an N-2th-level left-side reset control signal generating unit R012, and an N-1th-level left-side reset control signal generating unit R013. 013. The left reset control signal generating circuit includes an N-th level left reset control signal generating unit R014 which is electrically connected to the first row reset control line R1, the second row reset control line R2, the third row reset control line R3, the fourth row reset control line R4, the N-3rd row reset control line R01, the N-2nd row reset control line R02, the N-1st row reset control line R03 and the N-row reset control line R04, respectively, and is used to provide corresponding reset control signals to the first row reset control line R1, the second row reset control line R2, the third row reset control line R3, the fourth row reset control line R4, the N-3rd row reset control line R01, the N-2nd row reset control line R02, the N-1st row reset control line R03 and the N-row reset control line R04, respectively;

[0373] The right reset control signal generating circuit includes a first-level right reset control signal generating unit R21, a second-level right reset control signal generating unit R22, a third-level right reset control signal generating unit R23, a fourth-level right reset control signal generating unit R24, an N-3-th right reset control signal generating unit R021, an N-2-th right reset control signal generating unit R022, and an N-1-th right reset control signal generating unit R023. 023. The right reset control signal generating circuit includes an N-th level right reset control signal generating unit R024 which is electrically connected to the first row reset control line R1, the second row reset control line R2, the third row reset control line R3, the fourth row reset control line R4, the N-3rd row reset control line R01, the N-2nd row reset control line R02, the N-1st row reset control line R03 and the N-row reset control line R04, respectively, and is used to provide corresponding reset control signals to the first row reset control line R1, the second row reset control line R2, the third row reset control line R3, the fourth row reset control line R4, the N-3rd row reset control line R01, the N-2nd row reset control line R02, the N-1st row reset control line R03 and the N-row reset control line R04, respectively;

[0374] The left-side light-emitting control signal generating circuit includes a first-level left-side light-emitting control signal generating unit E11 electrically connected to the first-row light-emitting control line E1 and the second-row light-emitting control line E2, the left-side light-emitting control signal generating circuit includes a second-level left-side light-emitting control signal generating unit E12 electrically connected to the third-row light-emitting control line E3 and the fourth-row light-emitting control line E4, the left-side light-emitting control signal generating circuit includes an N-1th-level left-side light-emitting control signal generating unit E011 electrically connected to the N-3th-row light-emitting control line E01 and the N-2th-row light-emitting control line E02, and the left-side light-emitting control signal generating circuit includes an N-level left-side light-emitting control signal generating unit E012 electrically connected to the N-1th-row light-emitting control line E03 and the N-row light-emitting control line E04; E11 provides light-emitting control signals for E1 and E2, E12 provides light-emitting control signals for E3 and E4, E011 provides light-emitting control signals for E01 and E02, and E012 provides light-emitting control signals for E03 and E04;

[0375] The right side light emitting control signal generating circuit includes a first-level right side light emitting control signal generating unit E21 which is electrically connected to the first row light emitting control line E1 and the second row light emitting control line E2; the right side light emitting control signal generating circuit includes a second-level right side light emitting control signal generating unit E22 which is electrically connected to the third row light emitting control line E3 and the fourth row light emitting control line E4; the right side light emitting control signal generating circuit includes an N-1th level right side light emitting control signal generating unit E021 which is electrically connected to the N-3th row light emitting control line E01 and the N-2th row light emitting control line E02, and the right side light emitting control signal generating circuit includes an N-1th level right side light emitting control signal generating unit E022 which is electrically connected to the N-1th row light emitting control line E03 and the Nth row light emitting control line E04; E21 provides light emitting control signals for E1 and E2, E22 provides light emitting control signals for E3 and E4, E021 provides light emitting control signals for E01 and E02, and E022 provides light emitting control signals for E03 and E04;

[0376] like Fig.14 As shown, the multiplexing control line includes a first multiplexing control line M1, a second multiplexing control line M2, a first column gate control line S1 and a second column gate control line S2;

[0377] exist Fig.14 , the terminal labeled I1 is the first data writing terminal, the terminal labeled I2 is the second data writing terminal, the terminal labeled I01 is the P-1th data writing terminal, and the terminal labeled I02 is the Pth data writing terminal; P is an integer greater than 3;

[0378] exist Fig.14 In the figure, the transistor labeled T11 is the first multiplexing transistor of the first column, the transistor labeled T12 is the first multiplexing transistor of the second column; the transistor labeled T21 is the first multiplexing transistor of the first row, the transistor labeled T22 is the first multiplexing transistor of the second row, the transistor labeled T23 is the first multiplexing transistor of the third row, and the transistor labeled T24 is the first multiplexing transistor of the fourth row; the transistor labeled T31 is the second multiplexing transistor of the first column, and the transistor labeled T32 is the second multiplexing transistor of the second column; the transistor labeled T41 is the second multiplexing transistor of the first row, the transistor labeled T42 is the second multiplexing transistor of the second row, the transistor labeled T43 is the second multiplexing transistor of the third row, and the transistor labeled T44 is the second multiplexing transistor of the fourth row;

[0379] exist Fig.14, the transistor labeled T011 is the P-1th first column multiplexing transistor, the transistor labeled T012 is the P-1th second column multiplexing transistor; the transistor labeled T021 is the P-1th first row multiplexing transistor, the transistor labeled T022 is the P-1th second row multiplexing transistor, the transistor labeled T023 is the P-1th third row multiplexing transistor, and the transistor labeled T024 is the P-1th fourth row multiplexing transistor; the transistor labeled T031 is the Pth first column multiplexing transistor, the transistor labeled T032 is the Pth second column multiplexing transistor; the transistor labeled T041 is the Pth first row multiplexing transistor, the transistor labeled T042 is the Pth second row multiplexing transistor, the transistor labeled T043 is the Pth third row multiplexing transistor, and the transistor labeled T044 is the Pth fourth row multiplexing transistor;

[0380] The left light emitting control signal generating circuit and the right light emitting control signal generating circuit are connected to the first light emitting control clock signal and the second light emitting control clock signal;

[0381] The left reset control signal generating circuit and the right reset control signal generating circuit are connected to the first reset control clock signal and the second reset control clock signal;

[0382] The first left gate driving circuit and the first right gate driving circuit are connected to the first clock signal and the second clock signal;

[0383] The second left gate driving circuit and the second right gate driving circuit are connected to the third clock signal and the fourth clock signal;

[0384] The third left gate driving circuit and the third right gate driving circuit are connected to the fifth clock signal and the sixth clock signal;

[0385] The fourth left-side gate driving circuit and the fourth right-side gate driving circuit are connected to the seventh clock signal and the eighth clock signal.

[0386] like Fig.14 As shown, the first left gate driving circuit, the second left gate driving circuit, the third left gate driving circuit, the fourth left gate driving circuit, the left reset control signal generating circuit and the left light emission control signal generating circuit are arranged on the left side of the display panel;

[0387] The first right side gate driving circuit, the second right side gate driving circuit, the third right side gate driving circuit, the fourth right side gate driving circuit, the right side reset control signal generating circuit, and the right side light emitting control signal generating circuit are arranged on the right side of the display panel.

[0388] like Fig.15 As shown, in Fig.10Based on at least one embodiment of the display panel shown, the display device according to at least one embodiment of the present invention further includes a first left gate driving circuit 101, a second left gate driving circuit 102, a third left gate driving circuit 103 and a fourth left gate driving circuit 104, a left reset control signal generating circuit 110 and a left light emission control signal generating circuit 120;

[0389] The first left gate driving circuit 101 is electrically connected to G11 and G31 respectively, and is used to provide corresponding gate driving signals to G11 and G31 respectively;

[0390] The second left gate driving circuit 102 is electrically connected to G12 and G32 respectively, and is used to provide corresponding gate driving signals to G12 and G32 respectively;

[0391] The third left gate driving circuit 103 is electrically connected to G21 and G41 respectively, and is used to provide corresponding gate driving signals to G21 and G41 respectively;

[0392] The fourth left gate driving circuit 104 is electrically connected to G22 and G42 respectively, and is used to provide corresponding gate driving signals to G22 and G42 respectively;

[0393] The left reset control signal generating circuit 110 is electrically connected to the first row reset control line R1, the second row reset control line R2, the third row reset control line R3 and the fourth row reset control line R4, respectively, for providing corresponding reset control signals to the first row reset control line R1, the second row reset control line R2, the third row reset control line R3 and the fourth row reset control line R4;

[0394] The left-side light-emitting control signal generating circuit 120 is electrically connected to the first row of light-emitting control lines E1, the second row of light-emitting control lines E2, the third row of light-emitting control lines E3 and the fourth row of light-emitting control lines E4, respectively, and is used to provide corresponding light-emitting control signals to the first row of light-emitting control lines E1, the second row of light-emitting control lines E2, the third row of light-emitting control lines E3 and the fourth row of light-emitting control lines E4, respectively.

[0395] Fig.16 is based on Fig.15 In the specific implementation, such as Fig.16 As shown, a gate driving circuit, a reset control signal generating circuit and a light emitting control signal generating circuit may be respectively arranged on the left and right sides of the pixel circuit.

[0396] like Fig.16 As shown, the display panel includes a plurality of rows and columns of pixel circuits P0;

[0397] The first row of pixel circuits is electrically connected to the first row of gate lines G11 and the second row of gate lines G12;

[0398] The second row of pixel circuits is electrically connected to the third row of gate lines G21 and the fourth row of gate lines G22;

[0399] The third row of pixel circuits is electrically connected to the fifth row of gate lines G31 and the sixth row of gate lines G32;

[0400] The fourth row of pixel circuits is electrically connected to the seventh row of gate line G41 and the eighth row of gate line G42;

[0401] The pixel circuit of the N-3th row is electrically connected to the gate line G011 of the 2N-7th row and the gate line G012 of the 2N-6th row;

[0402] The pixel circuit of the N-2th row is electrically connected to the gate line G021 of the 2N-5th row and the gate line G022 of the 2N-4th row;

[0403] The pixel circuit of the N-1th row is electrically connected to the gate line G031 of the 2N-3th row and the gate line G032 of the 2N-2th row;

[0404] The pixel circuit of the Nth row is electrically connected to the gate line G041 of the 2N-1th row and the gate line G042 of the 2Nth row.

[0405] The first column pixel circuit is electrically connected to the first column data line D11 and the second column data line D12;

[0406] The second column pixel circuit is electrically connected to the third column data line D21 and the fourth column data line D22;

[0407] The third column pixel circuit is electrically connected to the fifth column data line D31 and the sixth column data line D32;

[0408] The fourth column pixel circuit is electrically connected to the seventh column data line D41 and the eighth column data line D42;

[0409] The pixel circuit in the M-3 column is electrically connected to the data line D011 in the 2M-7 column and the data line D012 in the 2M-6 column;

[0410] The pixel circuit in the M-2 column is electrically connected to the data line D021 in the 2M-5 column and the data line D022 in the 2M-4 column;

[0411] The pixel circuit in the M-1th column is electrically connected to the data line D031 in the 2M-3th column and the data line D032 in the 2M-2nd column;

[0412] The pixel circuit in the Mth column is electrically connected to the data line D041 in the 2M-1th column and the data line D042 in the 2Mth column;

[0413] The first row of pixel circuits are electrically connected to the first row of reset control lines R1 and the first row of light emitting control lines E1 respectively;

[0414] The second row of pixel circuits are electrically connected to the second row of reset control lines R2 and the second row of light emitting control lines E2 respectively;

[0415] The third row of pixel circuits are electrically connected to the third row of reset control lines R3 and the third row of light emitting control lines E3 respectively;

[0416] The fourth row of pixel circuits are electrically connected to the fourth row of reset control lines R4 and the fourth row of light emitting control lines E4 respectively;

[0417] The pixel circuits in the N-3rd row are electrically connected to the reset control line R01 in the N-3rd row and the light emission control line E01 in the N-3rd row respectively;

[0418] The pixel circuits in the N-2th row are electrically connected to the reset control line R02 in the N-2th row and the light emission control line E02 in the N-2th row respectively;

[0419] The pixel circuits in the N-1th row are electrically connected to the reset control line R03 in the N-1th row and the light emission control line E03 in the N-1th row;

[0420] The pixel circuits in the Nth row are electrically connected to the reset control line R04 in the Nth row and the light emission control line E04 in the Nth row respectively;

[0421] The display device described in at least one embodiment of the present invention further includes a first left-side gate driving circuit, a second left-side gate driving circuit, a third left-side gate driving circuit, a fourth left-side gate driving circuit, a first right-side gate driving circuit, a second right-side gate driving circuit, a third right-side gate driving circuit, a fourth right-side gate driving circuit, a left-side reset control signal generating circuit, a right-side reset control signal generating circuit, a left-side light-emitting control signal generating circuit, and a right-side light-emitting control signal generating circuit;

[0422] A first-stage left-side shift register unit L11 included in the first left-side gate driving circuit, a second-stage left-side shift register unit L12 included in the first left-side gate driving circuit, a third-stage left-side shift register unit L13 included in the first left-side gate driving circuit, and a fourth-stage left-side shift register unit L14 included in the first left-side gate driving circuit are electrically connected to G11, G31, G011, and G031, respectively, and are used to provide corresponding gate driving signals to G11, G31, G011, and G031, respectively;

[0423] A first-stage right-side shift register unit L21 included in the first right-side gate driving circuit, a second-stage right-side shift register unit L22 included in the first right-side gate driving circuit, a third-stage right-side shift register unit L23 included in the first right-side gate driving circuit, and a fourth-stage right-side shift register unit L24 included in the first right-side gate driving circuit are electrically connected to G11, G31, G011, and G031, respectively, and are used to provide corresponding gate driving signals to G11, G31, G011, and G031, respectively;

[0424] A first-stage left-side shift register unit L31 included in the second left-side gate driving circuit, a second-stage left-side shift register unit L32 included in the second left-side gate driving circuit, a third-stage left-side shift register unit L33 included in the second left-side gate driving circuit, and a fourth-stage left-side shift register unit L34 included in the second left-side gate driving circuit are electrically connected to G12, G32, G012, and G032, respectively, and are used to provide corresponding gate driving signals to G12, G32, G012, and G032, respectively;

[0425] The first-stage right shift register unit L41 included in the second right gate driving circuit, the second-stage right shift register unit L42 included in the second right gate driving circuit, the third-stage right shift register unit L43 included in the second right gate driving circuit, and the fourth-stage right shift register unit L44 included in the second right gate driving circuit are electrically connected to G12, G32, G012 and G032 respectively, and are used to provide corresponding gate driving signals to G12, G32, G012 and G032 respectively;

[0426] A first-stage left-side shift register unit L51 included in the third left-side gate driving circuit, a second-stage left-side shift register unit L52 included in the third left-side gate driving circuit, a third-stage left-side shift register unit L53 included in the third left-side gate driving circuit, and a fourth-stage left-side shift register unit L54 included in the third left-side gate driving circuit are electrically connected to G21, G41, G021, and G041, respectively, and are used to provide corresponding gate driving signals to G21, G41, G021, and G041, respectively;

[0427] A first-stage right-side shift register unit L61 included in the third right-side gate driving circuit, a second-stage right-side shift register unit L62 included in the third right-side gate driving circuit, a third-stage right-side shift register unit L63 included in the third right-side gate driving circuit, and a fourth-stage right-side shift register unit L64 included in the third right-side gate driving circuit are electrically connected to G21, G41, G021, and G041, respectively, for providing corresponding gate driving signals to G21, G41, G021, and G041, respectively;

[0428] A first-stage left-side shift register unit L71 included in the fourth left-side gate driving circuit, a second-stage left-side shift register unit L72 included in the fourth left-side gate driving circuit, a third-stage left-side shift register unit L73 included in the fourth left-side gate driving circuit, and a fourth-stage left-side shift register unit L74 included in the fourth left-side gate driving circuit are electrically connected to G22, G42, G022, and G042, respectively, and are used to provide corresponding gate driving signals to G22, G42, G022, and G042, respectively;

[0429] The first-stage right shift register unit L81 included in the fourth right gate driving circuit, the second-stage right shift register unit L82 included in the fourth right gate driving circuit, the third-stage right shift register unit L83 included in the fourth right gate driving circuit, and the fourth-stage right shift register unit L84 included in the fourth right gate driving circuit are electrically connected to G22, G42, G022 and G042 respectively, and are used to provide corresponding gate driving signals to G22, G42, G022 and G042 respectively;

[0430] The left-side reset control signal generating circuit includes a first-level left-side reset control signal generating unit R11, a second-level left-side reset control signal generating unit R12, a third-level left-side reset control signal generating unit R13, a fourth-level left-side reset control signal generating unit R14, an N-3th-level left-side reset control signal generating unit R011, an N-2th-level left-side reset control signal generating unit R012, and an N-1th-level left-side reset control signal generating unit R013. 013. The left reset control signal generating circuit includes an N-th level left reset control signal generating unit R014 which is electrically connected to the first row reset control line R1, the second row reset control line R2, the third row reset control line R3, the fourth row reset control line R4, the N-3rd row reset control line R01, the N-2nd row reset control line R02, the N-1st row reset control line R03 and the N-row reset control line R04, respectively, and is used to provide corresponding reset control signals to the first row reset control line R1, the second row reset control line R2, the third row reset control line R3, the fourth row reset control line R4, the N-3rd row reset control line R01, the N-2nd row reset control line R02, the N-1st row reset control line R03 and the N-row reset control line R04, respectively;

[0431] The right reset control signal generating circuit includes a first-level right reset control signal generating unit R21, a second-level right reset control signal generating unit R22, a third-level right reset control signal generating unit R23, a fourth-level right reset control signal generating unit R24, an N-3-th right reset control signal generating unit R021, an N-2-th right reset control signal generating unit R022, and an N-1-th right reset control signal generating unit R023. 023. The right reset control signal generating circuit includes an N-th level right reset control signal generating unit R024 which is electrically connected to the first row reset control line R1, the second row reset control line R2, the third row reset control line R3, the fourth row reset control line R4, the N-3rd row reset control line R01, the N-2nd row reset control line R02, the N-1st row reset control line R03 and the N-row reset control line R04, respectively, and is used to provide corresponding reset control signals to the first row reset control line R1, the second row reset control line R2, the third row reset control line R3, the fourth row reset control line R4, the N-3rd row reset control line R01, the N-2nd row reset control line R02, the N-1st row reset control line R03 and the N-row reset control line R04, respectively;

[0432] The left-side light emitting control signal generating circuit includes a first-level left-side light emitting control signal generating unit E11, a second-level left-side light emitting control signal generating unit E12, a third-level left-side light emitting control signal generating unit E13, a fourth-level left-side light emitting control signal generating unit E14, an N-3th-level left-side light emitting control signal generating unit E011, an N-2th-level left-side light emitting control signal generating unit E012, and an N-1th-level left-side light emitting control signal generating unit E15. 013. The left-side light-emitting control signal generating circuit includes an N-th level left-side light-emitting control signal generating unit E014 which is electrically connected to the first-row light-emitting control line E1, the second-row light-emitting control line E2, the third-row light-emitting control line E3, the fourth-row light-emitting control line E4, the N-3-th-row light-emitting control line E01, the N-2-th-row light-emitting control line E02, the N-1-th-row light-emitting control line E03 and the N-th-row light-emitting control line E04, respectively, and is used to provide corresponding light-emitting control signals to the first-row light-emitting control line E1, the second-row light-emitting control line E2, the third-row light-emitting control line E3, the fourth-row light-emitting control line E4, the N-3-th-row light-emitting control line E01, the N-2-th-row light-emitting control line E02, the N-1-th-row light-emitting control line E03 and the N-th-row light-emitting control line E04, respectively;

[0433] The right side light emitting control signal generating circuit includes a first level right side light emitting control signal generating unit E21, a second level right side light emitting control signal generating unit E22, a third level right side light emitting control signal generating unit E23, a fourth level right side light emitting control signal generating unit E24, an N-3 level right side light emitting control signal generating unit E021, an N-2 level right side light emitting control signal generating unit E022, and an N-1 level right side light emitting control signal generating unit E023. 023. The right-side light-emitting control signal generating circuit includes an N-th right-side light-emitting control signal generating unit E024 which is electrically connected to the first-row light-emitting control line E1, the second-row light-emitting control line E2, the third-row light-emitting control line E3, the fourth-row light-emitting control line E4, the N-3-th-row light-emitting control line E01, the N-2-th-row light-emitting control line E02, the N-1-th-row light-emitting control line E03 and the N-th-row light-emitting control line E04, respectively, and is used to provide corresponding light-emitting control signals to the first-row light-emitting control line E1, the second-row light-emitting control line E2, the third-row light-emitting control line E3, the fourth-row light-emitting control line E4, the N-3-th-row light-emitting control line E01, the N-2-th-row light-emitting control line E02, the N-1-th-row light-emitting control line E03 and the N-th-row light-emitting control line E04, respectively;

[0434] like Fig.16 As shown, the multiplexing control line includes a first multiplexing control line M1, a second multiplexing control line M2, a third reset control line M3 and a fourth reset control line M4;

[0435] exist Fig.16 , the terminal labeled I1 is the first data writing terminal, the terminal labeled I2 is the second data writing terminal, the terminal labeled I01 is the P-1th data writing terminal, and the terminal labeled I02 is the Pth data writing terminal; P is an integer greater than 3;

[0436] exist Fig.16 , the first multiplexing transistor labeled T71 is the first multiplexing transistor, the first multiplexing transistor labeled T72 is the first multiplexing transistor, the first multiplexing transistor labeled T73 is the first multiplexing transistor, and the first multiplexing transistor labeled T74 is the first multiplexing transistor; the second multiplexing transistor labeled T81 is the second multiplexing transistor, the second multiplexing transistor labeled T82 is the second multiplexing transistor, the second multiplexing transistor labeled T83 is the second multiplexing transistor, and the second multiplexing transistor labeled T84 is the second multiplexing transistor;

[0437] exist Fig.16, the P-1th first multiplexing transistor is labeled T071, the P-1th second multiplexing transistor is labeled T072, the P-1th third multiplexing transistor is labeled T073, and the P-1th fourth multiplexing transistor is labeled T074; the P-1th first multiplexing transistor is labeled T081, the P-th second multiplexing transistor is labeled T082, the P-th third multiplexing transistor is labeled T083, and the P-th fourth multiplexing transistor is labeled T084;

[0438] Furthermore, the left light emitting control signal generating circuit and the right light emitting control signal generating circuit are connected to the first light emitting control clock signal and the second light emitting control clock signal;

[0439] The left reset control signal generating circuit and the right reset control signal generating circuit are connected to the first reset control clock signal and the second reset control clock signal;

[0440] The first left gate driving circuit and the first right gate driving circuit are connected to the first clock signal and the second clock signal;

[0441] The second left gate driving circuit and the second right gate driving circuit are connected to the third clock signal and the fourth clock signal;

[0442] The third left gate driving circuit and the third right gate driving circuit are connected to the fifth clock signal and the sixth clock signal;

[0443] The fourth left-side gate driving circuit and the fourth right-side gate driving circuit are connected to the seventh clock signal and the eighth clock signal.

[0444] like Fig.16 As shown, the first left gate driving circuit, the second left gate driving circuit, the third left gate driving circuit, the fourth left gate driving circuit, the left reset control signal generating circuit and the left light emission control signal generating circuit are arranged on the left side of the display panel;

[0445] The first right side gate driving circuit, the second right side gate driving circuit, the third right side gate driving circuit, the fourth right side gate driving circuit, the right side reset control signal generating circuit and the right side light emitting control signal generating circuit are arranged on the right side of the display panel.

[0446] Fig.17 is based on Fig.15 The overall structure diagram of the Fig.17 As shown, a gate driving circuit, a reset control signal generating circuit and a light emitting control signal generating circuit may be respectively arranged on the left and right sides of the pixel circuit.

[0447] like Fig.17 As shown, the display panel includes a plurality of rows and columns of pixel circuits P0;

[0448] The first row of pixel circuits is electrically connected to the first row of gate lines G11 and the second row of gate lines G12;

[0449] The second row of pixel circuits is electrically connected to the third row of gate lines G21 and the fourth row of gate lines G22;

[0450] The third row of pixel circuits is electrically connected to the fifth row of gate lines G31 and the sixth row of gate lines G32;

[0451] The fourth row of pixel circuits is electrically connected to the seventh row of gate line G41 and the eighth row of gate line G42;

[0452] The pixel circuit of the N-3th row is electrically connected to the gate line G011 of the 2N-7th row and the gate line G012 of the 2N-6th row;

[0453] The pixel circuit of the N-2th row is electrically connected to the gate line G021 of the 2N-5th row and the gate line G022 of the 2N-4th row;

[0454] The pixel circuit of the N-1th row is electrically connected to the gate line G031 of the 2N-3th row and the gate line G032 of the 2N-2th row;

[0455] The pixel circuit of the Nth row is electrically connected to the gate line G041 of the 2N-1th row and the gate line G042 of the 2Nth row.

[0456] The first column pixel circuit is electrically connected to the first column data line D11 and the second column data line D12;

[0457] The second column pixel circuit is electrically connected to the third column data line D21 and the fourth column data line D22;

[0458] The third column pixel circuit is electrically connected to the fifth column data line D31 and the sixth column data line D32;

[0459] The fourth column pixel circuit is electrically connected to the seventh column data line D41 and the eighth column data line D42;

[0460] The pixel circuit in the M-3 column is electrically connected to the data line D011 in the 2M-7 column and the data line D012 in the 2M-6 column;

[0461] The pixel circuit in the M-2 column is electrically connected to the data line D021 in the 2M-5 column and the data line D022 in the 2M-4 column;

[0462] The pixel circuit in the M-1th column is electrically connected to the data line D031 in the 2M-3th column and the data line D032 in the 2M-2nd column;

[0463] The pixel circuit in the Mth column is electrically connected to the data line D041 in the 2M-1th column and the data line D042 in the 2Mth column;

[0464] The first row of pixel circuits are electrically connected to the first row of reset control lines R1 and the first row of light emitting control lines E1 respectively;

[0465] The second row of pixel circuits are electrically connected to the second row of reset control lines R2 and the second row of light emitting control lines E2 respectively;

[0466] The third row of pixel circuits are electrically connected to the third row of reset control lines R3 and the third row of light emitting control lines E3 respectively;

[0467] The fourth row of pixel circuits are electrically connected to the fourth row of reset control lines R4 and the fourth row of light emitting control lines E4 respectively;

[0468] The pixel circuits in the N-3rd row are electrically connected to the reset control line R01 in the N-3rd row and the light emission control line E01 in the N-3rd row respectively;

[0469] The pixel circuits in the N-2th row are electrically connected to the reset control line R02 in the N-2th row and the light emission control line E02 in the N-2th row respectively;

[0470] The pixel circuits in the N-1th row are electrically connected to the reset control line R03 in the N-1th row and the light emission control line E03 in the N-1th row;

[0471] The pixel circuits in the Nth row are electrically connected to the reset control line R04 in the Nth row and the light emission control line E04 in the Nth row respectively;

[0472] The display device described in at least one embodiment of the present invention further includes a first left-side gate driving circuit, a second left-side gate driving circuit, a third left-side gate driving circuit, a fourth left-side gate driving circuit, a first right-side gate driving circuit, a second right-side gate driving circuit, a third right-side gate driving circuit, a fourth right-side gate driving circuit, a left-side reset control signal generating circuit, a right-side reset control signal generating circuit, a left-side light-emitting control signal generating circuit, and a right-side light-emitting control signal generating circuit;

[0473] A first-stage left-side shift register unit L11 included in the first left-side gate driving circuit, a second-stage left-side shift register unit L12 included in the first left-side gate driving circuit, a third-stage left-side shift register unit L13 included in the first left-side gate driving circuit, and a fourth-stage left-side shift register unit L14 included in the first left-side gate driving circuit are electrically connected to G11, G31, G011, and G031, respectively, and are used to provide corresponding gate driving signals to G11, G31, G011, and G031, respectively;

[0474] A first-stage right-side shift register unit L21 included in the first right-side gate driving circuit, a second-stage right-side shift register unit L22 included in the first right-side gate driving circuit, a third-stage right-side shift register unit L23 included in the first right-side gate driving circuit, and a fourth-stage right-side shift register unit L24 included in the first right-side gate driving circuit are electrically connected to G11, G31, G011, and G031, respectively, and are used to provide corresponding gate driving signals to G11, G31, G011, and G031, respectively;

[0475] A first-stage left-side shift register unit L31 included in the second left-side gate driving circuit, a second-stage left-side shift register unit L32 included in the second left-side gate driving circuit, a third-stage left-side shift register unit L33 included in the second left-side gate driving circuit, and a fourth-stage left-side shift register unit L34 included in the second left-side gate driving circuit are electrically connected to G12, G32, G012, and G032, respectively, and are used to provide corresponding gate driving signals to G12, G32, G012, and G032, respectively;

[0476] The first-stage right shift register unit L41 included in the second right gate driving circuit, the second-stage right shift register unit L42 included in the second right gate driving circuit, the third-stage right shift register unit L43 included in the second right gate driving circuit, and the fourth-stage right shift register unit L44 included in the second right gate driving circuit are electrically connected to G12, G32, G012 and G032 respectively, and are used to provide corresponding gate driving signals to G12, G32, G012 and G032 respectively;

[0477] A first-stage left-side shift register unit L51 included in the third left-side gate driving circuit, a second-stage left-side shift register unit L52 included in the third left-side gate driving circuit, a third-stage left-side shift register unit L53 included in the third left-side gate driving circuit, and a fourth-stage left-side shift register unit L54 included in the third left-side gate driving circuit are electrically connected to G21, G41, G021, and G041, respectively, and are used to provide corresponding gate driving signals to G21, G41, G021, and G041, respectively;

[0478] A first-stage right-side shift register unit L61 included in the third right-side gate driving circuit, a second-stage right-side shift register unit L62 included in the third right-side gate driving circuit, a third-stage right-side shift register unit L63 included in the third right-side gate driving circuit, and a fourth-stage right-side shift register unit L64 included in the third right-side gate driving circuit are electrically connected to G21, G41, G021, and G041, respectively, for providing corresponding gate driving signals to G21, G41, G021, and G041, respectively;

[0479] A first-stage left-side shift register unit L71 included in the fourth left-side gate driving circuit, a second-stage left-side shift register unit L72 included in the fourth left-side gate driving circuit, a third-stage left-side shift register unit L73 included in the fourth left-side gate driving circuit, and a fourth-stage left-side shift register unit L74 included in the fourth left-side gate driving circuit are electrically connected to G22, G42, G022, and G042, respectively, and are used to provide corresponding gate driving signals to G22, G42, G022, and G042, respectively;

[0480] The first-stage right shift register unit L81 included in the fourth right gate driving circuit, the second-stage right shift register unit L82 included in the fourth right gate driving circuit, the third-stage right shift register unit L83 included in the fourth right gate driving circuit, and the fourth-stage right shift register unit L84 included in the fourth right gate driving circuit are electrically connected to G22, G42, G022 and G042 respectively, and are used to provide corresponding gate driving signals to G22, G42, G022 and G042 respectively;

[0481] The left-side reset control signal generating circuit includes a first-level left-side reset control signal generating unit R11, a second-level left-side reset control signal generating unit R12, a third-level left-side reset control signal generating unit R13, a fourth-level left-side reset control signal generating unit R14, an N-3th-level left-side reset control signal generating unit R011, an N-2th-level left-side reset control signal generating unit R012, and an N-1th-level left-side reset control signal generating unit R013. 013. The left reset control signal generating circuit includes an N-th level left reset control signal generating unit R014 which is electrically connected to the first row reset control line R1, the second row reset control line R2, the third row reset control line R3, the fourth row reset control line R4, the N-3rd row reset control line R01, the N-2nd row reset control line R02, the N-1st row reset control line R03 and the N-row reset control line R04, respectively, and is used to provide corresponding reset control signals to the first row reset control line R1, the second row reset control line R2, the third row reset control line R3, the fourth row reset control line R4, the N-3rd row reset control line R01, the N-2nd row reset control line R02, the N-1st row reset control line R03 and the N-row reset control line R04, respectively;

[0482] The right reset control signal generating circuit includes a first-level right reset control signal generating unit R21, a second-level right reset control signal generating unit R22, a third-level right reset control signal generating unit R23, a fourth-level right reset control signal generating unit R24, an N-3-th right reset control signal generating unit R021, an N-2-th right reset control signal generating unit R022, and an N-1-th right reset control signal generating unit R023. 023. The right reset control signal generating circuit includes an N-th level right reset control signal generating unit R024 which is electrically connected to the first row reset control line R1, the second row reset control line R2, the third row reset control line R3, the fourth row reset control line R4, the N-3rd row reset control line R01, the N-2nd row reset control line R02, the N-1st row reset control line R03 and the N-row reset control line R04, respectively, and is used to provide corresponding reset control signals to the first row reset control line R1, the second row reset control line R2, the third row reset control line R3, the fourth row reset control line R4, the N-3rd row reset control line R01, the N-2nd row reset control line R02, the N-1st row reset control line R03 and the N-row reset control line R04, respectively;

[0483] The left-side light-emitting control signal generating circuit includes a first-level left-side light-emitting control signal generating unit E11 electrically connected to the first-row light-emitting control line E1 and the second-row light-emitting control line E2, the left-side light-emitting control signal generating circuit includes a second-level left-side light-emitting control signal generating unit E12 electrically connected to the third-row light-emitting control line E3 and the fourth-row light-emitting control line E4, the left-side light-emitting control signal generating circuit includes an N-3-level left-side light-emitting control signal generating unit E011 electrically connected to the N-3-row light-emitting control line E01 and the N-2-row light-emitting control line E02, and the left-side light-emitting control signal generating circuit includes an N-2-level left-side light-emitting control signal generating unit E012 electrically connected to the N-1-row light-emitting control line E03 and the N-row light-emitting control line E04; E11 provides light-emitting control signals for E1 and E2, E12 provides light-emitting control signals for E3 and E4, E011 provides light-emitting control signals for E01 and E02, and E012 provides light-emitting control signals for E03 and E04;

[0484] The right side light emitting control signal generating circuit includes a first-level right side light emitting control signal generating unit E21 which is electrically connected to the first row light emitting control line E1 and the second row light emitting control line E2; the right side light emitting control signal generating circuit includes a second-level right side light emitting control signal generating unit E22 which is electrically connected to the third row light emitting control line E3 and the fourth row light emitting control line E4; the right side light emitting control signal generating circuit includes an N-1th level right side light emitting control signal generating unit E021 which is electrically connected to the N-3th row light emitting control line E01 and the N-2th row light emitting control line E02, and the right side light emitting control signal generating circuit includes an N-1th level right side light emitting control signal generating unit E022 which is electrically connected to the N-1th row light emitting control line E03 and the Nth row light emitting control line E04; E21 provides light emitting control signals for E1 and E2, E22 provides light emitting control signals for E3 and E4, E021 provides light emitting control signals for E01 and E02, and E022 provides light emitting control signals for E03 and E04;

[0485] like Fig.17 As shown, the multiplexing control line includes a first multiplexing control line M1, a second multiplexing control line M2, a third reset control line M3 and a fourth reset control line M4;

[0486] exist Fig.17 , the terminal labeled I1 is the first data writing terminal, the terminal labeled I2 is the second data writing terminal, the terminal labeled I01 is the P-1th data writing terminal, and the terminal labeled I02 is the Pth data writing terminal; P is an integer greater than 3;

[0487] exist Fig.17 , the first multiplexing transistor labeled T71 is the first multiplexing transistor, the first multiplexing transistor labeled T72 is the first multiplexing transistor, the first multiplexing transistor labeled T73 is the first multiplexing transistor, and the first multiplexing transistor labeled T74 is the first multiplexing transistor; the second multiplexing transistor labeled T81 is the second multiplexing transistor, the second multiplexing transistor labeled T82 is the second multiplexing transistor, the second multiplexing transistor labeled T83 is the second multiplexing transistor, and the second multiplexing transistor labeled T84 is the second multiplexing transistor;

[0488] exist Fig.17 , the P-1th first multiplexing transistor is labeled T071, the P-1th second multiplexing transistor is labeled T072, the P-1th third multiplexing transistor is labeled T073, and the P-1th fourth multiplexing transistor is labeled T074; the P-1th first multiplexing transistor is labeled T081, the P-th second multiplexing transistor is labeled T082, the P-th third multiplexing transistor is labeled T083, and the P-th fourth multiplexing transistor is labeled T084;

[0489] Furthermore, the left light emitting control signal generating circuit and the right light emitting control signal generating circuit are connected to the first light emitting control clock signal and the second light emitting control clock signal;

[0490] The left reset control signal generating circuit and the right reset control signal generating circuit are connected to the first reset control clock signal and the second reset control clock signal;

[0491] The first left gate driving circuit and the first right gate driving circuit are connected to the first clock signal and the second clock signal;

[0492] The second left gate driving circuit and the second right gate driving circuit are connected to the third clock signal and the fourth clock signal;

[0493] The third left gate driving circuit and the third right gate driving circuit are connected to the fifth clock signal and the sixth clock signal;

[0494] The fourth left-side gate driving circuit and the fourth right-side gate driving circuit are connected to the seventh clock signal and the eighth clock signal.

[0495] like Fig.17 As shown, the first left gate driving circuit, the second left gate driving circuit, the third left gate driving circuit, the fourth left gate driving circuit, the left reset control signal generating circuit and the left light emission control signal generating circuit are arranged on the left side of the display panel;

[0496] The first right side gate driving circuit, the second right side gate driving circuit, the third right side gate driving circuit, the fourth right side gate driving circuit, the right side reset control signal generating circuit and the right side light emitting control signal generating circuit are arranged on the right side of the display panel.

[0497] A display panel driving method according to at least one embodiment of the present invention is applied to the above-mentioned display panel, and the display panel driving method includes:

[0498] The reset control line of the same row provides a reset control signal for the pixel circuits of the same row;

[0499] One of the two rows of gate lines corresponding to the same row of pixel circuits provides corresponding gate drive signals for odd-numbered pixel circuits in the same row of pixel circuits, and the other of the two rows of gate lines provides corresponding gate drive signals for even-numbered pixel circuits in the same row of pixel circuits;

[0500] One of the two data lines corresponding to the same column of pixel circuits provides corresponding data voltages for odd-numbered pixel circuits in the same column of pixel circuits, and the other of the two data lines provides corresponding data voltages for even-numbered pixel circuits in the same column of pixel circuits;

[0501] The gate driving signal on the row gate line is delayed by H / 2 compared with the row gate driving signal on the adjacent previous row gate line, where H is the row period.

[0502] In the driving method of the display panel described in at least one embodiment of the present invention, gate driving signals are respectively provided to the odd and even column pixel circuits in the same row through two rows of gate lines, and gate driving signals are respectively provided to the odd and even row pixel circuits in the same column through two columns of data lines, so that the compensation time reaches twice the row period, which can have sufficient time to compensate the threshold voltage of the driving transistor in the pixel circuit, thereby ensuring the display effect and achieving a higher data refresh speed.

[0503] In at least one embodiment of the present invention, since a multiplexing circuit is used to provide data voltages for data lines in a time-sharing manner, and a row of pixel circuits corresponds to two rows of gate lines, and a column of pixel circuits corresponds to two columns of data lines, in order to provide corresponding data voltages to odd-row odd-column pixel circuits, odd-row even-column pixel circuits, even-row odd-column pixel circuits, and even-row even-column pixel circuits, respectively, the gate drive signals on adjacent rows of gate lines need to be set to be spaced H / 2 apart from each other.

[0504] Optionally, the display panel further includes a plurality of rows of light emitting control lines; and the method for driving the display panel further includes:

[0505] The light emitting control lines in the same row provide light emitting control signals for the pixel circuits in the same row.

[0506] Optionally, the nth row display phase includes an nth reset time period, an nth data writing time period and an nth light emitting control time period which are sequentially arranged; n is a positive integer;

[0507] In the nth reset time period, the nth row reset control signal line provides a valid nth row reset control signal;

[0508] In the 2n-1th row writing time period included in the nth data writing time period, the 2n-1th row gate line provides a valid gate driving signal;

[0509] In the 2nth row writing time period included in the nth data writing time period, the 2nth row gate line provides a valid gate driving signal;

[0510] In the nth light emitting control period, the nth row of light emitting control signal lines provides a valid gate driving signal;

[0511] The 2nth row writing period is delayed by H / 2 from the 2n-1th row writing period.

[0512] In a specific implementation, the display panel further includes a plurality of multiplexing circuits; and the display panel driving method according to at least one embodiment of the present invention further includes:

[0513] The multiplexing circuit controls the data voltage provided by the data input terminal to be input to the four column data lines in a time-sharing manner under the control of the multiplexing control signal provided by the multiplexing control line.

[0514] In at least one embodiment of the present invention, a multiplexing circuit is used to provide data voltages to four columns of data lines through a data input terminal in a time-sharing manner, thereby reducing the number of channels of the data driver IC (Integrated Circuit) required and reducing the cost of the display panel.

[0515] According to a specific implementation, the multiplexing control line includes a first multiplexing control line, a second multiplexing control line, a first column gating control line and a second column gating control line; the p-th multiplexing circuit includes a p-th row multiplexing subcircuit and a p-th column multiplexing subcircuit; the data providing cycle includes a first data providing stage, a second data providing stage, a third data providing stage and a fourth data providing stage which are arranged in sequence; p is a positive integer;

[0516] The multiplexing circuit, under the control of the multiplexing control signal provided by the multiplexing control line, controls the data voltage provided by the data input terminal to be input to the four column data lines in a time-sharing manner, including:

[0517] In the first data providing stage and the third data providing stage, the p-th column multiplexing subcircuit controls the connection between the p-th data input terminal and the 2p-1-th write node to be turned on, and controls the connection between the p-th data input terminal and the 2p-1-th write node to be turned off, under the control of the first column enabling control signal provided by the first column enabling control line and the second column enabling control signal provided by the second column enabling control line;

[0518] In the second data providing stage and the fourth data providing stage, the p-th column multiplexing subcircuit controls, under the control of the first column selection control signal and the second column selection control signal, to disconnect the connection between the p-th data input terminal and the 2p-1th write node, and controls to connect the connection between the p-th data input terminal and the 2p-1th write node;

[0519] In the first data providing stage and the second data providing stage, the p-th row multiplexing subcircuit controls the connection between the 2p-1th write node and the 4p-3th column data line, and controls the connection between the 2p write node and the 4p column data line, under the control of the first multiplexing control signal provided by the first multiplexing control line and the second multiplexing control signal provided by the second multiplexing control line;

[0520] In the third data providing stage and the fourth data providing stage, the p-th row multiplexing sub-circuit controls the connection between the 2p-1th write node and the 4p-2th column data line, and controls the connection between the 2pth write node and the 4p-1th column data line under the control of the first multiplexing control signal and the second multiplexing control signal.

[0521] In a specific implementation, the multiplexing control line may include a first multiplexing control line, a second multiplexing control line, a first column selection control line and a second column selection control line; the pth multiplexing circuit includes a pth row multiplexing sub-circuit and a pth column multiplexing sub-circuit, the pth column multiplexing sub-circuit is used to control the connection between the pth data input terminal and the 2p-1th write node or the 2pth write node, the pth row multiplexing sub-circuit controls the connection between the 2p-1th write node and the 4p-3th column data line or the 4p-2th column data line, and controls the connection between the 2p write node and the 4p-1th column data line or the 4p column data line, so as to realize the time-sharing provision of the data voltage provided by the pth data input terminal to the 4p-3th column data line, the 4p-2th column data line, the 4p-1th column data line and the 4p column data line.

[0522] According to another specific implementation, the multiplexing control line includes a first multiplexing control line, a second multiplexing control line, a third multiplexing control line and a fourth multiplexing control line, the p-th multiplexing circuit includes a p-th first multiplexing sub-circuit, a p-th second multiplexing sub-circuit, a p-th third multiplexing sub-circuit and a p-th fourth multiplexing sub-circuit; the data providing cycle includes a first data providing stage, a second data providing stage, a third data providing stage and a fourth data providing stage which are arranged in sequence; p is a positive integer;

[0523] The multiplexing circuit, under the control of the multiplexing control signal provided by the multiplexing control line, controls the data voltage provided by the data input terminal to be input to the four column data lines in a time-sharing manner, including:

[0524] In the first data providing stage, the pth first multiplexing subcircuit, under the control of the first multiplexing control signal provided by the first multiplexing control line, turns on the connection between the pth data input terminal and the 4p-3th column data line;

[0525] In the second data providing stage, the pth fourth multiplexing subcircuit, under the control of the second multiplexing control signal provided by the second multiplexing control line, conducts the connection between the pth data input terminal and the 4pth column data line;

[0526] In the third data providing stage, the pth second multiplexing subcircuit, under the control of the third multiplexing control signal provided by the third multiplexing control line, conducts the connection between the pth data input terminal and the 4p-2th column data line;

[0527] In the fourth data providing stage, the pth third multiplexing sub-circuit, under the control of the fourth multiplexing control signal provided by the fourth multiplexing control line, turns on the connection between the pth data input terminal and the 4p-1th column data line.

[0528] In a specific implementation, the multiplexing control line may include a first multiplexing control line, a second multiplexing control line, a third multiplexing control line and a fourth multiplexing control line, the pth multiplexing circuit may include a pth first multiplexing sub-circuit, a pth second multiplexing sub-circuit, a pth third multiplexing sub-circuit and a pth fourth multiplexing sub-circuit, the pth first multiplexing sub-circuit, the pth second multiplexing sub-circuit, the pth third multiplexing sub-circuit and the pth fourth multiplexing sub-circuit control the pth data input terminal to provide data voltage to the 4p-3 column data line, the 4p-2 column data line, the 4p-1 column data line and the 4p column data line in a time-sharing manner.

[0529] A display device according to at least one embodiment of the present invention includes the above-mentioned display panel.

[0530] In a specific implementation, the display device described in at least one embodiment of the present invention further includes a first gate driving circuit, a second gate driving circuit, a third gate driving circuit and a fourth gate driving circuit;

[0531] The first gate driving circuit is used to provide a 4a-3 row gate driving signal for the 4a-3 row gate line;

[0532] The second gate driving circuit is used to provide a 4a-2 row gate driving signal for the 4a-2 row gate line;

[0533] The third gate driving circuit is used to provide the 4a-1th row gate driving signal for the 4a-1th row gate line;

[0534] The fourth gate driving circuit is used for providing a 4a row gate driving signal for the 4a row gate line;

[0535] a is a positive integer.

[0536] Optionally, the first gate driving circuit may include a multi-stage first shift register unit;

[0537] The gate drive signal output end of the a-th level first shift register unit is electrically connected to the 4a-3 row gate line, and the input end of the a+1-th level first shift register unit is electrically connected to the 4a-3 row gate line; the gate drive signal output end of the a+1-th level first shift register unit is electrically connected to the 4a+1 row gate line; the reset end of the a-th level first shift register unit is electrically connected to the 4a+1 row gate line.

[0538] like Fig.18As shown, the first gate driving circuit may include a B-level first shift register unit; Fig.18 , the unit labeled U11 is the first shift register unit of the first stage, the unit labeled U12 is the second first shift register unit, the unit labeled U13 is the third first shift register unit, the unit labeled U1a is the a-th first shift register unit, the unit labeled U1a+1 is the a+1-th first shift register unit, and the unit labeled U1B is the B-th first shift register unit, wherein a is a positive integer, and B is a positive integer greater than 5;

[0539] The input terminal of U11 is connected to the first start signal X1, the gate drive signal output terminal of U11 is electrically connected to the first row gate line G11, and the gate drive signal output terminal of U11 is electrically connected to the input terminal of U12; the reset terminal of U11 is electrically connected to the fifth row gate line G31;

[0540] The gate drive signal output terminal of U12 is electrically connected to the fifth row of gate line G31, and the gate drive signal output terminal of U12 is electrically connected to the input terminal of U13; the reset terminal of U12 is electrically connected to the ninth row of gate line G51;

[0541] The gate drive signal output terminal of U13 is electrically connected to the ninth row gate line G51, and the gate drive signal output terminal of U13 is electrically connected to the fourth stage first shift register unit ( Fig.18 The reset terminal of U13 is electrically connected to the thirteenth row gate line G71;

[0542] The gate drive signal output terminal of U1a is electrically connected to the gate line G(2a-1)1 of the 4a-3 row; the input terminal of U1a is electrically connected to the gate line of the 4a-7 row;

[0543] The input terminal of U1a+1 is electrically connected to the 4a-3 row gate line G(2a-1)1; the gate drive signal output terminal of U1a+1 is electrically connected to the 4a+1 row gate line G(2a+1)1; the reset terminal of U1a is electrically connected to the 4a+1 row gate line G4(2a+1)1; the reset terminal of U1a+1 is electrically connected to the 4a+5 row gate line;

[0544] The gate drive signal output terminal of U1B is electrically connected to the 4B-3 row gate line G(2B-1)1, and the input terminal of U1B is electrically connected to the 4B-7 row gate line.

[0545] Optionally, the second gate driving circuit includes a multi-stage second shift register unit;

[0546] The gate drive signal output end of the a-th level second shift register unit is electrically connected to the 4a-2 row gate line, and the input end of the a+1-th level second shift register unit is electrically connected to the 4a-2 row gate line; the gate drive signal output end of the a+1-th level second shift register unit is electrically connected to the 4a+2 row gate line; the reset end of the a-th level second shift register unit is electrically connected to the 4a+2 row gate line.

[0547] like Fig.19 As shown, the second gate driving circuit may include a B-level second shift register unit; Fig.19 , the unit labeled U21 is the first-stage second shift register unit, the unit labeled U22 is the second-stage second shift register unit, the unit labeled U23 is the third-stage second shift register unit, the unit labeled U2a is the a-th-stage second shift register unit, the unit labeled U2a+1 is the a+1-th-stage second shift register unit, and the unit labeled U2B is the B-th-stage second shift register unit, wherein a is a positive integer, and B is a positive integer greater than 5;

[0548] The input terminal of U21 is connected to the second start signal X2, the gate drive signal output terminal of U21 is electrically connected to the second row gate line G12, the gate drive signal output terminal of U21 is electrically connected to the input terminal of U22; the reset terminal of U21 is electrically connected to the sixth row gate line G32;

[0549] The gate drive signal output terminal of U22 is electrically connected to the sixth row of gate line G32, and the gate drive signal output terminal of U22 is electrically connected to the input terminal of U23; the reset terminal of U22 is electrically connected to the tenth row of gate line G52;

[0550] The gate drive signal output terminal of U23 is electrically connected to the tenth row gate line G52, and the gate drive signal output terminal of U23 is electrically connected to the fourth stage second shift register unit ( Fig.19 The reset terminal of U23 is electrically connected to the fourteenth row of gate line G72;

[0551] The gate drive signal output terminal of U2a is electrically connected to the gate line G(2a-1)2 of the 4a-2 row; the input terminal of U2a is electrically connected to the gate line of the 4a-6 row;

[0552] The input terminal of U2a+1 is electrically connected to the 4a-2 row gate line G(2a-1)2; the gate drive signal output terminal of U2a+1 is electrically connected to the 4a+2 row gate line G(2a+1)2; the reset terminal of U2a is electrically connected to the 4a+2 row gate line G(2a+1)2; the reset terminal of U2a+1 is electrically connected to the 4a+6 row gate line;

[0553] The gate drive signal output terminal of U2B is electrically connected to the gate line G(2B-1)2 of the 4B-2 row, and the input terminal of U2B is electrically connected to the gate line of the 4B-6 row.

[0554] Optionally, the third gate driving circuit includes a multi-stage third shift register unit;

[0555] The gate drive signal output end of the third shift register unit of the ath level is electrically connected to the 4a-1th row gate line, and the input end of the second shift register unit of the a+1th level is electrically connected to the 4a-1th row gate line; the gate drive signal output end of the third shift register unit of the a+1th level is electrically connected to the 4a+3th row gate line; the reset end of the third shift register unit of the ath level is electrically connected to the 4a+3th row gate line.

[0556] like Fig. 20 As shown, the third gate driving circuit may include a B-level third shift register unit; Fig. 20 , the unit labeled U31 is the third shift register unit of the first stage, the unit labeled U32 is the third shift register unit of the second stage, the unit labeled U33 is the third shift register unit of the third stage, the unit labeled U3a is the third shift register unit of the ath stage, the unit labeled U3a+1 is the third shift register unit of the a+1th stage, and the unit labeled U3B is the third shift register unit of the Bth stage, wherein a is a positive integer, and B is a positive integer greater than 5;

[0557] The input terminal of U31 is connected to the third start signal X3, the gate drive signal output terminal of U31 is electrically connected to the third row gate line G21, and the gate drive signal output terminal of U31 is electrically connected to the input terminal of U32; the reset terminal of U31 is electrically connected to the seventh row gate line G41;

[0558] The gate drive signal output terminal of U32 is electrically connected to the seventh row of gate line G41, and the gate drive signal output terminal of U32 is electrically connected to the input terminal of U33; the reset terminal of U32 is electrically connected to the eleventh row of gate line G61;

[0559] The gate drive signal output terminal of U33 is electrically connected to the eleventh row gate line G61, and the gate drive signal output terminal of U33 is electrically connected to the fourth stage third shift register unit ( Fig. 20 The reset terminal of U33 is electrically connected to the fifteenth row of gate line G81;

[0560] The gate drive signal output terminal of U3a is electrically connected to the 4a-1th row gate line G4a-1; the input terminal of U3a is electrically connected to the 4a-5th row gate line;

[0561] The input terminal of U3a+1 is electrically connected to the 4a-1th row gate line G(2a)1; the gate drive signal output terminal of U3a+1 is electrically connected to the 4a+3th row gate line G(2a+2)1; the reset terminal of U3a is electrically connected to the 4a+3th row gate line G(2a+2)1; the reset terminal of U3a+1 is electrically connected to the 4a+7th row gate line;

[0562] The gate drive signal output terminal of U3B is electrically connected to the gate line G(2B)1 of the 4B-1 row, and the input terminal of U3B is electrically connected to the gate line of the 4B-5 row. Optionally, the fourth gate drive circuit includes a multi-stage fourth shift register unit;

[0563] The gate drive signal output end of the fourth shift register unit of the ath level is electrically connected to the 4a row gate line, and the input end of the fourth shift register unit of the a+1th level is electrically connected to the 4a row gate line; the gate drive signal output end of the fourth shift register unit of the a+1th level is electrically connected to the 4a+4 row gate line; the reset end of the fourth shift register unit of the ath level is electrically connected to the 4a+4 row gate line.

[0564] like Fig.21 As shown, the fourth gate driving circuit may include a B-level fourth shift register unit; Fig.21 , the unit labeled U41 is the fourth shift register unit of the first stage, the unit labeled U42 is the fourth shift register unit of the second stage, the unit labeled U43 is the fourth shift register unit of the third stage, the unit labeled U4a is the fourth shift register unit of the ath stage, the unit labeled U4a+1 is the fourth shift register unit of the a+1th stage, and the unit labeled U4B is the fourth shift register unit of the Bth stage, wherein a is a positive integer, and B is a positive integer greater than 5;

[0565] The input terminal of U41 is connected to the fourth start signal X4, the gate drive signal output terminal of U41 is electrically connected to the fourth row gate line G22, the gate drive signal output terminal of U41 is electrically connected to the input terminal of U42; the reset terminal of U41 is electrically connected to the eighth row gate line G42;

[0566] The gate drive signal output terminal of U42 is electrically connected to the eighth row of gate line G42, and the gate drive signal output terminal of U42 is electrically connected to the input terminal of U43; the reset terminal of U42 is electrically connected to the twelfth row of gate line G62;

[0567] The gate drive signal output terminal of U43 is electrically connected to the twelfth row gate line G62, and the gate drive signal output terminal of U43 is electrically connected to the fourth shift register unit of the fourth stage ( Fig.21 The reset terminal of U43 is electrically connected to the sixteenth row of gate line G82;

[0568] The gate drive signal output terminal of U4a is electrically connected to the 4a-th row gate line G(2a)2; the input terminal of U4a is electrically connected to the 4a-4th row gate line;

[0569] The input terminal of U4a+1 is electrically connected to the 4a-th row gate line G(2a)2; the gate drive signal output terminal of U4a+1 is electrically connected to the 4a+4-th row gate line G(2a+2)2; the reset terminal of U4a is electrically connected to the 4a+4-th row gate line G(2a+2)2; the reset terminal of U4a+1 is electrically connected to the 4a+8-th row gate line;

[0570] The gate drive signal output terminal of U4B is electrically connected to the gate line G(2B)2 of the 4Bth row, and the input terminal of U4B is electrically connected to the gate line of the 4B-4th row.

[0571] In at least one embodiment of the present invention, the display panel further includes a plurality of rows of reset control lines; the display device further includes a reset control signal generating circuit, and the reset control signal generating circuit is used to provide a corresponding reset control signal for each row of reset control lines.

[0572] In at least one embodiment of the present invention, if the reset control signal is provided by the gate driving circuit, since one row of pixel circuits corresponds to two rows of gate driving signals, there are also two reset control signals provided for one row of pixel circuits. In order to save the wiring space of the display panel, one row of pixel circuits only corresponds to one row of reset control lines. Therefore, in at least one embodiment of the present invention, a separate reset control signal generating circuit is used to provide corresponding reset control signals for each row of reset control lines, instead of the gate driving circuit providing the reset control signal.

[0573] In a specific implementation, the display panel further includes a plurality of rows of light-emitting control lines; the display device further includes a light-emitting control signal generating circuit; the light-emitting control signal generating circuit is used to provide corresponding light-emitting control signals for each row of light-emitting control lines.

[0574] The display device provided in at least one embodiment of the present invention may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, or the like.

[0575] Unless otherwise defined, the technical terms or scientific terms used in the present invention should be understood by people with ordinary skills in the field to which the present invention belongs. The words "first", "second" and similar words used in the present invention do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and similar words mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect", "couple" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0576] The above is a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A display panel, characterized in that: It includes multiple rows and columns of pixel circuits, multiple rows of gate lines, multiple rows of reset control lines and multiple columns of data lines; The same row of pixel circuits corresponds to two rows of gate lines, one of the two rows of gate lines is electrically connected to the odd-numbered column pixel circuits in the row of pixel circuits, and is used to provide corresponding gate drive signals for the odd-numbered column pixel circuits in the row of pixel circuits; the other row of gate lines is electrically connected to the even-numbered column pixel circuits in the row of pixel circuits, and is used to provide corresponding gate drive signals for the even-numbered column pixel circuits in the row of pixel circuits; The same row of pixel circuits corresponds to a row of reset control lines, and the reset control lines provide corresponding reset control signals for the corresponding row of pixel circuits; The same column of pixel circuits corresponds to two columns of data lines, and one of the two columns of data lines is electrically connected to the odd-numbered rows of pixel circuits in the column of pixel circuits, for providing corresponding data voltages to the odd-numbered rows of pixel circuits in the column of pixel circuits; Another column of the two columns of data lines is electrically connected to the even-numbered rows of pixel circuits in the column of pixel circuits, and is used to provide corresponding data voltages to the even-numbered rows of pixel circuits in the column of pixel circuits; The display panel also includes a plurality of multiplexing circuits; The pth multiplexing circuit is used to control the data voltage provided by the pth data input terminal to be input to the four column data lines in a time-sharing manner under the control of the multiplexing control signal provided by the multiplexing control line; p is a positive integer; The multiplexing control line includes a first multiplexing control line, a second multiplexing control line, a first column gating control line and a second column gating control line; the p-th multiplexing circuit includes a p-th row multiplexing sub-circuit and a p-th column multiplexing sub-circuit; The p-th column multiplexing subcircuit is electrically connected to the p-th data input terminal, the first column selection control line, the second column selection control line, the 2p-1th write node and the 2p write node respectively, and is used for controlling the connection between the p-th data input terminal and the 2p-1th write node to be turned on or off, and controlling the connection between the p-th data input terminal and the 2p write node to be turned on or off, under the control of a first column selection control signal provided by the first column selection control line and a second column selection control signal provided by the second column selection control line; The p-th row multiplexing sub-circuit is electrically connected to the 2p-1th write node, the 2p write node, the first multiplexing control line, the second multiplexing control line, the first column data line, the second column data line, the third column data line and the fourth column data line, respectively, and is used to control the connection between the 2p-1th write node and the first column data line or the second column data line, and to control the connection between the 2p write node and the third column data line or the fourth column data line under the control of a first multiplexing control signal provided by the first multiplexing control line and a second multiplexing control signal provided by the second multiplexing control line.

2. The display panel according to claim 1, wherein: The gate driving signal on the gate line is delayed by H / 2 compared with the gate driving signal on the adjacent previous row of gate lines, where H is the row period.

3. The display panel according to claim 1, wherein: The p-th column multiplexing subcircuit includes a p-th first column multiplexing transistor and a p-th second column multiplexing transistor, wherein: The control electrode of the pth first column multiplexing transistor is electrically connected to the first column selection control line, the first electrode of the pth first column multiplexing transistor is electrically connected to the pth data input terminal, and the second electrode of the pth first column multiplexing transistor is electrically connected to the 2p-1th write node; The control electrode of the pth second column multiplexing transistor is electrically connected to the second column selection control line, the first electrode of the pth second column multiplexing transistor is electrically connected to the pth data input terminal, and the second electrode of the pth second column multiplexing transistor is electrically connected to the 2pth write node.

4. The display panel according to claim 1, wherein: The p-th row multiplexing subcircuit includes a p-th first row multiplexing transistor, a p-th second row multiplexing transistor, a p-th third row multiplexing transistor and a p-th fourth row multiplexing transistor; The control electrode of the pth first-row multiplexing transistor is electrically connected to the first multiplexing control line, the first electrode of the pth first-row multiplexing transistor is electrically connected to the 2p-1th write node, and the second electrode of the pth first-row multiplexing transistor is electrically connected to the first column data line; The control electrode of the pth second-row multiplexing transistor is electrically connected to the second multiplexing control line, the first electrode of the pth second-row multiplexing transistor is electrically connected to the 2p-1th write node, and the second electrode of the pth second-row multiplexing transistor is electrically connected to the second column data line; The control electrode of the pth third-row multiplexing transistor is electrically connected to the second multiplexing control line, the first electrode of the pth third-row multiplexing transistor is electrically connected to the 2pth write node, and the second electrode of the pth third-row multiplexing transistor is electrically connected to the third column data line; The control electrode of the pth fourth row multiplexing transistor is electrically connected to the first multiplexing control line, the first electrode of the pth fourth row multiplexing transistor is electrically connected to the 2pth write node, and the second electrode of the pth fourth row multiplexing transistor is electrically connected to the fourth column data line.

5. The display panel according to any one of claims 1 to 4, characterized in that: Also included are multiple rows of light-emitting control lines; The pixel circuits in the same row are electrically connected to the reset control line and the light emitting control line in the same row respectively. The reset control line in the same row is used to provide a reset control signal for the pixel circuits in the same row, and the light emitting control line in the same row is used to provide a light emitting control signal for the pixel circuits in the same row.

6. A method for driving a display panel, applied to the display panel according to any one of claims 1 to 5, characterized in that: The driving method of the display panel includes: The reset control line of the same row provides a reset control signal for the pixel circuits of the same row; One of the two rows of gate lines corresponding to the same row of pixel circuits provides corresponding gate drive signals for the odd-numbered column pixel circuits in the same row of pixel circuits, and the other of the two rows of gate lines provides corresponding gate drive signals for the even-numbered column pixel circuits in the same row of pixel circuits; One of the two data lines corresponding to the same column of pixel circuits provides corresponding data voltages for odd-numbered pixel circuits in the same column of pixel circuits, and the other of the two data lines provides corresponding data voltages for even-numbered pixel circuits in the same column of pixel circuits; The gate drive signal on the gate line is delayed by H / 2 compared with the gate drive signal on the adjacent previous row of gate lines, where H is the row period; The display panel further includes a plurality of multiplexing circuits; and the driving method of the display panel further includes: The p-th multiplexing circuit controls the data voltage provided by the data input terminal to be input to the four column data lines in a time-sharing manner under the control of the multiplexing control signal provided by the multiplexing control line; The multiplexing control line includes a first multiplexing control line, a second multiplexing control line, a first column gating control line and a second column gating control line; the p-th multiplexing circuit includes a p-th row multiplexing subcircuit and a p-th column multiplexing subcircuit; the data providing cycle includes a first data providing stage, a second data providing stage, a third data providing stage and a fourth data providing stage which are arranged in sequence; p is a positive integer; The step of controlling the data voltage provided by the data input terminal to be input to the four columns of data lines in a time-sharing manner under the control of the multiplexing control signal provided by the multiplexing control line comprises: In the first data providing stage and the third data providing stage, the p-th column multiplexing subcircuit controls the connection between the p-th data input terminal and the 2p-1-th write node to be turned on, and controls the connection between the p-th data input terminal and the 2p-1-th write node to be turned off, under the control of the first column enabling control signal provided by the first column enabling control line and the second column enabling control signal provided by the second column enabling control line; In the second data providing stage and the fourth data providing stage, the p-th column multiplexing subcircuit controls, under the control of the first column selection control signal and the second column selection control signal, to disconnect the connection between the p-th data input terminal and the 2p-1th write node, and controls to connect the connection between the p-th data input terminal and the 2p-1th write node; In the first data providing stage and the second data providing stage, the p-th row multiplexing subcircuit controls the connection between the 2p-1th write node and the first column data line, and controls the connection between the 2p write node and the fourth column data line, under the control of the first multiplexing control signal provided by the first multiplexing control line and the second multiplexing control signal provided by the second multiplexing control line; In the third data providing stage and the fourth data providing stage, the p-th row multiplexing sub-circuit controls the connection between the 2p-1th write node and the second column data line, and controls the connection between the 2p write node and the third column data line under the control of the first multiplexing control signal and the second multiplexing control signal.

7. The method for driving a display panel according to claim 6, wherein: The display panel further includes a plurality of rows of light emitting control lines; and the driving method of the display panel further includes: The light emitting control lines in the same row provide light emitting control signals for the pixel circuits in the same row.

8. The method for driving a display panel according to claim 7, wherein: The n-th row display phase includes an n-th reset time period, an n-th data writing time period and an n-th light emitting control time period which are arranged in sequence; n is a positive integer; In the nth reset time period, the nth row reset control line provides a valid nth row reset control signal; In the 2n-1th row writing time period included in the nth data writing time period, the 2n-1th row gate line provides a valid gate driving signal; In the 2nth row writing time period included in the nth data writing time period, the 2nth row gate line provides a valid gate driving signal; In the nth light emitting control period, the nth row of light emitting control lines provides a valid light emitting control signal; The 2nth row writing period is delayed by H / 2 from the 2n-1th row writing period.

9. A display device, characterized in that: The invention comprises a display panel as claimed in any one of claims 1 to 5.

10. The display device according to claim 9, characterized in that Also includes a first gate driving circuit, a second gate driving circuit, a third gate driving circuit and a fourth gate driving circuit; The first gate driving circuit is used to provide a first row of gate driving signals for a first row of gate lines; The second gate driving circuit is used for providing a second row of gate driving signals for the second row of gate lines; The third gate driving circuit is used to provide a third row of gate driving signals for the third row of gate lines; The fourth gate driving circuit is used for providing a fourth row of gate driving signals for a fourth row of gate lines.

11. The display device according to claim 10, wherein: The first gate driving circuit includes a multi-stage first shift register unit; The gate drive signal output terminal of the a-th first shift register unit is electrically connected to the first row gate line, and the input terminal of the a+1-th first shift register unit is electrically connected to the first row gate line; the gate drive signal output terminal of the a+1-th first shift register unit is electrically connected to the fifth row gate line; the reset terminal of the a-th first shift register unit is electrically connected to the fifth row gate line; The second gate driving circuit includes a multi-stage second shift register unit; The gate drive signal output terminal of the a-th second shift register unit is electrically connected to the second row gate line, and the input terminal of the a+1-th second shift register unit is electrically connected to the second row gate line; the gate drive signal output terminal of the a+1-th second shift register unit is electrically connected to the sixth row gate line; the reset terminal of the a-th second shift register unit is electrically connected to the sixth row gate line; The third gate driving circuit includes a multi-stage third shift register unit; The gate drive signal output terminal of the third shift register unit of the ath level is electrically connected to the third row gate line, and the input terminal of the second shift register unit of the a+1th level is electrically connected to the third row gate line; the gate drive signal output terminal of the third shift register unit of the a+1th level is electrically connected to the seventh row gate line; the reset terminal of the third shift register unit of the ath level is electrically connected to the seventh row gate line; The fourth gate driving circuit includes a multi-stage fourth shift register unit; The gate drive signal output end of the fourth shift register unit of the ath level is electrically connected to the fourth row gate line, and the input end of the fourth shift register unit of the a+1th level is electrically connected to the fourth row gate line; the gate drive signal output end of the fourth shift register unit of the a+1th level is electrically connected to the eighth row gate line; the reset end of the fourth shift register unit of the ath level is electrically connected to the eighth row gate line.

12. The display device according to claim 9, wherein: The display panel further includes a plurality of rows of reset control lines; the display device further includes a reset control signal generating circuit, and the reset control signal generating circuit is used to provide corresponding reset control signals for the reset control lines of each row.

13. The display device according to claim 9, wherein: The display panel further includes a plurality of rows of light-emitting control lines; the display device further includes a light-emitting control signal generating circuit; the light-emitting control signal generating circuit is used to provide corresponding light-emitting control signals for each row of light-emitting control lines.

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