Processor load monitoring method and monitoring device

Abstract

The present application provides a method and apparatus for monitoring processor load, which are advantageous for reducing processor load monitoring delays, thereby improving system response speed. The method comprises: counting the operating hours of cores in a processor during multiple sub-time periods within a first time period, obtaining first activity information of the cores during the first time period; based on the first activity information, determining whether the core load during the first time period is normal; if the core load during the first time period is normal, counting the operating hours of the cores during multiple sub-time periods within a second time period, obtaining second activity information of the cores during the second time period; and determining whether the core load during the second time period is normal based on the second activity information.

Description

Technical Field

[0001] The present application relates to the field of computers, and in particular to a method and device for monitoring processor load. Background Art

[0002] Whether in load balancing management or internal chip load monitoring, rapid tracking of processor load status is required to provide low-latency control and system management. In actual application scenarios, dynamic monitoring of processor load is often required. Based on the monitoring results, the processor power consumption surge can be controlled, the processor frequency can be increased, or the load can be migrated to meet application needs.

[0003] The current solution is to monitor the processor load by periodically reading the performance monitor unit (PMU) counter. This is implemented by software, and the monitoring delay is too large, resulting in slow system response. Summary of the Invention

[0004] The present application provides a processor load monitoring method and monitoring device, which are conducive to reducing the monitoring delay of the processor load, thereby improving the response speed of the system.

[0005] In a first aspect, a method for monitoring processor load is provided, comprising: counting the working hours of cores in a processor in a plurality of sub-time periods in a first time period, and obtaining first activity information of the cores in the first time period; judging whether the load of the cores in the first time period is normal based on the first activity information; if the load of the cores in the first time period is normal, counting the working hours of the cores in a plurality of sub-time periods in a second time period, and obtaining second activity information of the cores in the second time period, wherein the start time of the second time period belongs to the first time period, and the second time period is delayed by one or more sub-time periods than the first time period; judging whether the load of the cores in the second time period is normal based on the second activity information.

[0006] In an embodiment of the present application, the monitoring device can adopt a sliding window strategy to monitor the load of the core in the processor. By monitoring the load of the core in the processor in each sub-time period, the activity information of the above-mentioned core in the new time period can be recalculated every sub-time period, which is conducive to improving the accuracy of the activity information of the core in the processor, reducing the monitoring delay of the processor load, and thus improving the response speed of the system.

[0007] In conjunction with the first aspect, in a certain implementation of the first aspect, the first activity information is an average activity of the core in the first time period, and the average activity is calculated based on the following formula:

[0008]

[0009] Wherein, N is the number of the above sub-time periods contained in the above first time period, t i is the working time of the core in the i-th sub-time period of the first time period, T i is the duration of the i-th sub-time period in the above-mentioned first time period.

[0010] In an embodiment of the present application, the monitoring device uses the average activity of the cores in the processor in the first time period as the first activity information, which can effectively reflect the average load condition or working status of the cores in the processor in the first time period.

[0011] In combination with the first aspect, in a certain implementation of the first aspect, based on the above-mentioned first activity information, it is determined whether the load of the above-mentioned core is normal during the above-mentioned first time period, including: if the above-mentioned first activity information is greater than the first threshold value, it is determined that the above-mentioned core is too heavily loaded during the above-mentioned first time period; if the above-mentioned first activity information is less than the second threshold value, it is determined that the above-mentioned core is too lightly loaded during the above-mentioned first time period; or, if the above-mentioned first activity information is greater than or equal to the above-mentioned second threshold value and less than or equal to the above-mentioned first threshold value, it is determined that the load of the above-mentioned core is normal during the above-mentioned first time period, and the first threshold value is greater than the second threshold value.

[0012] In the embodiment of the present application, the monitoring device can effectively determine whether the load of the core in the processor is normal by comparing the first activity information with a preset threshold value.

[0013] In combination with the first aspect, in a certain implementation of the first aspect, the above-mentioned processor is a single-core processor, and the above-mentioned method also includes: if the above-mentioned core is overloaded during the above-mentioned first time period, increasing the frequency and power of the above-mentioned processor; or, if the above-mentioned core is too lightly loaded during the above-mentioned first time period, reducing the frequency and power of the above-mentioned processor.

[0014] In the embodiment of the present application, when the load on a core in a single-core processor is abnormal, the frequency and voltage of the processor can be adjusted, thereby effectively ensuring the stability of the single-core processor.

[0015] In combination with the first aspect, in a certain implementation of the first aspect, the above-mentioned processor is a multi-core processor, and the above-mentioned core is a small core. The above-mentioned method also includes: if the above-mentioned core is overloaded during the above-mentioned first time period, migrating the load on the above-mentioned core to the large core in the above-mentioned processor, or increasing the frequency and power of the above-mentioned medium core; if the above-mentioned core is too lightly loaded during the above-mentioned first time period, reducing the frequency and power of the above-mentioned core.

[0016] In the embodiment of the present application, when the load on the small cores of the many-core processor is abnormal, a variety of load balancing management methods can be used to effectively ensure the stability of the many-core processor.

[0017] In combination with the first aspect, in a certain implementation of the first aspect, the above-mentioned processor is a multi-core processor, and the above-mentioned core is a large core. The above-mentioned method also includes: if the load on the above-mentioned core is too light during the above-mentioned first time period, migrating the load on the above-mentioned core to the small core in the above-mentioned processor, or reducing the frequency and power of the above-mentioned core; if the load on the above-mentioned core is heavy during the above-mentioned first time period, increasing the frequency and power of the above-mentioned core.

[0018] In the embodiment of the present application, when the load on a large core in a many-core processor is abnormal, a variety of load balancing management methods can be used to effectively ensure the stability of the many-core processor.

[0019] In a second aspect, a processor load monitoring device is provided, comprising: an acquisition module and a processing module; wherein the acquisition module is used to count the working hours of the cores in the processor in multiple sub-time periods in a first time period, and obtain first activity information of the above-mentioned cores in the above-mentioned first time period; the processing module is used to determine whether the load of the above-mentioned cores in the above-mentioned first time period is normal based on the above-mentioned first activity information; the above-mentioned acquisition module is used to count the working hours of the above-mentioned cores in multiple sub-time periods in a second time period, and obtain second activity information of the above-mentioned cores in the above-mentioned second time period, when the load of the above-mentioned cores in the above-mentioned first time period is normal, and the start time of the above-mentioned second time period belongs to the above-mentioned first time period, and the above-mentioned second time period is delayed by one or more of the above-mentioned sub-time periods than the above-mentioned first time period; the above-mentioned processing module is used to determine whether the load of the above-mentioned cores in the above-mentioned second time period is normal based on the above-mentioned second activity information.

[0020] In conjunction with the second aspect, in a certain implementation of the second aspect, the first activity information is an average activity of the core in the first time period, and the average activity is calculated based on the following formula:

[0021]

[0022] Wherein, N is the number of the above sub-time periods contained in the above first time period, t i is the working time of the core in the i-th sub-time period of the first time period, T i is the duration of the i-th sub-time period in the above-mentioned first time period.

[0023] In combination with the second aspect, in a certain implementation of the second aspect, the above-mentioned processing module is used to: if the above-mentioned first activity information is greater than the first threshold value, determine that the above-mentioned core is too heavily loaded during the above-mentioned first time period; if the above-mentioned first activity information is less than the second threshold value, determine that the above-mentioned core is too lightly loaded during the above-mentioned first time period; or, if the above-mentioned first activity information is greater than or equal to the above-mentioned second threshold value and less than or equal to the above-mentioned first threshold value, determine that the above-mentioned core is normally loaded during the above-mentioned first time period, and the first threshold value is greater than the second threshold value.

[0024] In combination with the second aspect, in a certain implementation of the second aspect, the above-mentioned processor is a single-core processor, and the above-mentioned processing module is used to: if the above-mentioned core is overloaded during the above-mentioned first time period, increase the frequency and power of the above-mentioned processor; or, if the above-mentioned core is too lightly loaded during the above-mentioned first time period, reduce the frequency and power of the above-mentioned processor.

[0025] In combination with the second aspect, in a certain implementation of the second aspect, the above-mentioned processor is a multi-core processor, the above-mentioned core is a small core, and the above-mentioned processing module is used to: if the above-mentioned core is overloaded during the above-mentioned first time period, migrate the load on the above-mentioned core to the large core in the above-mentioned processor, or increase the frequency and power of the above-mentioned core; if the above-mentioned core is too lightly loaded during the above-mentioned first time period, reduce the frequency and power of the above-mentioned core.

[0026] In combination with the second aspect, in a certain implementation of the second aspect, the above-mentioned processor is a multi-core processor, the above-mentioned core is a large core, and the above-mentioned processing module is used to: if the load on the above-mentioned core is too light during the above-mentioned first time period, migrate the load on the above-mentioned core to the small core in the above-mentioned processor, or reduce the frequency and power of the above-mentioned core; if the load on the above-mentioned core is heavy during the above-mentioned first time period, increase the frequency and power of the above-mentioned core.

[0027] In a third aspect, another processor load monitoring device is provided, comprising a processor coupled to a memory and configured to execute instructions in the memory to implement the method of any possible implementation of any of the aforementioned aspects. Optionally, the device further comprises a memory. Optionally, the device further comprises a communication interface, the processor coupled to the communication interface.

[0028] In a fourth aspect, a processor is provided, comprising: an input circuit, an output circuit, and a processing circuit. The processing circuit is configured to receive a signal through the input circuit and transmit a signal through the output circuit, so that the processor executes the method of any possible implementation of the first aspect.

[0029] In a specific implementation, the processor may be a chip, the input circuit may be an input pin, the output circuit may be an output pin, and the processing circuit may be a transistor, a gate circuit, a trigger, or various logic circuits. The input signal received by the input circuit may be, for example, but not limited to, received and input by a receiver, and the signal output by the output circuit may be, for example, but not limited to, output to and transmitted by a transmitter. The input circuit and the output circuit may be the same circuit, which functions as an input circuit and an output circuit at different times. The embodiments of the present application do not limit the specific implementation of the processor and various circuits.

[0030] In a fifth aspect, a processing device is provided, comprising a processor and a memory. The processor is configured to read instructions stored in the memory and receive signals via a receiver and transmit signals via a transmitter to execute the method of any possible implementation of the first aspect.

[0031] Optionally, there are one or more processors and one or more memories.

[0032] Optionally, the memory may be integrated with the processor, or the memory may be provided separately from the processor.

[0033] In the specific implementation process, the memory can be a non-transitory memory, such as a read-only memory (ROM), which can be integrated with the processor on the same chip or can be set on different chips. The embodiments of the present application do not limit the type of memory and the setting method of the memory and the processor.

[0034] The processing device in the above-mentioned fifth aspect can be a chip. The processor can be implemented by hardware or by software. When implemented by hardware, the processor can be a logic circuit, an integrated circuit, etc.; when implemented by software, the processor can be a general-purpose processor, which is implemented by reading the software code stored in the memory. The memory can be integrated in the processor or can be located outside the processor and exist independently.

[0035] In a sixth aspect, a computer program product is provided, which includes: a computer program (also referred to as code, or instructions), which, when executed, enables a computer to execute the method in any possible implementation of the first aspect.

[0036] In the seventh aspect, a computer-readable storage medium is provided, which stores a computer program (also referred to as code, or instructions) which, when run on a computer, enables the computer to execute the method in any possible implementation of the first aspect above. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 is a schematic flow chart of a method for monitoring processor load provided in an embodiment of the present application;

[0038] Figure 2 This is a schematic diagram of the working time of a core in a statistical processor within a sub-time period provided by an embodiment of the present application;

[0039] Figure 3 is a schematic diagram of the sliding window process provided in an embodiment of the present application;

[0040] Figure 4 is a schematic block diagram of a processor load monitoring system provided in an embodiment of the present application;

[0041] Figure 5 Schematic diagram of a single-core processor load balancing management operation provided by an embodiment of the present application;

[0042] Figure 6 is a schematic diagram of a many-core processor provided in an embodiment of the present application;

[0043] Figure 7 Schematic diagram of the load balancing management operation of a multi-core processor provided by an embodiment of the present application;

[0044] Figure 8 Schematic diagram of another multi-core processor load balancing management operation provided by an embodiment of the present application;

[0045] Figure 9 Schematic diagram of another multi-core processor load balancing management operation provided by an embodiment of the present application;

[0046] Figure 10 Schematic diagram of another multi-core processor load balancing management operation provided by an embodiment of the present application;

[0047] Figure 11 is a schematic block diagram of a processor load monitoring device provided in an embodiment of the present application;

[0048] Figure 12 This is a schematic block diagram of another processor load monitoring device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0049] The technical solution in this application will be described below with reference to the accompanying drawings.

[0050] To facilitate understanding, the relevant terms involved in this application are first explained.

[0051] The function of a processor is mainly to interpret computer instructions and process data in computer software. The processor of the present application can be a different type of processor, for example, a central processing unit (CPU), an artificial intelligence processing unit (AICPU), a graphics processing unit (GPU), or a microprocessor (MPU), etc., and the embodiments of the present application are not limited to this.

[0052] Processors can be categorized as single-core or multi-core processors based on the number of cores they contain. A single-core processor has only one logical core (referred to herein as a core), while a multi-core processor has multiple logical cores. A multi-core processor can include both large and small cores. The large core is the main processor, offering high performance and is activated when running large programs. The small core has a lower clock speed and offers lower performance, but consumes less power.

[0053] Processor load includes the number of processes occupying the processor within a certain period of time (the number of processes currently executing) and the number of processes waiting for processor time (the number of processes waiting for processor time here refers to the number of processes waiting to be awakened). To ensure that the overall performance of the processor is not affected when there are many processes, it is necessary to monitor the load of the processor cores for load balancing management.

[0054] Whether in load balancing management or internal chip load monitoring, rapid tracking of processor load status is required to provide low-latency control and system management. In actual application scenarios, dynamic monitoring of processor load is often required. Based on the monitoring results, the processor power consumption surge can be controlled, the processor frequency can be increased, or the load can be migrated to meet application needs.

[0055] The current solution is to monitor processor load by periodically reading the performance monitoring unit (PMU) counter. However, the monitoring delay is too large, resulting in slow system response, which in turn leads to untimely management of load migration and corresponding frequency and power consumption adjustments.

[0056] In view of this, the present application provides a method and a monitoring device for monitoring processor load, which monitors the load of the core in the processor by adopting a sliding window strategy (referred to as the sliding window strategy in this article), obtains the activity information of the core, and obtains the activity information of the processor based on the activity information of the core, thereby reducing the monitoring delay of the processor load, improving the response speed of the system, and thereby improving the timeliness of load migration and corresponding frequency adjustment and power consumption adjustment management.

[0057] Before introducing the processor load monitoring method and monitoring device provided in the embodiments of the present application, the following points are explained.

[0058] First, in the embodiments described below, various terms and abbreviations, such as core active status (CAS) and core active monitor (CAM), are provided for ease of description and should not limit this application in any way. This application does not exclude the possibility of defining other terms in existing or future protocols that can achieve the same or similar functions.

[0059] Second, in the embodiments shown below, the first, second, and various numerical numbers are merely for the convenience of description and are not intended to limit the scope of the embodiments of the present application. For example, the first active information and the second active information are merely used to distinguish different information.

[0060] Third, "at least one" means one or more, and "more" means two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship. "At least one of the following items" or similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b and c can mean: a, or b, or c, or a and b, or a and c, or b and c, or a, b and c, where a, b, c can be single or multiple.

[0061] In order to make the purpose and technical solution of this application clearer and more intuitive, the method and device provided by the embodiment of this application will be described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0062] It should be understood that the method of the embodiment of the present application can be executed by a device capable of monitoring the processor load, which is referred to as a monitoring device in the embodiment of the present application.

[0063] Figure 1 FIG. 1 is a schematic flow chart of a method 100 for monitoring processor load in an embodiment of the present application. Figure 1 As shown, the method 100 includes the following steps:

[0064] S101 , counting working hours of cores in a processor in a plurality of sub-time periods within a first time period, to obtain first activity information of the cores in the first time period.

[0065] It should be understood that the first time period is composed of multiple sub-time periods, and the durations of the multiple sub-time periods may be equal or unequal, which is not limited in the present embodiment. The first time period is used to monitor the state of the processor load, so the first time period can also be called the first observation window.

[0066] Exemplarily, the monitoring device may configure the duration of the first time period to be 10 ms, and the first time period includes 10 sub-time periods of 1 ms.

[0067] S102: Based on the first activity information, determine whether the load of the core is normal within a first time period.

[0068] In an embodiment of the present application, the monitoring device may compare the first activity information with a preset threshold and determine whether the load of the core in the first time period is normal based on the comparison result.

[0069] In one possible implementation, the monitoring device may compare the first activity information with a preset threshold to determine whether the core load is normal during the first time period. For example, when the first activity information is less than the preset threshold, the monitoring device may determine that the core load of the processor during the first time period is normal; otherwise, the monitoring device may determine that the core load of the processor during the first time period is abnormal.

[0070] In another possible implementation, the monitoring device may compare the first activity information with multiple preset thresholds to determine whether the core load is normal during the first time period. Exemplarily, the multiple preset thresholds include a first threshold and a second threshold, and the first threshold is greater than the second threshold. When the first activity information is greater than the first threshold, the monitoring device may determine that the core load of the processor during the first time period is too high. When the first activity information is less than the second threshold, the monitoring device may determine that the core load of the processor during the first time period is too low. Alternatively, when the first activity information is greater than between the first threshold and the second threshold, that is, the first activity information is greater than or equal to the second threshold and less than or equal to the first threshold, the monitoring device may determine that the core load of the processor during the first time period is normal.

[0071] It should be understood that the monitoring device can configure the first threshold value and the second threshold value according to the requirements of different application scenarios.

[0072] Exemplarily, the monitoring device may obtain relevant load data through testing during the initialization of the deep learning application, and configure the threshold value based on the load data. The load data may be the maximum load bearing data of the core in the processor, etc.

[0073] S103, when the load of the above-mentioned core is normal in the first time period, the working time of the core is counted in multiple sub-time periods in the second time period to obtain the second active information of the core in the second time period, the start time of the above-mentioned second time period belongs to the above-mentioned first time period, and the above-mentioned second time period is delayed by one or more of the above-mentioned sub-time periods than the above-mentioned first time period.

[0074] For example, the start time of the second time period may be the end time of the first sub-time period in the first time period, and the end time of the second time period may be the time obtained by sliding the end time of the first time period backward by the length of the first sub-time period.

[0075] The second time period is equal to the first time period, and the second time period is also used to monitor the state of the processor load, so the second time period can also be called a second observation window.

[0076] In an embodiment of the present application, if the load of the core in the processor is normal within the first time period, the monitoring device can adopt a sliding window strategy to slide the first time period as a whole backward to the first sub-time period in the above-mentioned first time period to obtain a second time period, and continue to count the working time of the core in the above-mentioned processor in multiple sub-time periods in the second time period to obtain the second activity information of the core in the processor in the second time period.

[0077] It should be understood that when the load of the core in the processor is normal in the first time period, the monitoring device may not perform any balancing management on the load of the core in the processor, so the load of the core in the processor remains unchanged, and the monitoring device may continue to monitor whether the load of the core in the processor is normal in the second time period.

[0078] When the load of a core in a processor is abnormal during the first time period, the monitoring device can balance the load of the core in the processor, for example, migrate the load of the core in the processor to other cores in the processor, or adjust the frequency and power of the processor.

[0079] If the monitoring device continues to monitor the load of the processor core during the second time period after the load of the processor core has been migrated to another core, the load of the processor core monitored during the first time period will differ from the load of the processor core monitored during the second time period, thereby causing the second activity information obtained by the monitoring device during the second time period to be inaccurate. Therefore, when the load of the processor core during the first time period is abnormal, the monitoring device needs to start a new monitoring task to monitor the new load of the processor core during the new time period.

[0080] S104: Based on the second activity information, determine whether the load of the core is normal in the second time period.

[0081] The method of judging whether the core load is normal based on the second active information is similar to the method of judging whether the core load is normal based on the first active information, and the subsequent processing operations are also similar. If the core load in the processor is normal within the second time period, the monitoring device can use a sliding window strategy to continue to monitor the load of the core in the processor. If the core load in the processor is abnormal within the second time period, the monitoring device can balance the load of the core in the processor. It will not be repeated here.

[0082] In an embodiment of the present application, the monitoring device can adopt a sliding window strategy to monitor the load of the core in the processor. By monitoring the load of the core in the processor in each sub-time period, the activity information of the above-mentioned core in the new time period can be recalculated every sub-time period, which is conducive to improving the accuracy of the activity information of the core in the processor, reducing the monitoring delay of the processor load, and thus improving the response speed of the system.

[0083] Exemplarily, the first time period includes sub-time periods T1, T2, T3, T4, T5 and T6. Figure 2 This is a schematic diagram of counting the working time of the cores in the processor in the first sub-time period T1 in the first time period. Figure 2 As shown, based on the monitoring clock, the monitoring device can obtain T1 contains 32 monitoring clocks through the sub-time period counter. The upward bulge of the fluctuation graph of the single-core working status indicates that the core in the processor is in a working state. The monitoring device can count through the single-core working status counter when the fluctuation graph of the single-core working status bulges upward, and obtain that the working time of the core in the sub-time period T1 is 15 monitoring clocks.

[0084] Figure 2 Taking sub-time period T1 as an example, the working time of the core in the statistical processor is explained. For other sub-time periods, the monitoring device can use the same method to obtain the corresponding working time, which is not listed here one by one.

[0085] In an embodiment of the present application, after counting the working hours of the cores in the above-mentioned processor, the monitoring device can obtain the above-mentioned first activity information in a variety of ways, which is not limited in this embodiment of the present application.

[0086] In one possible implementation, the first activity information is the total activity of the cores in the processor during the first time period. In other words, the monitoring device may add up the working time of the cores in the processor obtained in each of the sub-time periods to obtain the first activity information for the first time period.

[0087] For example, the monitoring device can be based on the formula The total activity of the cores in the processor in the first time period is calculated, where N is the number of sub-time periods included in the first time period, and t i is the working time of the core in the i-th sub-time period in the above-mentioned first time period.

[0088] It should be understood that the monitoring device may preset the first threshold and the second threshold based on the total activity of the cores in the processor during the first time period.

[0089] In another possible implementation, the first activity information is the average activity of the processor cores during the first time period. The monitoring device may divide the working time of the processor cores calculated in each of the sub-time periods by the corresponding sub-time period to obtain sub-activity information of the processor cores in each sub-time period, and divide the sum of the sub-activity information by the total number of sub-time periods in the first time period to obtain the first activity information of the cores in the first time period.

[0090] For example, the monitoring device can use the formula The average activity of the cores in the processor during the first time period is calculated. Where N is the number of the sub-time periods contained in the first time period, t i is the working time of the core in the i-th sub-time period of the first time period, T i is the duration of the i-th sub-time period in the above-mentioned first time period.

[0091] It should be understood that the monitoring device may preset the first threshold and the second threshold with reference to the average activity of the cores in the processor during the first time period.

[0092] Figure 3 The sliding window process of the above example is shown as Figure 3 As shown, the monitoring device can adopt a sliding window strategy to slide the first time period as a whole backward by the time interval of the first sub-time period T1 to obtain a second time period, which includes sub-time periods T2, T3, T4, T5, T6 and T7, and the length of T7 is equal to T1. Figure 2As shown, the monitoring device can use the method of counting the operating hours of the processor cores in sub-periods T1 within the first time period to count the operating hours of the processor cores in sub-periods T2, T3, T4, T5, T6, and T7 within the second time period to obtain the second activity information of the processor cores in the second time period. Since the monitoring device has already obtained the statistical results of the first five sub-periods of the second activity information in the previous window, the monitoring device only needs to obtain the statistical results of the new sub-period T7, which greatly shortens the monitoring delay.

[0093] Therefore, after the first time period, the monitoring device of the embodiment of the present application can recalculate the activity information of the above-mentioned core in the new time period every sub-time period, which is beneficial to improving the accuracy of the activity information of the core in the processor, reducing the monitoring delay of the processor load, and thus improving the response speed of the system.

[0094] In one possible implementation, the monitoring device may be a core activity monitor (CAM) or a device including a CAM, wherein the CAM is connected to the processor and can implement the operations in S101 to S104. The following description uses the CAM as an example of the monitoring device.

[0095] Figure 4 FIG. 1 shows a schematic block diagram of a processor load monitoring system provided by an embodiment of the present application. Figure 4 As shown in the figure, according to the core active status (CAS), the CAM can count the working time T1CAS, T2CAS, ..., T1CAS of the core in the processor in each sub-time period through the core active counter (CAC). n-1 CAS, T n CAS, outputs the working time data of the core of the processor in the sub-time period to the cache every sub-time period. The cache is a first-in first-out (FIFO) memory. At the same time, CAM can accumulate the working time data in the register. When the cache is filled with the working time data, that is, after the working time of the core of the processor in all sub-time periods in the first time period is counted, the CAM can compare the accumulated result in the register with the preset threshold through the comparison module. When the accumulated result in the register is within the above threshold range, the CAM can adopt a sliding window strategy to subtract the earliest working time data T1CAS in the cache through the register. The CAM can continue the above steps and use CAC to count the sub-time period T of the core of the processor in the second time period. n+1 Working hours within T n+1CAS, and saves the data of the working time of the core of the processor in the sub-time period into the cache, completing the monitoring task of the core of the processor in the second time period. To avoid repetition, it is not repeated here.

[0096] Optionally, when the accumulated result of the register is not within the threshold range, the CAM can also perform corresponding load balancing management on the processor according to the accumulated result of the register. The following describes the execution of load balancing management on the processor in two cases.

[0097] As an optional embodiment, the above-mentioned processor is a single-core processor, and the above-mentioned method further includes: if the above-mentioned core is overloaded in the first time period, increasing the frequency and power; or, if the above-mentioned core is too lightly loaded in the first time period, reducing the frequency and power.

[0098] Figure 5 This is a schematic diagram of the load balancing management operation of a single-core processor provided in an embodiment of the present application. Figure 5 As shown, CAM can take corresponding load balancing management for the cores according to the load status of the cores in the processor.

[0099] For example, when the core is overloaded in the first time period, it means that the core in the processor is close to its maximum computing power. In order to improve the processing efficiency of the core in the processor, the frequency of the core in the processor can be increased to speed up the execution of the current task. Before increasing the frequency, the power needs to be increased. Figure 5 As shown, the CAM can increase the voltage of the processor through the DC voltage conversion unit to achieve the purpose of increasing power, and increase the clock of the processor through the clock generation unit to achieve the purpose of increasing frequency.

[0100] For example, when the core load is too light in the first time period, it means that there are too many idle cores in the processor. Considering the constraints of the total system power consumption, the frequency and power can be reduced to reduce power consumption. Figure 5 As shown, the CAM can reduce the voltage of the processor through the DC voltage conversion unit to achieve the purpose of reducing power, and reduce the clock of the processor through the clock generation unit to achieve the purpose of reducing frequency.

[0101] The above describes the load balancing method for a single-core processor. The following describes the load balancing management of processors in a multi-core processor. Figure 6 A schematic block diagram of a multi-core processor is provided for an embodiment of the present application. Figure 6 As shown, each core in the many-core processor may correspond to a CAM. Here, taking one CAM corresponding to one core as an example, a load balancing method for the many-core processor is described.

[0102] As an optional embodiment, the above-mentioned processor is a multi-core processor, and the above-mentioned core is a small core. The above-mentioned method also includes: if the above-mentioned core is overloaded within the first time period, migrating the load on the above-mentioned small core to the large core in the processor, or increasing the frequency and power of the above-mentioned small core; if the above-mentioned core is too lightly loaded within the above-mentioned first time period, reducing the frequency and power of the above-mentioned small core.

[0103] In one possible implementation, if the load on a small core in the many-core processor is too light during a first time period, the CAM may reduce the frequency and power of the core in the processor.

[0104] In another possible implementation, if a small core in the many-core processor is overloaded during a first time period, the monitoring device may migrate the load on the small core to a large core in the many-core processor.

[0105] As an optional embodiment, the above-mentioned processor is a multi-core processor, and the above-mentioned core is a large core. The above-mentioned method also includes: if the load on the above-mentioned core is too light within the first time period, migrating the load on the above-mentioned core to the small core in the processor, or reducing the frequency and power of the above-mentioned large core; if the above-mentioned core is heavily loaded within the first time period, increasing the frequency and power of the above-mentioned large core.

[0106] In one possible implementation, if a large core in the many-core processor is overloaded during a first time period, the CAM may increase the frequency and power of the core in the many-core processor.

[0107] In another possible implementation, if the load on a large core in the many-core processor is too light during the first time period, the monitoring device may migrate the load on the large core to the small core in the many-core processor.

[0108] Figure 7 This is a schematic diagram of the load balancing management operation of the multi-core processor provided in the embodiment of the present application. Figure 7 As shown, each core in the multi-core processor corresponds to a DC voltage conversion unit and a clock generation unit, and each core in the multi-core processor corresponds to a CAM. Each CAM can independently control its corresponding DC voltage conversion unit and clock generation unit to achieve frequency and power regulation.

[0109] For any small core in a multi-core processor, similar Figure 5 In the situation shown, if the load of the small core is too light in the first time period, the power and frequency of the small core can be reduced to reduce power consumption. The CAM can lower the voltage of the small core through the DC voltage conversion unit to achieve the purpose of reducing power, and lower the clock of the above-mentioned small core in the multi-core processor through the clock generation unit to achieve the purpose of reducing frequency.

[0110] For any large core in a multi-core processor, similar Figure 5 In the situation shown, if the large core is overloaded in the first time period, in order to improve the processing efficiency of the large core, the frequency and power of the large core can be increased. The CAM can increase the voltage of the large core through the DC voltage conversion unit to achieve the purpose of increasing power, and increase the clock of the above-mentioned large core in the multi-core processor through the clock generation unit to achieve the purpose of increasing frequency.

[0111] Optionally, when a core in the many-core processor has an underload or overload in the first time period, the CAM may report the load monitoring result of the corresponding core in the many-core processor to the central management processing core in real time.

[0112] Optionally, each core in the multi-core processor corresponds to a DC voltage conversion unit, a clock generation unit and a CAM. Figure 8 This is a schematic diagram of another multi-core processor load balancing management operation provided in an embodiment of the present application. Figure 8 As shown, there is an independently running central management processing core, which is used to summarize the load of multiple cores in the multi-core processor and perform unified management of the load of the cores in the multi-core processor. Figure 8 In the multi-core processor, each CAM can report the monitoring results of the load of its corresponding core in the above-mentioned processor to the central management processing core in real time. The central management processing core can notify the CAM corresponding to the core to adjust the frequency and power of the core through the DC voltage conversion unit and the clock generation unit based on the load monitoring results of the core in the multi-core processor.

[0113] For any small core in the many-core processor, when the load of the small core is too light in the first time period, the CAM can report the monitoring results of the load of the small core in the many-core processor to the central management processing core in real time. The central management processing core can notify the CAM corresponding to the small core to reduce the voltage of the small core through the DC voltage conversion unit to achieve the purpose of reducing power, and reduce the clock of the above-mentioned small core in the many-core processor through the clock generation unit to achieve the purpose of reducing frequency.

[0114] For any large core in the many-core processor, when the load of the large core is too high within the first time period, the CAM can report the monitoring results of the load of the large core in the many-core processor to the central management processing core in real time. The central management processing core can notify the CAM corresponding to the large core to increase the voltage of the large core through the DC voltage conversion unit to achieve the purpose of increasing power, and increase the clock of the above-mentioned large core in the many-core processor through the clock generation unit to achieve the purpose of increasing frequency.

[0115] Optionally, the multi-core processor corresponds to a DC voltage conversion unit and a clock generation unit. Figure 9A schematic diagram of another multi-core processor load balancing management operation provided in an embodiment of the present application is shown as follows: Figure 9 As shown, the central management processing core can comprehensively consider the loads of all cores and adjust the frequency and power of the multi-core processor through the DC voltage conversion unit and the clock generation unit according to the monitoring results of the core loads.

[0116] It should be understood that if a core in the many-core processor is overloaded or underloaded during the first time period, the monitoring device may further migrate the load on the core to other cores in the many-core processor.

[0117] Figure 10 FIG. 1 is a schematic block diagram of another embodiment of the present application for load balancing management of a multi-core processor, as shown in FIG. Figure 10 As shown, each core in the many-core processor corresponds to a CAM. The CAM can report the load monitoring results of the cores in the many-core processor to the central management processing core in real time. The central management processing core can summarize the load conditions of multiple cores in the many-core processor and migrate the load of the core in the many-core processor if the load of the core in the many-core processor is abnormal within a first time period.

[0118] If any small core in a many-core processor is overloaded during a first time period, the load of the small core can be migrated to a lighter-loaded large core in the many-core processor to improve the processing efficiency of the many-core processor. If any large core in a many-core processor is underloaded during a first time period, the load of the large core can be migrated to a heavier-loaded small core in the many-core processor to reduce power consumption. In this case, the CAM and the central management processing core act as the monitoring devices described above.

[0119] Optionally, if the small cores in the many-core processor are overloaded during the first time period, the CAM can also increase the frequency and power of the middle cores in the processor. If the large cores in the many-core processor are underloaded during the first time period, the CAM can also reduce the frequency and power of the middle cores in the processor.

[0120] Optionally, when a core in the many-core processor has an excessively light or heavy load within a first time period and there are no other cores that can be migrated, the central management processing core may suspend the load tasks on the core.

[0121] In an embodiment of the present application, the monitoring device can use a sliding window strategy to monitor the load of the core in the processor, obtain the activity information of the core in the processor, reduce the monitoring delay of the processor load, improve the response speed of the system, and thereby improve the timeliness of load migration and corresponding frequency adjustment and power consumption adjustment management.

[0122] It should be understood that the size of the serial numbers of the above processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0123] Combined with the above Figures 1 to 10 , describes in detail the processor load monitoring method provided by the embodiment of the present application, and will be combined with the attached Figure 11 and Figure 12 , describes in detail the processor load monitoring device provided in an embodiment of the present application.

[0124] Figure 11 A processor load monitoring device 1100 provided in an embodiment of the present application is shown, including: an acquisition module 1101 and a processing module 1102.

[0125] Among them, the acquisition module 1101 is used to count the working time of the core in the processor in multiple sub-time periods in the first time period, and obtain the first active information of the above-mentioned core in the above-mentioned first time period; the processing module 1102 is used to judge whether the load of the above-mentioned core in the above-mentioned first time period is normal based on the above-mentioned first active information; the above-mentioned acquisition module 1101 is used to count the working time of the above-mentioned core in multiple sub-time periods in the second time period when the load of the above-mentioned core in the above-mentioned first time period is normal, and obtain the second active information of the above-mentioned core in the above-mentioned second time period, the start time of the above-mentioned second time period is the end time of the first sub-time period in the above-mentioned first time period, the start time of the above-mentioned second time period belongs to the above-mentioned first time period, and is delayed by one or more above-mentioned sub-time periods than the above-mentioned first time period; the above-mentioned processing module 1102 is used to judge whether the load of the above-mentioned core in the above-mentioned second time period is normal based on the above-mentioned second active information.

[0126] Optionally, the first activity information is the average activity of the core in the first time period, and the average activity is calculated based on the following formula:

[0127]

[0128] Wherein, N is the number of the above sub-time periods contained in the above first time period, t i is the working time of the core in the i-th sub-time period of the first time period, T i is the duration of the i-th sub-time period in the above-mentioned first time period.

[0129] Optionally, the processing module 1102 is used to determine that the core is overloaded during the first time period if the first activity information is greater than a first threshold value; if the first activity information is less than a second threshold value, determine that the core is too lightly loaded during the first time period; or, if the first activity information is greater than or equal to the second threshold value and less than or equal to the first threshold value, determine that the core is normally loaded during the first time period, and the first threshold value is greater than the second threshold value.

[0130] Optionally, the above-mentioned processor is a single-core processor, and the processing module 1102 is used to increase the frequency and power of the above-mentioned processor if the above-mentioned core is overloaded during the above-mentioned first time period; or, if the above-mentioned core is too lightly loaded during the above-mentioned first time period, reduce the frequency and power of the above-mentioned processor.

[0131] Optionally, the above-mentioned processor is a multi-core processor, and the above-mentioned core is a small core. The processing module 1102 is used to migrate the load on the above-mentioned core to the large core in the above-mentioned processor if the above-mentioned core is overloaded during the above-mentioned first time period; or, to increase the frequency and power of the above-mentioned core; if the above-mentioned core is too lightly loaded during the above-mentioned first time period, to reduce the frequency and power of the above-mentioned core.

[0132] Optionally, the above-mentioned processor is a multi-core processor, and the above-mentioned core is a large core. The processing module 1102 is used to migrate the load on the above-mentioned core to the small core in the above-mentioned processor if the load on the above-mentioned core is too light during the above-mentioned first time period, or to reduce the frequency and power of the above-mentioned core; if the load on the above-mentioned core is heavily during the above-mentioned first time period, to increase the frequency and power of the above-mentioned core.

[0133] It should be understood that the device 1100 here is embodied in the form of a functional module. The term "module" here can refer to an application specific integrated circuit (ASIC), an electronic circuit, a processor (such as a shared processor, a dedicated processor or a group processor, etc.) and a memory for executing one or more software or firmware programs, a combined logic circuit and / or other suitable components that support the described functions. In an optional example, those skilled in the art will understand that the device 1100 can be specifically the monitoring device in the above-mentioned embodiment, or the functions of the monitoring device in the above-mentioned embodiment can be integrated into the device 1100, and the device 1100 can be used to execute the various processes and / or steps corresponding to the monitoring device in the above-mentioned method embodiment. To avoid repetition, they will not be described here.

[0134] The apparatus 1100 has the function of implementing the corresponding steps executed by the monitoring device in the above method; the above functions can be implemented by hardware, or by hardware executing corresponding software. The hardware or software includes one or more modules corresponding to the above functions.

[0135] In the embodiments of this application, Figure 11 The device 1100 may also be a chip or a chip system, such as a system on chip (SoC).

[0136] Figure 12 Another processor load monitoring device 1200 provided in an embodiment of the present application is shown. Device 1200 includes a processor 1201, a memory 1202, a communication interface 1203, and a bus 1204. Memory 1202 is configured to store instructions, and processor 1201 is configured to execute the instructions stored in memory 1202. Processor 1201, memory 1202, and communication interface 1203 are communicatively connected to each other via bus 1204.

[0137] Among them, processor 1201 is used to count the working time of the core in the processor in multiple sub-time periods in the first time period, and obtain the first activity information of the above-mentioned core in the above-mentioned first time period; based on the above-mentioned first activity information, judge whether the load of the above-mentioned core in the above-mentioned first time period is normal; when the load of the above-mentioned core in the above-mentioned first time period is normal, count the working time of the above-mentioned core in multiple sub-time periods in the second time period, and obtain the second activity information of the above-mentioned core in the above-mentioned second time period, the start time of the above-mentioned second time period belongs to the first time period, and is delayed by one or more sub-time periods than the first time period; and, based on the above-mentioned second activity information, judge whether the load of the above-mentioned core in the above-mentioned second time period is normal.

[0138] It should be understood that the device 1200 can be specifically the monitoring device in the above-mentioned embodiment, or the functions of the monitoring device in the above-mentioned embodiment can be integrated into the device 1200, and the device 1200 can be used to execute the various steps and / or processes corresponding to the monitoring device in the above-mentioned method embodiment. Optionally, the memory 1202 may include a read-only memory and a random access memory, and provide instructions and data to the processor. A portion of the memory may also include a non-volatile random access memory. For example, the memory may also store information about the device type. The processor 1201 can be used to execute the instructions stored in the memory, and when the processor executes the instructions, the processor can execute the various steps and / or processes corresponding to the monitoring device in the above-mentioned method embodiment.

[0139] It should be understood that in the embodiments of the present application, the processor may be a central processing unit (CPU), or may be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or any conventional processor.

[0140] During implementation, each step of the above method can be completed by an integrated logic circuit of hardware in a processor or by instructions in the form of software. The steps of the method disclosed in conjunction with the embodiments of the present application can be directly embodied as being executed by a hardware processor, or can be executed by a combination of hardware and software modules in the processor. The software module can be located in a storage medium mature in the art, such as a random access memory, a flash memory, a read-only memory, a programmable read-only memory, or an electrically erasable programmable memory, a register, etc. The storage medium is located in a memory, and the processor executes the instructions in the memory, and completes the steps of the above method in conjunction with its hardware. To avoid repetition, it will not be described in detail here.

[0141] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0142] Those skilled in the art will clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0143] In the several embodiments provided in this application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are merely schematic. For example, the division of the units is merely a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0144] The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0145] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0146] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0147] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A method for monitoring processor load, characterized in that: include: counting working hours of cores in the processor in a plurality of sub-time periods within the first time period, respectively, to obtain first activity information of the cores in the first time period; determining, based on the first activity information, whether the load of the core is normal during the first time period; When the load of the core is normal during the first time period, counting the working hours of the core in multiple sub-time periods of a second time period to obtain second activity information of the core in the second time period, where the start time of the second time period falls within the first time period and the second time period is later than the first time period by one or more sub-time periods; Based on the second activity information, it is determined whether the load of the core is normal during the second time period.

2. The method according to claim 1, characterized in that The first activity information is the average activity of the core in the first time period, and the average activity is calculated based on the following formula: Wherein, N is the number of the sub-time periods contained in the first time period, t i is the working time of the core in the i-th sub-time period of the first time period, T i is the duration of the i-th sub-time period in the first time period.

3. The method according to claim 1 or 2, characterized in that The determining, based on the first activity information, whether the load of the core is normal during the first time period includes: If the first activity information is greater than a first threshold, determining that the core is overloaded during the first time period; If the first activity information is less than a second threshold value, it is determined that the core is underloaded during the first time period; or, If the first activity information is greater than or equal to the second threshold value and less than or equal to the first threshold value, it is determined that the core load is normal within the first time period and the first threshold value is greater than the second threshold value.

4. The method according to claim 3, characterized in that The processor is a single-core processor, and the method further includes: If the core is overloaded during the first time period, increasing the frequency and power of the processor; or If the core is underloaded during the first time period, the frequency and power of the processor are reduced.

5. The method according to claim 3, characterized in that The processor is a many-core processor, the core is a small core, and the method further includes: If the core is overloaded during the first time period, migrating the load on the core to a large core in the processor, or increasing the frequency and power of the core; If the core is underloaded during the first time period, the frequency and power of the core are reduced.

6. The method according to claim 3, characterized in that The processor is a many-core processor, the core is a large core, and the method further includes: If the core is underloaded during the first time period, migrating the load on the core to a small core in the processor, or reducing the frequency and power of the core; If the core is heavily loaded during the first time period, the frequency and power of the core are increased.

7. A processor load monitoring device, characterized in that: include: An acquisition module, configured to count working hours of cores in the processor in a plurality of sub-time periods within a first time period, and obtain first activity information of the cores in the first time period; a processing module, configured to determine whether the load of the core is normal during the first time period based on the first activity information; The acquisition module is further configured to, when the load of the core is normal during the first time period, respectively count the working hours of the core in a plurality of sub-time periods in a second time period to obtain second activity information of the core in the second time period, wherein a start time of the second time period falls within the first time period and the second time period is later than the first time period by one or more of the sub-time periods; The processing module is further configured to determine whether the load of the core is normal within the second time period based on the second activity information.

8. The device according to claim 7, characterized in that The first activity information is the average activity of the core in the first time period, and the average activity is calculated based on the following formula: Wherein, N is the number of the sub-time periods contained in the first time period, t i is the working time of the core in the i-th sub-time period of the first time period, T i is the duration of the i-th sub-time period in the first time period.

9. The device according to claim 7 or 8, characterized in that The processing module is configured to: determine that the core is overloaded during the first time period if the first activity information is greater than a first threshold; If the first activity information is less than a second threshold, determining that the core is underloaded during the first time period; or, If the first activity information is greater than or equal to the second threshold value and less than or equal to the first threshold value, it is determined that the core load is normal within the first time period and the first threshold value is greater than the second threshold value.

10. The device according to claim 9, characterized in that The processor is a single-core processor, and the processing module is used for: If the core is overloaded during the first time period, increasing the frequency and power of the processor; or If the core is underloaded during the first time period, the frequency and power of the processor are reduced.

11. The device according to claim 9, characterized in that The processor is a many-core processor, the core is a small core, and the processing module is used to: If the core is overloaded during the first time period, migrating the load on the core to a large core in the processor; or increasing the frequency and power of the core; If the core is underloaded during the first time period, the frequency and power of the core are reduced.

12. The device according to claim 9, characterized in that The processor is a multi-core processor, the core is a large core, and the processing module is used to: If the core is underloaded during the first time period, migrating the load on the core to a small core in the processor, or reducing the frequency and power of the core; If the core is heavily loaded during the first time period, the frequency and power of the core are increased.

13. A processor load monitoring device, characterized in that: include: A processor is coupled to a memory, wherein the memory is used to store a computer program, and when the processor calls the computer program, the device is caused to execute the method according to any one of claims 1 to 6.

14. A computer-readable storage medium, characterized in that Used to store a computer program, the computer program comprising instructions for implementing the method according to any one of claims 1 to 6.

15. A computer program product, comprising computer program code, characterized in that: When the computer program code is run on a computer, the computer is caused to implement the method according to any one of claims 1 to 6.

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