Semiconductor structure and method of manufacturing the same

Abstract

Semiconductor structures and methods of manufacturing the same are provided. A semiconductor structure according to the present invention includes a transistor and an interconnect structure disposed above the transistor. The interconnect structure includes a first dielectric layer, a first conductive feature located in the first dielectric layer, a first etch stop layer (ESL) disposed above the first dielectric layer and the first conductive feature, a dielectric feature disposed in the first ESL, an electrode disposed above the dielectric feature, and a second ESL disposed above the first ESL and the electrode.

Description

Technical Field

[0001] Embodiments of the present invention relate to a semiconductor structure and a method for manufacturing the same. Background Technology

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advancements in IC materials and design have led to several generations of ICs, each featuring smaller and more complex circuitry than the previous generation. Throughout IC evolution, functional density (the number of interconnect devices per area of ​​a chip) has generally increased, while its geometry (the smallest element (or line) that can be manufactured using a manufacturing process) has decreased. This scaling down generally benefits production efficiency and reduces associated costs. However, this scaling down also increases the complexity of processing and manufacturing ICs.

[0003] The ever-shrinking size of high-voltage devices poses a challenge to their fabrication, such as one-time programmable (OTP) memories. Larger high-voltage devices can lead to topology issues and potentially compress space for other components. The higher operating voltages of high-voltage devices can also break down the gate oxide layer, resulting in unintended device activation. Therefore, while OTP memory structures are generally sufficient for their intended purpose, they are not entirely satisfactory. Summary of the Invention

[0004] According to one aspect of the present invention, a semiconductor structure is provided, comprising: a transistor; and an interconnect structure disposed above the transistor.

[0005] The interconnect structure includes: a first dielectric layer; a first conductive component located in the first dielectric layer; a first etch stop layer (ESL) disposed above the first dielectric layer and the first conductive component; a dielectric component disposed in the first ESL; an electrode disposed above the dielectric component; and a second ESL disposed on the first ESL and the electrode.

[0006] According to another aspect of the present invention, a semiconductor structure is provided, comprising: a transistor; an interlayer dielectric (ILD) layer disposed above the transistor; a first conductive component located in the ILD layer; a first etch stop layer (ESL) disposed above the ILD layer and the first conductive component; a high-k dielectric component disposed in the first ESL; a metal component disposed above the high-k dielectric component; and a second ESL disposed on the first ESL and the metal component.

[0007] According to another aspect of the present invention, a method for manufacturing a semiconductor structure is provided, comprising: receiving a workpiece,

[0008] The workpiece includes: a transistor, an interlayer dielectric (ILD) layer disposed above the transistor, a first conductive component located in the ILD layer, a first etch stop layer (ESL) disposed above the ILD layer and the first conductive component, and a second ESL disposed on the first ESL;

[0009] An opening is formed through the second ESL and the first ESL to expose the first conductive component; a high-k dielectric layer is deposited over the opening; a metal layer is deposited over the high-k dielectric layer; the workpiece is planarized to remove the high-k dielectric layer and the metal layer over the top surface of the second ESL; and a contact via is formed after planarization to couple to the top surface of the metal layer. Attached Figure Description

[0010] The various aspects of the invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, the various components are not drawn to scale. In fact, the dimensions of the various components may be arbitrarily increased or decreased for clarity of discussion. It should also be emphasized that the accompanying drawings illustrate only typical embodiments of the invention and should therefore not be considered as limiting the scope, as the invention is equally applicable to other embodiments.

[0011] Figure 1 This is a flowchart illustrating a method for manufacturing a semiconductor structure according to various aspects of the present invention.

[0012] Figures 2 to 9 The basis for various aspects of the invention is shown. Figure 1 The method involves schematic partial cross-sectional views of the workpiece at each manufacturing stage.

[0013] Figure 10 It represents Figure 9 The circuit diagram of the semiconductor structure is shown.

[0014] Figures 11 to 13 The use of various aspects of the invention is shown. Figure 1 A schematic top view of a one-time programmable (OTP) memory device manufactured using this method.

[0015] Figures 14 to 15 The use of various aspects of the invention is shown. Figure 1 A schematic partial cross-sectional view of an alternative semiconductor structure fabricated using this method.

[0016] Figures 16 to 19 The use of various aspects of the invention is shown. Figure 1 A schematic top view of a high-resistance (Hi-R) device or high-resistance (Hi-R) resistor manufactured using this method.

[0017] Figure 20Semiconductor structures comprising both OTP memory devices and high-resistivity (Hi-R) devices according to various aspects of the present invention are shown. Detailed Implementation

[0018] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the invention. Of course, these are merely examples and are not intended to limit the invention. For example, in the following description, forming a first component above or on a second component can include embodiments where the first and second components are in direct contact, and can also include embodiments where an additional component can be formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, reference numerals and / or characters may be repeated in various instances of the invention. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0019] Furthermore, for ease of description, spatial relative terms such as "below," "under," "lower," "above," and "upper" may be used to describe the relationship between one element or component and another (or other elements or components) as shown in the figure. In addition to the orientation shown in the figure, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0020] Furthermore, as those skilled in the art will understand, when using terms such as "about," "approximately," etc., to describe numerical values ​​or ranges, the term is intended to encompass values ​​within a reasonable range, taking into account variations inherent during manufacturing. For example, based on known manufacturing tolerances associated with a manufactured part, the part has characteristics associated with a numerical value, and the numerical value or range encompasses a reasonable range including the described numerical value, such as within + / -10% of the described numerical value. For example, a material layer with a thickness of "about 5 nm" may cover a size range of 4.25 nm to 5.75 nm, where a manufacturing tolerance associated with the deposited material layer is known to those skilled in the art to be + / -15%. Furthermore, the present invention may repeat reference numerals and / or letters in various instances. Such repetition is for the purpose of brevity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0021] Semiconductor memory devices are generally classified into two types—volatile memory devices and non-volatile memory devices. Volatile memory devices lose their stored information when power is lost. Conversely, non-volatile memory devices retain their stored information even after power is lost. Non-volatile memory devices can be further divided into two subcategories: Multiple-Programmable-Package (MTP) memory devices allow for multiple programming operations. One-Time Programmable-Package (OTP) memory devices allow only one irreversible programming operation. In some existing technologies, transistor structures formed in the front-end process (FEOL) can be used to form OTP memory devices. In existing technologies, the gate dielectric layer can serve as a fuse element or a programming element. However, as semiconductor devices continue to shrink in size, using transistor structures to form OTP memory devices while still maintaining satisfactory high voltage tolerance or reliability may become challenging.

[0022] This invention provides a method for forming an OTP memory device together with a high-resistance (Hi-R) resistor in an interconnect structure formed during a back-to-end (BEOL) process. The OTP memory device of this invention includes a metal-insulator-metal (MIM) structure and a U-shaped breakdown layer surrounding a top electrode component. According to this invention, forming the OTP memory device and Hi-R resistor in a BEOL structure reduces circuit area and lowers manufacturing costs associated with photomasks.

[0023] Various aspects of the invention will now be described in more detail with reference to the accompanying drawings. In this regard, Figure 1 This is a flowchart illustrating a method 100 for forming a semiconductor structure according to an embodiment of the present invention. Method 100 is merely an example and is not intended to limit the invention to what is explicitly shown in method 100. Additional steps may be provided before, during, and after these methods, and some steps described may be replaced, eliminated, or moved for additional embodiments of method 100. For simplicity, not all steps are described in detail herein. The following is in conjunction with... Figures 2 to 9 Description method 100, Figures 2 to 9 This is a partial cross-sectional view of the workpiece 200 at different manufacturing stages according to an embodiment of method 100. Because the workpiece 200 will be manufactured into a semiconductor structure or semiconductor device at the end of the manufacturing process, the workpiece 200 may also be referred to as semiconductor structure 200 or semiconductor device 200 as the context requires. Furthermore, throughout this application, unless otherwise stated, the same reference numerals denote the same parts.

[0024] refer to Figure 1 and Figure 2 Method 100 includes a frame 102 for receiving workpiece 200. For example... Figure 2As shown, workpiece 200 may include substrate 202 and interconnect structure 300 disposed above substrate 202. Substrate 202 may be a silicon (Si) substrate. In some other embodiments, substrate 202 may include other semiconductors, such as germanium (Ge), silicon germanium (SiGe), or III-V semiconductor materials. Examples of III-V semiconductor materials may include gallium arsenide (GaAs), indium phosphide (InP), gallium phosphide (GaP), gallium nitride (GaN), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), indium gallium gallium phosphide (GaInP), and indium gallium arsenide (InGaAs). Substrate 202 may also include an insulating layer, such as a silicon oxide layer, to have a silicon-on-insulator (SOI) structure.

[0025] Workpiece 200 also includes a transistor 260 formed on substrate 202. Transistor 260 may be a multi-gate device, such as a FinFET or a multi-bridge channel (MBC) transistor. In a FinFET, the high-side channel is surrounded by a gate over multiple sides (e.g., the gate wraps around the top and sidewalls of a semiconductor material “fin” extending from the substrate). The gate structure of an MBC transistor may extend partially or entirely around the channel region to provide access to the channel regions on both sides or more sides. Because the gate structure of an MBC transistor surrounds the channel region, it may also be referred to as a gate-around-the-side (SGT) transistor or a gate-all-around (GAA) transistor. The channel region of an MBC transistor may take the form of a nanowire, nanosheet, or other nanostructure, and therefore, it may also be referred to as a nanowire transistor or a nanosheet transistor. Figure 2 As shown, transistor 260 includes a source component 208S, a drain component 208D, an active region 203 disposed between the source component 208S and the drain component 208D, a gate dielectric layer 204 disposed above the active region 203, and a gate electrode 206 disposed above the gate dielectric layer 204. Depending on the type of transistor 260, the active region 203 may have a fin shape or may have multiple channel members extending between the source component 208S and the drain component 208D. The detailed structure of the active region 203 may not be explicitly shown in the figure.

[0026] Transistor 260 can be n-type or p-type. When transistor 260 is n-type, source component 208S and drain component 208D may comprise silicon (Si) and n-type dopants such as phosphorus (P) or arsenic (As). When transistor 260 is p-type, source component 208S and drain component 208D may comprise silicon germanium (SiGe) and p-type dopants such as boron (b) or boron difluoride (BF2). In one embodiment, gate dielectric layer 204 may comprise hafnium oxide, or other suitable high-k dielectric material with a dielectric constant greater than that of silicon dioxide (about 3.9). Gate electrode 206 may comprise a single layer or an optional multilayer structure, such as various combinations of metal-filled layers and multiple work function metal layers. For example, gate electrode 206 may comprise titanium nitride (TiN), titanium aluminum (TiAl), titanium aluminum nitride (TiAlN), tantalum nitride (TaN), tantalum aluminum (TaAl), tantalum aluminum nitride (TaAlN), tantalum aluminum carbide (TaAlC), tantalum carbonitride (TaCN), aluminum (Al), tungsten (W), nickel (Ni), titanium (Ti), ruthenium (Ru), cobalt (Co), platinum (Pt), tantalum carbide (TaC), tantalum silicon nitride (TaSiN), copper (Cu), other refractory metals or other suitable metallic materials or combinations thereof. Gate dielectric layer 204 and gate electrode 206 may be collectively referred to as gate structure. Transistor 260 may be configured as a logic device or select transistor for an OTP memory device. When transistor 260 is used as a select transistor for an OTP memory device, gate electrode 206 is coupled to word line (WL) and source component 208S is coupled to source line (SL).

[0027] Workpiece 200 includes end-of-line process (MEOL) components to electrically connect transistors to interconnect structure 300. In the depicted embodiment, transistor 260 in workpiece 200 includes a source contact 210S above source component 208S, a drain contact 210D above drain component 208D, a source contact via 212S disposed on source contact 210S, and a drain contact via 212D disposed on drain contact 210D. Each of source contact 210S, drain contact 210D, source contact via 212S, and drain contact via 212D may include a metal filler layer formed of ruthenium (Ru), tungsten (W), cobalt (Co), nickel (Ni), copper (Cu), or molybdenum (Mo). In some embodiments, each of the source contact 210S, drain contact 210D, source contact via 212S, and drain contact via 212D may further include a barrier layer to prevent unwanted oxygen diffusion or electromigration. When formed, the barrier layer may comprise titanium nitride or tantalum nitride. Although not explicitly shown in the figures, the source contact 210S, drain contact 210D, source contact via 212S, and drain contact via 212D are disposed in at least one interlayer dielectric (ILD) layer. The at least one ILD layer may comprise tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass, or doped silicon oxide, such as borosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron-doped silicon glass (BSG), and / or other suitable dielectric materials.

[0028] Interconnect structure 300 is formed in a BEOL process and is considered a BEOL structure. Interconnect structure 300 may include multiple interconnect layers. Each interconnect layer includes conductive lines and contact vias disposed in an intermetallic dielectric (IMD) layer. Conductive lines and contact vias may include aluminum (Al), tungsten (W), nickel (Ni), ruthenium (Ru), cobalt (Co), copper (Cu), or combinations thereof. The IMD layer may include tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass, or doped silicon oxide, such as borosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron-doped silica glass (BSG), and / or other suitable dielectric materials. The dielectric materials of the ILD and IMD layers are low-k dielectric materials, with a dielectric constant less than that of silicon dioxide (approximately 3.9). The low dielectric constant of the ILD and IMD layers helps to reduce parasitic capacitance between adjacent conductive components.

[0029] In some embodiments, the fully formed interconnect structure 300 may include about eight and about sixteen interconnect layers. Figure 2In the depicted embodiment, the interconnect structure 300 includes a first conductive line 214 located above and in direct contact with the drain contact via 212D. The first conductive line 214 is located in the bottom interconnect layer of the interconnect structure 300. A second conductive line 220 is disposed above the first conductive line 214 and may be a conductive line in an intermediate interconnect layer, which is above the bottom interconnect layer of the interconnect structure but below the top interconnect layer. For example, when the interconnect structure 300 includes 10 interconnect layers, the second conductive line 220 may be any one of the second, third, fourth, fifth, sixth, seventh, eighth, or ninth interconnect layers. The first conductive line 214 may be coupled to the upper interconnect layers through a first contact via 216. Figure 2 As shown, the second conductive line 220 and other conductive lines in the same interconnect layer are disposed in the first IMD layer 218, which may include tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass or doped silicon oxide, such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron-doped silica glass (BSG) and / or other suitable dielectric materials.

[0030] Conductive lines and contact vias in different interconnect layers can have different dimensions. In some instances, the first four or five interconnect layers closer to the FEOL structure may have smaller dimensions, while the upper interconnect layers may have larger dimensions. As will be described below, the operations of method 100 will be performed above the second conductive line 220 in the intermediate interconnect layer. It is economical to have intermediate interconnect layers with larger conductive components because performing photolithography and etching processes on such higher layers requires lower precision and has higher tolerance. The presence of other BEOL structures is another factor in determining which interconnect layer to perform method 100 on. Having a high density of BEOL structures in an interconnect layer may increase process complexity and potentially reduce yield.

[0031] refer to Figure 1 , Figure 2 and Figure 3 Method 100 includes a block 104 in which a first etch stop layer (ESL) 222 and a second ESL 224 are deposited over a workpiece 200. The composition of the first ESL 222 is different from that of the second ESL 224. In some embodiments, the first ESL 222 may be a nitrogen-containing layer and the second ESL 224 may be an oxygen-containing layer. The second ESL 224 is disposed on the first ESL 222. The first ESL 222 may include silicon nitride, silicon oxynitride, or silicon carbonitride. The second ESL 224 may include silicon oxide. Figure 2 The dashed rectangular area in the image is enlarged and... Figure 3 As shown in the figure, Figure 3 This is also a partial cross-sectional view of workpiece 200. For example... Figure 3 As shown, the first total thickness TT1 of the first ESL 222 and the second ESL 224 along the Z direction can be between approximately 50 nm and approximately 1000 nm. In the depicted embodiment, the second thickness T2 of the second ESL 224 is approximately [missing information - likely a number] times greater than the first thickness T1 of the first ESL 222. to approximately This allows the second ESL 224 to have sufficient thickness to withstand the planarization process. In some instances, the second thickness T2 of the second ESL 224 can be between approximately 130 nm and approximately 400 nm. The first thickness T1 of the first ESL 222 can be between approximately 10 nm and approximately 100 nm. If the first thickness T1 is less than 10 nm, it may not provide a sufficient etch rate difference signal to allow for etch endpoint detection. If the first thickness T1 is greater than 100 nm, breaking through the first ESL 222 may cause undesirable damage to the second ESL 224. The ratio of the second thickness T2 to the first thickness T1 can be between approximately 4 and approximately 15. At block 104, chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), or atomic layer deposition (ALD) can be used to deposit the first ESL 222 and the second ESL 224. It should be noted that, depending on the process, different interconnect layers may have different numbers of etch stop layers. Although Figure 3 Two etch stop layers are not shown, but the invention is not limited thereto, and workpiece 200 may include three or even four etch stop layers. Details of embodiments with more etch stop layers are omitted.

[0032] refer to Figure 1 and Figure 4Method 100 includes a frame 106 in which an opening 226 is formed in a workpiece 200 to expose a second conductive line 220. In an example process, spin coating is used to deposit a photoresist layer over a second ESL 224. After the photoresist layer is deposited, photolithography and etching processes are performed to pattern the photoresist layer. The patterned photoresist layer is then used as an etching mask in the etched workpiece 200 (including the second ESL 224 and the first ESL 222) to form the opening 226. At block 106, the first ESL 222 and the second ESL 224 can be anisotropically etched using a reactive ion etching (RIE) process. This process uses oxygen, hydrogen, fluorine-containing gases (e.g., CF4, NF3, SF6, CH2F2, CHF3, and / or C2F6), hydrocarbons (e.g., methane), chlorine-containing gases (e.g., Cl2, CHCl3, CCl4, and / or BCl3), bromine-containing gases (e.g., HBr and / or CHBr3), iodine-containing gases, other suitable gases and / or plasma, and / or combinations thereof. In some implementations, the etching process at block 106 can be time-controlled to stop when a portion of the second conductive line 220 is exposed. Here, as will be described below, the exposed portion of the second conductive line 220 can be considered as the bottom electrode. Figure 4 As shown, the second conductive line 220 may have a first width W1 along the X direction, while the opening 226 may have a second width W2 along the X direction. The second width W2 may be equal to, greater than, or less than the first width W1 to meet different breakdown voltage requirements of the OTP memory device to be formed. When everything else remains constant, a larger second width W2 may result in a lower breakdown voltage because more detection and defects may be present in the larger area, potentially leading to breakdown paths. Each of the first width W1 and the second width W2 may be between approximately 50 nm and approximately 500 nm.

[0033] refer to Figure 1 and Figure 5Method 100 includes a block 108 in which a breakdown layer 228 is located above an interconnect structure 300. The breakdown layer 228 includes a high-k dielectric layer with a dielectric constant greater than that of silicon dioxide (approximately 3.9). In some embodiments, the breakdown layer 228 may include hafnium oxide (HfO), aluminum oxide (AlO), aluminum nitride (AlN), titanium oxide (TiO), hafnium zirconium oxide (HfZrO), tantalum oxide (TaO), hafnium aluminum oxide (HfAlO), hafnium silicon oxide (HfSiO), zirconium oxide (ZrO), zirconium oxide (ZrSiO), lanthanum oxide (LaO), yttrium oxide (YO), strontium titanium oxide (SrTiO), barium titanium barium oxide (BaTiO), barium zirconium oxide (BaZrO), lanthanum hafnium oxide (HfLaO), lanthanum silicon oxide (LaSiO), aluminum silicon oxide (AlSiO), hafnium tantalum oxide (HfTaO), and hafnium titanium oxide (HfTiO). In one embodiment, the breakdown layer 228 may be formed of aluminum oxide (AlO), hafnium oxide (HfO), or aluminum nitride (AlN). The breakdown layer 228 may be deposited using ALD, PECVD, or CVD. Depending on the design, the thickness of the breakdown layer 228 can be between approximately With the agreement Between. Assuming the breakdown layers 228 have the same mass and a fixed area, the thickness of the breakdown layer 228 essentially determines the breakdown voltage of the OTP memory device it forms. For example, when the breakdown layer 228 has approximately When the thickness is such that the breakdown voltage of the breakdown layer 228 (or the OTP memory device formed therefrom) is between approximately 1.5V and approximately 2V, the breakdown voltage of the breakdown layer 228 is between approximately 1.5V and approximately 2V. When the thickness of the breakdown layer 228 is less than [a certain value], the breakdown voltage of the breakdown layer 228 is between approximately 1.5V and approximately 2V. The breakdown layer 228 may have experienced premature breakdown at voltages below the design voltage. When the thickness of the breakdown layer 228 is greater than... At that time, the breakdown voltage of the breakdown layer 228 may be higher than the maximum operating voltage of the semiconductor device 200.

[0034] refer to Figure 1 and Figure 6Method 100 includes block 110, in which a top electrode layer 230 is deposited over opening 226. The top electrode layer 230 may comprise a metal or a conductive metal nitride. In some embodiments, the top electrode layer 230 may comprise titanium nitride (TiN), tantalum nitride (TaN), tungsten (W), nickel (Ni), titanium (Ti), ruthenium (Ru), cobalt (Co), copper (Cu), other refractory metals, or other suitable metallic materials or combinations thereof. The top electrode layer 230 may be deposited over the breakdown layer 228 and opening 226 by ALD, PVD, CVD, electron beam evaporation, or other suitable processes. In some embodiments, the top electrode layer 230 may be used as a resistive element of a high-resistance resistor. In those embodiments, the top electrode layer 230 may be formed of a weakly conductive material such as tantalum nitride (TaN), and the composition of the top electrode layer 230 may differ from the composition of the second conductive line 220. Alternatively, when the top electrode layer 230 is used as a resistive element and is formed of a relatively highly conductive material such as tungsten (W) or cobalt (Co), the opening 226 may have an elongated shape to have a desired resistance value.

[0035] refer to Figure 1 and Figure 7 Method 100 includes block 112, in which workpiece 200 is planarized to form top electrode 230. After depositing top electrode layer 230, a planarization process such as CMP can be performed to remove excess material, thereby providing a substantially flat top surface. Figure 7 As shown, planarization at block 112 is performed until all breakdown layers 228 and top electrode layers 230 are removed from the top surface of the second ESL 224. In some implementations, planarization at block 112 is also intended to reduce the total thickness of the first ESL 222 and the second ESL 224 from... Figure 3 The first total thickness TT1 shown is reduced to Figure 7 The smaller second total thickness TT2 is shown. Specifically, the flattening at frame 112 reduces the second thickness T2 of the second ESL 224 to a third thickness T3, which can be between approximately With the agreement Between. As mentioned above, the first thickness T1 can be between approximately With the agreement In some instances, the ratio of the third thickness T3 to the first thickness T1 can be between approximately 1 and 3. The first thickness T1 represents the thickness of the breakdown layer 228 and substantially determines the breakdown voltage of the OTP memory device formed thereon. When the first thickness T1 is less than... At this time, the breakdown layer 228 may break down prematurely below the design voltage. When the first thickness T1 is greater than At this time, the breakdown voltage of the breakdown layer 228 may be higher than the highest operating voltage of the semiconductor device 200. In some instances, the second total thickness TT2 may be between about 50 nm and about 500 nm. That is, planarization at block 112 is performed to substantially reduce the total thickness of the first ESL 222 and the second ESL 224 by approximately to approximately The reduction in the total thickness of the first ESL 222 and the second ESL 224 prevents the interconnect layer (where the second conductive line 220 is located) from becoming too thick to be integrated into the interconnect structure 300. For example... Figure 7 As shown, the top electrode 230 is disposed in the breakdown layer 228, which is U-shaped when viewed along the Y direction. The sidewalls and bottom surface of the top electrode 230 are surrounded by the breakdown layer 228, thereby separating the top electrode 230 from the second ESL 224, the first ESL 222, the first IMD layer 218, and the second conductive line 220.

[0036] refer to Figure 1 and Figure 8 Method 100 includes a frame 114 in which a third ESL 232 and a second IMD layer 234 are deposited over a workpiece 200. In some embodiments, the third ESL 232 may comprise a nitrogen-containing dielectric material, such as silicon nitride, silicon oxycarbonitride, or silicon carbonitride. The second IMD layer 234 may comprise materials such as tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass, or doped silicon oxide, such as borosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), borosilicate glass (BSG), and / or other suitable dielectric materials. The third ESL 232 may be deposited using ALD or CVD. The second IMD layer 234 may be deposited using spin coating, flowable CVD (FCVD), or other suitable deposition techniques.

[0037] Still referencing Figure 1 and Figure 8Method 100 includes a frame 116 in which an OTP contact via 236 is formed to couple to a top electrode 230, and a third conductive line 238 is formed to couple to the OTP contact via 236. In some embodiments, a dual damascene process may be used at frame 116 to form the contact via and the conductive line. In the depicted embodiment, the OTP contact via 236 is formed through a third ESL 232 and a second IMD layer 234 to couple to the top electrode 230, the third conductive line 238 is formed over the OTP contact via 236, a second contact via 240 is formed to couple to another conductive line 221 in a first IMD layer 218, and a fourth conductive line 242 is formed over the second contact via 240. In an example process, the second IMD layer 234 undergoes two patterning processes to form a contact via opening and a trench above the contact via opening. A liner and a seed layer are then deposited in the contact via opening and the trench. In some instances, the liner may comprise titanium nitride and the seed layer may comprise titanium. Then, electroplating is used to deposit conductive materials, such as aluminum (Al), tungsten (W), nickel (Ni), ruthenium (Ru), cobalt (Co), and copper (Cu), into the contact vias and trenches. Figure 8 As shown, the OTP contact via 236 is in direct contact with the top electrode 230, and the third conductive line 238 is in direct contact with the OTP contact via 236. The second contact via 240 extends through the first ESL 222, the second ESL 224, the third ESL 232, and the second IMD layer 234 to couple to another conductive line 221 in the first IMD layer 218. A fourth conductive line 242 is disposed on the second contact via 240. Although the conductive lines and contact vias in the second IMD layer 234 may have similar compositions, their shapes differ, such as... Figure 8 As shown. It should be noted that both the third conductive line 238 and the fourth conductive line 242 extend longitudinally along the Y direction. Figure 8 In the embodiment shown, along the Z direction, the height of the second contact via 240 is greater than the height of the OTP contact via 236 by a second total thickness TT2.

[0038] Still referencing Figure 1 and Figure 9 The method includes block 118 for performing additional processing. Such additional processing may include planarizing the workpiece 200 and forming additional interconnect layers over the dielectric layer 248. Figure 9In the illustrated embodiment, an additional process at block 118 may form a third contact via 244 above the third conductive line 238, and a fifth conductive line 246 may be disposed above the third contact via 244. Similar to the OTP contact via 236 and the third conductive line 238, the third contact via 244 and the fifth conductive line 246 are disposed in an IMD layer (omitted) above the second IMD layer 234. In some embodiments, the fifth conductive line 246 may be used as a bit line of an OTP memory device. The third contact via 244 and the fifth conductive line 246 are also part of the interconnect structure 300.

[0039] At the end of the operation of box 118, OTP storage device 400 (or OTP memory cell or OTP antifuse cell) is formed. Figure 9 As shown, the OTP memory device 400 includes a fusible link, a gate electrode 206 serving as a word line, and a fifth conductive line 246 serving as a bit line. The fusible link includes a second conductive line 220 (i.e., the bottom electrode), a breakdown layer 228, and a top electrode 230. The OTP memory device 400 is selected when a voltage greater than the threshold voltage of transistor 260 is applied at the gate electrode 206. When a high-resistance state is written, the voltage across the fifth conductive line 246 (i.e., the bit line) is 0V. Because the voltage applied across the breakdown layer 228 is 0V, the breakdown layer 228 remains intact and has high resistance. When a low-resistance state is to be written, a breakdown voltage, such as 2V, is applied across the fifth conductive line 246 (i.e., the bit line). The breakdown voltage can be controlled by an input / output (I / O) transistor. This high voltage will cause the breakdown layer 228 to break down, resulting in electrical connection between the top electrode 230 and the second conductive line 220 (i.e., the bottom electrode). Those skilled in the art will recognize that a high-resistance state or a low-resistance state can be represented as state "0" or "1," depending on design preference. During a read operation, a voltage is applied to the gate electrode 206 (i.e., the word line) to turn on transistor 260. A non-zero voltage, such as 1.2V, below the breakdown voltage is applied to the fifth conductive line 246 (i.e., the bit line). The voltage at the source line coupled to the source contact via 212S can be 0V. When the OTP memory device 400 is in a high-resistance state, a low current is detected at the bit line. When the OTP memory device 400 is in a low-resistance state, a high current is detected at the bit line. The bit line current is therefore used to determine the state of the OTP memory device 400.

[0040] refer to Figure 10 , Figure 10 yes Figure 9The circuit diagram of the semiconductor structure 200 is shown. A gate electrode 206 is coupled to a word line and controls a transistor 260. The source of transistor 260 is coupled to a source line, and the drain of transistor 260 is coupled to a fifth conductive line 246 via a fusible link. The fifth conductive line 246 serves as a bit line. The fusible link includes a second conductive line 246 serving as a bottom electrode, a breakdown layer 228, and a top electrode 230.

[0041] Now for reference Figure 11 , Figure 12 and Figure 13 Besides the thickness of the breakdown layer 228, the vertical projected area of ​​the breakdown layer 228 may affect the breakdown voltage of the breakdown layer 228. Figure 11 In some embodiments shown, opening 226 ( Figure 4 As shown, the breakdown layer 228 is wider than the second conductive line 220 along the X and Y directions, and its larger area is more likely to contain more defects, which could cause breakdown paths through the breakdown layer 228. Figure 12 In some other embodiments shown, opening 226 (e.g.) Figure 4 (As shown) has the same dimensions as the second conductive line 220 and substantially overlaps along the Z direction. Figure 11 Compared to the 228 breakdown layer, Figure 12 The smaller area of ​​the 228 breakdown layer makes it more likely to have fewer defects, resulting in a higher breakdown voltage. Figure 13 In other embodiments shown, opening 226 ( Figure 4 (As shown) is smaller than the second conductive line 220. (And) Figure 12 Compared to the breakdown layer 228 in the middle, Figure 13 The area of ​​the breakdown layer 228 in the middle is even smaller, making it more likely to have even fewer defects, thus resulting in an even higher breakdown voltage. Figure 11 , Figure 12 and Figure 13 In all the embodiments shown, the second conductive line 220 and the third conductive line 238 extend longitudinally in different directions. The second conductive line 220 extends longitudinally along the Y direction. The third conductive line 238 extends longitudinally along the X direction.

[0042] Note that in Figure 11 , Figure 12 and Figure 13In the illustrated embodiment, the top electrode 230 is entirely disposed within the vertical projection region of the breakdown layer 228 to ensure that breakdown occurs within the breakdown layer 228 and not in other dielectric layers (such as the first ESL 222, the second ESL 224, or the first IMD 218). Otherwise, the breakdown voltage might be unpredictable because different dielectric materials result in different breakdown voltages. That is, according to the invention, the area of ​​the electrode 230 in the XY plane is smaller than the area of ​​the breakdown layer 228 in the XY plane. The difference between the XY plane area of ​​the breakdown layer 228 and the XY plane area of ​​the top electrode layer 230 depends on the overlap precision of the photolithography process. Higher overlap precision may require a smaller area difference, while lower overlap precision may require a larger area difference. In some instances, the XY plane area of ​​the breakdown layer 228 exceeds the XY plane area of ​​the top electrode 230 by approximately 20% to approximately 50%.

[0043] In some prior art, Hi-R resistors are formed within the interconnect structure, while fusible links for OTP memory devices are formed at the FEOL level. Therefore, they are formed using very different processes, increasing manufacturing costs and the number of photolithography steps. Forming fusible links at the FEOL level can also increase device size because they are formed side-by-side with transistors, rather than vertically above them. According to the invention, the method 100 described above can also be used to form high-resistance (Hi-R) resistors. In fact, method 100 can be used to simultaneously form fusible links for both OTP memory devices and Hi-R resistors. When this occurs, only one photomask may be needed to form the fusible links for both the OTP memory device and the Hi-R resistors, and the fusible links may be positioned above the transistors rather than beside them. It has been observed that moving the fusible lines from the FEOL level to the BEOL level can reduce device size by approximately 15% to approximately 25%.

[0044] exist Figure 14 The image shows an enlarged view of the Hi-R resistor 500. Figure 14 The Hi-R resistor 500 in the middle is similar to Figure 8 The top electrode 230 is shown. A Hi-R resistor 500 is disposed above and surrounded by a U-shaped breakdown layer 228. The breakdown layer 228 is disposed on the second conductive line 220. In some embodiments, the breakdown layer 228 is wider along the X direction than the second conductive line 220, and the breakdown layer 228 also contacts the first IMD layer 218. The breakdown layer 228 is disposed within the first ESL 222 and the second ESL 224. The Hi-R resistor 500 is spaced apart from the first ESL 222, the second ESL 224, the first IMD layer 218, and the second conductive line 220 by the breakdown layer 228. Figure 8 The structure differs from that of the Hi-R resistor 500; multiple contact vias are arranged on and coupled to it. Figure 14In the embodiment shown, a first lead contact via 2361 and a second lead contact via 2362 are disposed on and resistively coupled to the Hi-R resistor 500. A first lead conductive wire 2381 is disposed on and contacts the first lead contact via 2361. A second lead conductive wire 2382 is disposed on and contacts the second lead contact via 2362. The first lead contact via 2361 and the second lead contact via 2362 extend through a third ESL 232 and a second IMD layer 234. The first lead conductive wire 2381 and the second lead conductive wire 2382 are disposed in the second IMD layer 234. The first ESL 222 and the second ESL 224 have a second total thickness T2.

[0045] Figure 15 Workpiece 200 is shown, wherein a Hi-R resistor 500 is located in an interconnect structure 300 disposed above transistor 260. Figure 15 In the illustrated embodiment, the first lead conductive line 2381 is electrically coupled to the sixth conductive line 2462 through the fourth contact via 2442, and the second lead conductive line 2382 is electrically coupled to the seventh conductive line 2464 through the fifth contact via 2444. The seventh conductive line 2464 is electrically coupled to the drain contact via 212D through all the contact vias and the conductive lines therebetween. These contact vias and conductive lines include contact via 2446, the fourth conductive line 242, the second contact via 240, conductive line 221, the first contact via 216, and the first conductive line 214.

[0046] Refer again Figure 14 In use, current flows through the Hi-R resistor 500 from one of the first lead contact vias 2361 and 2362 to the other. Like the top electrode 230, the Hi-R resistor 500 may comprise titanium nitride (TiN), tantalum nitride (TaN), tungsten (W), nickel (Ni), titanium (Ti), ruthenium (Ru), cobalt (Co), copper (Cu), other refractory metals, or other suitable metallic materials or combinations thereof. In some embodiments, the Hi-R resistor 500 may be formed of a weakly conductive material such as tantalum nitride (TaN). In some other embodiments where the Hi-R resistor 500 is formed of a relatively strongly conductive material such as copper (Cu) or tungsten (W), the X-direction dimension of the Hi-R resistor 500 may be enlarged, allowing the contact points of the first lead contact via 2361 and the second lead contact via 2362 to be positioned further apart to increase resistance.

[0047] In some implementations, the effective resistance of the Hi-R resistor 500 can be adjusted by increasing the number of lead contact vias or changing the distance between the lead contact vias. Now refer to... Figures 16 to 19 .exist Figure 16 In the illustrated embodiment, each of the first lead conductive line 2381 and the second lead conductive line 2382 is coupled to the Hi-R resistor 500 through a lead contact via (first lead contact via 2361 or second lead contact via 2362). To ensure satisfactory via-line contact, each of the first lead contact via 2361 and the second lead contact via 2362 may have a rectangular or elongated shape. Figure 16 As shown, the first lead contact via 2361 may have a via width (VW) along the X direction and a via length (VL) along the Y direction, wherein the via length (VL) is greater than the via width (VW). In some examples, the via width (VW) may be between about 25 nm and about 50 nm, and the via length (VL) may be between about 80 nm and about 120 nm. The first lead conductor 2381 or the second lead conductor 2382 may have a linewidth (LW) along the Y direction, and the linewidth (LW) may be between about 100 nm and about 200 nm. Thus, the first lead contact via 2361 intersects with the linewidth (LW) of the first lead conductor 2381, which has a longer via length (VL) than a shorter via width (VW). In some implementations, the line width (LW) can be approximately the same as the via length (VL), making the line width (LW) and via length (VL) essentially connected.

[0048] To ensure that the first lead contact via 2361 and the second lead contact via 2362 fall on the Hi-R resistor 500, each edge of the first lead contact via 2361 and the second lead contact via 2362 is spaced apart from the boundary of the Hi-R resistor 500 by a margin (M). The margin (M) is directly related to the precision and resolution of the photolithography process. For example, when the photolithography process implements a radiation source with a wavelength of approximately 248 nm, the margin (M) may be equal to or greater than approximately 30 nm. If the margin (M) is less than approximately 30 nm, defects associated with lead contact via misalignment may occur, which is undesirable. The margin (M) should be less than approximately 100 nm; otherwise, the Hi-R resistor 500 may be too large to be included in the breakdown layer 228. When using different radiation sources with smaller wavelengths, the margin (M) may have a smaller range. For example, when the wavelength of the radiation source is approximately 193 nm, the margin (M) may be between 20 nm and approximately 60 nm. The margin (M) can also be characterized as the ratio of margin (M) to via length (VL). In some instances, the ratio (M / VL) can be between about 0.2 and about 0.3. When the ratio (M / VL) is less than 0.2, the probability that the lead contact via falls outside the Hi-R resistor 500 is unsatisfactory. When the ratio (M / VL) is greater than 1.3, the storage density of the lead contact via may be too low, resulting in an unnecessary increase in device size. To achieve the desired effective resistance using the Hi-R resistor 500, the Y-direction spacing (S) between the first lead contact via 2361 and the second lead contact via 2362 can be between about 100 nm and about 12 μm. When the Y-direction spacing (S) is less than about 100 nm, the resistance may not reach the desired level. When the Y-direction spacing (S) is greater than about 12 μm, mounting the Hi-R resistor 500 in its interconnect layer may become difficult.

[0049] To maximize the via-to-via distance (D) while maintaining a given Y-direction spacing (S), the first lead contact via 2361 and the second lead contact via 2362 can be arranged to fall diagonally on the top electrode 230, such as... Figure 17 As shown. In some instances, the via-to-via distance (D) can be between approximately 1.2 and approximately 3 times the Y-direction spacing (S). That is, the ratio of the via-to-via distance (D) to the Y-direction spacing (S) can be between approximately 1.2 and 3. However, it should be noted that when the ratio (D / S) is less than 1.2 or greater than 1.6, diagonal via placement may not result in significant absolute space savings, as doing so only alters the longitudinal orientation of the Hi-R resistor 500. Because the via-to-via distance (D) is directly related to the effective resistance, Figure 17The embodiments illustrated provide flexibility in adapting to different orientations of the top electrode 230. For example, depending on the layout in the interconnect layer where the Hi-R resistor 500 resides, the Hi-R resistor 500 may have a shape elongated along the X direction rather than along the Y direction, as shown below. Figure 17 As shown.

[0050] When needed Figure 16 When the effective resistance of the Hi-R resistor 500 is half (1 / 2), each of the first lead conductor 2381 and the second lead conductor 2382 is coupled to the Hi-R resistor 500 through two lead contact vias, as follows: Figure 18 As shown. In Figure 18 In this configuration, the first conductive lead 2381 is coupled to the Hi-R resistor 500 through the first lead contact via 2361 and the third lead contact via 2363; and the second conductive lead 2382 is coupled to the Hi-R resistor 500 through the second lead contact via 2362 and the fourth lead contact via 2364. If necessary... Figure 16 If one-third (1 / 3) of the effective resistance value of the Hi-R resistor 500 is used, then each of the first conductive lead 2381 and the second conductive lead 2382 is coupled to the Hi-R resistor 500 through three lead contact vias, as follows: Figure 19 As shown. In Figure 19 In this configuration, the first conductive lead 2381 is coupled to the Hi-R resistor 500 through the first lead contact via 2361, the third lead contact via 2363, and the fifth lead contact via 2365; and the second conductive lead 2382 is coupled to the Hi-R resistor 500 through the second lead contact via 2362, the fourth lead contact via 2364, and the sixth lead contact via 2366. It is understood that more lead contact vias can be implemented to further reduce the resistance of the Hi-R resistor 500. Figures 16 to 19 The examples shown demonstrate that the method 100 of the present invention can be used to form Hi-R resistors with different effective resistances.

[0051] Figure 20 Show Figure 9 The workpiece 200 shown and Figure 15 The workpiece 200 shown is likely a single workpiece 200 comprising both the Hi-R resistor 500 and the OTP memory device 400. For simplicity, [details omitted]. Figure 20 Detailed description. It should be noted that throughout this invention, the same reference numerals denote the same parts.

[0052] Embodiments of the present invention offer benefits. The method of the present invention can simultaneously form a high-resistance (Hi-R) resistor and an OTP memory device within a BEOL interconnect structure. Forming these two types of devices together within a BEOL interconnect structure reduces manufacturing costs due to a smaller number of photomasks and reduced device size. The present invention also provides mechanisms or structures for adjusting the effective resistance of the high-resistance resistor or the breakdown voltage of the OTP memory device.

[0053] Therefore, in one aspect, the present invention provides a semiconductor structure. The semiconductor structure includes: a transistor; and an interconnect structure disposed above the transistor. The interconnect structure includes: a first dielectric layer; a first conductive member located in the first dielectric layer; a first etch stop layer (ESL) disposed above the first dielectric layer and the first conductive member; a dielectric member disposed in the first ESL; an electrode disposed above the dielectric member; and a second ESL disposed on the first ESL and the electrode.

[0054] In some embodiments, the dielectric component comprises aluminum oxide, hafnium oxide, or aluminum nitride. In some instances, the electrode comprises titanium nitride, tantalum nitride, copper, tungsten, cobalt, or ruthenium. In some implementations, the dielectric component comprises a dielectric material between approximately... With the agreement The thickness between the first ESL and the first dielectric layer. In some embodiments, the interconnect structure further includes a third ESL disposed between the first ESL and the first dielectric layer, and the dielectric component is also disposed in the third ESL. In some embodiments, the composition of the third ESL is different from the composition of the second ESL. In some instances, the dielectric component is in direct contact with the first ESL, the third ESL, the second ESL, and the first conductive component. In some embodiments, the electrode is spaced apart from the first ESL, the third ESL, and the first conductive component by the dielectric component. In some embodiments, the width of the dielectric component is greater than the width of the first conductive component, the dielectric component is also in contact with the first dielectric layer, and the electrode is spaced apart from the first dielectric layer by the dielectric component. In some instances, the interconnect structure further includes: a second dielectric layer disposed on the second ESL; a contact via disposed in the second ESL and the second dielectric layer and coupled to the electrode; and a second conductive component disposed in the second dielectric layer and coupled to the contact via. In some instances, the drain of the transistor is electrically coupled to the first conductive component.

[0055] Another aspect of the present invention relates to an image sensor. The image sensor includes: a transistor; an interlayer dielectric (ILD) layer disposed above the transistor; a first conductive component located in the ILD layer; a first etch stop layer (ESL) disposed above the ILD layer and the first conductive component; a high-k dielectric component disposed in the first ESL; a metal component disposed above the high-k dielectric component; and a second ESL disposed on the first ESL and the metal component.

[0056] In some embodiments, the composition of the metal component differs from the composition of the first conductive component. In some instances, the semiconductor structure may further include: a second ILD layer disposed on the second ESL; a first contact via disposed in the second ESL and the second ILD layer and coupled to the metal component; a second contact via disposed in the second ESL and the second ILD layer and coupled to the metal component; a second conductive component disposed in the second ILD layer and coupled to the first contact via; and a third conductive component disposed in the second ILD layer and coupled to the first contact via. In some implementations, the first contact via is resistively coupled to the second contact via through the metal component. In some embodiments, the drain of the transistor is electrically coupled to the second conductive component.

[0057] Another aspect of the present invention relates to a method. The method includes: receiving a workpiece comprising: a transistor; an interlayer dielectric (ILD) layer disposed above the transistor; a first conductive component located in the ILD layer; a first etch stop layer (ESL) disposed above the ILD layer and the first conductive component; and a second ESL disposed on the first ESL. The method further includes forming an opening through the second ESL and the first ESL to expose the first conductive component; depositing a high-k dielectric layer over the opening; depositing a metal layer over the high-k dielectric layer; planarizing the workpiece to remove the high-k dielectric layer and the metal layer over the top surface of the second ESL; and forming a contact via after the planarization to couple to the top surface of the metal layer.

[0058] In some embodiments, the first conductive member includes a first width in a certain direction, wherein the opening includes a second width along the direction, wherein the second width is greater than the first width. In some instances, the deposition of the high-k dielectric layer includes depositing aluminum oxide, hafnium oxide, zirconium oxide, titanium oxide, zinc oxide, yttrium oxide, tantalum oxide, or aluminum nitride over the opening. In some implementations, the deposition of the metal layer includes depositing titanium nitride, tantalum nitride, copper, tungsten, cobalt, or ruthenium.

[0059] In some embodiments, a semiconductor structure includes: a transistor; and an interconnect structure disposed above the transistor, wherein the interconnect structure includes: a first dielectric layer; a first conductive component located in the first dielectric layer; a first etch stop layer (ESL) disposed above the first dielectric layer and the first conductive component; a dielectric component disposed in the first ESL; an electrode disposed above the dielectric component; and a second ESL disposed on the first ESL and the electrode.

[0060] In the above semiconductor structure, the dielectric component includes aluminum oxide, hafnium oxide, or aluminum nitride. In the above semiconductor structure, the electrodes include titanium nitride, tantalum nitride, copper, tungsten, cobalt, or ruthenium. In the above semiconductor structure, the dielectric component includes materials between approximately... With the agreement The thickness between the two layers. In the above semiconductor structure, the interconnect structure further includes a third ESL disposed between the first ESL and the first dielectric layer, wherein a dielectric component is also disposed in the third ESL. In the above semiconductor structure, the composition of the third ESL is different from the composition of the second ESL. In the above semiconductor structure, the dielectric component is in direct contact with the first ESL, the third ESL, the second ESL, and the first conductive component. In the above semiconductor structure, the electrode is spaced apart from the first ESL, the third ESL, and the first conductive component by the dielectric component. In the above semiconductor structure, the width of the dielectric component is greater than the width of the first conductive component, the dielectric component is also in contact with the first dielectric layer, and the electrode is spaced apart from the first dielectric layer by the dielectric component. In the above semiconductor structure, the interconnect structure further includes: a second dielectric layer disposed on the second ESL; a contact via disposed in the second ESL and the second dielectric layer and coupled to the electrode; and a second conductive component disposed in the second dielectric layer and coupled to the contact via. In the above semiconductor structure, the drain of the transistor is electrically coupled to the first conductive component.

[0061] In some embodiments, a semiconductor structure includes: a transistor; an interlayer dielectric (ILD) layer disposed above the transistor; a first conductive component located in the ILD layer; a first etch stop layer (ESL) disposed above the ILD layer and the first conductive component; a high-k dielectric component disposed in the first ESL; a metal component disposed above the high-k dielectric component; and a second ESL disposed on the first ESL and the metal component.

[0062] In the above semiconductor structure, the composition of the metal component differs from that of the first conductive component. The semiconductor structure further includes: a second ILD layer disposed on a second ESL; a first contact via disposed in the second ESL and the second ILD layer and coupled to the metal component; a second contact via disposed in the second ESL and the second ILD layer and coupled to the metal component; a second conductive component disposed in the second ILD layer and coupled to the first contact via; and a third conductive component disposed in the second ILD layer and coupled to the first contact via. In the above semiconductor structure, the first contact via is resistively coupled to the second contact via through the metal component. In the above semiconductor structure, the drain of the transistor is electrically coupled to the second conductive component.

[0063] In some embodiments, a method of manufacturing a semiconductor structure includes: receiving a workpiece comprising: a transistor; an interlayer dielectric (ILD) layer disposed above the transistor; a first conductive component located in the ILD layer; a first etch stop layer (ESL) disposed above the ILD layer and the first conductive component; and a second ESL disposed on the first ESL; forming an opening through the second ESL and the first ESL to expose the first conductive component; depositing a high-k dielectric layer above the opening; depositing a metal layer above the high-k dielectric layer; planarizing the workpiece to remove the high-k dielectric layer and the metal layer above the top surface of the second ESL; and forming a contact via after planarization to couple to the top surface of the metal layer.

[0064] In the above method, the first conductive component includes a first width along a certain direction, wherein the opening includes a second width along the direction, wherein the second width is greater than the first width. In the above method, the deposition of the high-k dielectric layer includes depositing aluminum oxide, hafnium oxide, zirconium oxide, titanium oxide, zinc oxide, yttrium oxide, tantalum oxide, or aluminum nitride over the opening. In the above method, the deposition of the metal layer includes depositing titanium nitride, tantalum nitride, copper, tungsten, cobalt, or ruthenium.

[0065] The features of several embodiments have been summarized above to enable those skilled in the art to better understand aspects of the invention. Those skilled in the art should understand that they can readily use this invention as a basis to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the invention, and that various changes, substitutions, and alterations can be made herein without departing from the spirit and scope of the invention. For example, different resistances of the conductors can be achieved by using different thicknesses of the solid lines of the bit line conductor and the word line conductor. However, other techniques can also be used to change the resistance of the metallic conductors.

Claims

1. A semiconductor structure, comprising: transistor; as well as An interconnect structure is disposed above the transistor, wherein the interconnect structure includes: First dielectric layer; The first conductive component is located in the first dielectric layer; A first etch stop layer is disposed above the first dielectric layer and the first conductive component; Dielectric components are disposed in the first etch stop layer; An electrode is disposed above the dielectric component, the bottom surface and sidewalls of the electrode being surrounded by the dielectric component to space the electrode from the first etch stop layer and the first conductive component; and A second etch stop layer is disposed on the first etch stop layer and the electrode.

2. The semiconductor structure according to claim 1, wherein, The dielectric component includes aluminum oxide, hafnium oxide, or aluminum nitride.

3. The semiconductor structure according to claim 1, wherein, The electrodes include titanium nitride, tantalum nitride, copper, tungsten, cobalt, or ruthenium.

4. The semiconductor structure according to claim 1, wherein, The dielectric component has a thickness between about 10 Å and about 100 Å.

5. The semiconductor structure according to claim 1, in, The interconnect structure further includes a third etch stop layer disposed between the first etch stop layer and the first dielectric layer. The dielectric component is also disposed in the third etch stop layer.

6. The semiconductor structure according to claim 5, wherein, The composition of the third etch stop layer is different from that of the second etch stop layer.

7. The semiconductor structure according to claim 5, wherein, The dielectric component is in direct contact with the first etch stop layer, the third etch stop layer, the second etch stop layer, and the first conductive component.

8. The semiconductor structure according to claim 5, wherein, The electrode is spaced apart from the first etch stop layer, the third etch stop layer, and the first conductive component by the dielectric component.

9. The semiconductor structure according to claim 5, in, The width of the dielectric component is greater than the width of the first conductive component. The dielectric component is also in contact with the first dielectric layer. The electrode is spaced apart from the first dielectric layer by the dielectric component.

10. The semiconductor structure according to claim 1, wherein, The interconnection structure further includes: A second dielectric layer is disposed on the second etch stop layer; A contact via is disposed in the second etch stop layer and the second dielectric layer and coupled to the electrode; and The second conductive component is disposed in the second dielectric layer and coupled to the contact via.

11. The semiconductor structure according to claim 1, wherein, The drain of the transistor is electrically coupled to the first conductive component.

12. A semiconductor structure, comprising: transistor; An interlayer dielectric layer is disposed above the transistor; The first conductive component is located in the interlayer dielectric layer; A first etch stop layer is disposed above the interlayer dielectric layer and the first conductive component; A high-k dielectric component is disposed in the first etch stop layer; A metal component is disposed above the high-k dielectric component, the bottom surface and sidewalls of the metal component being surrounded by the high-k dielectric component, thereby separating the metal component from the first etch stop layer and the first conductive component; as well as A second etch stop layer is disposed on the first etch stop layer and the metal component.

13. The semiconductor structure according to claim 12, wherein, The composition of the metal component is different from that of the first conductive component.

14. The semiconductor structure according to claim 12, further comprising: The second interlayer dielectric layer is disposed on the second etch stop layer; A first contact via is disposed in the second etch stop layer and the second interlayer dielectric layer and coupled to the metal component; The second contact via is disposed in the second etch stop layer and the second interlayer dielectric layer and coupled to the metal component; The second conductive component is disposed in the second interlayer dielectric layer and coupled to the first contact via; as well as The third conductive component is disposed in the second interlayer dielectric layer and coupled to the first contact via.

15. The semiconductor structure according to claim 14, wherein, The first contact via is resistively coupled to the second contact via through the metal component.

16. The semiconductor structure according to claim 14, wherein, The drain of the transistor is electrically coupled to the second conductive component.

17. A method for manufacturing a semiconductor structure, comprising: A workpiece is received, the workpiece comprising: a transistor; an interlayer dielectric layer disposed above the transistor; a first conductive component located in the interlayer dielectric layer; a first etch stop layer disposed above the interlayer dielectric layer and the first conductive component; and a second etch stop layer disposed on the first etch stop layer. An opening is formed through the second etch stop layer and the first etch stop layer to expose the first conductive component; A high-k dielectric layer is deposited above the opening; A metal layer is deposited above the high-k dielectric layer; Planarize the workpiece to remove the high-k dielectric layer and the metal layer above the top surface of the second etch stop layer, to form a bottom surface and sidewalls in the opening surrounded by the high-k dielectric layer, such that the metal layer is spaced apart from the first etch stop layer, the second etch stop layer, and the first conductive component; and After planarization, contact vias are formed to couple to the top surface of the metal layer.

18. The method according to claim 17, in, The first conductive component includes a first width along the direction. The opening includes a second width along the direction. The second width is greater than the first width.

19. The method according to claim 17, wherein, The deposition of the high-k dielectric layer includes depositing aluminum oxide, hafnium oxide, zirconium oxide, titanium oxide, zinc oxide, yttrium oxide, tantalum oxide, or aluminum nitride over the opening.

20. The method of claim 17, wherein, The deposition of the metal layer includes the deposition of titanium nitride, tantalum nitride, copper, tungsten, cobalt, or ruthenium.

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