Method for manufacturing silicon carbide semiconductor device and power conversion device using silicon carbide semiconductor device

Abstract

The method for manufacturing a silicon carbide semiconductor device disclosed herein includes: a step of forming an insulating film on a portion above a silicon carbide layer; a step of forming an ohmic electrode on the silicon carbide layer adjacent to the insulating film; a step of removing an oxide layer on the ohmic electrode; a step of forming an opening on the opposite side of the side of the ohmic electrode adjacent to the insulating film, forming a mask on the ohmic electrode with the oxide layer removed and on the insulating film; and a step of wet etching the film to be etched using hydrofluoric acid while the mask is formed. According to the method for manufacturing a silicon carbide semiconductor device disclosed herein, it is possible to manufacture a silicon carbide semiconductor device with fewer defects.

Description

Technical Field

[0001] This disclosure relates to a method for manufacturing a silicon carbide semiconductor device made of silicon carbide and a method for manufacturing a power conversion device using a silicon carbide semiconductor device. Background Technology

[0002] There are known silicon carbide semiconductor devices that incorporate an SBD (Schottky Barrier Diode) within a silicon carbide (SiC) insulated-gate field-effect transistor (MOSFET) to prevent bipolar current from flowing through the MOSFET during recirculation.

[0003] A known manufacturing method involves forming a Schottky contact and an ohmic contact within the same contact hole in a SiC-MOSFET with an integrated SBD. An ohmic electrode for the ohmic contact is formed while the Schottky contact is covered with a protective film at a predetermined location. After the ohmic electrode is formed, a Schottky electrode is formed on the surface where the protective film has been removed with hydrofluoric acid, thereby forming the Schottky contact (e.g., Patent Document 1).

[0004] Patent Document 1: Japanese Patent Application Publication No. 2014-157896 Summary of the Invention

[0005] The problem that the invention aims to solve

[0006] When manufacturing SiC-MOSFETs with built-in SBDs, during the etching of the protective film with hydrofluoric acid, the protective film adjacent to the ohmic electrode is sometimes etched while the ohmic electrode is covered by a photoresist mask or similar material. If the surface of the ohmic electrode is oxidized, during wet etching of the protective film with hydrofluoric acid, the hydrofluoric acid may erode the interface between the ohmic electrode and the photoresist mask, etching into unexpected areas such as the gate insulating film near the MOSFET's gate electrode. This can result in manufacturing defects such as gate insulating film defects or poor insulation of the gate insulating film.

[0007] In addition, not limited to the manufacturing of SiC-MOSFETs with built-in SBDs, when manufacturing silicon carbide semiconductor devices, a resist mask is formed on the ohmic electrode and an etchant containing hydrofluoric acid is used to wet etch the insulating film adjacent to the ohmic electrode. Sometimes, the hydrofluoric acid erodes the interface between the ohmic electrode and the resist mask, etching to unexpected locations.

[0008] This disclosure was made to solve the aforementioned problems, and its purpose is to provide a method for manufacturing a silicon carbide semiconductor device with fewer defects, which prevents etching of unintended areas caused by hydrofluoric acid.

[0009] Methods for solving problems

[0010] The method for manufacturing a silicon carbide semiconductor device disclosed herein includes: a step of forming an insulating film on a portion above a silicon carbide layer; a step of forming an ohmic electrode on the silicon carbide layer adjacent to the insulating film; a step of removing an oxide layer on the ohmic electrode; a step of forming an opening on the opposite side of the ohmic electrode adjacent to the insulating film, forming a mask on the ohmic electrode with the oxide layer removed and on the insulating film; a step of wet etching the etchable film using hydrofluoric acid while a resist mask is formed; and a step of removing the mask after wet etching the etchable film.

[0011] The effects of the invention

[0012] According to the manufacturing method of the silicon carbide semiconductor device disclosed herein, it is possible to manufacture silicon carbide semiconductor devices with fewer defects. Attached Figure Description

[0013] Figure 1 This is a cross-sectional view of a silicon carbide semiconductor device manufactured using the manufacturing method of the silicon carbide semiconductor device according to Embodiment 1.

[0014] Figure 2 This is a top view of a silicon carbide semiconductor device manufactured using the manufacturing method of the silicon carbide semiconductor device according to Embodiment 1.

[0015] Figure 3 This is a top view of another embodiment of a silicon carbide semiconductor device manufactured using the manufacturing method of the silicon carbide semiconductor device according to Embodiment 1.

[0016] Figure 4 This is a cross-sectional view illustrating the manufacturing method of the silicon carbide semiconductor device according to Embodiment 1.

[0017] Figure 5 This is a cross-sectional view illustrating the manufacturing method of the silicon carbide semiconductor device according to Embodiment 1.

[0018] Figure 6 This is a cross-sectional view illustrating the manufacturing method of the silicon carbide semiconductor device according to Embodiment 1.

[0019] Figure 7 This is a cross-sectional view illustrating the manufacturing method of the silicon carbide semiconductor device according to Embodiment 1.

[0020] Figure 8 This is a cross-sectional view illustrating the manufacturing method of the silicon carbide semiconductor device according to Embodiment 1.

[0021] Figure 9 This is a cross-sectional view illustrating the manufacturing method of the silicon carbide semiconductor device according to Embodiment 1.

[0022] Figure 10 This is a cross-sectional view illustrating a manufacturing method without employing the manufacturing method of the silicon carbide semiconductor device described in Embodiment 1.

[0023] Figure 11 This is a cross-sectional view illustrating a manufacturing method without employing the manufacturing method of the silicon carbide semiconductor device described in Embodiment 1.

[0024] Figure 12 This is a cross-sectional view illustrating a manufacturing method without employing the manufacturing method of the silicon carbide semiconductor device described in Embodiment 1.

[0025] Figure 13 This is a cross-sectional view illustrating a manufacturing method without employing the manufacturing method of the silicon carbide semiconductor device described in Embodiment 1.

[0026] Figure 14 This is a cross-sectional view of a silicon carbide semiconductor device manufactured using the manufacturing method of the silicon carbide semiconductor device according to Embodiment 2.

[0027] Figure 15 This is a top view of a silicon carbide semiconductor device manufactured using the manufacturing method of the silicon carbide semiconductor device according to Embodiment 2.

[0028] Figure 16 This is a cross-sectional view illustrating the manufacturing method of the silicon carbide semiconductor device according to Embodiment 2.

[0029] Figure 17 This is a cross-sectional view illustrating the manufacturing method of the silicon carbide semiconductor device according to Embodiment 2.

[0030] Figure 18 This is a cross-sectional view illustrating the manufacturing method of the silicon carbide semiconductor device according to Embodiment 2.

[0031] Figure 19 This is a cross-sectional view illustrating the manufacturing method of the silicon carbide semiconductor device according to Embodiment 2.

[0032] Figure 20 This is a cross-sectional view illustrating the manufacturing method of the silicon carbide semiconductor device according to Embodiment 2.

[0033] Figure 21 This is a cross-sectional view illustrating the manufacturing method of the silicon carbide semiconductor device according to Embodiment 2.

[0034] Figure 22 This is a cross-sectional view illustrating the manufacturing method of the silicon carbide semiconductor device according to Embodiment 2.

[0035] Figure 23This is a cross-sectional view illustrating the manufacturing method of the silicon carbide semiconductor device according to Embodiment 2.

[0036] Figure 24 This is a cross-sectional view illustrating the manufacturing method of the silicon carbide semiconductor device according to Embodiment 3.

[0037] Figure 25 This is a cross-sectional view illustrating the manufacturing method of the silicon carbide semiconductor device according to Embodiment 3.

[0038] Figure 26 This is a cross-sectional view illustrating the manufacturing method of the silicon carbide semiconductor device according to Embodiment 3.

[0039] Figure 27 This is a cross-sectional view illustrating the manufacturing method of the silicon carbide semiconductor device according to Embodiment 3.

[0040] Figure 28 This is a cross-sectional view illustrating the manufacturing method of the silicon carbide semiconductor device according to Embodiment 3.

[0041] Figure 29 This is a cross-sectional view illustrating the manufacturing method of the silicon carbide semiconductor device according to Embodiment 3.

[0042] Figure 30 This is a schematic diagram showing the configuration of a power conversion device manufactured using the manufacturing method of the power conversion device according to Embodiment 4. Detailed Implementation

[0043] The embodiments will now be described with reference to the accompanying drawings. It should be noted that the drawings are schematic representations, and the dimensions and relative positions of the images shown in different drawings may not be accurately depicted and can be appropriately varied. Furthermore, in the following description, the same reference numerals are used to illustrate the same constituent elements, and their names and functions are also the same. Therefore, detailed descriptions of them are sometimes omitted.

[0044] Implementation Method 1

[0045] First, the configuration of a silicon carbide semiconductor device manufactured using the manufacturing method according to Embodiment 1 of this disclosure will be explained.

[0046] Figure 1 This is a cross-sectional view of a unit cell of the active region of a silicon carbide semiconductor device, namely a Schottky barrier diode-embedded silicon carbide MOSFET (SBD-embedded SiC-MOSFET), manufactured using the manufacturing method described in Embodiment 1.

[0047] exist Figure 1In this process, a drift layer 20 made of n-type silicon carbide is formed on the surface of a semiconductor substrate 10 made of n-type low-resistivity silicon carbide. A pair of well regions 30 made of p-type silicon carbide, which are separated in cross-section, are provided on the surface portion of the drift layer 20. The pair of well regions 30 form a first separation region 21 that is part of the drift layer 20.

[0048] The outer side of the well region 30, which sandwiches the first separation region 21, becomes the second separation region 22, which is part of the drift layer 20. At a predetermined interval extending inward from the end of the well region 30 on the side of the second separation region 22 toward the first separation region 21, a source region 40 made of n-type silicon carbide is formed. Furthermore, on the surface portion of the well region 30, further inside the source region 40, a contact region 35 made of low-resistance p-type silicon carbide is formed. Here, regardless of whether ion implantation is present, the region made of silicon carbide (the region formed as the drift layer 20) is referred to as the silicon carbide layer.

[0049] Ohmic electrodes 70 are formed on the surfaces of the source region 40 and the contact region 35. A gate insulating film 50 is formed on the surface of the source region 40 within the well region 30, on the second separation region 22, and on the well region 30 between the source region 40 and the second separation region 22. A gate electrode 60 is formed on the gate insulating film 50 extending from the source region 40 to the second separation region 22. Below the location where the gate electrode 60 is formed, the surface portion of the well region 30, separated by the gate insulating film 50 and opposite to the gate electrode 60, forms a channel region.

[0050] An interlayer insulating film 55 is formed on the gate electrode 60 and the gate insulating film 50. An active electrode 80 is formed on the first separation region 21, the contact region 35, and the ohmic electrode 70, where the interlayer insulating film 55 and the gate insulating film 50 are not formed. The first separation region 21 is Schottky-bonded to the source electrode 80, which is also a Schottky electrode. The interface between the source electrode 80 and the first separation region 21 is called the Schottky interface.

[0051] Additionally, a back ohmic electrode 71 is formed on the side of the semiconductor substrate 10 opposite to the drift layer 20, and a drain electrode 85 is formed on the outside of the back ohmic electrode 71.

[0052] Figure 2 This is a top view of a unit cell of the active region of an SBD-embedded SiC-MOSFET manufactured using the manufacturing method described in Embodiment 1 of this disclosure. Figure 2 This is a diagram showing the various regions on the surface of a unit cell of silicon carbide layer, with the ohmic electrode 70 formation region indicated by dashed lines. Figure 2In the first separation region 21, a well region 30, a contact region 35, a source region 40, a well region 30, and a second separation region 22 are formed sequentially from the inside. A gate electrode 60 (not shown) is formed outside the ohmic electrode 70. It should be noted that the unit cell of the active region of the SBD-embedded SiC-MOSFET manufactured using the manufacturing method of Embodiment 1 of this disclosure is as follows: Figure 3 As shown in its top view, it can also be a strip-shaped unit.

[0053] like Figure 1 and Figure 2 As shown, the ohmic electrode 70 and the source electrode 80 (Schottky electrode) are formed in a contact hole that penetrates the gate insulating film 50 and the interlayer insulating film 55.

[0054] Depend on Figure 2 It can be seen that, in Figure 1 Multiple well regions 30, as seen in the cross-section, can also be connected along the depth direction. Additionally, repeated configuration... Figures 1 to 3 The structure of the unit cells shown in the diagram becomes the active region.

[0055] Here, use Figures 4-9 The cross-sectional schematic diagram illustrates the manufacturing method of the SBD-embedded SiC-MOSFET of the silicon carbide semiconductor device according to Embodiment 1 of this disclosure.

[0056] Figure 4 It is shown Figures 1-3 The cross-sectional view shown in Embodiment 1 of this disclosure illustrates the state of an intermediate stage in the manufacturing process of the SBD-embedded SiC-MOSFET, and describes the process up to this stage.

[0057] First, on a semiconductor substrate 10 composed of n-type low-resistivity silicon carbide with a polymorphism of 4H, and with the first main surface oriented as a (0001) plane having an offset angle, chemical vapor deposition (CVD) is used to deposit a 1×10⁻⁶ ohmmeter. 15 Up to 1×10 17 cm -3 The impurity concentration allows for the epitaxial growth of a drift layer 20, consisting of n-type silicon carbide with a thickness of 5 to 80 μm. The thickness of the drift layer 20 can be 80 μm or more, depending on the voltage withstand capability of the silicon carbide semiconductor device.

[0058] Next, an implantation mask is formed in a designated area on the surface of the drift layer 20 using a photoresist or similar agent, and Al (aluminum) as a p-type impurity is ion implanted. At this time, the depth of Al ion implantation is approximately 0.5 to 3 μm, not exceeding the thickness of the drift layer 20. Furthermore, the impurity concentration of the ion-implanted Al is 1 × 10⁻⁶.17 Up to 1×10 19 cm -3 The range is higher than the impurity concentration of drift layer 20. Then, the implantation mask is removed. The region implanted with Al ions through this process is the trap region 30.

[0059] Next, an implantation mask is formed using a photoresist or the like, with an opening at a predetermined location inside the well region 30 on the surface of the drift layer 20, and N (nitrogen) as an n-type impurity is implanted. The ion implantation depth of N is shallower than the thickness of the well region 30. Furthermore, the impurity concentration of the implanted N is 1 × 10⁻⁶. 18 Up to 1×10 21 cm -3 The range exceeds the p-type impurity concentration in the well region 30. In this process, the region implanted with N represents the n-type region and becomes the source region 40. Then, the implantation mask is removed.

[0060] Alternatively, using the same method, Al is implanted into a designated region inside the trap region 30 with impurity concentration ions higher than the impurity concentration of the trap region 30, thereby forming a contact region 35.

[0061] Secondly, an annealing process is performed using a heat treatment apparatus at a temperature of 1300 to 1900°C for 30 seconds to 1 hour in an atmosphere of inert gas such as argon (Ar). This annealing process electrically activates the ion-implanted N and Al.

[0062] Next, the silicon carbide surfaces of the drift layer 20, well region 30, source region 40, and contact region 35 are thermally oxidized to form a gate insulating film 50, i.e., a silicon oxide film, of a specified thickness. Then, a conductive polysilicon film is formed on the gate insulating film 50 using a reduced-pressure CVD method, and patterned to form the gate electrode 60. Next, an interlayer insulating film 55 composed of silicon oxide is formed using a reduced-pressure CVD method.

[0063] Additionally, a back ohmic electrode 71 is formed on the side of the semiconductor substrate 10 where the drift layer 20 is not formed. Figure 4 The structure shown in the figure is a cross-sectional view.

[0064] Secondly, a contact hole is formed by dry etching, penetrating the interlayer insulating film 55 and the gate insulating film 50 to reach the contact region 35 and the source region 40 within the active region. By using dry etching to form the contact hole, it is possible to form a contact hole with its side perpendicular to the surface of the silicon carbide layer, thereby reducing the repetition period (cell pitch) per unit cell and increasing the conduction current density per unit area.

[0065] Next, a nickel (Ni)-based metal film is formed using sputtering or similar methods, followed by heat treatment at 600-1100°C. This causes the Ni-based metal film to react with the silicon carbide layer within the contact holes, forming a silicide between the silicon carbide layer and the metal film. In the case of a Ni-based metal film, the silicide becomes nickel silicide. Then, the remaining metal film, excluding the silicide formed during the reaction, is removed by wet etching. The resulting silicide forms the ohmic electrode 70. An oxide layer 75 is unintentionally formed on the surface of the ohmic electrode 70.

[0066] Figure 5 This is a cross-sectional view of the stage in which an ohmic electrode 70 is formed in the contact hole, the ohmic electrode 70 being adjacent to the gate insulating film 50 or the gate insulating film 50 and the interlayer insulating film 55.

[0067] Secondly, as in Figure 6 As shown in the cross-sectional view, the oxide layer 75 on the surface of the ohmic electrode 70 is removed by photolithography using hydrofluoric acid. During photolithography, the etching amount is controlled by time or the concentration of hydrofluoric acid, depending on the extent to which the exposed interlayer insulating film 55 remains. The oxide layer 75 can also be removed by photoplasma etching. Here, "removal" means not only complete elimination but also includes the presence of some oxide layer components remaining after removal.

[0068] Next, as in Figure 7 As shown in the cross-sectional view, on the surface of the ohmic electrode 70 and the interlayer insulating film 55 after the oxide layer 75 has been removed, there is an opening on the opposite side to the side adjacent to the gate insulating film 50 or the gate insulating film 50 and the interlayer insulating film 55 formed on the side where the gate electrode 60 is formed, and a photoresist mask 90 and the like are formed by photolithography to etch the gate insulating film 50 and the interlayer insulating film 55 above the region containing the first separation region 21.

[0069] Secondly, such as Figure 8 As shown, with the resist mask 90 formed, a wet etching solution containing hydrofluoric acid is used to etch the gate insulating film 50 and the interlayer insulating film 55 above the surface region containing the first separation region 21. In this case, the gate insulating film 50 and the interlayer insulating film 55 above the surface region containing the first separation region 21 become the etched films. The region to be wet-etched is the region containing the first separation region 21, the surface of the well region 30 adjacent to the first separation region 21, and the surface of the contact region 35. Here, it is preferable that the concentration of hydrofluoric acid in the etch solution used for wet etching of the gate insulating film 50 and the interlayer insulating film 55 is higher than the concentration of hydrofluoric acid used for photo-etching the oxide layer 75 on the surface of the ohmic electrode 70.

[0070] Next, as in Figure 9As shown in the cross-sectional view, the resist mask 90 is removed. Next, a source electrode 80, connected to the first separation region 21 via a Schottky junction, is formed on the first separation region 21 and its surrounding area, and a drain electrode 85 is formed by grounding to the back ohmic electrode on the back side, thereby enabling the fabrication of… Figure 1 The cross-sectional view of the SBD-embedded SiC-MOSFET is shown in the figure.

[0071] It should be noted that the source electrode 80 can be made of a single material, but as long as it is connected to the first separation region 21 in a Schottky configuration, it can also be a two-layer structure with Ti on the bottom and Al on the top, etc., made of multiple materials.

[0072] In addition, silicides are not limited to nickel silicides; they can also be titanium silicides, aluminum silicides, etc.

[0073] Furthermore, an example of a silicon oxide film being used as the insulating film to be etched was described, but the film to be etched can also be a silicon oxide film containing nitrogen, phosphorus, and boron.

[0074] For reference, here, use Figures 10-13 A cross-sectional schematic diagram illustrating the case where the oxide layer 75 on the ohmic electrode 70 is not removed is provided. Figure 5 The cross-sectional view shows the process of manufacturing the product up to the point of production, such as... Figure 10 A resist mask 90 is formed as shown in the cross-sectional view, and the gate insulating film 50 and the interlayer insulating film 55 are wet-etched using an etchant containing hydrofluoric acid. Thus, as... Figure 11 As shown in the cross-sectional view, sometimes the oxide layer 75 on the ohmic electrode 70 is etched by an acid containing hydrofluoric acid, etching to the gate insulating film 50 and the interlayer insulating film 55 near the gate electrode 60 on the opposite side of the resist mask 90.

[0075] Next, as Figure 12 As shown in the cross-sectional view, when the resist mask 90 is removed and the source electrode 80 is formed, as shown in the diagram, Figure 13 As shown in the cross-sectional view, the source electrode 80 and the gate electrode 60 are short-circuited, resulting in a defective product.

[0076] According to the manufacturing method of the silicon carbide semiconductor device, namely SBD-embedded SiC-MOSFET, in this embodiment, since a resist mask 90 is formed on the ohmic electrode 70 after the oxide layer 75 formed on the surface of the ohmic electrode 70 is removed, the etching solution cannot reach the vicinity of the gate electrode 60 during subsequent wet etching using an etching solution containing hydrofluoric acid, thus preventing the generation of defective products.

[0077] Implementation Method 2

[0078] First, the configuration of a silicon carbide semiconductor device manufactured using the manufacturing method according to Embodiment 2 of this disclosure will be explained.

[0079] Figure 14 This is a cross-sectional schematic diagram of a unit cell of the active region of a silicon carbide semiconductor device, namely a Schottky barrier diode-embedded silicon carbide MOSFET (SBD-embedded SiC-MOSFET), manufactured using the manufacturing method described in Embodiment 2. Additionally, Figure 15 This is a top view of the active region of the SiC-MOSFET built into the SBD, with the ohmic electrode 70 forming region marked by dashed lines. Figure 14 (a) shows having Figure 15 The profile of the source region 40, Figure 14 (b) shows having Figure 15 The contact area 35 is a cross-section. In the following... Figures 16-23 In the text, each (a) shows that it has Figure 15 (b) shows a cross-section of the source region 40, with Figure 15 The contact area 35 is a cross-section.

[0080] In Embodiment 1, a method for manufacturing a silicon carbide semiconductor device integrating a planar MOSFET and an SBD was described. However, in this Embodiment 2, a method for manufacturing a silicon carbide semiconductor device integrating a trench-type MOSFET and an SBD formed on the trench sidewall is described. In the SBD-integrated SiC-MOSFET of this embodiment, the MOSFET is formed in the gate trench GT, and the SBD is formed in the Schottky trench ST. A first protective diffusion region 31 of the second conductivity type is formed in the drift layer 20 connected to the bottom of the gate trench GT, and a second protective diffusion region 32 of the second conductivity type is formed in the drift layer 20 connected to the bottom of the Schottky trench ST. In addition, as Figure 15 As shown, on the surface side of the well region 30 in the region between the gate trench GT and the Schottky trench ST, the source region 40 and the contact region 35 are alternately arranged along the extension direction of the strip trench. Other aspects are the same as in Embodiment 1, so detailed descriptions are omitted.

[0081] exist Figure 14 In this process, a drift layer 20 made of n-type silicon carbide is formed on the surface of a semiconductor substrate 10 made of n-type low-resistivity silicon carbide. A well region 30 is provided on the surface portion of the drift layer 20, and on the surface portion of the well region 30, as shown... Figure 14 (a) and Figure 14 As shown in (b), an active electrode region 40 or a contact region 35 is formed. Two types of strip-shaped trenches, which penetrate the source electrode region 40 or the contact region 35 and the sink region 30 to reach the drift layer 20, are formed at intervals in a direction orthogonal to the trench extension direction.

[0082] One of the two types of trenches is a gate trench GT, in which a gate electrode 60 is formed with respect to a gate insulating film 50. An ohmic electrode 70 is formed above the source region 40 and the contact region 35. Furthermore, a p-type first protective diffusion region 31 is formed in the drift layer 20 that is in contact with the bottom surface of the gate trench GT. In addition, an interlayer insulating film 55 is formed above the gate electrode 60.

[0083] The other of the two types of trenches is a Schottky trench ST, in which a p-type second protective diffusion region 32 is formed within the drift layer 20, which is in contact with the bottom surface of the Schottky trench ST. Additionally, a source electrode 80, which is Schottky bonded to the drift layer 20, is formed within the Schottky trench ST. The interface between the source electrode 80 and the drift layer 20 is called a Schottky interface. The source electrode 80 is also formed on the upper part of the interlayer insulating film 55 and the upper part of the ohmic electrode 70.

[0084] A back ohmic electrode 71 is formed on the side of the semiconductor substrate 10 opposite to the drift layer 20, and a drain electrode 85 is formed on the outside of the back ohmic electrode 71.

[0085] The following uses Figures 16-23 The cross-sectional schematic diagram illustrates the manufacturing method of the SBD-embedded SiC-MOSFET of the silicon carbide semiconductor device according to Embodiment 2 of this disclosure.

[0086] Figure 16 It is shown Figure 14 , Figure 15 The cross-sectional view shown in Embodiment 2 of this disclosure illustrates the state of an intermediate stage in the manufacturing process of the SBD-embedded SiC-MOSFET, and describes the process up to this stage.

[0087] First, on a semiconductor substrate 10 made of n-type low-resistivity silicon carbide with a polymorphism of 4H, with a (0001) plane having an offset angle on the first main surface, a CVD method is used to achieve a 1×10⁻⁶ ohm diameter. 15 Up to 1×10 17 cm -3 The impurity concentration enables the epitaxial growth of a drift layer 20 composed of n-type silicon carbide with a thickness of 5 to 80 μm.

[0088] Next, Al, acting as a p-type impurity, is ion-implanted from the surface of the drift layer 20. At this time, the depth of Al ion implantation is approximately 0.5 to 3 μm, not exceeding the thickness of the drift layer 20. Furthermore, the impurity concentration of the ion-implanted Al is 1 × 10⁻⁶. 17 Up to 1×10 19 cm -3 The range is higher than the impurity concentration of the drift layer 20. The region where Al was ion-implanted through this process becomes the trap region 30.

[0089] Next, an implantation mask is formed using a photoresist or similar agent, with openings at predetermined locations on the surface of the well region 30. N, an n-type impurity, is then implanted. The N ion implantation depth is shallower than the thickness of the well region 30. Furthermore, the impurity concentration of the implanted N is 1 × 10⁻⁶. 18 Up to 1×10 21 cm -3 The range exceeds the p-type impurity concentration in the well region 30. In this process, the region where N-type impurities are implanted becomes the source region 40. Then, the implantation mask is removed.

[0090] Alternatively, using the same method, Al is implanted into a designated region inside the trap region 30 with impurity concentration ions higher than the impurity concentration of the trap region 30, thereby forming a contact region 35.

[0091] Next, a resist mask with openings in the region where the active electrode region 40 is formed and the region where the contact region 35 is formed is used to form a gate trench GT and a Schottky trench ST that penetrate the source electrode region 40 or the contact region 35 and the well region 30 to reach the drift layer 20 using a dry etching method. Then, as in Figure 17 As shown in the cross-sectional schematic diagram, p-type impurities are implanted into the drift layer 20 at the bottom of the gate trench GT and the Schottky trench ST to form the first protective diffusion region 31 and the second protective diffusion region 32, respectively.

[0092] Next, the ion-implanted N and Al are electrically activated through heat treatment.

[0093] Next, the silicon carbide surface inside the gate trench GT and Schottky trench ST is thermally oxidized to form a gate insulating film 50, i.e., a silicon oxide film, of a specified thickness. Then, a conductive polysilicon film is formed on the gate insulating film 50 using a reduced-pressure CVD method, and then patterned and etched back, thereby forming the gate electrode 60 only on the gate trench GT side. Next, as in... Figure 18 As shown in the cross-sectional schematic diagram, an interlayer insulating film 55 composed of silicon oxide is formed by depressurized CVD.

[0094] Next, as in Figure 19 As shown in the cross-sectional view, a back ohmic electrode 71 is formed on the side of the semiconductor substrate 10 where the drift layer 20 is not formed. Additionally, a contact hole is formed using a dry etching method, penetrating the interlayer insulating film 55 and the gate insulating film 50, reaching the contact region 35 and the source region 40 within the active region. A silicide serving as the ohmic electrode 70 is formed within the contact hole. An oxide layer 75 is unintentionally formed on the surface of the ohmic electrode 70.

[0095] Secondly, as in Figure 20As shown in the cross-sectional view, the oxide layer 75 on the surface of the ohmic electrode 70 is removed by photolithography with hydrofluoric acid.

[0096] Next, as in Figure 21 As shown in the cross-sectional view, on the surface of the ohmic electrode 70 with the oxide layer 75 removed and the interlayer insulating film 55, an opening is made on the opposite side of the insulating film adjacent to the side where the gate electrode 60 is formed, and a resist mask 90 is formed by photolithography to etch the interlayer insulating film 55 above the Schottky trench ST.

[0097] Secondly, as in Figure 22 As shown in the cross-sectional view, the interlayer insulating film 55 (which may also include the gate insulating film 50) above the Schottky trench ST is wet-etched using an etchant containing hydrofluoric acid. In this case, the interlayer insulating film 55 (which may also include the gate insulating film 50) above the Schottky trench ST becomes the etched film. The area to be wet-etched includes the Schottky trench ST, the surface of the well region 30 adjacent to the interior of the Schottky trench ST, and the surface of the contact region 35.

[0098] Next, as in Figure 23 As shown in the cross-sectional view, the resist mask 90 is removed. Next, a source electrode 80, bonded to the drift layer 20 in a Schottky trench ST, is formed, and a drain electrode 85 is formed by grounding to the back ohmic electrode 71 on the back side, thereby enabling the fabrication of… Figure 14 The SBD shown has a built-in SiC-MOSFET.

[0099] The manufacturing method of the SBD-embedded SiC-MOSFET of the silicon carbide semiconductor device involved in this embodiment also forms a resist mask 90 on the ohmic electrode 70 after removing the oxide layer 75 formed on the surface of the ohmic electrode 70. Therefore, it is possible to prevent the etchant from reaching the vicinity of the gate electrode 60 during subsequent wet etching with an etchant containing hydrofluoric acid, and thus prevent the generation of defective products.

[0100] It should be noted that the gate trench GT and the Schottky trench ST can also be etched separately to form different depths.

[0101] Alternatively, the trap region 30 and the source region 40 can be formed by epitaxy instead of ion implantation.

[0102] Implementation Method 3

[0103] In Embodiment 1, an ohmic electrode 70 is formed with the gate insulating film 50 and interlayer insulating film 55 remaining above the region containing the Schottky junction surface that forms the surface of the first separation region 21. Then, the gate insulating film 50 and interlayer insulating film 55 on the surface of the first separation region 21 are wet-etched. However, the difference lies in that, in this embodiment, after removing the gate insulating film 50 and interlayer insulating film 55 together with the region containing the Schottky junction surface that forms the surface of the first separation region 21 and the region where the ohmic electrode 70 is formed, the ohmic electrode 70 is formed with the Schottky junction surface that forms the surface of the first separation region 21 protected by an additional protective film. Other aspects are the same as in Embodiment 1, therefore detailed descriptions are omitted.

[0104] The silicon carbide semiconductor device manufactured using the manufacturing method of this embodiment is different from the device manufactured using the manufacturing method of Embodiment 1. Figures 1-3 The SBD shown is the same as the built-in SiC-MOSFET.

[0105] The following uses Figures 24-29 The cross-sectional view illustrates the manufacturing method of the SBD-embedded SiC-MOSFET of the silicon carbide semiconductor device according to Embodiment 3 of this disclosure.

[0106] Figure 24 It is shown Figures 1-3 The diagram shows a cross-sectional view of the intermediate stage of the manufacturing process of the SBD-embedded SiC-MOSFET according to Embodiment 1 of this disclosure. Figure 24 In implementation method 1 Figure 4 After the process, a cross-sectional view of the contact hole stage is formed by dry etching. The contact hole extends from the first separation region 21, including the well region 30, to the region extending over the contact region 35 and the source region 40, and penetrates the interlayer insulating film 55 and the gate insulating film 50.

[0107] Secondly, as in Figure 25 As shown in the cross-sectional view, sacrificial oxidation is performed within the contact holes. A sacrificial oxide film 51 composed of silicon oxide is formed in the area of ​​sacrificial oxidation. By performing sacrificial oxidation, the damage layer on the silicon carbide surface generated during dry etching can be removed, and the characteristics of the SBD formed in this area can be made more uniform. Next, as in Figure 26 As shown in the cross-sectional view, within the sacrificial oxide film 51 inside the contact hole, the sacrificial oxide film 51 on the upper part of the contact region 35 and the source region 40 is removed. At the removed location, an ohmic electrode 70 is formed using the same method as in Embodiment 1. At this time, an oxide layer 75 is unintentionally formed on the surface of the ohmic electrode 70.

[0108] Next, as in Figure 27As shown in the cross-sectional view, the oxide layer 75 on the surface of the ohmic electrode 70 is removed by photolithography with hydrofluoric acid.

[0109] Next, as in Figure 28 As shown in the cross-sectional view, on the surface of the ohmic electrode 70 (with the oxide layer 75 removed) and the interlayer insulating film 55, a resist mask 90 is formed by photolithography on the opposite side of the insulating film adjacent to the side where the gate electrode 60 is formed, for etching the sacrificial oxide film 51 above the region containing the first separation region 21. Next, as in... Figure 29 As shown in the cross-sectional view, a sacrificial oxide film 51 above the surface containing the first separation region 21 is wet-etched using an etchant containing hydrofluoric acid. In this case, the sacrificial oxide film 51 becomes the etched film. The area being wet-etched is the area containing the first separation region 21, the surface of the well region 30 adjacent to the first separation region 21, and the surface of the contact region 35.

[0110] Next, in accordance with Implementation Method 1 Figure 9 Similarly, in the cross-sectional view, the resist mask 90 is removed. Next, a source electrode 80, Schottky-bonded to the first separation region 21, is formed on the first separation region 21 and its surrounding region, and a drain electrode 85 is formed by grounding to the back ohmic electrode 71 on the back side, thereby enabling the fabrication of... Figure 1 The SBD shown here incorporates a SiC-MOSFET.

[0111] In the manufacturing method of this embodiment, an ohmic electrode 70 is formed by protecting the area containing the surface that becomes the Schottky junction surface with a sacrificial oxide film 51. However, the protective film is not limited to the sacrificial oxide film 51, and may also be a protective film formed of carbon, etc.

[0112] The manufacturing method of the SBD-embedded SiC-MOSFET of the silicon carbide semiconductor device according to this embodiment also forms a resist mask 90 on the ohmic electrode 70 after removing the oxide layer 75 formed on the surface of the ohmic electrode 70. Therefore, it is possible to prevent the etch solution from reaching the vicinity of the gate electrode 60 during subsequent wet etching with an acid containing hydrofluoric acid, and thus prevent the generation of defective products.

[0113] It should be noted that in embodiments 1 to 3, Al is used as the p-type impurity, but the p-type impurity can also be boron (B) or gallium (Ga). The n-type impurity can also be phosphorus (P) instead of N. In the MOSFETs described in embodiments 1 to 3, the gate insulating film is not necessarily an oxide film such as SiO2, but can be an insulating film other than an oxide film, or a combination of an insulating film other than an oxide film and an oxide film. As the gate insulating film 50, silicon oxide formed by thermal oxidation of silicon carbide is used, but it can also be silicon oxide deposited by CVD. In addition, in the above embodiments, specific examples such as crystal structure, surface orientation of the main surface, offset angle, and various implantation conditions are used for description, but the application scope is not limited to these numerical ranges.

[0114] Furthermore, as an example of a mask, a photoresist mask is shown, but hard masks such as silicon nitride, gallium nitride, aluminum nitride, and metals such as tungsten, molybdenum, nickel, and chromium, which are resistant to hydrofluoric acid, can also be used. Alternatively, a laminate of these hard masks and photoresist masks can also be used. These hard masks can also remain directly within the silicon carbide semiconductor device without being removed.

[0115] Furthermore, in the above embodiment, the case of embedding the SBD in a so-called vertical MOSFET with the drain electrode formed on the back side of the semiconductor substrate 10 was described. However, it can also be applied to the case of embedding the SBD in a so-called horizontal MOSFET such as a RESURF-type MOSFET with the drain electrode formed on the surface of the drift layer 20. Furthermore, the silicon carbide semiconductor device can also be a device in which the SBD is embedded in an insulated gate bipolar transistor (IGBT). Additionally, it can also be applied to MOSFETs with superjunction structures and MOSFETs with embedded SBDs in IGBTs.

[0116] Implementation Method 4

[0117] This embodiment applies the manufacturing method of the silicon carbide semiconductor device described in Embodiments 1 to 3 to the manufacturing of a power conversion device. This disclosure is not limited to a specific manufacturing method of a power conversion device; hereinafter, as Embodiment 4, the application of this disclosure to a manufacturing method of a three-phase inverter will be described.

[0118] Figure 30 This is a block diagram showing the configuration of a power conversion system using the power conversion device according to this embodiment.

[0119] Figure 30The power conversion system shown consists of a power source 100, a power conversion device 200, and a load 300. The power source 100 is a DC power source, supplying DC power to the power conversion device 200. The power source 100 can be composed of various power sources, such as a DC system, solar cells, or batteries, or it can be composed of a rectifier circuit or an AC / DC converter connected to an AC system. Alternatively, the power source 100 can also be composed of a DC / DC converter that converts DC power output from a DC system into a specified power.

[0120] The power conversion device 200 is a three-phase inverter connected between the power source 100 and the load 300, which converts the DC power supplied from the power source 100 into AC power and supplies AC power to the load 300. For example... Figure 30 As shown, the power conversion device 200 includes: a main conversion circuit 201 that converts DC power into AC power and outputs it; a drive circuit 202 that outputs drive signals to drive each switching element of the main conversion circuit 201; and a control circuit 203 that outputs control signals to control the drive circuit 202.

[0121] The drive circuit 202 controls the shutdown by making the voltage of the gate electrode of each normally closed switching element the same potential as the voltage of the source electrode.

[0122] Load 300 is a three-phase motor driven by AC power supplied from power conversion device 200. It should be noted that load 300 is not limited to a specific application, but is a motor mounted on various electrical equipment, such as for use as a motor in hybrid vehicles, electric vehicles, railway vehicles, elevators, or air conditioning equipment.

[0123] The power conversion device 200 will be described in detail below. The main conversion circuit 201 includes switching elements (not shown), which switch the DC power supplied from the power source 100 to AC power and supply it to the load 300. The main conversion circuit 201 has various specific circuit configurations, but the main conversion circuit 201 in this embodiment is a two-level three-phase full-bridge circuit, which can be composed of six switching elements and six freewheeling diodes connected in reverse parallel with each switching element. Each switching element in the main conversion circuit 201 uses a silicon carbide semiconductor device manufactured using the manufacturing method of any one of embodiments 1 to 3 described above. Every two of the six switching elements are connected in series to form upper and lower arms, and each upper and lower arm constitutes a phase (U phase, V phase, W phase) of the full-bridge circuit. Furthermore, the output terminals of each upper and lower arm, i.e., the three output terminals of the main conversion circuit 201, are connected to the load 300.

[0124] The drive circuit 202 generates drive signals to drive the switching elements of the main conversion circuit 201 and supplies them to the control electrodes of the switching elements of the main conversion circuit 201. Specifically, based on the control signal from the control circuit 203 (described later), drive signals that turn the switching elements on and off are output to the control electrodes of each switching element. When the switching element is kept on, the drive signal is a voltage signal above the threshold voltage of the switching element (on signal); when the switching element is kept off, the drive signal is a voltage signal below the threshold voltage of the switching element (off signal).

[0125] Control circuit 203 controls the switching elements of main conversion circuit 201 to supply the desired power to load 300. Specifically, based on the power to be supplied to load 300, the time (on-time) during which each switching element of main conversion circuit 201 should be in the on state is calculated. For example, main conversion circuit 201 can be controlled by PWM control that modulates the on-time of the switching elements according to the output voltage. Furthermore, control commands (control signals) are output to drive circuit 202, causing on signals to be output to the switching elements that should be in the on state and off signals to be output to the switching elements that should be in the off state at each time. Drive circuit 202 outputs on or off signals as drive signals to the control electrodes of each switching element according to the control signal.

[0126] In the manufacturing method of the power conversion device according to this embodiment, the switching element of the main conversion circuit 201 is a silicon carbide semiconductor device manufactured using the manufacturing method of the silicon carbide semiconductor device according to embodiments 1 to 3. Therefore, a power conversion device with low loss and improved reliability of high-speed switching can be realized.

[0127] In this embodiment, an example of applying the present disclosure to a two-level three-phase inverter has been described, but the present disclosure is not limited thereto and can be applied to various power conversion devices. In this embodiment, a two-level power conversion device is used, but it can also be a three-level or multi-level power conversion device. When supplying power to a single-phase load, the present disclosure can also be applied to a single-phase inverter. Furthermore, when supplying power to DC loads, the present disclosure can also be applied to DC / DC converters and AC / DC converters.

[0128] Furthermore, the power conversion device disclosed herein is not limited to the case where the load is an electric motor. For example, it can also be used as a power supply device for electrical discharge machining, laser processing machines, induction heating cookers, contactless power supply systems, and as a power regulator for solar power generation systems, energy storage systems, etc.

[0129] Explanation of reference numerals in the attached figures

[0130] 10 Semiconductor substrate, 20 Drift layer, 21 First separation region, 22 Second separation region, 30 Well region, 35 Contact region, 40 Source region, 50 Gate insulating film, 51 Sacrificial oxide film, 55 Interlayer insulating film, 60 Gate electrode, 70 Ohmic electrode, 71 Backside ohmic electrode, 75 Oxide layer, 80 Source electrode, 85 Drain electrode, 90 Resist mask, 100 Power supply, 200 Power conversion device, 201 Main conversion circuit, 202 Drive circuit, 203 Control circuit, 300 Load, GT Gate trench, ST Schottky trench.

Claims

1. A method of manufacturing a silicon carbide semiconductor device, characterized by, include: In the insulating film formation process, a well region is formed in a drift layer made of silicon carbide, a source region and a contact region are formed in the well region, a gate insulating film is formed on the silicon carbide surface of the drift layer, the well region, the source region and the contact region, the gate insulating film exposes the area where the source region and the contact region are connected, a patterned gate electrode is formed on the gate insulating film, and then an interlayer insulating film is formed covering the surface of the gate electrode and the gate insulating film. An ohmic electrode forming process, wherein a contact hole is formed that penetrates the interlayer insulating film and the gate insulating film, reaching the contact region and the source region within the active region, and an ohmic electrode is formed within the contact hole; The process of removing the oxide layer on the ohmic electrode is as follows: the oxide layer is formed by reacting a metal film with a silicon carbide layer in the contact hole to form a silicide between the silicon carbide layer and the metal film, the formed silicide becomes the ohmic electrode, and an oxide layer is formed on the surface of the ohmic electrode. A mask forming process, wherein a mask is formed on the ohmic electrode and the interlayer insulating film after the oxide layer has been removed, and the mask has an opening formed on the interlayer insulating film on the side of the contact hole away from the gate electrode and exposing the upper surface of the interlayer insulating film; A process of wet etching the etched films, which serve as the gate insulating film and the interlayer insulating film, using hydrofluoric acid while the mask is formed; and The process of removing the mask after wet etching the etched film.

2. The method for manufacturing a silicon carbide semiconductor device according to claim 1, wherein The oxide layer was removed by photolithography using hydrofluoric acid.

3. The method for manufacturing a silicon carbide semiconductor device according to claim 1 or 2, wherein The ohmic electrode is a silicide.

4. The method for manufacturing a silicon carbide semiconductor device according to claim 3, wherein The silicide is nickel silicide.

5. The method for manufacturing a silicon carbide semiconductor device according to claim 1 or 2, wherein The etched film is silicon oxide.

6. The method for manufacturing a silicon carbide semiconductor device according to claim 1 or 2, wherein, The interlayer insulating film is silicon oxide.

7. The method for manufacturing a silicon carbide semiconductor device according to claim 1 or 2, wherein, A Schottky interface is formed on the surface of the silicon carbide layer after the etched film has been removed by the wet etching, which bonds the silicon carbide layer to the source electrode.

8. The method for manufacturing a silicon carbide semiconductor device according to claim 7, wherein, The interlayer insulating film is an interlayer insulating film formed by grounding the gate electrode of the MOSFET, and the silicon carbide semiconductor device is an SBD built-in MOSFET.

9. The method for manufacturing a silicon carbide semiconductor device according to claim 8, wherein, The SBD-embedded MOSFET has the ohmic electrode and the Schottky interface within a contact hole formed through the interlayer insulating film.

10. The method for manufacturing a silicon carbide semiconductor device according to claim 9, wherein, The Schottky interface is formed by the ohmic electrode surrounding it.

11. The method for manufacturing a silicon carbide semiconductor device according to any one of claims 8-10, wherein, The SBD has a built-in MOSFET with a trench-type MOSFET and an SBD formed in the trench.

12. The method for manufacturing a silicon carbide semiconductor device according to claim 5, wherein, The etched film is the interlayer insulating film.

13. The method for manufacturing a silicon carbide semiconductor device according to claim 5, wherein, The etched film is a sacrificial oxide film.

14. A power conversion device comprising: The main conversion circuit has a silicon carbide semiconductor device manufactured using the manufacturing method of a silicon carbide semiconductor device according to any one of claims 1 to 13, which converts and outputs the input power; The driving circuit performs a disconnection operation by setting the voltage of the gate electrode of the silicon carbide semiconductor device below a threshold voltage, and outputs a driving signal for driving the silicon carbide semiconductor device to the silicon carbide semiconductor device. and A control circuit that outputs control signals to the drive circuit to control the drive circuit.

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