Display panel and display device

Abstract

The present application provides a display panel and a display device; by making at least a portion of at least one of a reset signal line and a low-potential signal line located in a gate drive circuit area, the display panel can at least reduce the area occupied by the reset signal line and the low-potential signal line disposed in the gate drive circuit area, reduce the width of the frame required for the portion, and thus reduce the frame of the display panel. In addition, the solution does not require the gate drive circuit to be disposed on a light-emitting unit, thereby reducing the process difficulty of display panel preparation and improving the yield of the display panel.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] In order to achieve narrow borders, existing display devices extend the gate drive circuit to the display area, set the light-emitting unit on the gate drive circuit, and compress the pixel unit to reduce the border. However, this method is only applicable to display devices with lower resolution. As the resolution increases, the pixel size cannot be further compressed, resulting in a still large border of the display device. In addition, the process requires multiple line changes to achieve control of the light-emitting unit, resulting in a complex process and low yield. In addition, since the display panel uses LTPO (Low Temperature Poly-Oxide, LTPO) technology to reduce power consumption, this will further increase the difficulty of the process and reduce the yield.

[0003] Therefore, the existing display device has a technical problem that the light-emitting unit is arranged on the gate driving circuit, which leads to a low yield of the display device. Summary of the invention

[0004] Embodiments of the present application provide a display panel and a display device, which are used to alleviate the technical problem that the light-emitting unit of the existing display device is disposed on the gate driving circuit, resulting in a low yield of the display device.

[0005] An embodiment of the present application provides a display panel, the display panel comprising:

[0006] A display area, wherein the display area is provided with a pixel light emitting unit and a pixel driving circuit for controlling the pixel light emitting unit;

[0007] A non-display area, located at the periphery of the display area, the non-display area includes a gate drive circuit area, and the non-display area is provided with a reset signal line and a low potential signal line;

[0008] Among them, the reset signal line is connected to the pixel driving circuit, the low potential signal line is connected to the pixel light-emitting unit, the gate driving circuit area is provided with a gate driving circuit, at least a portion of at least one of the reset signal line and the low potential signal line is arranged in the gate driving circuit area, and the reset signal line and the low potential signal line are insulated from the gate driving circuit.

[0009] In some embodiments, the gate driving circuit includes multiple metal layers, and at least part of the reset signal line and the low potential signal line are arranged in a different layer from any metal layer in the gate driving circuit.

[0010] In some embodiments, the display panel includes:

[0011] substrate;

[0012] A semiconductor layer, disposed on one side of the substrate;

[0013] A first metal layer is disposed on a side of the semiconductor layer away from the substrate;

[0014] A second metal layer is disposed on a side of the first metal layer away from the semiconductor layer;

[0015] A first source-drain electrode layer is disposed on a side of the second metal layer away from the first metal layer;

[0016] A second source-drain electrode layer, disposed on a side of the first source-drain electrode layer away from the second metal layer;

[0017] Wherein, the gate drive circuit includes a transistor and a capacitor, the transistor includes a gate, a source and a drain, the capacitor includes a capacitor plate, the gate is arranged on the first metal layer, the capacitor plate is arranged on the second metal layer, the source and the drain are arranged on the first source-drain layer, and at least part of the reset signal line and the low-potential signal line are arranged in a metal different layer from the first metal layer, the second metal layer, the first source-drain layer and the second source-drain layer in the gate drive circuit.

[0018] In some embodiments, the display panel also includes a third source and drain layer, a first planarization layer, and a second planarization layer, the third source and drain layer is arranged on a side of the second source and drain layer away from the first source and drain layer, the first planarization layer is arranged between the first source and drain layer and the second source and drain layer, and the second planarization layer is arranged between the second source and drain layer and the third source and drain layer; at least one of the reset signal line and the low potential signal line includes a first overlapping portion arranged in the third source and drain layer, and a projection of the first overlapping portion on the substrate overlaps with a projection of the gate drive circuit on the substrate.

[0019] In some embodiments, the reset signal line is disposed in the third source-drain layer, and a projection of the reset signal line on the substrate overlaps with a projection of the gate driving circuit on the substrate.

[0020] In some embodiments, the projection of the reset signal line on the substrate overlaps with the projection of the source on the substrate, or the projection of the reset signal line on the substrate overlaps with the projection of the drain on the substrate, or the projection of the reset signal line on the substrate overlaps with the projection of the gate on the substrate, or the projection of the reset signal line on the substrate overlaps with the projection of the capacitor plate on the substrate.

[0021] In some embodiments, the pixel driving circuit includes a first reset transistor and a second reset transistor, the second source and drain layer includes a connecting metal, the reset signal line passes through a via hole in the second planarization layer and is connected to the connecting metal, the connecting metal extends from the gate driving circuit area to the display area and is connected to the first reset transistor and the second reset transistor.

[0022] In some embodiments, the low potential signal line is disposed in the third source-drain layer, and a projection of the low potential signal line on the substrate overlaps with a projection of the gate driving circuit on the substrate.

[0023] In some embodiments, the low-potential signal line includes a first part, a second part and a third part, the first part is arranged in the first source and drain layer, the second part is arranged in the second source and drain layer, the third part is arranged in the third source and drain layer, the second part is connected to the first part through a via hole in the first planarization layer, the third part is connected to the second part through a via hole in the second planarization layer, the projection of the third part on the substrate overlaps with the projection of the gate drive circuit on the substrate, and the width of the third part is greater than the width of the first part, and the width of the third part is greater than the width of the second part.

[0024] In some embodiments, the display panel also includes a fourth source and drain layer, the fourth source and drain layer is arranged on a side of the third source and drain layer away from the second source and drain layer, the reset signal line is arranged in the fourth source and drain layer, and the projection of the reset signal line on the substrate overlaps with the projection of the third part on the substrate.

[0025] In some embodiments, the display panel also includes a light-shielding layer, which is disposed between the substrate and the semiconductor layer, and at least one of the reset signal line and the low-potential signal line includes a second overlapping portion disposed in the light-shielding layer, and a projection of the second overlapping portion on the substrate overlaps with a projection of the gate drive circuit on the substrate.

[0026] In some embodiments, the reset signal line is disposed on the light shielding layer, and a projection of the reset signal line on the substrate overlaps with a projection of the gate driving circuit on the substrate.

[0027] In some embodiments,

[0028] The low potential signal line includes a first portion, a second portion and a fourth portion, the first portion is arranged on the first source-drain electrode layer, the second portion is arranged on the second source-drain electrode layer, and the fourth portion is arranged on the light shielding layer;

[0029] The display panel further includes a first insulating layer, a second insulating layer, a third insulating layer, a fourth insulating layer, a fifth insulating layer, an active layer and a third metal layer, wherein the first insulating layer is disposed between the semiconductor layer and the first metal layer, the second insulating layer is disposed between the first metal layer and the second metal layer, the third insulating layer is disposed between the second metal layer and the active layer, the fourth insulating layer is disposed between the active layer and the third metal layer, and the fifth insulating layer is disposed between the third metal layer and the first source-drain electrode layer.

[0030] Among them, the second part is connected to the first part through the via hole of the first planarization layer, the first part is connected to the fourth part through the via holes of the first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer and the fifth insulating layer, the projection of the fourth part on the substrate overlaps with the projection of the gate driving circuit on the substrate, and the width of the fourth part is greater than the width of the first part, and the width of the fourth part is greater than the width of the second part.

[0031] At the same time, an embodiment of the present application provides a display device, which includes the display panel and the driving chip described in any of the above embodiments.

[0032] Beneficial effects: The present application provides a display panel and a display device; the display panel includes a display area and a non-display area, the display area is provided with a pixel light-emitting unit and a pixel driving circuit for controlling the pixel light-emitting unit, the non-display area is located outside the display area, the non-display area includes a gate driving circuit area, the non-display area is provided with a reset signal line and a low potential signal line, wherein the reset signal line is connected to the pixel driving circuit, the low potential signal line is connected to the pixel light-emitting unit, the gate driving circuit is provided in a gate driving circuit, at least a portion of at least one of the reset signal line and the low potential signal line is provided in the gate driving circuit area, and the reset signal line and the low potential signal line are insulated from the gate driving circuit. The present application can at least reduce the area occupied by the reset signal line and the low potential signal line provided in the gate driving circuit area by making at least a portion of at least one of the reset signal line and the low potential signal line provided in the gate driving circuit area, reduce the width of the frame required for the portion, thereby reducing the frame of the display panel, and the scheme does not need to provide the gate driving circuit on the light-emitting unit, reduce the process difficulty of display panel preparation, and improve the yield of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The technical solution and other beneficial effects of the present application will be made apparent by describing in detail the specific implementation methods of the present application in conjunction with the accompanying drawings.

[0034] Figure 1 A first schematic diagram of a display panel provided in an embodiment of the present application.

[0035] Figure 2 A circuit diagram of a display panel provided in an embodiment of the present application.

[0036] Figure 3 A second schematic diagram of a display panel provided in an embodiment of the present application.

[0037] Figure 4 A comparison diagram of the arrangement areas of the components of the current display device provided in the embodiment of the present application and the display panel of the present application.

[0038] Figure 5 A first perspective view of a display panel provided in an embodiment of the present application.

[0039] Figure 6 A second perspective view of the display panel provided in an embodiment of the present application.

[0040] Figure 7 A third perspective view of the display panel provided in the embodiment of the present application. DETAILED DESCRIPTION

[0041] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0042] In view of the technical problem that the light-emitting unit of the existing display device is disposed on the gate driving circuit, which leads to a low yield of the display device, the embodiments of the present application provide a display panel and a display device to alleviate the above technical problem.

[0043] like Figure 1 , Figure 2 As shown, an embodiment of the present application provides a display panel, and the display panel 1 includes:

[0044] A display area 181, wherein the display area 181 is provided with a pixel light emitting unit LED and a pixel driving circuit 21 for controlling the pixel light emitting unit LED;

[0045] A non-display area 182 is located at the periphery of the display area 181. The non-display area 182 includes a gate drive circuit area 183. The non-display area 182 is provided with a reset signal line 171 and a low potential signal line 16;

[0046] Among them, the reset signal line 171 is connected to the pixel driving circuit 21, the low potential signal line 16 is connected to the pixel light-emitting unit LED, the gate driving circuit area 183 is provided with a gate driving circuit 22, and at least a portion of at least one of the reset signal line 171 and the low potential signal line 16 is arranged in the gate driving circuit area 183, and the reset signal line 171 and the low potential signal line 16 are insulated from the gate driving circuit 22.

[0047] An embodiment of the present application provides a display panel. By setting at least a portion of at least one of a reset signal line and a low-potential signal line in a gate drive circuit area, the display panel can at least reduce the area occupied by the portion of the reset signal line and the low-potential signal line set in the gate drive circuit area, reduce the width of the frame required for this portion, and thus reduce the frame of the display panel. In addition, this solution does not require the gate drive circuit to be set on the light-emitting unit, reduces the process difficulty of display panel preparation, and improves the yield of the display panel.

[0048] It should be noted that Figure 1 is a cross-sectional view of the display panel, therefore, Figure 1 All components of a single sub-pixel are not shown, only some transistors, wirings and capacitors are shown, so it can be understood that Figure 1 The pixel driving circuit in includes not only two transistors, but also other components; similarly, Figure 1 The gate driving circuit shown includes not only a single transistor, but also other components. Specifically, the components included in the pixel driving circuit may be Figure 2 The circuit shown has multiple components.

[0049] It should be noted that in Figure 1 In the cross-sectional view shown in FIG. 1 , the low potential signal line is labeled with reference numeral 16. Figure 2 In the circuit diagram shown in the figure, the low potential signal line is marked with ELVSS. This is just a different marking method in different diagrams. Figure 1 The low potential signal line in the cross-sectional view shown corresponds to Figure 2 The low-potential signal line in the circuit diagram shown is similarly the same component as the components with different marking methods in other cross-sectional views and circuit diagrams, which will not be described in detail here.

[0050] It should be noted that the projection of the reset signal line and the low-potential signal line on the plane where the gate drive circuit is located refers to the projection of the reset signal line and the low-potential signal line on the plane where any metal layer in the gate drive circuit is located. Taking the gate drive circuit including the metal of the gate layer as an example, the projection can be the projection of the reset signal line and the low-potential signal line on the gate layer. The projection is located in the gate drive circuit area and is insulated from the gate drive circuit, that is, a portion of at least one of the reset signal line and the low-potential signal line is arranged in the gate drive circuit area, and overlaps with the projection of the gate drive circuit, that is, the width of the border occupied by at least one of the reset signal line and the low-potential signal line is reduced, thereby reducing the border of the display panel.

[0051] It should be noted that, although the pixel light emitting unit is indicated by LED, the present application does not limit the pixel light emitting unit to a light emitting diode, and the pixel light emitting unit may be an organic light emitting diode.

[0052] In one embodiment, the gate driving circuit includes a transistor, the pixel driving circuit includes a connecting wire, the reset signal line is connected to the pixel driving circuit through the connecting wire, and at least a portion of the connecting wire is arranged in a metal layer in the metal layer where the transistor is located. By making at least a portion of the connecting wire be arranged in a metal layer in the metal layer where the transistor is located, the connecting wire does not need to increase the metal layer, thereby avoiding increasing the thickness of the display panel.

[0053] In one embodiment, the pixel driving circuit includes a connecting line, the reset signal line is connected to the pixel driving circuit through the connecting line, the connecting line extends from the gate driving circuit area to the display area, and the connecting line and the reset signal line are arranged in the same metal layer. By arranging the connecting line and the reset signal line in the same layer, there is no need to add a metal layer when forming the connecting line, thereby avoiding increasing the thickness of the display panel, and the connecting line and the reset signal line can be formed simultaneously by etching, thereby avoiding increasing the process difficulty.

[0054] In one embodiment, the display panel includes a connection hole, the connection hole is arranged in the display area, and the connection hole is located on the pixel driving circuit, and the connection line passes through the connection hole. By arranging the connection hole in the display area and on the pixel driving circuit, the connection line is formed by using the same metal layer as the reset signal line, so that the connection line can be directly connected to the pixel driving circuit through the connection hole without changing the position of the connection hole, thereby reducing the process complexity.

[0055] In one embodiment, the gate drive circuit includes multiple metal layers, and at least part of the reset signal line and the low potential signal line are arranged in a different layer from any metal layer in the gate drive circuit. By making the reset signal line and the low potential signal line arranged in a different layer from any metal in the gate drive circuit, when the reset signal line and the low potential signal line are arranged in the gate drive circuit area to reduce the frame, the reset signal line and the low potential signal line will not be arranged in the film layer where the gate drive circuit is located, thereby preventing the reset signal line and the low potential signal line from short-circuiting or interfering with the metal in the gate drive circuit.

[0056] In view of the small free space of each film layer in the gate drive circuit, setting a reset signal line or a low potential signal line may cause signal interference or short circuit and other problems. Figure 1 As shown, the display panel 1 includes:

[0057] Substrate 11;

[0058] The semiconductor layer 141 is disposed on one side of the substrate 11;

[0059] A first metal layer 143 is disposed on a side of the semiconductor layer 141 away from the substrate 11;

[0060] A second metal layer 145 is disposed on a side of the first metal layer 143 away from the semiconductor layer 141;

[0061] A first source-drain electrode layer 151 is disposed on a side of the second metal layer 145 away from the first metal layer 143;

[0062] A second source-drain electrode layer 153 is disposed on a side of the first source-drain electrode layer 151 away from the second metal layer 145;

[0063] In which, the gate drive circuit 22 includes a transistor and a capacitor, the transistor includes a gate 143a, a source 151d and a drain 151b, the capacitor includes a capacitor plate 145a, the gate 143a is arranged on the first metal layer 143, the capacitor plate 145a is arranged on the second metal layer 145, the source 151d and the drain 151b are arranged on the first source-drain layer 151, and at least part of the reset signal line 171 and the low-potential signal line 16 are arranged in a metal layer different from the metal layer 143, the second metal layer 145, the first source-drain layer 151 and the second source-drain layer 153 in the gate drive circuit 22.

[0064] by Figure 1 Taking the display panel shown as an example, Figure 1It can be seen that the reset signal line 171 and the low potential signal line 16 are arranged in a different layer from any metal in the gate drive circuit 22. When the reset signal line and the low potential signal line are arranged in the gate drive circuit area to reduce the border, the reset signal line and the low potential signal line will not be arranged in the film layer where the gate drive circuit is located, thereby avoiding short circuit or interference between the reset signal line and the low potential signal line and the metal in the gate drive circuit.

[0065] Specifically, from Figure 1 It can be seen that the gate drive circuit includes a transistor and a capacitor. The transistor includes a gate, a source, and a drain. The capacitor includes a capacitor plate. Therefore, when the parts of the reset signal line and the low-potential signal line set in the gate drive circuit are set in the film layer where these components are located, short circuit or interference will occur. The embodiment of the present application avoids interference between the reset signal line and the low-potential signal line and the components in the gate drive circuit, resulting in poor signal, by setting the reset signal line and the low-potential signal line in other film layers.

[0066] It should be noted that, in the embodiment of the present application, only the reset signal line and the low potential signal line are limited to the metal different layer arrangement in the gate drive circuit area, and the reset signal line and the low potential signal line are not limited to the part outside the gate drive circuit area. Figure 1 It can be seen that the low potential signal line also includes a portion arranged in the first source and drain layer.

[0067] The reset signal line or the low potential signal line is set in the metal film layer in the gate drive circuit, which may cause signal interference or short circuit. In one embodiment, Figure 1As shown, the display panel 1 also includes a third source-drain layer 154, a first planarization layer 152 and a second planarization layer 155, the third source-drain layer 154 is arranged on the side of the second source-drain layer 153 away from the first source-drain layer 151, the first planarization layer 152 is arranged between the first source-drain layer 151 and the second source-drain layer 153, and the second planarization layer 155 is arranged between the second source-drain layer 153 and the third source-drain layer 154; at least one of the reset signal line 171 and the low-potential signal line 16 includes a first overlapping portion arranged in the third source-drain layer 154, and the projection of the first overlapping portion on the substrate 11 overlaps with the projection of the gate drive circuit 22 on the substrate 11. By adding a third source and drain layer, the reset signal line and the low potential signal line can be set in the third source and drain layer, and will not be in the same film layer as the metal of the gate drive circuit, thereby avoiding interference or short circuit between the metal in the gate drive circuit (such as the gate) and the reset signal line and the low potential signal line, resulting in signal transmission errors between the gate drive circuit and the pixel drive circuit. In addition, the reset signal line and the low potential signal line are formed by the newly added third source and drain layer, which can increase the width of the reset signal line and the low potential signal line and reduce the impedance of the reset signal line and the low potential signal line.

[0068] Specifically, the first overlapped portion refers to the portion of the reset signal line and the low potential signal line that is in the gate drive circuit area. Figure 1 For example, all parts of the reset signal line are located in the gate drive circuit area, then the first overlapping part of the reset signal line refers to the entire reset signal line, and only a part of the low potential signal line is in the gate drive circuit area, then the first overlapping part of the low potential signal line refers to the third part 163 of the low potential signal line that is in the gate drive circuit area.

[0069] The reset signal line is arranged in the second source-drain layer, which may result in a larger frame of the display panel. Figure 1 As shown, the reset signal line 171 is arranged on the third source-drain electrode layer 154, and the projection of the reset signal line 171 on the substrate 11 overlaps with the projection of the gate driving circuit 22 on the substrate 11. By arranging the reset signal line on the third source-drain electrode layer, the width of the frame can be reduced, and the process connects the metal of the third source-drain electrode layer to the second source-drain electrode layer and other metal layers through vias, which will not cause process risks and improve the yield of the display panel.

[0070] Specifically, since the width of the reset signal line is relatively small, the reset signal line can be disposed entirely on the gate driving circuit, thereby eliminating the width of the frame occupied by the reset signal line and reducing the frame of the display panel.

[0071] In one embodiment, the projection of the reset signal line on the substrate overlaps with the projection of the source on the substrate, or the projection of the reset signal line on the substrate overlaps with the projection of the drain on the substrate, or the projection of the reset signal line on the substrate overlaps with the projection of the gate on the substrate, or the projection of the reset signal line on the substrate overlaps with the projection of the capacitor plate on the substrate. When the reset signal line is set in the third source and drain layer, since the width of the reset signal line is small, it is not necessary to occupy the entire area of ​​the gate drive circuit area. Therefore, the reset signal line can overlap with the projection of the source, drain, gate and capacitor plate on the substrate, so that the reset signal line is in the area where the gate drive circuit is located, and there is no need to set a frame area corresponding to the reset signal line, thereby reducing the frame of the display panel.

[0072] Specifically, the projection of the reset signal line on the substrate overlaps with the projection of the gate on the substrate. The third source-drain layer set for the reset signal line may generate parasitic capacitance with the metal of the second source-drain layer. The projection of the reset signal line and the gate on the substrate can be overlapped. Since the distance between the film layer where the reset signal line and the gate are located is large, the possibility of parasitic capacitance is reduced, thereby avoiding interference of the signal with the parasitic capacitance between the reset signal line and other metals.

[0073] In one embodiment, the pixel driving circuit includes a first reset transistor and a second reset transistor, the first source-drain electrode layer includes a connection metal, the reset signal line passes through a via hole in the second planarization layer and is connected to the connection metal, the connection metal extends from the gate driving circuit area to the display area and is connected to the first reset transistor and the second reset transistor. By forming the connection metal in the first source-drain electrode layer, the connection metal can connect the reset signal line and the first reset transistor and the second reset transistor, thereby achieving normal operation of the reset signal line.

[0074] Specifically, when the reset signal line is set in the third source and drain layer, the reset signal line can be connected to the second source and drain layer in the gate driving circuit area, and then the reset signal line is extended to the display area through the connecting metal of the second source and drain layer, and connected to the source and drain of the first reset transistor and the second reset transistor in the display area to realize signal input to the first reset transistor and the second reset transistor.

[0075] In one embodiment, if Figure 2As shown, the reset signal line includes a first reset signal line VI-G and a second reset signal line VI-ANO, at least one of the first reset signal line VI-G and the second reset signal line VI-ANO is arranged in the third source and drain layer, and the projection of the part of the first reset signal line VI-G and the second reset signal line VI-ANO arranged in the third source and drain layer on the substrate overlaps with the projection of the gate drive circuit on the substrate.

[0076] For a display panel having multiple reset signal lines, each reset signal line can be arranged in the third source-drain electrode layer, so that each reset signal line is arranged in the gate driving circuit area, thereby reducing the width of the frame occupied by each reset signal line.

[0077] The problem that the low-potential signal line is set in the first source-drain layer and the second source-drain layer will cause the border of the display panel to be larger. In one embodiment, the low-potential signal line is set in the third source-drain layer, and the projection of the low-potential signal line on the substrate overlaps with the projection of the gate drive circuit on the substrate. By setting the low-potential signal line in the third source-drain layer, the width of the border occupied by the low-potential signal line can be reduced, thereby reducing the border of the display panel, and the impedance of the low-potential signal line can be reduced by the third source-drain layer, thereby further reducing the border of the display panel.

[0078] In order to solve the problem that the width of the low potential signal line is large, the width of the border occupied by the low potential signal line is large. In one embodiment, Figure 1 As shown, the low-potential signal line 16 includes a first part 161, a second part 162 and a third part 163, the first part 161 is arranged on the first source-drain layer 151, the second part 162 is arranged on the second source-drain layer 153, the third part 163 is arranged on the third source-drain layer 154, the second part 162 is connected to the first part 161 through the via hole of the first planarization layer 152, the third part 163 is connected to the second part 162 through the via hole of the second planarization layer 155, the projection of the third part 163 on the substrate 11 overlaps with the projection of the gate drive circuit 22 on the substrate 11, and the width of the third part 163 is greater than the width of the first part 161, and the width of the third part 163 is greater than the width of the second part 162.

[0079] By setting the low-potential signal line to the first part, the second part and the third part, the signal can be transmitted to the display area through the connected first part, the second part and the third part, so that the low-potential signal line can work normally, and the third part is set in the third source and drain layer, and the third part overlaps with the projection of the gate drive circuit on the substrate, so the width of the border occupied by the third part can be reduced, and since the third part extends from the low-potential signal line setting area where the first part and the second part are located to the gate drive circuit area, the width of the third part is relatively large, which reduces the impedance of the low-potential signal line, and the third part is connected in parallel with the second part, and the second part is connected in parallel with the first part, which further reduces the impedance of the low-potential signal line, so that the impedance of the low-potential signal line meets the driving requirements or even reduces the impedance of the low-potential signal line, thereby reducing the width of the first part and the second part, reducing the width of the border occupied by the low-potential signal line, and thus reducing the width of the border of the display panel.

[0080] Specifically, Figure 1 As shown, the non-display area 182 also includes a low-potential signal line area 184, the first part 161 and the second part 162 are arranged in the low-potential signal line area 184, and the third part 163 extends from the low-potential signal line area 184 to the gate driving circuit area 183, thereby reducing the width of the border of the display panel.

[0081] The above embodiments are described in detail by taking the reset signal line and the low potential signal line as examples of setting the reset signal line and the low potential signal line in the third source and drain layer. It can be understood that the reset signal line and the low potential signal line can be set in the third source and drain layer at the same time to further reduce the border of the display panel. In this case, it is only necessary to insulate the reset signal line and the low potential signal line. The setting method of the reset signal line and the low potential signal line can be set as described in the above embodiments, which will not be repeated here.

[0082] The problem that setting the reset signal line and the low potential signal line in the third source and drain layer still leads to a larger border is addressed. In one embodiment, the display panel also includes a fourth source and drain layer, the fourth source and drain layer is arranged on the side of the third source and drain layer away from the second source and drain layer, the reset signal line is arranged in the fourth source and drain layer, and the projection of the reset signal line on the substrate overlaps with the projection of the third part on the substrate. By setting the reset signal line in the fourth source and drain layer, the third part of the low potential signal line can be set in all areas of the gate drive circuit, thereby further reducing the width of the border occupied by the low potential signal line, and the reset signal line is set in the fourth source and drain layer, which can also reduce the width of the border occupied by the reset signal line, so that the border of the display panel does not need to set the setting area of ​​the reset signal line, and the width of the set low potential signal setting area is smaller, further reducing the border of the display panel.

[0083] Specifically, when the reset signal line is set in the fourth source and drain layer, connecting metals can be set in the third source and drain layer and the second source and drain layer respectively, so that the reset signal line is connected to the connecting metal of the third source and drain layer, and then connected to the connecting metal of the second source and drain layer, and by extending the connecting metal to the display area and connecting to the source and drain of the first reset transistor and the second reset transistor, signal input to the first reset transistor and the second reset transistor is realized.

[0084] Setting a reset signal line and a low potential signal line for the newly added film layer will result in a technical problem that the thickness of the display panel is large. Figure 3 As shown, the display panel 1 further includes a light shielding layer 12, and the light shielding layer 12 is arranged between the substrate 11 and the semiconductor layer 141. At least one of the reset signal line 171 and the low potential signal line 16 includes a second overlapping portion arranged on the light shielding layer 12, and the projection of the second overlapping portion on the substrate 11 overlaps with the projection of the gate drive circuit 22 on the substrate 11. By arranging at least one of the reset signal line and the low potential signal line on the light shielding layer, the space occupied by the reset signal line and the low potential signal line can be reduced, the frame of the display panel can be reduced, and the reset signal line and the low potential signal line will not be in the same film layer as the metal of the gate drive circuit, thereby avoiding interference or short circuit between the metal (such as the gate) in the gate drive circuit and the reset signal line and the low potential signal line. By forming the reset signal line and the low potential signal line through the light shielding layer, the width of the reset signal line and the low potential signal line can be increased, and the impedance of the reset signal line and the low potential signal line can be reduced.

[0085] Specifically, the second overlapped portion refers to the portion of the reset signal line and the low potential signal line that is in the gate drive circuit area. Figure 3 For example, all parts of the reset signal line are located in the gate drive circuit area, and the second overlapping part of the reset signal line refers to the entire reset signal line; similarly, the second overlapping part of the low potential signal line refers to the part of the low potential signal line in the gate drive circuit area.

[0086] In one embodiment, if Figure 3 As shown, the reset signal line 171 is arranged on the light shielding layer 12, and the projection of the reset signal line 171 on the substrate 11 overlaps with the projection of the gate driving circuit 22 on the substrate 11. By arranging the reset signal line on the light shielding layer, the width of the frame occupied by the reset signal line can be reduced, thereby reducing the frame of the display panel, and since there is no need to increase the film layer, the thickness of the display panel will not be increased.

[0087] Specifically, when the reset signal line is set in the light-shielding layer, the second source and drain layer can form a connecting metal, and the connecting metal passes through the insulating layers and the planarization layer to be connected to the reset signal line, and extends to the display area through the connecting metal, and then is connected to the first reset transistor and the second reset transistor, thereby realizing signal input to the first reset transistor and the second reset transistor.

[0088] In one embodiment, the low potential signal line includes a first portion, a second portion and a fourth portion, the first portion is arranged on the first source-drain electrode layer, the second portion is arranged on the second source-drain electrode layer, and the fourth portion is arranged on the light shielding layer;

[0089] The display panel further includes a first insulating layer, a second insulating layer, a third insulating layer, a fourth insulating layer, a fifth insulating layer, an active layer and a third metal layer, wherein the first insulating layer is disposed between the semiconductor layer and the first metal layer, the second insulating layer is disposed between the first metal layer and the second metal layer, the third insulating layer is disposed between the second metal layer and the active layer, the fourth insulating layer is disposed between the active layer and the third metal layer, and the fifth insulating layer is disposed between the third metal layer and the first source-drain electrode layer.

[0090] Among them, the second part is connected to the first part through the via hole of the first planarization layer, the first part is connected to the fourth part through the via holes of the first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer and the fifth insulating layer, the projection of the fourth part on the substrate overlaps with the projection of the gate driving circuit on the substrate, and the width of the fourth part is greater than the width of the first part, and the width of the fourth part is greater than the second part.

[0091] By setting the low-potential signal line to the first part, the second part and the fourth part, the signal can be transmitted to the display area through the connected first part, the second part and the fourth part, so that the low-potential signal line can work normally, and the fourth part is set in the light shielding layer, and the fourth part overlaps with the projection of the gate driving circuit on the substrate, so the width of the border occupied by the fourth part can be reduced. Since the fourth part extends from the low-potential signal line setting area where the first part and the second part are located to the gate driving circuit area, the width of the fourth part is relatively large, which reduces the impedance of the low-potential signal line, so that the impedance of the low-potential signal line meets the driving requirements or even reduces the impedance of the low-potential signal line, thereby reducing the width of the first part and the second part, reducing the width of the border occupied by the low-potential signal line, and thus reducing the width of the border of the display panel. In addition, this setting method does not require a new film layer and will not increase the thickness of the display panel.

[0092] Specifically, when the fourth part of the low-potential signal line is arranged in the light-shielding layer, the distance between the light-shielding layer and the first source and drain layer is large, and the metal is easy to break in the via. It can be transferred through other film layers, such as through the first metal layer. The embodiment of the present application is not limited to this, and is based on the ability to achieve normal connection of the low-potential signal line.

[0093] The above embodiments are described in detail by taking the reset signal line and the low potential signal line as an example in which the reset signal line and the low potential signal line are set in the light-shielding layer. It can be understood that in order to further reduce the border, the reset signal line and the low potential signal line can be set in the light-shielding layer. In this case, it is only necessary to insulate the reset signal line and the low potential signal line. The setting method of the reset signal line and the low potential signal line can be set as described in the above embodiments, which will not be repeated here.

[0094] At the same time, when a third source and drain layer is added, the width of the gate drive circuit area occupied by the low-potential signal line can be increased by setting the reset signal line in the light-shielding layer and the third part of the low-potential signal line in the third source and drain layer, or by setting the reset signal line in the third source and drain layer and the low-potential signal line in the light-shielding layer, thereby further reducing the width of the border occupied by the low-potential signal line and further reducing the width of the border of the display panel.

[0095] like Figure 4 As shown, Figure 4 (a) is a schematic diagram of the arrangement area of ​​each component of the current display device. Figure 4 (b) is a schematic diagram of the arrangement area of ​​each part of the display panel of the present application. Figure 4 As can be seen from (a) in FIG. 2 , outside the display area 214, a gate drive circuit setting area 212, a low potential signal line setting area 211, and a reset signal line setting area 213 need to be set separately, resulting in a larger frame of the display device. However, the present application arranges the low potential signal line and the reset signal line in the gate drive circuit area, such as Figure 4 As shown in (b), it can be seen that the low-potential signal line setting area 221 and the gate drive circuit area 183 overlap, and the reset signal line setting area 222 is located in the gate drive circuit area 183, which reduces the border of the display panel.

[0096] like Figure 2As shown, the pixel driving circuit includes a first transistor T1, a second transistor T2, a third transistor T3, a first reset transistor T4, a first light emission control transistor T5, a second light emission control transistor T6, a second reset transistor T7, a storage capacitor Cst, a boost capacitor Cboost, a high potential signal line ELVDD, a data line Data, a first scan line P Scan(n), a second scan line P Scan(n-1), a third scan line N Scan(n), a fourth scan line N Scan(n-5) and a light emission control line EM.

[0097] Among them, P Scan(n) represents the scan line of this level, P Scan(n-1) represents the scan line of the previous level, and the above scan lines are used to control P-type transistors, N Scan(n) represents the scan line of this level, N Scan(n-5) represents the scan line of the previous five levels, and these two scan lines are used to control N-type transistors.

[0098] The working principle of the circuit is as follows: in the first stage, the first reset transistor T4 and the second reset transistor T7 are turned on, and the gate of the first transistor T1 is reset by the reset signal output by the first reset signal line VI-G, and the pixel light-emitting unit LED is reset by the reset signal output by the second reset signal line VI-ANO; in the second stage, the second transistor T2 and the third transistor T3 are turned on, and the data signal input by the data line Data is written into the gate of the first transistor T1; in the third stage, the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are turned on to drive the pixel light-emitting unit LED to emit light.

[0099] The embodiments of this application are Figure 2 The circuit diagram in is used as an example for detailed description, but the embodiments of the present application are not limited thereto. For example, a display panel using a 7T1C (7 transistors and one capacitor) circuit can also adopt the design of the present application.

[0100] In one embodiment, in order to improve the flexibility of the display panel and the ability to block water and oxygen, Figure 1 As shown, the substrate 11 includes a first flexible layer 111 , a barrier layer 112 and a second flexible layer 113 , and the display panel further includes a buffer layer 13 .

[0101] In one embodiment, if Figure 1 As shown, the display panel further includes a first insulating layer 142 , a second insulating layer 144 , a third insulating layer 146 , a fourth insulating layer 148 and a fifth insulating layer 150 .

[0102] In one embodiment, if Figure 1 As shown, the semiconductor layer 141 includes a semiconductor pattern 141 a .

[0103] In one embodiment, if Figure 1 As shown, the source 151d includes a first source portion 151a and a second source portion 151c.

[0104] In one embodiment, if Figure 1 As shown, the display panel further includes an active layer 147 and a third metal layer 149, wherein the material of the semiconductor layer is low temperature polysilicon, and the material of the active layer is oxide.

[0105] like Figure 1 As shown, the embodiment of the present application uses LTPO technology as an example to illustrate the structure of the display panel, but the embodiment of the present application is not limited to this. For example, the display panel can adopt LTPS (Low Temperature Poly-silicon) technology.

[0106] Specifically, for Figure 1 The perspective structure of the display panel shown in FIG. 1 is used to describe the specific design of the second source-drain electrode layer to the third source-drain electrode layer in detail. Figure 1 , Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 As shown, in the non-display area, the second source-drain layer 153 is formed with the second source portion 151c of the source 151d, the second portion 162 of the low potential signal line, and the connection metal, the connection metal is insulated from the second source portion 151c and the second portion 162 of the low potential signal line, and the connection metal is not shown in the figure. The second planarization layer 155 is formed with a via located on the connection metal and a via located on the second portion 162 of the low potential signal line, the third source-drain layer 154 is formed with a reset signal line 171 and the third portion 163 of the low potential signal line, the reset signal line passes through the via of the second planarization layer 155 and is connected to the connection metal, and then the connection metal extends to the display area and is connected to the electrodes of the first reset transistor and the second reset transistor, and the third portion 163 of the low potential signal line passes through the via of the second planarization layer 155 and is connected to the second portion 162 of the low potential signal line.

[0107] Specifically, the display panel also includes a third planarization layer, a pixel electrode layer, a light-emitting material layer, a pixel definition layer and a common electrode layer. The third planarization layer is arranged on the side of the third source and drain layer away from the second planarization layer. In the gate driving circuit area, a transfer metal is formed on the pixel electrode layer. The common electrode layer is connected to the transfer metal through the via holes of the pixel definition layer. The transfer metal is connected to the third part of the low-potential signal through the via holes of the third planarization layer.

[0108] Specifically, Figures 5 to 7 It is the perspective area of ​​the gate drive circuit area and the low potential signal line area of ​​the display panel. Figure 5 A perspective view of the display panel after the second source and drain layer is prepared. Figure 6 A perspective view of the display panel after the second planarization layer is prepared. Figure 7 This is a schematic diagram of the display panel after the third source and drain layer is prepared.

[0109] Specifically, Figure 5 The reference numeral 31 indicates a connection position reserved for a low potential signal line after the second source and drain layer is prepared, and the reference numeral 32 indicates a connection position reserved for a reset signal line after the second source and drain layer is prepared. Figure 6 The reference numeral 33 indicates the position of the connection hole of the low potential signal line after the second planarization layer is prepared. Figure 5 Set the connection hole of the reset signal line at the same position as the connection position reserved for the reset signal line in the figure. Figure 7 The reference numeral 34 indicates the connection between the third part of the low potential signal line and the second part of the low point signal line. Figure 5 The reset signal line is connected to the connection metal at the same position as the connection position reserved for the reset signal line in the circuit.

[0110] At the same time, an embodiment of the present application provides a display device, which includes the display panel and the driving chip described in any of the above embodiments.

[0111] According to the above embodiments, it can be seen that:

[0112] The embodiment of the present application provides a display panel and a display device; the display panel includes a display area and a non-display area, the display area is provided with a pixel light-emitting unit and a pixel driving circuit for controlling the pixel light-emitting unit, the non-display area is located outside the display area, the non-display area includes a gate driving circuit area, the non-display area is provided with a reset signal line and a low potential signal line, wherein the reset signal line is connected to the pixel driving circuit, the low potential signal line is connected to the pixel light-emitting unit, the gate driving circuit is arranged in a gate driving circuit, at least a portion of at least one of the reset signal line and the low potential signal line is arranged in the gate driving circuit area, and the reset signal line and the low potential signal line are insulated from the gate driving circuit. The present application enables at least a portion of at least one of the reset signal line and the low potential signal line to be arranged in the gate driving circuit area, thereby at least reducing the area occupied by the reset signal line and the low potential signal line arranged in the gate driving circuit area, reducing the width of the frame required for the portion, thereby reducing the frame of the display panel, and the scheme does not need to arrange the gate driving circuit on the light-emitting unit, reducing the process difficulty of display panel preparation, and improving the yield of the display panel.

[0113] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0114] The above is a detailed introduction to a display panel and a display device provided in the embodiments of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present application. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A display panel, characterized in that: include: A display area, wherein the display area is provided with a pixel light emitting unit and a pixel driving circuit for controlling the pixel light emitting unit; A non-display area, located at the periphery of the display area, the non-display area includes a gate drive circuit area, and the non-display area is provided with a reset signal line and a low potential signal line; The reset signal line is connected to the pixel driving circuit, the low potential signal line is connected to the pixel light emitting unit, the gate driving circuit area is provided with a gate driving circuit, at least a portion of at least one of the reset signal line and the low potential signal line is provided in the gate driving circuit area, and the reset signal line and the low potential signal line are insulated from the gate driving circuit; The display panel includes: a substrate, a semiconductor layer, a first metal layer, a second metal layer, a first source-drain layer and a second source-drain layer, the semiconductor layer is arranged on one side of the substrate; the first metal layer is arranged on the side of the semiconductor layer away from the substrate; the second metal layer is arranged on the side of the first metal layer away from the semiconductor layer; the first source-drain layer is arranged on the side of the second metal layer away from the first metal layer; the second source-drain layer is arranged on the side of the first source-drain layer away from the second metal layer; wherein the gate drive circuit includes a transistor and a capacitor, the transistor includes a gate, a source and a drain, the capacitor includes a capacitor plate, the gate is arranged on the first metal layer, the capacitor plate is arranged on the second metal layer, the source and the drain are arranged on the first source-drain layer, and at least part of the reset signal line and the low potential signal line are arranged in different metal layers from the metal layers located in the first metal layer, the second metal layer, the first source-drain layer and the second source-drain layer in the gate drive circuit.

2. The display panel according to claim 1, wherein: The gate driving circuit includes multiple metal layers, and at least a portion of the reset signal line and the low potential signal line are arranged in a different layer from any metal layer in the gate driving circuit.

3. The display panel according to claim 1, wherein: The display panel also includes a third source-drain layer, a first planarization layer and a second planarization layer, the third source-drain layer is arranged on a side of the second source-drain layer away from the first source-drain layer, the first planarization layer is arranged between the first source-drain layer and the second source-drain layer, and the second planarization layer is arranged between the second source-drain layer and the third source-drain layer; at least one of the reset signal line and the low-potential signal line includes a first overlapping portion arranged in the third source-drain layer, and a projection of the first overlapping portion on the substrate overlaps with a projection of the gate drive circuit on the substrate.

4. The display panel according to claim 3, wherein: The reset signal line is arranged on the third source-drain layer, and a projection of the reset signal line on the substrate overlaps with a projection of the gate driving circuit on the substrate.

5. The display panel according to claim 4, wherein: The projection of the reset signal line on the substrate overlaps with the projection of the source on the substrate, or the projection of the reset signal line on the substrate overlaps with the projection of the drain on the substrate, or the projection of the reset signal line on the substrate overlaps with the projection of the gate on the substrate, or the projection of the reset signal line on the substrate overlaps with the projection of the capacitor plate on the substrate.

6. The display panel according to claim 4, wherein: The pixel driving circuit includes a first reset transistor and a second reset transistor, the second source-drain layer includes a connecting metal, the reset signal line passes through a via hole in the second planarization layer and is connected to the connecting metal, the connecting metal extends from the gate driving circuit area to the display area and is connected to the first reset transistor and the second reset transistor.

7. The display panel according to claim 3, wherein: The low potential signal line is arranged in the third source-drain layer, and a projection of the low potential signal line on the substrate overlaps with a projection of the gate driving circuit on the substrate.

8. The display panel according to claim 7, wherein: The low-potential signal line includes a first part, a second part and a third part, the first part is arranged in the first source and drain layer, the second part is arranged in the second source and drain layer, the third part is arranged in the third source and drain layer, the second part is connected to the first part through a via hole in the first planarization layer, the third part is connected to the second part through a via hole in the second planarization layer, the projection of the third part on the substrate overlaps with the projection of the gate drive circuit on the substrate, and the width of the third part is greater than the width of the first part, and the width of the third part is greater than the width of the second part.

9. The display panel according to claim 8, wherein: The display panel also includes a fourth source-drain layer, which is arranged on a side of the third source-drain layer away from the second source-drain layer. The reset signal line is arranged in the fourth source-drain layer, and a projection of the reset signal line on the substrate overlaps with a projection of the third part on the substrate.

10. The display panel according to claim 1, wherein: The display panel also includes a shading layer, which is arranged between the substrate and the semiconductor layer. At least one of the reset signal line and the low-potential signal line includes a second overlapping portion arranged in the shading layer, and a projection of the second overlapping portion on the substrate overlaps with a projection of the gate drive circuit on the substrate.

11. The display panel according to claim 10, wherein: The reset signal line is arranged on the light shielding layer, and a projection of the reset signal line on the substrate overlaps with a projection of the gate driving circuit on the substrate.

12. The display panel according to claim 10, wherein: The low potential signal line includes a first portion, a second portion and a fourth portion, the first portion is arranged on the first source-drain electrode layer, the second portion is arranged on the second source-drain electrode layer, and the fourth portion is arranged on the light shielding layer; The display panel further includes a first insulating layer, a second insulating layer, a third insulating layer, a fourth insulating layer, a fifth insulating layer, an active layer and a third metal layer, wherein the first insulating layer is disposed between the semiconductor layer and the first metal layer, the second insulating layer is disposed between the first metal layer and the second metal layer, the third insulating layer is disposed between the second metal layer and the active layer, the fourth insulating layer is disposed between the active layer and the third metal layer, and the fifth insulating layer is disposed between the third metal layer and the first source-drain electrode layer. Among them, the second part is connected to the first part through the via hole of the first planarization layer, the first part is connected to the fourth part through the via holes of the first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer and the fifth insulating layer, the projection of the fourth part on the substrate overlaps with the projection of the gate driving circuit on the substrate, and the width of the fourth part is greater than the width of the first part, and the width of the fourth part is greater than the width of the second part.

13. A display device, characterized in that: It comprises a display panel and a driving chip as described in any one of claims 1 to 12.

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