A display panel and a display device

Abstract

The present invention provides a display panel and a display device. In the display panel, the shielding layer receives a fixed voltage signal, and in a direction perpendicular to the plane of the display panel, the orthographic projection of the shielding layer and the orthographic projection of the second part of the semiconductor layer have a first overlapping region. The shielding layer is used to reduce the coupling between the gate and the first pole of the driving transistor, and the area of the first overlapping region is different based on different sub-pixels, that is, different areas of the first overlapping region are designed for different sub-pixels, ensuring that the shielding layer in each sub-pixel can effectively reduce the coupling between the gate and the first pole of the driving transistor, thereby improving the stability of the driving transistor in each sub-pixel, making the brightness of each sub-pixel tend to be infinitely consistent when displaying the first frame, and finally improving the display effect of the display panel.

Description

Technical Field

[0001] The present invention relates to the field of display technologies, and more particularly, to a display panel and a display device. Background Art

[0002] With the continuous development of science and technology, modern society has entered the information age and is developing towards the intelligent direction. Display is a key link for realizing information exchange and intelligence. Among the numerous current display technologies, OLED (Organic Light-Emitting Diode) display technology is considered to be a disruptive next-generation display technology. OLED display technology is a device that uses a multi-layer organic thin-film structure to generate electroluminescence. Its manufacturing process is simple and only requires a relatively low driving voltage. These main characteristics make OLED very prominent in meeting the applications of display panels. Compared with LCD (Liquid Crystal Display) display panels, OLED display panels have the advantages of being thinner, brighter, lower power consumption, faster response, higher clarity, better flexibility, and higher luminous efficiency, and can meet the new demands of consumers for display technologies.

[0003] However, in existing OLED display panels, there is a problem that the brightness of the first frame of RGB three-color sub-pixels is inconsistent, resulting in smear and color deviation of the white screen, and thus affecting the display effect of the display panel. Summary of the Invention

[0004] In view of this, to solve the above problems, the present invention provides a display panel and a display device, and the technical solutions are as follows:

[0005] A display panel, the display panel includes: a plurality of sub-pixels;

[0006] The sub-pixels include:

[0007] A pixel circuit and a light-emitting element, the pixel circuit includes a driving transistor and a data writing transistor, the driving transistor is used to provide a driving current for the light-emitting element, and the data writing transistor is used to provide a data signal for the driving transistor;

[0008] The pixel circuit further includes a semiconductor layer and a shielding layer, the semiconductor layer includes a first part and a second part, the first part serves as the active layer of the data writing transistor, and the first pole of the driving transistor is electrically connected to the first pole of the data writing transistor through the second part;

[0009] The shielding layer receives a fixed voltage signal, and in a direction perpendicular to the plane of the display panel, a positive projection of the shielding layer and a positive projection of the second part have a first overlapping area;

[0010] The plurality of sub-pixels include: a plurality of first sub-pixels and a plurality of second sub-pixels, and an area of the first overlapping region in the first sub-pixels is larger than an area of the first overlapping region in the second sub-pixels.

[0011] A display device, the display device including the display panel described above.

[0012] Compared with the prior art, the beneficial effects achieved by the present invention are as follows:

[0013] In a display panel provided by the present invention, a shielding layer receives a fixed voltage signal, and in a direction perpendicular to a plane where the display panel is located, a positive projection of the shielding layer and a positive projection of a second part of a semiconductor layer have a first overlapping region. The coupling between a gate of a driving transistor and a first pole is reduced by the shielding layer, and the area of the first overlapping region is different based on different sub-pixels, that is, the area of the first overlapping region is designed differently for different sub-pixels, ensuring that the shielding layer in each sub-pixel can effectively reduce the coupling between the gate of the driving transistor and the first pole, thereby improving the stability of the driving transistor in each sub-pixel, making the brightness of each sub-pixel when displaying the first frame infinitely tend to be consistent, and finally improving the display effect of the display panel. Description of the Drawings

[0014] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on the provided drawings without creative efforts.

[0015] Figure 1 A schematic diagram of an RGB grayscale efficiency curve provided by an embodiment of the present invention;

[0016] Figure 2 A schematic structural diagram of a display panel provided by an embodiment of the present invention;

[0017] Figure 3 A schematic diagram of a sub-pixel provided by an embodiment of the present invention;

[0018] Figure 4 A schematic circuit layout diagram of a sub-pixel provided by an embodiment of the present invention;

[0019] Figure 5 A partial circuit layout diagram of a sub-pixel provided by an embodiment of the present invention;

[0020] Figure 6 A schematic comparison diagram of partial circuit layouts of two sub-pixels provided by an embodiment of the present invention;

[0021] Figure 7 Schematic diagram of partial circuit layouts of three sub-pixels provided by an embodiment of the present invention;

[0022] Figure 8 Schematic diagram of another sub-pixel provided by an embodiment of the present invention;

[0023] Figure 9 Schematic diagram of the circuit layout of the second electrode plate as a shielding layer and the second part provided by an embodiment of the present invention;

[0024] Figure 10 Schematic diagram of another sub-pixel provided by an embodiment of the present invention;

[0025] Figure 11 Schematic diagram of partial circuit layout of another sub-pixel provided by an embodiment of the present invention;

[0026] Figure 12 Schematic diagram of comparative partial circuit layouts of two sub-pixels provided by an embodiment of the present invention;

[0027] Figure 13 Schematic diagram of comparative partial circuit layouts of three sub-pixels provided by an embodiment of the present invention;

[0028] Figure 14 Schematic diagram of another sub-pixel provided by an embodiment of the present invention;

[0029] Figure 15 Schematic diagram of another sub-pixel provided by an embodiment of the present invention;

[0030] Figure 16 Schematic diagram of another sub-pixel provided by an embodiment of the present invention;

[0031] Figure 17 Schematic diagram of another sub-pixel provided by an embodiment of the present invention;

[0032] Figure 18 Schematic diagram of the structure of a display device provided by the present invention. Detailed implementation manners

[0033] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0034] Based on the content recorded in the background art, refer to Figure 1 , Figure 1A schematic diagram of the RGB grayscale efficiency curve provided by an embodiment of the present invention, where curve 1 represents the grayscale efficiency curve of the R sub-pixel, curve 2 represents the grayscale efficiency curve of the G sub-pixel, and curve 3 represents the grayscale efficiency curve of the B sub-pixel. As can be seen from Figure 1 the schematic diagram of the RGB grayscale efficiency curve shown, at low brightness, its efficiency decreases. At the same current density, as the brightness decreases, the B sub-pixel decreases first, and the change trends of the R sub-pixel and the G sub-pixel are relatively consistent. Therefore, there will be a problem of inconsistent brightness of the RGB three-color sub-pixels during the first-frame display, which will further cause ghosting and color deviation in the white screen, and further affect the display effect of the display panel.

[0035] Based on this, the present invention adjusts the RGB three-color sub-pixels to solve the technical problems existing in the prior art and improve the final display effect of the display panel.

[0036] To make the above objects, features, and advantages of the present invention more obvious and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0037] Refer to Figure 2 , Figure 2 A schematic diagram of the structure of a display panel provided by an embodiment of the present invention. The display panel includes: a plurality of sub-pixels 11. To achieve full-color display of the display panel, optionally, the plurality of sub-pixels 11 may include sub-pixels for emitting green light, sub-pixels for emitting blue light, and sub-pixels for emitting red light.

[0038] Refer to Figure 3 , Figure 3 A schematic diagram of a sub-pixel provided by an embodiment of the present invention. The sub-pixel 11 includes: a pixel circuit 12 and a light-emitting element Q. The pixel circuit 12 includes a driving transistor T1 and a data writing transistor 72. The driving transistor T1 is used to provide a driving current for the light-emitting element Q, and the data writing transistor T2 is used to provide a data signal Vdata for the driving transistor T1.

[0039] Among them, the control signal S1 received by the gate of the data writing transistor T2 is a pulse signal. During the data writing stage, the control signal S1 outputs an effective pulse to control the data writing transistor T2 to be in a conducting state, and then the data signal Vdata is written into the gate of the driving transistor at least through the data writing transistor T2.

[0040] Among them, the driving transistor T1 is coupled to the light-emitting element Q. The driving transistor T1 generates a corresponding driving current based on the data signal Vdata and transmits it to the light-emitting element Q, and the light-emitting element Q emits light based on the driving current.

[0041] It should be noted that in the embodiment of the present invention, one end of the gate of the driving transistor T1 is defined as the first node N1, and the connection point of the driving transistor T1 and the data transistor T2 is defined as the second node N2.

[0042] Reference Figure 4 , Figure 4 is a schematic diagram of the circuit layout of a sub-pixel provided by an embodiment of the present invention. Refer to Figure 5 , Figure 5 is a schematic diagram of a partial circuit layout of a sub-pixel provided by an embodiment of the present invention. The pixel circuit further includes a semiconductor layer 14 and a shielding layer 13. The semiconductor layer 14 includes a first part 141 and a second part 142. The first part 141 serves as the active layer of the data writing transistor T2. The first pole of the driving transistor T1 is electrically connected to the first pole of the data writing transistor T2 through the second part 142. At this time, the second part 142 can be understood as a partial position in the circuit layout where the second node N2 is located.

[0043] The shielding layer 13 receives a fixed voltage signal, and in the direction perpendicular to the plane of the display panel, the positive projection of the shielding layer 13 and the positive projection of the second part 142 have a first overlapping area.

[0044] Reference Figure 6 , Figure 6 is a schematic diagram for comparing the partial circuit layouts of two sub-pixels provided by an embodiment of the present invention. The multiple sub-pixels 11 include: multiple first sub-pixels 11a and multiple second sub-pixels 11b. The area of the first overlapping area in the first sub-pixel 11a is larger than the area of the first overlapping area in the second sub-pixel 11b.

[0045] For example, as Figure 6 shown, the area of the first overlapping area in the first sub-pixel 11a is the entire area of the second part 142, and the area of the first overlapping area in the second sub-pixel 11b is half of the area of the second part 142 in the width direction.

[0046] Specifically, the driving current Ids generated by the driving transistor T1 based on the data signal Vdata is:

[0047] Ids = K * (V N2 - V N1 - |Vth|) 2 = K * (PVDD - V N1 - |Vth|) 2

[0048] where K is the current coefficient; V N2 is the voltage of the second node N2; V N1is the voltage of the first node N1, and Vth is the threshold voltage of the driving transistor T1.

[0049] Specifically, in the process of the invention of the present invention, it is found that when the alignment relationship between the shielding layer 13 and the semiconductor layer 14 is not designed, a coupling capacitance will be formed between the first node N1 and the second node N2; when the first frame is displayed, the display panel starts to light up from the black state. Specifically:

[0050] When displaying in the black state, there is: V N1 = V data + Vth, V N2 = PVDD; at this time, the first node N1 is at a high potential, about 4.5V; among them, V data is the data voltage, and PVDD is the first power supply voltage, about 4.6V.

[0051] Before the first frame of white screen is displayed, first, the gate of the driving transistor T1 is reset, that is, there is: V N1 = V REF ; at this time, the first node N1 changes from a high potential to a low potential, about -4.5V. Correspondingly, due to the coupling between the first node N1 and the second node N2, the potential of the second node N2 is also pulled down, about -4.4V; among them, V REF is the gate reset voltage of the driving transistor T1.

[0052] Secondly, a data signal Vdata is written to the gate of the driving transistor T1, that is, there is: V N2 = V data ; at this time, the second node N2 changes from a low potential to a high potential, about 3V. Correspondingly, due to the coupling between the first node N1 and the second node N2, the potential of the first node N1 is also pulled up, about 2.9V.

[0053] During the display of the first frame of white screen, there is: V N1 = V data + Vth, V N2 = PVDD; at this time, the first node N1 is at a low potential, about 1.5V; the potential of the second node N2 is about 4.6V.

[0054] Before the second frame of white screen is displayed, similarly, the gate of the driving transistor T1 is reset again, that is, there is: V N1 = V REF ; at this time, the first node N1 changes from a high potential to a low potential, about -4.5V. Correspondingly, due to the coupling between the first node N1 and the second node N2, the potential of the second node N2 is also pulled down, about -1.4V.

[0055] Next, a data signal Vdata is written to the gate of the driving transistor T1, i.e., there is: V N2 = V data ; At this time, the second node N2 changes from a low potential to a high potential, about 3V. Correspondingly, due to the coupling between the first node N1 and the second node N2, the potential of the first node N1 is also pulled up at this time, about -0.1V.

[0056] It can be seen from this that the voltage of the first node N1 when the first frame of white screen is displayed is greater than the voltage of the first node N1 when the second frame of white screen is displayed, resulting in a driving current when the first frame of white screen is displayed being less than the driving current when the second frame of white screen is displayed, and further resulting in a lower brightness of the first frame.

[0057] Based on this, the display panel provided by the embodiment of the present invention improves the sub-pixels. The shielding layer 13 receives a fixed voltage signal, and in the direction perpendicular to the plane where the display panel is located, the positive projection of the shielding layer 13 and the positive projection of the second part 142 of the semiconductor layer 14 have a first overlapping area. The coupling between the gate of the driving transistor T1 and the first pole is reduced through the shielding layer 13, and the area of the first overlapping area is different based on different sub-pixels. For example, as Figure 1 shown, the area of the first overlapping area in the B sub-pixel can be greater than the area of the first overlapping area in the R sub-pixel, and can also be greater than the area of the first overlapping area in the G sub-pixel. That is to say, different areas of the first overlapping area are designed for sub-pixels with different gray-scale efficiencies, ensuring that the shielding layer 13 in each sub-pixel can effectively reduce the coupling between the gate of the driving transistor T1 and the first pole, that is, reduce the coupling between the first node N1 and the second node N2, and further improve the stability of the driving transistor T1 in each sub-pixel, so that the brightness of each sub-pixel when the first frame is displayed approaches infinity, and finally improve the display effect of the display panel.

[0058] Optionally, in another embodiment of the present invention, referring to Figure 7 , Figure 7 is a schematic diagram of a partial circuit layout comparison of three sub-pixels provided by the embodiment of the present invention. The plurality of sub-pixels further includes: a plurality of third sub-pixels 11c.

[0059] The area of the first overlapping area in the third sub-pixel 11c is equal to the area of the first overlapping area in the second sub-pixel 11b.

[0060] Specifically, as Figure 1It can be seen from the schematic diagram of the RGB grayscale efficiency curve shown that its efficiency decreases at low brightness. At the same current density, as the brightness decreases, the B sub-pixel decreases first, and the change trends of the R sub-pixel and the G sub-pixel are relatively consistent. Therefore, in the embodiments of the present invention, the B sub-pixel is taken as the first sub-pixel 11a, the R sub-pixel is taken as the second sub-pixel 11b, and the G sub-pixel is taken as the third sub-pixel 11c for illustration. At this time, in order to ensure that the brightness of the first frame of the RGB three-color sub-pixels approaches infinity and is consistent, in the embodiments of the present invention, the area of the first overlapping region in the first sub-pixel 11a is greater than the area of the first overlapping region in the second sub-pixel 11b and greater than the area of the first overlapping region in the third sub-pixel 11c.

[0061] In order to simplify the design of the sub-pixels in the display panel, in the embodiments of the present invention, the area of the first overlapping region in the third sub-pixel 11c is equal to the area of the first overlapping region in the second sub-pixel 11b.

[0062] For example, the area of the first overlapping region in the first sub-pixel 11a is the entire area of the second part 142, the area of the first overlapping region in the second sub-pixel 11b is half of the area in the width direction of the second part 142, and the area of the first overlapping region in the third sub-pixel 11c is also half of the area in the width direction of the second part 142.

[0063] Optionally, in another embodiment of the present invention, as Figure 3 and Figure 4 shown, the pixel circuit 12 further includes: a power supply signal line.

[0064] The power supply signal line is used to provide the fixed voltage signal.

[0065] Specifically, the fixed voltage signal is the first power supply voltage PVDD. That is to say, in the embodiments of the present invention, based on the existing power supply signal line in the sub-pixel being connected to the shielding layer 13, the required fixed voltage signal is directly provided for the shielding layer 13, without adding additional signal lines, thereby simplifying the wiring method of the display panel.

[0066] Optionally, in another embodiment of the present invention, referring to Figure 8 , Figure 8 which is a schematic diagram of another sub-pixel provided by the embodiments of the present invention, the pixel circuit 12 further includes: a storage capacitor C1.

[0067] The storage capacitor C1 includes a first electrode plate and a second electrode plate.

[0068] The first electrode plate is electrically connected to the gate of the driving transistor T1, and the second electrode plate is electrically connected to the power supply signal line.

[0069] Specifically, the first electrode plate is reused as the gate of the driving transistor T1; refer to Figure 9 , Figure 9 FIG. Figure 9 is a schematic layout diagram of a second electrode plate as a shielding layer and a second part of a circuit according to an embodiment of the present invention. The second electrode plate is reused as the shielding layer 13. When the second electrode plate serves as the shielding layer 13, it includes a third part 131 and a fourth part 132.

[0070] In a direction perpendicular to the plane of the display panel, the orthographic projection of the third part 131 completely overlaps with the orthographic projection of the first electrode plate, and the orthographic projection of the fourth part 132 has an overlapping area with the orthographic projection of the second part 142.

[0071] In this embodiment, the first electrode plate of the storage capacitor C1 is reused as the gate of the driving transistor T1, and the second electrode plate is reused as the shielding layer 13. By improving the second electrode plate, the orthographic projection of the third part 131 completely overlaps with the orthographic projection of the first electrode plate, and the orthographic projection of the fourth part 132 has an overlapping area with the orthographic projection of the second part 142. That is to say, the area where the second electrode plate functions as the shielding layer 13 is the area where the fourth part 132 is located, and the area where the third part 131 faces the first electrode plate is used as the effective area of the storage capacitor C1.

[0072] That is to say, in the embodiment of the present application, based on the existing storage capacitor C1 in the sub-pixel, the second electrode plate is improved to be used as the shielding layer 13, so that the orthographic projection of the fourth part 132 has an overlapping area with the orthographic projection of the second part 142, which can effectively reduce the coupling between the gate of the driving transistor T1 and the first electrode, that is, reduce the coupling between the first node N1 and the second node N2, and further improve the stability of the driving transistor T1 in each sub-pixel, so that the brightness of each sub-pixel in the first frame of display approaches infinity and is consistent, and finally improve the display effect of the display panel.

[0073] Optionally, in another embodiment of the present invention, refer to Figure 10 , Figure 10 FIG. Figure 10 is a schematic diagram of another sub-pixel according to an embodiment of the present invention. The pixel circuit 12 further includes: a first transistor T3; a first pole of the first transistor T3 receives the fixed voltage signal, that is, the first power supply voltage PVDD.

[0074] Refer to Figure 11 , Figure 11 FIG. Figure 11 is a partial circuit layout diagram of another sub-pixel according to an embodiment of the present invention. The semiconductor layer 14 further includes a third part 143 and a fourth part 144. The third part 143 serves as the active layer of the first transistor T3.

[0075] The first pole of the driving transistor T1 is electrically connected to the second pole of the first transistor T3 through the fourth portion 144.

[0076] As Figure 11 shown, both the second portion 142 and the fourth portion 144 extend along the first direction X, and one end of the second portion 142 is connected to one end of the fourth portion 144.

[0077] The first portion 141 is located at one end of the second portion 142 away from the fourth portion 144, and the third portion 143 is located at one end of the fourth portion 144 away from the second portion 142.

[0078] Since the first pole of the driving transistor T1 is connected to the data writing transistor T2 through the second portion 142 and connected to the first transistor T3 through the fourth portion 144, the region where the second portion 142 and the fourth portion 144 are located together can be understood as the position of the second node N2 in the circuit layout.

[0079] At this time, in the direction perpendicular to the plane of the display panel, the positive projection of the shielding layer 13 and the positive projection of the fourth portion 144 have a second overlapping region.

[0080] Refer to Figure 12 , Figure 12 which is a schematic diagram of the comparison of partial circuit layouts of two sub-pixels provided by an embodiment of the present invention. The multiple sub-pixels include: multiple first sub-pixels 11a and multiple second sub-pixels 11b. The area of the second overlapping region in the first sub-pixel 11a is larger than the area of the second overlapping region in the second sub-pixel 11b.

[0081] For example, the area of the second overlapping region in the first sub-pixel 11a is the entire area of the fourth portion 144, and the area of the second overlapping region in the second sub-pixel 11b is half of the area of the fourth portion 144 in the width direction.

[0082] Optionally, in another embodiment of the present invention, refer to Figure 13 , Figure 13 which is a schematic diagram of the comparison of partial circuit layouts of three sub-pixels provided by an embodiment of the present invention. The multiple sub-pixels further include: multiple third sub-pixels 11c.

[0083] The area of the second overlapping region in the third sub-pixel 11c is equal to the area of the second overlapping region in the second sub-pixel 11b.

[0084] Specifically, as Figure 1As can be seen from the schematic diagram of the RGB grayscale efficiency curve shown, its efficiency decreases at low brightness. At the same current density, as the brightness decreases, the B sub-pixel decreases first, and the changing trends of the R sub-pixel and the G sub-pixel are relatively consistent. Therefore, in the embodiments of the present invention, the B sub-pixel is taken as the first sub-pixel 11a, the R sub-pixel is taken as the second sub-pixel 11b, and the G sub-pixel is taken as the third sub-pixel 11c as an example for illustration. At this time, in order to ensure that the brightness of the first frame of the RGB three-color sub-pixels approaches infinity and is consistent, in the embodiments of the present invention, the area of the second overlapping region in the first sub-pixel 11a is greater than the area of the second overlapping region in the second sub-pixel 11b and greater than the area of the second overlapping region in the third sub-pixel 11c.

[0085] In order to simplify the design of the sub-pixels in the display panel, in the embodiments of the present invention, the area of the second overlapping region in the third sub-pixel 11c is equal to the area of the second overlapping region in the second sub-pixel 11b.

[0086] For example, the area of the second overlapping region in the first sub-pixel 11a is the entire area of the fourth part 144, the area of the second overlapping region in the second sub-pixel 11b is half of the area in the width direction of the fourth part 144, and the area of the second overlapping region in the third sub-pixel 11c is also half of the area in the width direction of the fourth part 144.

[0087] It should be noted that the width direction of the second part 142 and the width direction of the fourth part 144 are perpendicular to the first direction X.

[0088] That is to say, the display panel provided by the embodiments of the present invention improves the sub-pixels. The shielding layer 13 receives a fixed voltage signal, and in the direction perpendicular to the plane where the display panel is located, the positive projection of the shielding layer 13 and the positive projection of the second part 142 of the semiconductor layer 14 have a first overlapping region, and the positive projection of the shielding layer 13 and the positive projection of the fourth part 144 of the semiconductor layer 14 have a second overlapping region, so as to cover the second node N2 as comprehensively as possible, thereby reducing the coupling between the gate of the driving transistor T1 and the first pole to the greatest extent, and making the total area of the first overlapping region and the second overlapping region different based on different sub-pixels. For example, Figure 1The total area of the first overlapping region and the second overlapping region in the B sub-pixel shown can be greater than the total area of the first overlapping region and the second overlapping region in the R sub-pixel, and can also be greater than the total area of the first overlapping region and the second overlapping region in the G sub-pixel. That is to say, different total areas of the first overlapping region and the second overlapping region are designed for sub-pixels with different gray-scale efficiencies, ensuring that the shielding layer 13 in each sub-pixel can effectively reduce the coupling between the gate of the driving transistor T1 and the first pole, that is, reduce the coupling between the first node N1 and the second node N2, thereby improving the stability of the driving transistor T1 in each sub-pixel, making the brightness of each sub-pixel tend to be consistent infinitely when displaying the first frame, and finally improving the display effect of the display panel.

[0089] Optionally, in another embodiment of the present invention, referring to Figure 14 , Figure 14 is a schematic diagram of another sub-pixel provided by an embodiment of the present invention. The pixel circuit 12 further includes: a second transistor T4.

[0090] The first pole of the second transistor T4 is electrically connected to the second pole of the driving transistor T1, and the second pole of the second transistor T4 is electrically connected to the anode of the light-emitting element Q.

[0091] Specifically, in this embodiment, the first transistor T3 and the second transistor T4 are two light-emitting control transistors used by the pixel circuit 12 to control the light-emitting of the light-emitting element Q. The gates of the first transistor T3 and the second transistor T4 receive the control signal S2 at the same time. Under the control of the control signal S2, the second transistor T4 is in a conducting state or a non-conducting state; the control signal S2 received by the gate of the second transistor T4 is a pulse signal. During the light-emitting stage, the control signal S2 outputs an effective pulse to control the second transistor T4 to be in a conducting state, then the driving current provided by the driving transistor T1 flows into the light-emitting element Q to make it emit light; during the non-light-emitting stage, the control signal S2 outputs an invalid pulse to control the second transistor T4 to be in a non-conducting state, then the light-emitting element Q does not emit light.

[0092] Optionally, in another embodiment of the present invention, referring to Figure 15 , Figure 15 is a schematic diagram of another sub-pixel provided by an embodiment of the present invention. The pixel circuit 12 further includes: a compensation transistor T5.

[0093] The first pole of the compensation transistor T5 is electrically connected to the second pole of the driving transistor T1, and the second pole of the compensation transistor T5 is electrically connected to the gate of the driving transistor T1.

[0094] Specifically, the compensation transistor T5 is used to compensate for the threshold voltage of the driving transistor T1. The first pole of the compensation transistor T5 is electrically connected to the second pole of the driving transistor T1, the second pole of the compensation transistor T5 is electrically connected to the gate of the driving transistor T1, and the gate of the compensation transistor T5 is used to receive the control signal S1. Among them, the control signal S1 received by the compensation transistor T5 is a pulse signal. The effective pulse of the control signal S1 controls the compensation transistor T5 to be in the on state to compensate for the threshold voltage of the driving transistor T1; the invalid pulse of the control signal S1 controls the compensation transistor T5 to be in the off state. Therefore, under the control of the control signal S1, the compensation transistor T5 selectively compensates for the threshold voltage of the driving transistor T1.

[0095] Optionally, in another embodiment of the present invention, refer to Figure 16 , Figure 16 which is a schematic diagram of another sub-pixel provided by the embodiment of the present invention. The pixel circuit 12 further includes: a first reset transistor T6.

[0096] The first pole of the first reset transistor T6 receives the first reset signal V REF1 , and the second pole of the first reset transistor T6 is electrically connected to the gate of the driving transistor T1.

[0097] Specifically, the first pole of the first reset transistor T6 receives the first reset signal V REF1 , the second pole of the first reset transistor T6 is electrically connected to the gate of the driving transistor T1, and the gate of the first reset transistor T6 is used to receive the control signal S3. Among them, the control signal S3 received by the first reset transistor T6 is a pulse signal. The effective pulse of the control signal S3 controls the first reset transistor T6 to be in the on state to reset the gate of the driving transistor T1; the invalid pulse of the control signal S3 controls the first reset transistor T6 to be in the off state.

[0098] Optionally, in another embodiment of the present invention, refer to Figure 17 , Figure 17 which is a schematic diagram of another sub-pixel provided by the embodiment of the present invention. The pixel circuit 12 further includes: a second reset transistor T7.

[0099] The first pole of the second reset transistor T7 receives the second reset signal V REF2 , and the second pole of the second reset transistor T7 is electrically connected to the anode of the light-emitting element Q.

[0100] Specifically, the first pole of the second reset transistor T7 is used to receive the second reset signal V REF2, the second pole of the second reset transistor T7 is electrically connected to the anode of the light-emitting element Q, and the gate of the second reset transistor T7 is used to receive a control signal S2. Among them, the control signal S2 received by the second reset transistor T7 is a pulse signal. The effective pulse of the control signal S2 controls the second reset transistor T7 to be in an on state to reset the anode of the light-emitting element Q; the ineffective pulse of the control signal S2 controls the second reset transistor T7 to be in an off state.

[0101] The cathode of the light-emitting element Q is connected to the second power supply voltage terminal for receiving the second power supply voltage PVEE.

[0102] Optionally, based on all the above embodiments of the present invention, in another embodiment of the present invention, a display device is further provided. Refer to Figure 18 , Figure 18 is a schematic structural diagram of a display device provided by the present invention.

[0103] The display device 100 includes the display panel described in the above embodiments of the present application.

[0104] The display device 100 includes, but is not limited to, display devices such as mobile phones and tablets. The display device has at least the same technical effects as the display panel.

[0105] The above has introduced in detail a display panel and a display device provided by the present invention. Specific examples are used in this article to elaborate on the principle and implementation manner of the present invention. The description of the above embodiments is only used to help understand the method and its core idea of the present invention; at the same time, for those of ordinary skill in the art, according to the idea of the present invention, there will be changes in the specific implementation manner and application scope. In summary, the content of this specification should not be construed as a limitation to the present invention.

[0106] It should be noted that the embodiments in this specification are all described in a progressive manner. Each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the device disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple, and the relevant parts can be referred to the description of the method part.

[0107] It should also be noted that, in this text, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that the elements inherent in a process, method, article or device comprising a series of elements, or those elements that also include the elements inherent in these processes, methods, articles or devices. Without further limitation, an element defined by the statement "comprising an..." does not exclude the existence of additional identical elements in the process, method, article or device comprising the said element.

[0108] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present invention. Various modifications to these embodiments will be obvious to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to these embodiments shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A display panel, characterized in that, The display panel includes: a plurality of sub-pixels; The sub-pixels include: a pixel circuit and a light-emitting element, the pixel circuit includes a driving transistor and a data writing transistor, the driving transistor is configured to provide a driving current for the light-emitting element, and the data writing transistor is configured to provide a data signal for the driving transistor; The pixel circuit further includes a semiconductor layer and a shielding layer, the semiconductor layer includes a first portion and a second portion, the first portion serves as the active layer of the data writing transistor, and a first pole of the driving transistor is electrically connected to a first pole of the data writing transistor through the second portion; The shielding layer receives a fixed voltage signal, and in a direction perpendicular to the plane where the display panel is located, a positive projection of the shielding layer and a positive projection of the second portion have a first overlapping region; The plurality of sub-pixels includes: a plurality of first sub-pixels and a plurality of second sub-pixels, and an area of the first overlapping region in the first sub-pixels is larger than an area of the first overlapping region in the second sub-pixels; The plurality of sub-pixels further includes: a plurality of third sub-pixels; An area of the first overlapping region in the third sub-pixels is equal to an area of the first overlapping region in the second sub-pixels.

2. The display panel according to claim 1, wherein The pixel circuit further includes: a power supply signal line; The power supply signal line is configured to provide the fixed voltage signal.

3. The display panel according to claim 2, wherein, The pixel circuit further includes: a storage capacitor; The storage capacitor includes a first electrode plate and a second electrode plate; The first electrode plate is electrically connected to a gate of the driving transistor, and the second electrode plate is electrically connected to the power supply signal line.

4. The display panel according to claim 3, wherein The second electrode plate is multiplexed as the shielding layer, and the second electrode plate includes a third portion and a fourth portion; In a direction perpendicular to the plane where the display panel is located, a positive projection of the third portion and a positive projection of the first electrode plate completely overlap, and a positive projection of the fourth portion and a positive projection of the second portion have an overlapping region.

5. The display panel according to claim 3, wherein The first electrode plate is multiplexed as the gate of the driving transistor.

6. The display panel according to claim 1, wherein The pixel circuit further includes: a first transistor; A first pole of the first transistor receives the fixed voltage signal, and the semiconductor layer further includes a third portion and a fourth portion, and the third portion serves as the active layer of the first transistor; A first pole of the driving transistor is electrically connected to a second pole of the first transistor through the fourth portion.

7. The display panel according to claim 6, wherein Both the second portion and the fourth portion extend along a first direction, and one end of the second portion is connected to one end of the fourth portion; The first portion is located at an end of the second portion away from the fourth portion, and the third portion is located at an end of the fourth portion away from the second portion.

8. The display panel according to claim 7, characterized in that, In a direction perpendicular to the plane where the display panel is located, a positive projection of the shielding layer and a positive projection of the fourth portion have a second overlapping region; An area of the second overlapping region in the first sub-pixels is larger than an area of the second overlapping region in the second sub-pixels.

9. The display panel according to claim 8, wherein An area of the second overlapping region in the third sub-pixels is equal to an area of the second overlapping region in the second sub-pixels.

10. The display panel according to claim 1, wherein The pixel circuit further includes: a second transistor; A first pole of the second transistor is electrically connected to a second pole of the driving transistor, and a second pole of the second transistor is electrically connected to an anode of the light-emitting element.

11. The display panel according to claim 1, wherein, The pixel circuit further includes: a compensation transistor; A first pole of the compensation transistor is electrically connected to a second pole of the driving transistor, and a second pole of the compensation transistor is electrically connected to a gate of the driving transistor.

12. The display panel according to claim 1, wherein, The pixel circuit further includes: a first reset transistor; A first pole of the first reset transistor receives a first reset signal, and a second pole of the first reset transistor is electrically connected to a gate of the driving transistor.

13. The display panel according to claim 1, wherein The pixel circuit further includes: a second reset transistor; A first pole of the second reset transistor receives a second reset signal, and a second pole of the second reset transistor is electrically connected to an anode of the light-emitting element.

14. A display device, characterized in that, The display device includes the display panel according to any one of claims 1-13.

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