Power module schottky diode chip structure and preparation method

Abstract

The application provides a power module Schottky diode chip structure and a preparation method thereof, and the chip structure comprises an As-doped silicon semiconductor substrate and a P-doped silicon semiconductor epitaxial layer located above the silicon semiconductor substrate; the edge of the chip structure is an oxide layer passivation layer structure, and the main junction of the chip is a composite junction barrier structure formed by a ring-shaped P+, a hexagonal P+ and a platinum-silicon Schottky junction; a front multi-layer metal electrode is arranged on the front surface of the composite junction barrier structure, and a multi-layer metal electrode is arranged on the back surface of the silicon semiconductor substrate; the method is simple, low in cost, practical and effective, the NiPt alloy is used as a Schottky barrier metal to form a composite metal silicide-silicon contact barrier (NiPtSi-Si), the barrier height is low, the reverse current is small, and the barrier height can be adjusted by adjusting the alloy component.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of power module Schottky diode, in particular to a power module Schottky diode chip structure and a preparation method thereof. BACKGROUND

[0002] The statements in this section merely provide background technology related to the present application and do not necessarily constitute the prior art.

[0003] The power Schottky diode is made by using the metal-semiconductor junction principle of metal and semiconductor contact, and the junction terminal structure and the junction barrier structure are optimized at the same time to realize the high-voltage and large-current Schottky chip structure. The electrical parameters of the power Schottky device mainly include forward voltage drop, reverse voltage, reverse leakage, etc. It is a kind of low-power and super-speed semiconductor device, and is often used as a high-frequency, low-voltage and large-current rectifier diode.

[0004] The inventor finds that the chip in the existing power Schottky device cannot effectively balance the forward characteristic and the reverse characteristic; the Schottky metal barrier generates a large amount of heat in the high-voltage and large-current state, which reduces the performance of the device; the existing chip adopts a single Schottky barrier structure, which is sensitive to temperature, has a large reverse leakage current, and the leakage current will rapidly increase with temperature, which leads to failure of the device; or a single JBS structure is adopted, which can effectively control the leakage, but increases the forward voltage drop of the device, which leads to large power consumption of the device and reduces the service life of the device. SUMMARY

[0005] In order to solve the problems of the prior art, the present application provides a power module Schottky diode chip structure and a preparation method thereof, which improves the working performance under high voltage and large current, and improves the ESD resistance and the anti-reverse energy impact resistance.

[0006] In order to achieve the above-mentioned purpose, the present application adopts the following technical scheme:

[0007] The present application provides a power module Schottky diode chip structure in the first aspect.

[0008] A power module Schottky diode chip structure comprises:

[0009] An N-type silicon semiconductor substrate and an N-type silicon semiconductor epitaxial layer located above the N-type silicon semiconductor substrate;

[0010] The edge of the chip structure is an oxide passivation layer structure, and the main junction of the chip is a composite junction barrier structure formed by a ring-shaped P+, a hexagonal P+ and a platinum-silicon Schottky junction.

[0011] A front multi-layer metal electrode is arranged on the front surface of the composite junction barrier structure, and a multi-layer metal electrode is arranged on the back surface of the silicon semiconductor substrate.

[0012] As an optional implementation, the N-type silicon semiconductor substrate is an N-type silicon semiconductor substrate doped with high-concentration As, and the N-type silicon semiconductor epitaxial layer is a silicon semiconductor epitaxial layer doped with low-concentration P.

[0013] As an optional implementation, the front surface of the N-type silicon semiconductor epitaxial layer is provided with an oxide layer, the oxide layer has a junction barrier structure at a middle position, and annular P+ and hexagonal P+ pattern regions are distributed at equal intervals, with a platinum barrier structure between the two regions, and a NiPtSi barrier layer directly contacts the N-type silicon semiconductor epitaxial layer.

[0014] As an optional implementation, the NiPtSi barrier layer is arranged in a window of the oxide layer on the N-type silicon semiconductor epitaxial layer.

[0015] As an optional implementation, the annular P+ is a guard ring arranged in the N-type silicon semiconductor epitaxial layer, the guard ring is located at an edge of the window and surrounds the window, and the guard ring is formed by boron diffusion.

[0016] As an optional implementation, a longitudinal section of the window is T-shaped, and an inner sidewall of the window is step-shaped.

[0017] As an optional implementation, the NiPtSi barrier layer covers the step-shaped terrace and extends to a highest surface of the oxide layer.

[0018] As an optional implementation, the front surface multi-layer metal electrode sequentially comprises a titanium metal layer, a nickel metal layer and an aluminum metal layer from bottom to top, and the back surface multi-layer metal electrode sequentially comprises a titanium metal layer, a nickel metal layer and a silver metal layer from top to bottom.

[0019] The second aspect of the present application provides a preparation method of a power module Schottky diode chip structure.

[0020] A preparation method of a power module Schottky diode chip structure comprises the following processes:

[0021] Oxidizing the P-doped silicon semiconductor epitaxial layer to form an oxide layer;

[0022] Performing first photoetching to form a window on the oxide layer;

[0023] Performing boron diffusion to form an annular guard ring and a hexagonal P+ region in the etched area;

[0024] Performing high-temperature main diffusion at a preset temperature to advance the junction depth of the guard ring;

[0025] Performing second photoetching to form a barrier region window;

[0026] Magnetron sputtering a barrier metal layer on the P-doped silicon semiconductor epitaxial layer in the barrier region window, and the barrier metal layer is made of nickel-platinum alloy.

[0027] Vacuum annealing to form NiPtSi-Si potential barrier;

[0028] Cleaning the surplus potential barrier metal not forming potential barrier;

[0029] Preparation of front Ti, Ni, Al multi-layer metal electrode on the potential barrier metal layer by electron beam evaporation;

[0030] Third photoetching is performed to etch the front metal electrode;

[0031] Back thinning of the semiconductor substrate is performed;

[0032] Preparation of back multi-layer metal electrode on the back of the semiconductor substrate by electron beam evaporation;

[0033] Alloying treatment deepens the binding force between the metal layers and removes the natural oxide layer on the surface of the electrode metal.

[0034] As an optional implementation, the nickel content in the nickel-platinum alloy is 85wt%, the platinum content is 15wt%, and the purity of Ni and Pt is greater than 99.999%.

[0035] As an optional implementation, the conditions of magnetron sputtering are as follows: argon flow is 20SCCM, sputtering power is 1kw, time is 60s, and silicon wafer heating temperature is 150-200℃.

[0036] As an optional implementation, the conditions of annealing are as follows: temperature is 500-550℃, and time is 20-40 minutes.

[0037] As an optional implementation, the etching liquid of the aluminum metal layer in the third photoetching is concentrated phosphoric acid, and the etching liquid composition of the titanium metal layer and the nickel metal layer is as follows: the volume ratio of HNO3:HH:H2O is 8:1:100.

[0038] Compared with the prior art, the beneficial effects of the present application are as follows:

[0039] 1. The method is simple, low in cost, practical and effective, adopts NiPt alloy as Schottky potential barrier metal, forms composite metal silicide-silicon contact potential barrier (NiPtSi-Si), is low in potential barrier height, small in reverse current, and can adjust the potential barrier height by adjusting the alloy components.

[0040] 2. The alloy metals Ti and Ni are selected as diffusion barriers, effectively block the mutual diffusion between the metals and silicides, and greatly improve the fatigue resistance of the device.

[0041] 3、The application has greatly improved the reliability of the produced Schottky device by adjusting the process parameters, overcome the contradiction between the positive pressure drop and the reverse leakage of the single barrier metal process, and overcome the defects of low reliability such as high temperature, anti-static, and reverse energy.

[0042] 4、The composite barrier Schottky chip structure reduces the reverse leakage current and the forward voltage of the device, and improves the high temperature resistance, anti-static performance and reverse energy impact performance of the device.

[0043] The advantages of the additional aspects of the application will be partially given in the following description, partially become obvious from the following description, or be known by the practice of the application. BRIEF DESCRIPTION OF DRAWINGS

[0044] The drawings constituting a part of the specification of the application are used to provide further understanding of the application, the illustrative embodiments of the application and the description thereof are used to explain the application, and do not constitute improper limitation to the application.

[0045] Figure 1 A cross-sectional schematic view of a Schottky diode chip structure provided for embodiment 1 of the application.

[0046] Figure 2 A cross-sectional schematic view of a Schottky diode chip structure provided for embodiment 1 of the application.

[0047] Figure 3 A JBS junction barrier structure schematic diagram provided for embodiment 1 of the application.

[0048] Wherein, 1-protective ring; 2-oxide layer; 3-barrier layer; 4-titanium metal layer; 5-nickel metal layer; 6-aluminum metal layer; 7-titanium metal layer; 8-nickel metal layer; 9-silver metal layer; 10-semiconductor substrate; 11-JBS junction barrier structure. DETAILED DESCRIPTION

[0049] The application will be further described below in combination with the drawings and embodiments.

[0050] It should be pointed out that the following detailed description is exemplary, and is intended to provide further description of the application. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as generally understood by those skilled in the art to which the application belongs.

[0051] It is to be understood that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments in accordance with the present application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising," when used in this specification, specify the presence of stated features, steps, operations, elements, components, and / or groups thereof, but do not preclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups thereof.

[0052] In the present application, the terms such as "upper", "lower", "left", "right", "front", "back", "vertical", "horizontal", "side", "bottom" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, which are only the relationship words determined for the purpose of describing the structural relationship of the components or elements of the present application, and are not intended to specify any component or element in the present application, and cannot be understood as a limitation of the present application.

[0053] The embodiments in the present application and the features in the embodiments can be combined with each other without conflict.

[0054] Embodiment 1

[0055] As shown in Figure 1 , Figure 2 and Figure 3 , the embodiment 1 of the present application provides a power module Schottky diode chip structure, which comprises a high-concentration As-doped silicon semiconductor substrate, a lower-concentration P-doped silicon semiconductor epitaxial layer, an oxide passivation layer structure at the edge of the chip, a new composite junction barrier structure formed by a ring-shaped P+, a hexagonal P+ and a platinum-silicon Schottky junction together at the main junction of the chip, and a back multilayer metal electrode provided on the high-concentration As-doped silicon semiconductor substrate.

[0056] An oxide layer is provided on the front surface of the lower-concentration P-doped silicon semiconductor epitaxial layer, the middle part of the oxide layer has a junction barrier structure, the ring-shaped P+ and the hexagonal P+ patterned areas are distributed at equal intervals, and a platinum barrier structure is used between the two areas, and the barrier layer is in direct contact with the lower-concentration P-doped silicon semiconductor epitaxial layer.

[0057] Specifically, as shown in Figure 1 , the Schottky diode chip structure comprises:

[0058] A semiconductor substrate 10, the substrate is an N-type silicon wafer, the N-type silicon wafer comprises a high-concentration As-doped silicon semiconductor substrate and a lower-concentration P-doped silicon semiconductor epitaxial layer;

[0059] An oxide layer 2 of silicon dioxide is provided on the front surface of the lower-concentration P-doped silicon semiconductor epitaxial layer, the middle part of the oxide layer 2 has a window, the longitudinal section of the window is T-shaped, so that the inner sidewall of the oxide layer window is stepped;

[0060] A barrier layer 3 is arranged in the window, the barrier layer 3 covers the mesa of the oxide layer and extends to the highest surface of the oxide layer 2, the material of the barrier layer 3 is NiPtSi, the barrier layer 3 is in direct contact with the lower-concentration P-doped silicon semiconductor epitaxial layer, forming a NiPtSi-Si barrier;

[0061] A front multi-layer metal electrode is arranged on the barrier layer 3, and a back multi-layer metal electrode is arranged on the back surface of the high-concentration As-doped silicon semiconductor substrate;

[0062] A guard ring 1 is further arranged in the lower-concentration P-doped silicon semiconductor epitaxial layer, the guard ring surrounds the window and is located at the edge of the window, and the guard ring 1 is formed by boron diffusion.

[0063] The thickness of the barrier layer 3 of the NiPtSi is preferably

[0064] The front multi-layer metal electrode is sequentially composed of a titanium metal layer 4, a nickel metal layer 5 and a silver metal layer 6 from bottom to top, the thickness of the titanium metal layer is The thickness of the nickel metal layer is The thickness of the aluminum metal layer is 3 μm. The back multi-layer metal electrode is sequentially composed of a titanium metal layer 7, a nickel metal layer 8 and a silver metal layer 9 from top to bottom, the thickness of the titanium metal layer is The thickness of the nickel metal layer is The thickness of the silver metal layer is 2 μm.

[0065] The composite metal silicide-silicon contact barrier (NiPtSi-Si) is selected, surface defects and contamination are avoided, the influence of surface state is reduced, the forward characteristics, reverse voltage resistance, reverse energy impact, high-temperature resistance, anti-static and anti-burning capacity of the device are improved, the chip reverse leakage current is small, the high-temperature performance requirement and the forward performance requirement are met, and the barrier height can be adjusted by adjusting the Ni and Pt components.

[0066] In order to improve the reverse voltage resistance and reverse characteristics, a guard ring is arranged at the edge of the barrier, and the curvature radius of the edge depletion layer of the metal layer is increased through the guard ring.

[0067] The refractory metal titanium is selected as the diffusion barrier, the mutual diffusion between metals is effectively blocked, and the fatigue resistance of the device is greatly improved.

[0068] The power module Schottky diode chip structure can be used to manufacture various power Schottky devices, and the power Schottky devices including the Schottky diode chip of the application are within the protection scope of the application.

[0069] Example 2:

[0070] The embodiment 2 of the present application provides a preparation method of a power module Schottky diode chip structure, comprising initial oxidation, first photoetching, boron diffusion, main diffusion, second photoetching, sputtering of barrier metal, vacuum annealing, cleaning before metallization, electron beam front multi-layer metal, third photoetching, back thinning, back metallization, alloying, and intermediate testing and dicing.

[0071] Specifically, the method comprises the following processes:

[0072] (1) oxidizing an N-type silicon semiconductor substrate to form an oxide layer;

[0073] (2) performing first photoetching to form a window on the oxide layer, specifically, the window is T-shaped in vertical section, the surface of the photoetched oxide layer is a plane, and the oxide layer has a mesa on one side of the annular groove window, the height of the mesa being lower than that of the surface of the oxide layer, so that the annular groove window side of the oxide layer has a stepped edge;

[0074] (3) forming a protection ring on the edge of the window by boron diffusion of solid sheet BN;

[0075] (4) advancing the junction depth by high-temperature main diffusion; the protection ring is advanced in junction depth by high-temperature main diffusion, specifically, the main diffusion is performed at a high temperature of 1110 ℃ for about 2 hours to advance the junction depth of the protection ring;

[0076] (5) performing second photoetching to form a barrier region window;

[0077] (6) magnetron sputtering a barrier metal layer on the lower-concentration P-doped silicon semiconductor epitaxial layer in the window, the barrier metal layer extending onto part of the oxide layer, and the barrier metal layer being made of nickel-platinum alloy;

[0078] (7) vacuum annealing to generate a metal silicide NiPtSi between the barrier metal and the silicon wafer, thereby forming a NiPtSi-Si barrier;

[0079] (8) cleaning the excess barrier metal that has not formed a barrier before metallization;

[0080] (9) preparing a front multi-layer metal electrode on the barrier metal layer by electron beam evaporation;

[0081] (10) performing third photoetching to etch the front metal electrode;

[0082] (11) thinning the semiconductor substrate from the back;

[0083] (12) preparing a back multi-layer metal electrode on the back of the semiconductor substrate by electron beam evaporation;

[0084] (13) alloying to deepen the bonding force between the metal layers and remove the natural oxide layer on the surface of the electrode metal.

[0085] In the embodiment, the nickel content in the nickel-platinum alloy is 85wt%, and the platinum content is 15wt%; the purity of Ni and Pt is more than 99.95%.

[0086] In the embodiment, the magnetron sputtering conditions are as follows: argon flow rate is 20 SCCM, sputtering power is 1kw, time is 60s; and the silicon wafer heating temperature is 150-200℃.

[0087] In the embodiment, the annealing conditions are as follows: temperature is 500-550℃, time is 20-40 minutes, and preferably 540℃ for 30 minutes.

[0088] In the embodiment, the etching liquid composition for the aluminum metal layer in the third photoetching is concentrated phosphoric acid, and the etching liquid composition for the titanium metal layer and the nickel metal layer is HNO3:HH:H2O with a volume ratio of 8:1:100.

[0089] The present application forms NiPtSi silicide-NiPtSi by using NiPt alloy as the barrier metal and through process treatment, and forms NiPtSi-Si barrier, which replaces the traditional metal-semiconductor contact mode.

[0090] The present application selects NiPt alloy as the barrier metal, which has stronger controllability than single metal, and can realize the adjustment of barrier height through the change of alloy component ratio, thereby providing more flexibility for balancing the contradiction between the forward and reverse characteristics; secondly, the stability and reliability of the contact must be considered when selecting the barrier metal, and from the stability of the barrier, for N-type silicon, the NiPt alloy barrier height is low, and it is stable with Si in metallurgy, so the NiPt has good high-temperature stability; selecting NiPt alloy as the barrier metal overcomes the contradiction between the forward and reverse characteristics, and better plays the advantages of the new JBS junction barrier structure.

[0091] The NiPtSi silicide not only can provide a suitable Schottky barrier, but also can prevent the reaction between the electrode metal and silicon, but since the metal electrode also reacts with the silicide to form metal compounds, which affects the electrical characteristics of the device, so a diffusion barrier is needed; the most important parameters for selecting the diffusion barrier material are recrystallization temperature, resistivity and atomic diffusion coefficient, the present application selects Ti as the diffusion barrier, which has good adhesion and can effectively block the mutual diffusion between the metals and the silicide, and selects Ni as the barrier layer between the Al and Ti electrode layers, which further greatly improves the fatigue resistance and electromigration resistance of the device.

[0092] The above merely provides the preferred embodiments of the present application, and is not used to limit the present application. For those skilled in the art, the present application can have various modifications and changes. Any modifications, equivalent replacements, improvements, etc. made within the principles and technical scope of the present application shall fall into the scope of the present application.

Claims

1. A power module Schottky diode chip structure, comprising: an N-type silicon semiconductor substrate and an N-type silicon semiconductor epitaxial layer on the N-type silicon semiconductor substrate; an edge of the chip structure is an oxide passivation layer structure, and a main junction of the chip is a composite junction barrier structure formed by a ring-shaped P+, a hexagonal P+, and a platinum-silicon Schottky junction; a front surface multi-layer metal electrode is provided on the front surface of the composite junction barrier structure, and a back surface multi-layer metal electrode is provided on the back surface of the silicon semiconductor substrate; wherein the front surface of the N-type silicon semiconductor epitaxial layer is provided with an oxide layer, the oxide layer has a junction barrier structure at a middle position, the ring-shaped P+ and the hexagonal P+ patterned regions are distributed at equal intervals, and a platinum barrier structure is provided between the two regions, and a NiPtSi barrier layer is in direct contact with the N-type silicon semiconductor epitaxial layer; wherein the N-type silicon semiconductor substrate is an N-type silicon semiconductor substrate doped with high-concentration As, and the N-type silicon semiconductor epitaxial layer is a silicon semiconductor epitaxial layer doped with low-concentration P. 2.The power module Schottky diode chip structure of claim 1, wherein: the NiPtSi barrier layer is arranged in a window of the oxide layer on the N-type silicon semiconductor epitaxial layer. 3.The power module Schottky diode chip structure of claim 2, wherein: the ring-shaped P+ is a guard ring arranged in the N-type silicon semiconductor epitaxial layer, the guard ring is located at an edge of the window and surrounds the window, and the guard ring is formed by boron diffusion. 4.The power module Schottky diode chip structure of claim 2, wherein: a longitudinal section of the window is T-shaped, and an inner sidewall of the window is stepped. 5.The power module Schottky diode chip structure of claim 4, wherein: the NiPtSi barrier layer covers the stepped terrace and extends to a highest surface of the oxide layer. 6.The power module Schottky diode chip structure of claim 1, wherein: the front surface multi-layer metal electrode comprises, from bottom to top, a titanium metal layer, a nickel metal layer, and an aluminum metal layer, and the back surface multi-layer metal electrode comprises, from top to bottom, a titanium metal layer, a nickel metal layer, and a silver metal layer. 7.A method for manufacturing a power module Schottky diode chip structure, comprising the following processes: forming an oxide layer by oxidizing a P-doped silicon semiconductor epitaxial layer; performing first photolithography to form a window on the oxide layer; performing boron diffusion to form a ring-shaped guard ring and a hexagonal P+ region in the etched area; performing high-temperature main diffusion at a preset temperature to advance the junction depth of the guard ring; performing second photolithography to form a barrier region window; magnetron sputtering a barrier metal layer on the P-doped silicon semiconductor epitaxial layer in the barrier region window, the barrier metal layer being made of nickel-platinum alloy; vacuum annealing to form a NiPtSi-Si barrier; cleaning excess barrier metal that does not form a barrier; preparing a front surface multi-layer metal electrode on the barrier metal layer by electron beam evaporation; performing third photolithography to etch the front surface metal electrode; thinning the back surface of the semiconductor substrate; preparing a back surface multi-layer metal electrode on the back surface of the semiconductor substrate by electron beam evaporation; alloying to deepen the bonding force between the metal layers and remove the natural oxide layer on the surface of the electrode metal; ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ The positive surface of the N-type silicon semiconductor epitaxial layer is provided with an oxidation layer, the middle position of the oxidation layer has a junction barrier structure, the annular P+ and hexagonal P+ pattern areas are distributed at equal intervals, the two areas are separated by a platinum barrier structure, and the NiPtSi barrier layer is in direct contact with the N-type silicon semiconductor epitaxial layer. The N-type silicon semiconductor substrate is an N-type silicon semiconductor substrate doped with high-concentration As, and the N-type silicon semiconductor epitaxial layer is a silicon semiconductor epitaxial layer doped with low-concentration P.

8. The preparation method of the power module Schottky diode chip structure according to claim 7, wherein: The nickel content in the nickel-platinum alloy is 85wt%, the platinum content is 15wt%, and the purity of Ni and Pt is greater than 99.95%; Or, The magnetron sputtering conditions are as follows: argon flow rate is 20 SCCM, sputtering power is 1kw, time is 60s, and the silicon wafer heating temperature is 150-200℃; Or, The annealing conditions are as follows: temperature is 500-550℃, and time is 20-40 minutes; Or, In the third photoetching, the etching solution for the aluminum metal layer is concentrated phosphoric acid, and the etching solution for the titanium metal layer and the nickel metal layer is composed of HNO3, HF and H2O in a volume ratio of 8:1:100.

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