Driving substrate and display panel thereof

Abstract

The present application provides a driving substrate and a display panel thereof, wherein the driving substrate includes a substrate, a plurality of scanning lines, a plurality of data lines, and a scanning driving circuit. The substrate has a display area; a plurality of scanning lines and a plurality of data lines are arranged on the substrate; a plurality of scanning lines and a plurality of data lines are crisscrossed vertically and horizontally to define a plurality of pixel areas; and the pixel areas are located in the display area; wherein the row directions of the plurality of pixel areas are parallel to the scanning lines; the scanning driving circuit is arranged in the display area of ​​the substrate, and the scanning driving circuit includes a plurality of cascaded scanning driving units; the same scanning driving unit is arranged in at least two rows of pixel areas, and can output at least one row of gate scanning signals. The present application reduces the space occupied by the scanning driving unit in a single row of pixel areas by dispersing the single scanning driving unit arranged in the display area in the plurality of rows of pixel areas, thereby improving the pixel aperture ratio.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a driving substrate and a display panel thereof. Background Art

[0002] As people's demand for display tastes increases day by day, the demand for borderless displays is getting higher and higher. The display of the prior art includes non-display areas on the top, bottom, left and right sides, where the left and right non-display areas are mainly occupied by the array substrate row driver (Gate Driver on Array, GOA) circuit, so that the left and right borders cannot be borderless.

[0003] In this regard, the conventional method is to place the GOA circuit of the current row in the pixel display area of ​​the corresponding row. However, as the GOA circuit is placed in the display area, the aperture ratio of the pixel is greatly reduced, thereby causing the problem of insufficient brightness of the liquid crystal display. Summary of the invention

[0004] The main technical problem solved by the present application is to provide a driving substrate and a display panel thereof, so as to solve the problem in the prior art that the GOA circuit is placed in the pixel display area, resulting in a reduction in the pixel aperture ratio.

[0005] In order to solve the above technical problems, the first technical solution provided by the present application is: providing a driving substrate for a liquid crystal display panel, the driving substrate comprising a substrate, a plurality of scanning lines, a plurality of data lines and a scanning driving circuit. The substrate has a display area; a plurality of scanning lines and a plurality of data lines are arranged on the substrate; a plurality of scanning lines and a plurality of data lines are vertically and horizontally crossed to define a plurality of pixel areas; and the pixel areas are located in the display area; wherein the row direction of the plurality of pixel areas is parallel to the scanning lines; the scanning driving circuit is arranged in the display area of ​​the substrate, and the scanning driving circuit comprises a plurality of cascaded scanning driving units; the same scanning driving unit is arranged in at least two rows of pixel areas, and can output at least one row of gate scanning signals.

[0006] Among them, the scan driving unit includes a charging unit, a reset unit and an output unit; the output unit is located in one or two rows of pixel areas, and the charging unit and the reset unit are located in another row of pixel areas; or the output unit, the charging unit and the reset unit are each located in a row of pixel areas.

[0007] The scanning driving unit includes a plurality of thin film transistors, and the plurality of thin film transistors are dispersedly arranged in two or three rows of pixel regions.

[0008] The output unit includes a switch thin film transistor, a single switch thin film transistor includes a plurality of sub-thin film transistors, and the plurality of sub-thin film transistors are connected in parallel and dispersedly arranged in at least two rows of pixel regions.

[0009] The output unit includes a switch thin film transistor, and the switch thin film transistor is connected to a plurality of scan lines, so that the scan driving unit outputs a plurality of rows of gate scan signals simultaneously.

[0010] Wherein, the scanning driving unit includes a first thin film transistor, a second thin film transistor, a third thin film transistor, a fourth thin film transistor and a capacitor C;

[0011] The source of the first thin film transistor is connected to the drain of the first thin film transistor and is connected to the output end of the gate scanning signal of the previous stage, and the drain of the first thin film transistor is connected to the source of the fourth thin film transistor and the gate of the second thin film transistor respectively;

[0012] The source of the second thin film transistor is connected to the clock signal, and the drain of the second thin film transistor is connected to at least one scanning line to output at least one row of gate scanning signals;

[0013] The gates of the third thin film transistor and the fourth thin film transistor are connected to the same scan line, and the source of the third thin film transistor and the drain of the second thin film transistor are connected to the same scan line; the drain of the third thin film transistor and the drain of the fourth thin film transistor are respectively connected to a low level signal;

[0014] The capacitor C is connected to the gate electrode of the second thin film transistor and the drain electrode of the second thin film transistor respectively; wherein the gate electrode of the first thin film transistor, the drain electrode of the second thin film transistor and the gate electrode of the third thin film transistor are connected to different scan lines respectively.

[0015] Among them, the drain of the second thin film transistor is respectively connected to the scan line of the nth row and the scan line of the n+1th row to simultaneously output the gate scan signal of the nth row and the gate scan signal of the n+1th row; the gates of the third thin film transistor and the fourth thin film transistor are respectively connected to the scan line of the n+2th row; n is an integer greater than or equal to 1.

[0016] Among them, it also includes a clock signal line for providing a clock signal and a low-level signal line for providing a low-level signal. The clock signal line is spaced apart from the data line along the extension direction of the data line, and the clock signal line is connected to the source of the second thin film transistor; the low-level signal line is spaced apart from the data line along the extension direction of the data line, and the low-level signal line is respectively connected to the drain of the third thin film transistor and the drain of the fourth thin film transistor.

[0017] Wherein, the same scanning driving unit is arranged in at least two columns of pixel areas.

[0018] In order to solve the above technical problems, the second technical solution provided by the present application is: to provide a display panel, the display panel includes a first substrate, a second substrate and a liquid crystal layer. The first substrate is the above-mentioned driving substrate; the first substrate and the second substrate are arranged opposite to each other; the liquid crystal layer is arranged between the first substrate and the second substrate.

[0019] Beneficial effects of the present application: Different from the prior art, the present application provides a driving substrate and a display panel thereof, wherein the driving substrate includes a substrate, a plurality of scanning lines, a plurality of data lines and a scanning driving circuit. The substrate has a display area; a plurality of scanning lines and a plurality of data lines are arranged on the substrate; a plurality of scanning lines and a plurality of data lines are vertically and horizontally crossed to define a plurality of pixel areas; and the pixel areas are located in the display area; wherein the row directions of the plurality of pixel areas are parallel to the scanning lines; the scanning driving circuit is arranged in the display area of ​​the substrate, and the scanning driving circuit includes a plurality of cascaded scanning driving units; the same scanning driving unit is arranged in at least two rows of pixel areas, and can output at least one row of gate scanning signals. The present application reduces the space occupied by the scanning driving unit in a single row of pixel areas by dispersing the single scanning driving unit arranged in the display area in the plurality of rows of pixel areas, thereby improving the pixel aperture ratio. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0021] Figure 1 is a schematic structural diagram of an embodiment of a display panel provided by the present application;

[0022] Figure 2 is a structural schematic diagram of an embodiment of a driving substrate provided by the present application;

[0023] Figure 3 is a schematic diagram of a cascade structure of an embodiment of a scan driving circuit provided by the present application;

[0024] Figure 4 is a structural schematic diagram of a first embodiment of a scan drive unit in a drive substrate provided by the present application;

[0025] Figure 5 is a structural schematic diagram of a second embodiment of a scan drive unit in a drive substrate provided by the present application;

[0026] Figure 6 is a structural schematic diagram of a third embodiment of a scan drive unit in a drive substrate provided by the present application;

[0027] Figure 7 is a structural schematic diagram of a fourth embodiment of a scan drive unit in a drive substrate provided by the present application;

[0028] Figure 8 is a structural schematic diagram of a fifth embodiment of a scan drive unit in a drive substrate provided by the present application;

[0029] Fig. 9 is a structural schematic diagram of a sixth embodiment of a scan drive unit in a drive substrate provided by the present application;

[0030] Fig.10 It is a structural schematic diagram of another embodiment of the driving substrate provided in the present application.

[0031] Description of Figure Numbers:

[0032] first substrate-1, first substrate-11, display area-111, non-display area-112, scan line-12, data line-13, pixel electrode-14, scan drive circuit-15, scan drive unit-150, charging unit-151, reset unit-152, output unit-153, first thin film transistor-T1, second thin film transistor-T2, first sub-thin film transistor-T 2-1 The second sub-thin film transistor-T 2-2 , a third thin film transistor-T3, a fourth thin film transistor-T4, a fifth thin film transistor-T5, a sixth thin film transistor-T6, a seventh thin film transistor-T7, an eighth thin film transistor-T8, a capacitor-C, a clock signal line-CLK / CLKB, a low level signal line-Vss, a pixel area-17, a second substrate-2, a second substrate-21, a filter layer-22, a black matrix layer-23, a liquid crystal layer-3, a liquid crystal-31, a driving substrate-4, and a display panel-100. DETAILED DESCRIPTION

[0033] The scheme of the embodiment of the present application is described in detail below in conjunction with the drawings of the specification.

[0034] In the following description, for the purpose of explanation rather than limitation, specific details such as specific system structures, interfaces, and technologies are provided to facilitate a thorough understanding of the present application.

[0035] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0036] The terms "first", "second", "third" in this application are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Thus, the features defined as "first", "second", "third" can expressly or implicitly include at least one of the features. In the description of this application, the meaning of "multiple" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined. In the embodiments of the present application, all directional indications (such as up, down, left, right, front, back ...) are only used to explain the relative position relationship, movement, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication also changes accordingly. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device comprising a series of steps or regions is not limited to the steps or regions listed, but optionally also includes steps or regions that are not listed, or optionally also includes other steps or regions inherent to these processes, methods, products or devices.

[0037] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0038] See also Figure 1 , Figure 1 It is a schematic structural diagram of an embodiment of a display panel provided in the present application.

[0039] The display panel 100 is a liquid crystal panel. The display panel 100 includes a first substrate 1, a second substrate 2 and a liquid crystal layer 3. The first substrate 1 and the second substrate 2 are arranged opposite to each other, and the first substrate 1 and the second substrate 2 sandwich the liquid crystal layer 3 located in the space between the first substrate 1 and the second substrate 2.

[0040] One of the first substrate 1 and the second substrate 2 is an array substrate, and the other is a color filter substrate. In this embodiment, the first substrate 1 is an array substrate, and the second substrate 2 is a color filter substrate.

[0041] The second substrate 2, that is, the color filter substrate includes a second substrate 21, a filter layer 22 and a black matrix layer 23 located on the side of the second substrate 21 close to the array substrate. The filter layer 22 includes filter films of three colors: red, blue and green. The black matrix layer 23 can separate the three primary colors of red, green and blue in the filter layer 22 and prevent light leakage by means of materials with high light-shielding properties, thereby helping to improve the contrast of each color block. The filter layer 22 can achieve full-color display of the display panel 100. The material of the second substrate 21 generally adopts alkali-free borosilicate glass with excellent mechanical properties, heat resistance and chemical corrosion resistance. The color filter substrate may also include other functional layers, which are the same or similar to the prior art and are not limited here.

[0042] The liquid crystal layer 3 includes liquid crystal 31. The liquid crystal 31 plays a role similar to a light valve in the display, and can control the brightness of the transmitted light, thereby achieving the effect of information display.

[0043] See also Figure 1 and Figure 2 , Figure 2 It is a structural schematic diagram of an embodiment of a driving substrate provided in the present application.

[0044] The first substrate 1 in this embodiment can be a driving substrate 4, which includes a first substrate 11, a scan line 12, a data line 13, a pixel electrode 14, a scan drive circuit 15, a clock signal line CLK and a low-level signal line Vss. The first substrate 11 has a display area 111 and a non-display area 112. The material of the first substrate 11 generally adopts alkali-free borosilicate glass with excellent mechanical properties, heat resistance and chemical corrosion resistance. A plurality of scan lines 12 and a plurality of data lines 13 are arranged on one side of the first substrate 11 close to the second substrate 2. A plurality of scan lines 12 are arranged parallel to each other, and a plurality of data lines 13 are arranged parallel to each other. A plurality of scan lines 12 and a plurality of data lines 13 are cross-linked vertically and horizontally to define a plurality of pixel areas 17, and a pixel electrode 14 is arranged in the pixel area 17. The scan drive circuit 15 is arranged in the display area 111 of the first substrate 11, connected to the scan line 12, and used to output a gate scan signal. The low-level signal line Vss is used to provide a low-level signal, and the low-level signal line Vss is spaced apart from the data line 13 along the extension direction of the data line 13. The clock signal line CLK is used to provide a clock signal, and the voltage phases of the low-level signal line Vss and the clock signal line CLK are opposite. The clock signal line CLK is spaced apart from the data line 13 along the extension direction of the data line 13.

[0045] In an embodiment of the present application, the row direction of the pixel area 17 is parallel to the scan line 12. That is, each row of pixel areas 17 includes a plurality of pixel areas 17, and the plurality of pixel areas 17 in each row are sequentially arranged in a direction parallel to the scan line 12. Each pixel area 17 includes at least one pixel electrode 14. That is, there may be one pixel electrode 14 or multiple pixel electrodes 14 in a pixel area 17. For example, in a dual-gate drive circuit, there are two pixel electrodes 14 in a pixel area 17, and the two pixel electrodes 14 may be arranged at intervals along the extension direction of the data line 13 or the scan line 12, which is not limited here. In this embodiment, the example in which a pixel area 17 includes a pixel electrode 14 is mainly used for explanation.

[0046] See also Figure 3 , Figure 3 It is a schematic diagram of the cascade structure of an embodiment of a scan driving circuit provided in the present application.

[0047] The scanning driving circuit 15 is arranged on one side of the first substrate 1 close to the second substrate 2, and is connected to the scanning line 12, the clock signal line CLK and the low-level signal line Vss respectively. The positive projection of the black matrix layer 23 on the first substrate 1 covers the scanning driving circuit 15, so as not to affect the light passing through the opening area. The scanning driving circuit 15 includes a plurality of cascaded scanning driving units 150, the input signal (Input) of each level of scanning driving unit 150 is the output signal (Output) of the previous level of scanning driving unit 150, and the reset signal (Reset) of each level of scanning driving unit 150 is the output signal of the next level of scanning driving unit 150. For the first level of scanning driving unit 150, since there is no previous level of scanning driving unit 150, a frame start signal (not shown) is used as an input signal. For the last level of scanning driving unit 150, since there is no next level of scanning driving unit 150 to provide a reset signal, an additional redundant scanning driving unit (not shown) can be designed to provide a reset signal to the last row.

[0048] See also Figure 4 , Figure 4 It is a structural schematic diagram of the first embodiment of the scan drive unit in the drive substrate provided by the present application.

[0049] Each scan driving unit 150 includes a charging unit 151, a reset unit 152, an output unit 153 and at least one capacitor C. The charging unit 151 is used to receive the output signal of the scan driving unit 150 of the previous stage and charge the capacitor C. The reset unit 152 receives the output signal of the scan driving unit 150 of the next stage and discharges the capacitor C, thereby resetting the scan driving unit 150 of the current stage. The output unit 153 is used to output a gate scan signal to the scan line 12. The charging unit 151, the reset unit 152, and the output unit 153 all include thin film transistors. That is, each scan driving unit 150 includes a plurality of thin film transistors and at least one capacitor C.

[0050] The same scan driving unit 150 is disposed in at least two rows of pixel regions 17 and can simultaneously output at least one row of gate scan signals. In other words, multiple thin film transistors are dispersedly disposed in at least two rows of pixel regions 17 , and the output unit 153 is connected to at least one scan line 12 .

[0051] The following description will be made by taking a single scan driving unit 150 including four thin film transistors and one capacitor C as an example.

[0052] The scan driving unit 150 includes a first thin film transistor T1, a second thin film transistor T2, a third thin film transistor T3, a fourth thin film transistor T4 and a capacitor C. The first thin film transistor T1 is a charging unit 151, the second thin film transistor T2 is an output unit 153, and the third thin film transistor T3 and the fourth thin film transistor T4 are a reset unit 152.

[0053] The gate of the first thin film transistor T1 is connected to the source of the first thin film transistor T1 and to the n-1th (n is an integer greater than or equal to 1) row scan line 12, that is, connected to the gate scan signal output terminal of the previous stage, and the drain of the first thin film transistor T1 is connected to the source of the fourth thin film transistor T4 and the gate of the second thin film transistor T2 respectively. The source of the second thin film transistor T2 is connected to the clock signal line CLK to access the clock signal, and the drain of the second thin film transistor T2 is connected to the nth row scan line 12 to output the gate scan signal of the nth row scan line 12. The gates of the third thin film transistor T3 and the fourth thin film transistor T4 are connected to the n+1th row scan line 12 respectively, and the source of the third thin film transistor T3 is connected to the nth row scan line 12. The drain of the third thin film transistor T3 and the drain of the fourth thin film transistor T4 are connected to the low level signal line Vss respectively. The capacitor C is connected to the gate of the second thin film transistor T2 and the drain of the second thin film transistor T2 respectively. In this embodiment, in the same scan driving unit 150, the gate of the first thin film transistor T1, the drain of the second thin film transistor T2 and the gate of the third thin film transistor T3 are respectively connected to different scan lines 12, the gates of the third thin film transistor T3 and the fourth thin film transistor T4 are connected to the same scan line 12, and the source of the third thin film transistor T3 and the drain of the second thin film transistor T2 are connected to the same scan line 12.

[0054] In this embodiment, the scan drive unit 150 only outputs the gate scan signal of the n-th row of scan lines 12. The first thin film transistor T1, the second thin film transistor T2 and the third thin film transistor T3 are located in the n-th row of pixel regions 17, that is, the charging unit 151 and the reset unit 152 are located in another row of pixel regions 17. The second thin film transistor T2 is located in the n+1-th row of pixel regions 17, that is, the output unit 153 is located in a row of pixel regions 17. A single scan drive unit 150 is arranged in two rows of pixel regions 17, so that the space occupied by the single scan drive unit 150 in the single row of pixel regions 17 is reduced by more than half, which is conducive to the increase of the pixel aperture ratio. The third thin film transistor T3 and the fourth thin film transistor T4 are located in the pixel regions 17 of the same column, and the first thin film transistor T1, the second thin film transistor T2 and the third thin film transistor T3 are located in the pixel regions 17 of different columns. That is, a single scan drive unit 150 is arranged in multiple columns of pixel regions 17, so that the space occupied by the single scan drive unit 150 in the single column of pixel regions 17 is reduced, which is conducive to the increase of the pixel aperture ratio. Optionally, the first thin film transistor T1, the second thin film transistor T2 and the third thin film transistor T3 may also be located in different rows of pixel regions 17, and the third thin film transistor T3 and the fourth thin film transistor T4 may also be located in different columns of pixel regions 17. That is, a single scan driving unit 150 may be located in multiple rows of pixel regions 17 or in multiple columns of pixel regions 17, and the thin film transistors in each scan driving unit 150 may be dispersedly arranged in different rows of pixel regions 17 in a variety of ways, so that the space occupied by the scan driving unit 150 in each row of pixel regions 17 is as small as possible.

[0055] See also Figure 5 , Figure 5 It is a structural schematic diagram of the second embodiment of the scan drive unit in the drive substrate provided by the present application.

[0056] In one embodiment, a single scan driving unit 150 can output at least two rows of gate scan signals simultaneously. The drain of the second thin film transistor T2 is connected to the nth row of scan lines 12 and the n+1th row of scan lines 12, respectively, so as to output the gate scan signals of the nth row of scan lines 12 and the n+1th row of scan lines 12 simultaneously. The gates of the third thin film transistor T3 and the fourth thin film transistor T4 are connected to the n+2th row of scan lines 12, respectively, and the drain of the third thin film transistor T3 is connected to the nth row of scan lines 12 and the n+1th row of scan lines 12, respectively. In this embodiment, the scan driving unit 150 outputs two rows of gate scan signals simultaneously, and the second thin film transistor T2 is located in the pixel area 17 between the nth row of scan lines 12 and the n+1th row of scan lines 12, so as to be electrically connected to the nth row of scan lines 12 and the n+1th row of scan lines 12. Optionally, the drain of the second thin film transistor T2 can be connected to more than two scan lines 12, so as to output multiple rows of gate scan signals simultaneously.

[0057] See also Figure 6 , Figure 6 It is a structural schematic diagram of the third embodiment of the scan drive unit in the drive substrate provided in the present application.

[0058] In one embodiment, a single thin film transistor with a relatively large volume is split into a plurality of sub-thin film transistors, and the plurality of sub-thin film transistors are connected in parallel and dispersedly arranged in at least two rows of pixel regions 17, so as to reduce the space occupied by a single thin film transistor in a row of pixel regions 17 and increase the aperture ratio of the pixel. In this embodiment, the second thin film transistor T2 is split into two sub-thin film transistors. The two sub-thin film transistors are connected in parallel. The two sub-thin film transistors are respectively the first sub-thin film transistor T 2-1 and the second sub-thin film transistor T 2-2 The first thin film transistor T 2-1 and the second sub-thin film transistor T 2-2 The drain electrodes of the first sub-thin film transistors T are connected to the n-th row scanning line 12 and are also connected to one end of the capacitor C to output the gate scanning signal of the n-th row scanning line 12. 2-1 and the second sub-thin film transistor T 2-2 The gates of the first thin film transistors T1 and T2 are connected to the drain of the first thin film transistor T1 and are also connected to the other end of the capacitor C. 2-1 and the second sub-thin film transistor T 2-2 The sources of the first thin film transistor T3 and the fourth thin film transistor T4 are connected to the clock signal line CLK. The gates of the third thin film transistor T3 and the fourth thin film transistor T4 are connected to the n+1th row scanning line 12, and the source of the third thin film transistor T3 is connected to the nth row scanning line 12. 2-1 and the second sub-thin film transistor T 2-2Located in pixel areas 17 of different rows and located in pixel areas 17 of the same column. Optionally, the sub-thin film transistors can be located in pixel areas 17 of the same row or in pixel areas 17 of different columns, and the design is based on actual needs, and no excessive restrictions are made here. The second thin film transistor T2 is a switching thin film transistor in the output unit 153, and the volume of a single switching thin film transistor is larger than the volume of a single thin film transistor in the charging unit 151 and the reset unit 152. Splitting the switching thin film transistor can further reduce the space occupied by a single thin film transistor in a row of pixel areas 17. Optionally, the single thin film transistors in the charging unit 151 and the reset unit 152 can also be split, and there is no restriction here, and the design is based on actual needs.

[0059] See also Figure 7 , Figure 7 It is a structural schematic diagram of a fourth embodiment of a scan drive unit in a drive substrate provided in the present application.

[0060] In one embodiment, the first sub-thin film transistor T 2-1 and the second sub-thin film transistor T 2-2 The volume of the first thin film transistor T3 and the second thin film transistor T4 is the same, the gates of the third thin film transistor T3 and the fourth thin film transistor T4 are respectively connected to the n+2th row of scanning line 12, the source of the third thin film transistor T3 is connected to the nth row of scanning line 12, and is connected to one end of the capacitor C. 2-1 The drain electrode of the second sub-thin film transistor T is connected to the nth row scanning line 12. 2-2 The drain of the capacitor C is connected to the n+1th row of scanning line 12. One end of the capacitor C is connected to the first sub-thin film transistor T 2-1 and the second sub-thin film transistor T 2-2 The other end of the capacitor C is only connected to the gate of the first sub-thin film transistor T 2-1 In this embodiment, the first sub-thin film transistor T 2-1 The gate scanning signal is output to the n-th row scanning line 12, and the second sub-thin film transistor T 2-2 The gate scanning signal is output to the n+1th row scanning line 12. Optionally, one end of the capacitor C is connected to the first sub-thin film transistor T 2-1 and the second sub-thin film transistor T 2-2 The other end of the capacitor C is only connected to the gate of the first sub-thin film transistor T 2-1 The second thin film transistor T 2-2 The drain electrode and the first sub-thin film transistor T 2-1 The drain of the first sub-thin film transistor T is connected to the nth row scanning line 12. 2-1 and the second sub-thin film transistor T 2-2 The gate scanning signal is outputted commonly to the scanning lines 12 of the n-th row.

[0061] In another embodiment, the first sub-thin film transistor T 2-1 and the second sub-thin film transistor T 2-2 The volume of the first sub-thin film transistor T 2-1 The volume of the second sub-thin film transistor T 2-2 The volume of the first sub-thin film transistor T 2-1 Control the nth row of pixels to charge to a preset value, and the second sub-thin film transistor T 2-2 Control the pre-charging of the pixels in the n+1th row. The pre-charging gate voltage can be lower to save power.

[0062] See also Figure 8 , Figure 8 It is a structural schematic diagram of the fifth embodiment of the scan drive unit in the drive substrate provided by the present application.

[0063] In one embodiment, the scan driving unit 150 includes six thin film transistors and a capacitor C. The six thin film transistors are respectively a first thin film transistor T1, a second thin film transistor T2, a third thin film transistor T3, a fourth thin film transistor T4, a fifth thin film transistor T5 and a sixth thin film transistor T6. The first thin film transistor T1 is a charging unit 151, the second thin film transistor T2 is an output unit 153, the third thin film transistor T3 and the fourth thin film transistor T4 are a reset unit 152, and the fifth thin film transistor T5 and the sixth thin film transistor T6 are a reset unit 152. Compared with the scan driving unit 150 including four thin film transistors and a capacitor C, the reset unit 152 of the scan driving unit 150 in this embodiment is increased from one to two, and a clock signal line CLKB is also added. The voltage phases of the clock signal line CLK and the clock signal line CLKB are opposite. The clock signal line CLK and the clock signal line CLKB are arranged perpendicular to each other, and the clock signal line CLK is parallel to the low level signal line Vss. The gate and source of the first thin film transistor T1 are connected and connected to the n-1th row scanning line 12, the drain of the first thin film transistor T1 is respectively connected to the gates of the second thin film transistor T2 and the sixth thin film transistor T6, and is also connected to the source of the fourth thin film transistor T4. The source of the second thin film transistor T2 is connected to the clock signal line CLK, and the drain of the second thin film transistor T2 is connected to the nth row scanning line 12 to output the gate scanning signal of the nth row scanning line 12. The gate of the third thin film transistor T3 is respectively connected to the drain of the fifth thin film transistor T5 and the source of the sixth thin film transistor T6, the drain of the third thin film transistor T3 is connected to the low level signal line Vss, and the source of the third thin film transistor T3 is connected to the nth row scanning line 12. The gate of the fourth thin film transistor T4 is respectively connected to the drain of the fifth thin film transistor T5 and the source of the sixth thin film transistor T6, and the drain of the fourth thin film transistor T4 is connected to the low level signal line Vss. The fifth thin film transistor T5 and the sixth thin film transistor T6 are connected in series, and the source and gate of the fifth thin film transistor T5 are connected, and are connected to the clock signal line CLKB. The drain of the sixth thin film transistor T6 is connected to the low level signal line Vss. The two ends of the capacitor C are respectively connected to the gate and drain of the second thin film transistor T2. In this embodiment, the first thin film transistor T1 and the second thin film transistor T2 are located in the pixel area 17 of the nth row, the fifth thin film transistor T5 is located in the pixel area 17 of the n+1th row, and the third thin film transistor T3, the fourth thin film transistor T4 and the sixth thin film transistor T6 are located in the pixel area 17 of the n+2th row. The scan drive unit 150 is arranged in three different rows of pixel areas 17. That is, the charging unit 151 and the output unit 153 are located in a row of pixel areas 17, and the reset unit 152 is respectively located in the pixel area 17 of different rows from the charging unit 151 and the output unit 153.Optionally, the reset unit 152 , the charging unit 151 , and the output unit 153 may each be located in a different row of the pixel region 17 .

[0064] See also Fig. 9 , Fig. 9 It is a structural schematic diagram of a sixth embodiment of a scan drive unit in a drive substrate provided in the present application.

[0065] In one embodiment, the scan driving unit 150 includes eight thin film transistors and a capacitor C. The eight thin film transistors are respectively a first thin film transistor T1, a second thin film transistor T2, a third thin film transistor T3, a fourth thin film transistor T4, a fifth thin film transistor T5, a sixth thin film transistor T6, a seventh thin film transistor T7 and an eighth thin film transistor T8. The first thin film transistor T1 is a charging unit 151, the second thin film transistor T2 is an output unit 153, the third thin film transistor T3 and the seventh thin film transistor T7 are a reset unit 152, the fifth thin film transistor T5 and the sixth thin film transistor T6 are a reset unit 152, and the eighth thin film transistor T8 and the fourth thin film transistor T4 are a reset unit 152. Compared with the scan driving unit 150 including four thin film transistors and a capacitor C, the reset unit 152 of the scan driving unit 150 in this embodiment is increased from one to three, and a clock signal line CLKB is also added. The voltage phases of the clock signal line CLK and the clock signal line CLKB are opposite, and the clock signal line CLK, the clock signal line CLKB and the low level signal line Vss are respectively arranged in parallel with the scan line 12. The gate and source of the first thin film transistor T1 are connected and connected to the n-1th row scanning line 12, the drain of the first thin film transistor T1 is connected to the source of the third thin film transistor T3 and the seventh thin film transistor T7 respectively, and the drain of the first thin film transistor T1 is also connected to the gate of the second thin film transistor T2 and the sixth thin film transistor T6. The source of the second thin film transistor T2 is connected to the clock signal line CLK, and the drain of the second thin film transistor T2 is connected to the nth row scanning line 12 to output the scanning gate signal of the nth row scanning line 12. The third thin film transistor T3 and the seventh thin film transistor T7 are connected in parallel, the gate of the third thin film transistor T3 is connected to the gate of the eighth thin film transistor T8 and the source of the sixth thin film transistor T6 respectively, the drain of the third thin film transistor T3 is connected to the drain of the seventh thin film transistor T7, and is connected to the n+1th row scanning line 12, and the source of the third thin film transistor T3 is connected to the source of the seventh thin film transistor T7. The fifth thin film transistor T5 and the sixth thin film transistor T6 are connected in series, the source and gate of the fifth thin film transistor T5 are connected, and are connected to the clock signal line CLKB, and the drain of the fifth thin film transistor T5 is connected to the source of the sixth thin film transistor T6. The gate of the sixth thin film transistor T6 is connected to the gate of the second thin film transistor T2, the drain of the sixth thin film transistor T6 is connected to the low level signal line Vss, and the source of the sixth thin film transistor T6 is connected to the gates of the third thin film transistor T3 and the eighth thin film transistor T8. The eighth thin film transistor T8 and the fourth thin film transistor T4 are connected in parallel, the source of the eighth thin film transistor T8 and the fourth thin film transistor T4 are connected and connected to the n-th row scanning line 12, and the drain of the eighth thin film transistor T8 and the fourth thin film transistor T4 are connected and connected to the low level signal line Vss.The gate of the fourth thin film transistor T4 is connected to the n+1th row of scan line 12. Both ends of the capacitor C are connected to the gate and drain of the second thin film transistor T2, respectively. In this embodiment, the first thin film transistor T1, the second thin film transistor T2 and the fifth thin film transistor T5 are located in the nth row of pixel region 17, and the third thin film transistor T3, the fourth thin film transistor T4, the sixth thin film transistor T6, the seventh thin film transistor T7 and the eighth thin film transistor T8 are located in the n+1th row of pixel region 17. The scan driving unit 150 is disposed in two different rows of pixel regions 17.

[0066] See also Figure 4 and Fig.10 , Fig.10 It is a structural schematic diagram of another embodiment of the driving substrate provided in the present application.

[0067] In one embodiment, the same row of scan lines 12 can be divided into multiple segments for driving, and each segment of the scan line 12 can also be driven by one or two scan drive units 150, thereby reducing the load of the drive. In this embodiment, all scan lines 12 are divided into two parts along the extension direction of the scan line 12, and the segment positions of each row of scan lines 12 are the same. A scan drive unit 150 is set in each row of pixel areas 17 in each part of the scan line 12, and the scan drive units 150 are dispersed in two rows of pixel areas 17, and the row spacing of all pixel electrodes 14 is the same, and the column spacing is also the same. Each part of the scan line 12 includes a clock signal line CLK and a low-level signal line Vss. Optionally, the segment position of each row of scan lines 12 can be different, the number of segments of each row of scan lines 12 can also be different, and the number of scan drive units 150 of each segment of scan lines 12 can also be different. There are no excessive restrictions here, and the design is carried out according to the actual situation.

[0068] The present application provides a driving substrate, which includes a substrate, a plurality of scan lines, a plurality of data lines, and a scan drive circuit. The substrate has a display area; a plurality of scan lines and a plurality of data lines are arranged on the substrate; a plurality of scan lines and a plurality of data lines are crisscrossed vertically and horizontally to define a plurality of pixel areas; and the pixel areas are located in the display area; wherein the row directions of the plurality of pixel areas are parallel to the scan lines; the scan drive circuit is arranged in the display area of ​​the substrate, and the scan drive circuit includes a plurality of cascaded scan drive units; the same scan drive unit is arranged in at least two rows of pixel areas, and can output at least one row of gate scan signals. The present application reduces the space occupied by the scan drive unit in a single row of pixel areas by dispersing the single scan drive unit arranged in the display area in the plurality of rows of pixel areas, thereby improving the pixel aperture ratio.

[0069] The above are only implementation methods of the present application, and are not intended to limit the patent protection scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly used in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A driving substrate for a liquid crystal display panel, comprising: A substrate having a display area; A plurality of scan lines and a plurality of data lines are arranged on the substrate; the plurality of scan lines and the plurality of data lines are vertically and horizontally crossed to define a plurality of pixel areas; and the pixel areas are located in the display area; wherein the row directions of the plurality of pixel areas are parallel to the scan lines; A scan driving circuit is arranged in the display area of ​​the substrate, and the scan driving circuit comprises a plurality of cascaded scan driving units; The invention is characterized in that the same scanning driving unit is arranged in at least two rows of pixel regions and can output at least one row of gate scanning signals; The scan driving unit comprises a charging unit, a reset unit and an output unit; the output unit is located in one or two rows of pixel areas, and the charging unit and the reset unit are located in another row of pixel areas; or the output unit, the charging unit and the reset unit are respectively located in one row of pixel areas; The scanning driving unit includes a plurality of thin film transistors, and the plurality of thin film transistors are dispersedly arranged in two or three rows of pixel areas; The output unit includes a switch thin film transistor, a single switch thin film transistor includes a plurality of sub-thin film transistors, and the plurality of sub-thin film transistors are connected in parallel and dispersedly arranged in at least two rows of pixel regions.

2. The driving substrate according to claim 1, characterized in that: The output unit includes a switching thin film transistor, and the switching thin film transistor is connected to a plurality of the scanning lines, so that the scanning driving unit outputs a plurality of rows of gate scanning signals simultaneously.

3. The driving substrate according to claim 1, characterized in that: The scanning driving unit includes a first thin film transistor, a second thin film transistor, a third thin film transistor, a fourth thin film transistor and a capacitor C; The gate of the first thin film transistor is connected to the drain of the first thin film transistor and to the output end of the gate scanning signal of the previous stage, and the drain of the first thin film transistor is respectively connected to the source of the fourth thin film transistor and the gate of the second thin film transistor; The source of the second thin film transistor is connected to the clock signal, and the drain of the second thin film transistor is connected to at least one of the scan lines to output at least one row of the gate scan signal; The gates of the third thin film transistor and the fourth thin film transistor are connected to the same scan line, and the source of the third thin film transistor and the drain of the second thin film transistor are connected to the same scan line; the drain of the third thin film transistor and the drain of the fourth thin film transistor are respectively connected to a low level signal; The capacitor is connected to the gate electrode of the second thin film transistor and the drain electrode of the second thin film transistor respectively; The gate electrode of the first thin film transistor, the drain electrode of the second thin film transistor and the gate electrode of the third thin film transistor are respectively connected to different scan lines.

4. The driving substrate according to claim 3, characterized in that: The drain of the second thin film transistor is respectively connected to the scan line of the nth row and the scan line of the n+1th row to simultaneously output the gate scan signal of the nth row and the gate scan signal of the n+1th row; the gates of the third thin film transistor and the fourth thin film transistor are respectively connected to the scan line of the n+2th row; n is an integer greater than or equal to 1.

5. The driving substrate according to claim 3, characterized in that: It also includes a clock signal line for providing the clock signal and a low-level signal line for providing the low-level signal, the clock signal line is spaced apart from the data line along the extension direction of the data line, and the clock signal line is connected to the source of the second thin film transistor; the low-level signal line is spaced apart from the data line along the extension direction of the data line, and the low-level signal line is respectively connected to the drain of the third thin film transistor and the drain of the fourth thin film transistor.

6. The driving substrate according to claim 1, characterized in that: The same scan driving unit is disposed in at least two columns of pixel regions.

7. A display panel, characterized in that: include: a first substrate; The first substrate is a driving substrate according to any one of claims 1 to 6; a second substrate, arranged opposite to the first substrate; The liquid crystal layer is disposed between the first substrate and the second substrate.

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