Pixel circuit and display panel

Abstract

The present application discloses a pixel circuit and a display panel. The pixel circuit includes a light-emitting device, a driving transistor, a data signal writing module, a threshold voltage compensation module, a first initialization module, a light-emitting control module, and a coupling capacitor. The present application adds a coupling capacitor in the pixel circuit to ensure that the gate potential of the driving transistor is basically maintained at an initial value under long-term display. Thereby, when driving at a low frequency, the potential stability of the gate of the driving transistor is improved, flicker is reduced, and the display quality is improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a pixel circuit and a display panel. Background Art

[0002] Light-emitting devices such as mini LEDs, micro LEDs, and organic LEDs have the advantages of high brightness, high contrast, and high color gamut, and have been widely used in the field of high-performance displays. In existing pixel circuits, leakage is a serious problem. In the subsequent light-emitting process of the light-emitting device, due to leakage current, the gate potential of the driving transistor will change, resulting in a large change in brightness within a frame under low-frequency driving, resulting in flickering and affecting the display quality of the display device. Summary of the invention

[0003] The present application provides a pixel circuit and a display panel to solve the problem that the potential of the gate of a driving transistor changes due to leakage in the existing pixel circuit.

[0004] The present application provides a pixel circuit, which includes:

[0005] A light emitting device, one end of which is connected to a first power signal, and the other end of which is connected to a second power signal;

[0006] a data signal writing module, the data signal writing module receiving the first scanning signal and the data signal, and outputting the data signal in response to the first scanning signal;

[0007] A driving transistor, one of a source and a drain of the driving transistor is connected to the data signal writing module;

[0008] A threshold voltage compensation module, the threshold voltage compensation module is connected to the second scanning signal and the first power supply signal, and is connected to the other of the source and the drain of the driving transistor and the gate of the driving transistor;

[0009] A first initialization module, the first initialization module receives a control signal and a first initialization signal, and is connected to the gate of the driving transistor;

[0010] a light-emitting control module, the light-emitting control module receiving the light-emitting control signal and connected in series between the first power signal and the second power signal; and

[0011] A coupling capacitor, one end of which is connected to the adjustment signal, and the other end of which is connected to the first initialization module or the threshold voltage compensation module.

[0012] Optionally, in some embodiments of the present application, the threshold voltage compensation module includes a second transistor, a seventh transistor and a first capacitor;

[0013] Among them, the gate of the second transistor is connected to the second scanning signal, one of the source and the drain of the second transistor and one end of the first capacitor are connected to the gate of the driving transistor, the other of the source and the drain of the second transistor is connected to the first node with one of the source and the drain of the seventh transistor T7, the other of the source or the drain of the seventh transistor T7 is connected to the other of the source and the drain of the driving transistor, the gate of the seventh transistor is connected to the first scanning signal, and the other end of the first capacitor is connected to the first power supply signal.

[0014] Optionally, in some embodiments of the present application, one end of the coupling capacitor is connected to the first node, and the other end of the coupling capacitor is connected to the adjustment signal.

[0015] Optionally, in some embodiments of the present application, the second transistor is a dual-gate transistor, and the first gate and the second gate of the second transistor are both connected to the second scanning signal; one end of the coupling capacitor is connected to the dual gate node of the second transistor, and the other end of the coupling capacitor is connected to the adjustment signal.

[0016] Optionally, in some embodiments of the present application, the first initialization module includes a third transistor, a gate of the third transistor is connected to the control signal, one of the source and the drain of the third transistor is connected to the first initial signal, and the other of the source and the drain of the third transistor is connected to the first node.

[0017] Optionally, in some embodiments of the present application, the threshold voltage compensation module includes a second transistor and a first capacitor;

[0018] The gate of the second transistor is connected to the second scanning signal, one of the source and the drain of the second transistor and one end of the first capacitor are connected to the gate of the driving transistor, the other of the source and the drain of the second transistor is connected to the other of the source and the drain of the driving transistor, and the other end of the first capacitor is connected to the first power supply signal.

[0019] Optionally, in some embodiments of the present application, the second transistor is a dual-gate transistor, and the first gate and the second gate of the second transistor are both connected to the second scanning signal; one end of the coupling capacitor is connected to the dual gate node of the second transistor, and the other end of the coupling capacitor is connected to the adjustment signal.

[0020] Optionally, in some embodiments of the present application, the first initialization module includes a third transistor, the gate of the third transistor is connected to the control signal, one of the source and the drain of the third transistor is connected to the first initialization signal, and the other of the source and the drain of the third transistor is connected to the gate of the driving transistor;

[0021] The third transistor is a dual-gate transistor, and the pixel circuit further includes a second capacitor, one end of the second capacitor is connected to the dual-gate node of the third transistor, and the other end of the second capacitor is connected to the first initial signal.

[0022] Optionally, in some embodiments of the present application, the first initialization module includes a third transistor, the gate of the third transistor is connected to the control signal, one of the source and the drain of the third transistor is connected to the first initialization signal, and the other of the source and the drain of the third transistor is connected to the gate of the driving transistor;

[0023] The third transistor is a dual-gate transistor, one end of the coupling capacitor is connected to the dual-gate node of the third transistor, and the other end of the coupling capacitor is connected to the adjustment signal.

[0024] Optionally, in some embodiments of the present application, the second transistor is a dual-gate transistor, and the first gate and the second gate of the second transistor are both connected to the second scanning signal;

[0025] The pixel circuit further includes a second capacitor, one end of the second capacitor is connected to the dual gate node of the second transistor, and the other end of the second capacitor is connected to the first initial signal.

[0026] Optionally, in some embodiments of the present application, the pixel circuit further includes a second initialization module, and the second initialization module includes a sixth transistor;

[0027] The gate of the sixth transistor is connected to the first scanning signal, one of the source and the drain of the sixth transistor is connected to the other of the source and the drain of the driving transistor, and the other of the source and the drain of the sixth transistor is connected to the second initial signal.

[0028] Optionally, in some embodiments of the present application, the light control module includes a first light control unit and a second light control unit, the first light control unit includes a fourth transistor; the second light control unit includes a fifth transistor;

[0029] The gate of the fourth transistor and the gate of the fifth transistor are both connected to the light-emitting control signal, one of the source and the drain of the fourth transistor is connected to the first power supply signal, and the other of the source and the drain of the fourth transistor is connected to one of the source and the drain of the driving transistor; one of the source and the drain of the fifth transistor is connected to the first electrode of the light-emitting device, and the other of the source and the drain of the fifth transistor is connected to the other of the source and the drain of the driving transistor.

[0030] Optionally, in some embodiments of the present application, the coupling capacitor is a variable capacitor.

[0031] Correspondingly, the present application also provides a display panel, which includes a plurality of pixel units arranged in an array, and each of the pixel units includes any one of the pixel circuits described above.

[0032] The present application discloses a pixel circuit and a display panel. The pixel circuit includes a light-emitting device, a driving transistor, a data signal writing module, a threshold voltage compensation module, a first initialization module, a light-emitting control module, and a coupling capacitor. The present application couples the gate potential of the driving transistor by adding a coupling capacitor in the pixel circuit to ensure that the gate potential of the driving transistor is basically maintained at an initial value under long-term display. Thereby, when driving at a low frequency, the potential stability of the gate of the driving transistor is improved, flicker is reduced, and the display quality is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0034] Figure 1 A schematic diagram of the structure of a pixel circuit provided in this application;

[0035] Figure 2 A first circuit schematic diagram of a pixel circuit provided in the present application;

[0036] Figure 3 for Figure 2 A timing diagram of the pixel circuit shown;

[0037] Figure 4 A second circuit schematic diagram of a pixel circuit provided in the present application;

[0038] Figure 5 A third circuit schematic diagram of the pixel circuit provided in this application;

[0039] Figure 6 for Figure 5 A timing diagram of the pixel circuit shown;

[0040] Figure 7 A fourth circuit schematic diagram of the pixel circuit provided in the present application;

[0041] Figure 8 A fifth circuit schematic diagram of the pixel circuit provided in the present application;

[0042] Fig. 9 A schematic diagram of the structure of the display panel provided in this application;

[0043] Fig.10 A schematic diagram of brightness changes of the display panel provided in this application. DETAILED DESCRIPTION

[0044] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of this application.

[0045] In the description of the present application, it should be understood that the terms "first" and "second" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, features defined as "first" and "second" etc. may explicitly or implicitly include one or more of the said features, and therefore cannot be understood as limitations on the present application. In addition, it should be noted that, unless otherwise clearly specified and defined, the terms "connected" and "connected" should be understood in a broad sense, for example, it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the internal connection of two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0046] The present application provides a pixel circuit and a display panel, which are described in detail below. It should be noted that the description order of the following embodiments is not intended to limit the preferred order of the embodiments of the present application.

[0047] It should be noted that, since the source and drain of the transistor used in the present application are symmetrical, the source and drain are interchangeable.

[0048] See also Figure 1 , Figure 1In the embodiment of the present application, the pixel circuit 10 includes a light emitting device D, a driving transistor Td, a data signal writing module 101, a threshold voltage compensation module 102, a first initialization module 103, a light emitting control module 104 and a coupling capacitor Cst1.

[0049] One end of the light emitting device D is connected to the first power signal VDD, and the other end of the light emitting device D is connected to the second power signal VSS.

[0050] The data signal writing module 101 receives the first scanning signal S1 (n) and the data signal Da, and outputs the data signal Da in response to the first scanning signal S1 (n).

[0051] One of the source and the drain of the driving transistor Td is connected to the data signal writing module 101 .

[0052] The threshold voltage compensation module 102 receives the second scan signal S2 (n) and the first power signal VDD, and is connected to the other of the source and the drain of the driving transistor Td and the gate of the driving transistor Td.

[0053] The first initialization module 103 receives the control signal and the first initialization signal V1, and is connected to the gate G of the driving transistor Td. The control signal may be the third scanning signal S1(n-1). The first initialization module 103 may be directly connected to the gate G of the driving transistor Td, or may be indirectly connected to the gate G of the driving transistor Td through the threshold voltage compensation module 102, which will be specifically described in the following embodiments.

[0054] The light emitting control module 104 receives the light emitting control signal EM and is connected in series between the first power signal VDD and the second power signal VSS.

[0055] One end of the coupling capacitor Cst1 is connected to the adjustment signal EM1 (n), and the other end of the coupling capacitor Cst1 is connected to the first initialization module 103 or the threshold voltage compensation module 102 .

[0056] The initial potential of the gate G of the driving transistor Td refers to the potential of the gate G of the driving transistor Td when there is no leakage and the light emitting device D emits target brightness during the light emitting stage.

[0057] It should be noted that Figure 1 In the figure, the example in which the first initialization module 103 and the other end of the coupling capacitor Cst are both connected to the threshold voltage compensation module 102 is used for illustration, but it should not be understood as a limitation to the present application.

[0058] In the embodiment of the present application, a coupling capacitor Cst1 is added to the pixel circuit 10 to couple the gate potential of the driving transistor, thereby ensuring that the gate potential of the driving transistor is substantially maintained at an initial value during long-term display.

[0059] Specifically, in the light-emitting stage, the voltage value of the adjustment signal EM1(n) alternately changes between a first potential and a second potential, and the first potential is greater than the initial potential of the gate G of the driving transistor Td, and the second potential is less than the initial potential of the gate G of the driving transistor Td.

[0060] In the light-emitting stage, by adjusting the time occupied by the first potential and the second potential of the adjustment signal EM1(n), the node connected to the gate G of the driving transistor Td is potential coupled to reduce the leakage of the gate G of the driving transistor Td. It is ensured that the potential of the gate G of the driving transistor Td is basically maintained at the initial value under long-term display. Thereby, the potential stability of the gate G of the driving transistor Td is improved, the flicker during low-frequency driving is reduced, and the display quality during low-frequency driving is improved.

[0061] Please continue reading Figure 1 The pixel circuit 10 provided in the embodiment of the present application further includes a second initialization module 105. The second initialization module 105 receives the first scanning signal S1(n) and the second initialization signal V2, and is connected to the first electrode of the light-emitting device D. The second initialization module 105 is used to initialize the potential of the first electrode of the light-emitting device D under the control of the first scanning signal S1(n).

[0062] In the embodiment of the present application, when the light emitting device D is a light emitting diode, the first electrode of the light emitting device D may be an anode of the light emitting device D.

[0063] In the embodiment of the present application, the first initial signal V1 and the second initial signal V2 may be the same signal or different signals. The first initial signal V1 and the second initial signal V2 may be specifically set according to the reset requirement of the pixel circuit 10 .

[0064] In the embodiment of the present application, the second initialization module 105 is provided in the pixel circuit 10 to initialize the potential of the first electrode of the light-emitting device D, thereby preventing the residual charge of the first electrode of the light-emitting device D from affecting the light-emitting brightness of the light-emitting device D.

[0065] In the embodiments of this application, please refer to Figure 2 , Figure 2 This is a first circuit diagram of a pixel circuit provided in the present application. Figure 1 and Figure 2 As shown, the data signal writing module 101 includes a first transistor T1.

[0066] The gate of the first transistor T1 is connected to the first scanning signal S1(n). One of the source and the drain of the first transistor T1 is connected to the data signal Da. The other of the source and the drain of the first transistor T1 is electrically connected to one of the source and the drain of the driving transistor Td. Of course, it can be understood that the data signal writing module 101 can also be formed by connecting multiple transistors in series.

[0067] In the embodiment of the present application, the threshold voltage compensation module 102 includes a second transistor T2 , a seventh transistor T7 , and a first capacitor Cst2 .

[0068] The gate of the second transistor T2 is connected to the second scanning signal S2(n). One of the source and drain of the second transistor T2 and one end of the first capacitor Cst2 are connected to the gate of the driving transistor Td. The other of the source and drain of the second transistor T2 is connected to the first node Q with one of the source and drain of the seventh transistor T7. The other of the source or drain of the seventh transistor T7 is connected to the other of the source and drain of the driving transistor Td. The gate of the seventh transistor T7 is connected to the first scanning signal S1(n). The other end of the first capacitor Cst2 is connected to the first power supply signal VDD.

[0069] In the embodiment of the present application, one end of the coupling capacitor Cst is connected to the first node Q. The other end of the coupling capacitor Cst is connected to the adjustment signal EM1 (n).

[0070] It can be understood that one end of the coupling capacitor Cst is connected to the first node Q, and when the adjustment signal EM1(n) alternates between the first potential and the second potential, the potential of the first node Q is coupled. Since the first potential is greater than the initial potential of the gate G of the driving transistor Td, and the second potential is less than the initial potential of the gate G of the driving transistor Td, the potential of the first node Q is alternately coupled to a potential greater than the initial potential of the gate G of the driving transistor Td or less than the initial potential of the gate G of the driving transistor Td. Therefore, during the long light emission time, the alternation of high and low potentials of the first node Q causes the charging and discharging of the gate G of the driving transistor Td to offset each other, thereby keeping the initial potential of the gate G of the driving transistor Td substantially at the initial value.

[0071] In the embodiment of the present application, the first initialization module 103 includes a third transistor T3. The control signal connected to the gate of the third transistor T3 is the third scanning signal S1(n-1). One of the source and the drain of the third transistor T3 is connected to the first initialization signal V1. The other of the source and the drain of the third transistor T3 is connected to the first node Q.

[0072] It can be understood that the first initialization module 103 is set to be connected to the first node Q, and then electrically connected to the gate G of the driving transistor Td through the threshold voltage compensation module 102, so that the gate potential of the driving transistor Td can be initialized and the transistors connected to the gate G of the driving transistor Td can be reduced. Therefore, the leakage path of the gate G of the driving transistor Td is reduced, the potential stability of the gate G of the driving transistor Td is improved, and the flicker during low-frequency display is reduced, thereby improving the display quality.

[0073] In the embodiment of the present application, the light control module 104 includes a first light control unit 1041 and a second light control unit 1042. The first light control unit 1041 includes a fourth transistor T4. The second light control unit 1042 includes a fifth transistor T5. The gate of the fourth transistor T4 and the gate of the fifth transistor T5 are both connected to the light control signal EM(n). One of the source and the drain of the fourth transistor T4 is connected to the first power supply signal VDD. The other of the source and the drain of the fourth transistor T4 is electrically connected to one of the source and the drain of the driving transistor Td. One of the source and the drain of the fifth transistor T5 is electrically connected to the first electrode of the light emitting device D. The other of the source and the drain of the fifth transistor T5 is electrically connected to the other of the source and the drain of the driving transistor Td.

[0074] Of course, it is understandable that in the pixel circuit 10 provided in the embodiment of the present application, the light emitting control module 104 may include 3, 4 or more light emitting control units. Each light emitting control unit is connected in series between the first power supply signal VDD and the second power supply signal VSS. Multiple light emitting control units may be connected to the same light emitting control signal EM or to different light emitting control signals EM. In addition, it is understandable that each light emitting control unit may also be formed by connecting multiple transistors in series.

[0075] In the embodiment of the present application, the second initialization module 105 includes a sixth transistor T6. The gate of the sixth transistor T6 is connected to the first scanning signal S1(n). One of the source and the drain of the sixth transistor T6 is electrically connected to the other of the source and the drain of the driving transistor Td. The other of the source and the drain of the sixth transistor T6 is connected to the second initialization signal V2. Of course, it can be understood that the second initialization module 105 can also be formed by connecting a plurality of transistors in series.

[0076] In the embodiment of the present application, the first power signal VDD and the second power signal VSS are both used to output a preset voltage value. In addition, in the embodiment of the present application, the potential of the first power signal VDD is greater than the potential of the second power signal VSS. Specifically, the potential of the second power signal VSS can be the potential of the ground terminal. Of course, it can be understood that the potential of the second power signal VSS can also be other.

[0077] In an embodiment of the present application, each transistor in the pixel circuit 10 may be one or more of a low-temperature polysilicon thin film transistor, an oxide semiconductor thin film transistor, or an amorphous silicon thin film transistor. In addition, the transistor in the pixel circuit 10 provided by the present application may also be a P-type transistor or an N-type transistor. Further, the transistors in the pixel circuit 10 provided by the present application may be set to be transistors of the same type, thereby avoiding the influence of the differences between different types of transistors on the pixel circuit 10.

[0078] In addition, since the pixel circuit 10 of the present application effectively reduces leakage by setting the coupling capacitor Cst1 and reducing the leakage path of the gate potential of the driving transistor Td. Therefore, compared with the existing LTPO (Low Temperature Polycrystalline Oxide, low temperature polycrystalline oxide) technology, the IGZO (Indium Gallium Zinc Oxide, indium gallium zinc oxide) transistor with lower leakage current is used to solve the problem of severe flickering under low-frequency driving. The present application can only use LTPS (Low Temperature Poly-Silicon, low temperature polycrystalline silicon) transistors, and there is no need to combine LTPS transistors and IGZO transistors together. The structure and process of the pixel circuit 10 are simpler, which effectively reduces the cost.

[0079] It should be noted that the following embodiments of the present application are described by taking the transistors in the pixel circuit 10 as P-type transistors as an example, but this should not be construed as a limitation on the present application.

[0080] See also Figure 3 , Figure 3 for Figure 2 The timing diagram of the pixel circuit shown in FIG. The light-emitting control signal EM(n), the adjustment signal EM1(n), the first scanning signal S1(n), the second scanning signal S2(n) and the third scanning signal S1(n-1) are combined to correspond to the reset stage t1, the threshold voltage compensation stage t2 and the light-emitting stage t3. That is, within one frame time, the driving control timing of the pixel circuit 10 provided in the embodiment of the present application includes the reset stage t1, the threshold voltage compensation stage t2 and the light-emitting stage t3.

[0081] In the reset phase t1, the second scanning signal S2(n) and the third scanning signal S1(n-1) are both at low potentials. The first scanning signal S1(n) and the light emitting control signal EM(n) are both at high potentials. At this time, the first transistor T1, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 are all turned off. The second transistor T2 and the third transistor T3 are turned on. The first initial signal V1 is output to the gate of the driving transistor Td through the first transistor T1 and the second transistor T2. The potential of the gate of the driving transistor Td is reset to the potential of the first initial signal V1.

[0082] In the threshold voltage compensation stage t2, the first scanning signal S1(n) and the second scanning signal S2(n) are both at low potentials. The third scanning signal S1(n-1) and the light emitting control signal EM(n) are both at high potentials. At this time, the third transistor T3, the fourth transistor T4, and the fifth transistor T5 are all turned off. The first transistor T1, the second transistor T2, and the seventh transistor T7 are turned on. The data signal Da is written to the gate of the driving transistor Td through the first transistor T1, the driving transistor Td, the seventh transistor T7, and the second transistor T2. When the potential of the gate G of the driving transistor Td is charged to Vdata-Vth, the driving transistor Td is turned off, and the potential of the gate G of the driving transistor Td no longer rises. The first capacitor C1 stores the potential of the gate G of the driving transistor Td.

[0083] At the same time, since the first scanning signal S1(n) is at a low potential, the sixth transistor T6 is turned on, and the potential of the first electrode of the light emitting device D is reset to the potential of the second initial signal V2, thereby ensuring that the light emitting device D does not emit light in the threshold voltage compensation stage t2.

[0084] In the light-emitting stage t3, the light-emitting control signal EM(n) is at a low potential, and the first scanning signal S1(n), the second scanning signal S2(n) and the third scanning signal S1(n-1) are all at a high potential. At this time, the first transistor T1, the second transistor T2, the third transistor T3, the sixth transistor T6 and the seventh transistor T7 are all turned off. The driving transistor Td, the fourth transistor T4 and the fifth transistor T5 are all turned on. The driving transistor Td generates a driving current corresponding to the data signal Da through the potential of the gate G. The driving current flows to the light-emitting device D through the turned-on fourth transistor T4, the driving transistor Td and the fifth transistor T5, driving the light-emitting device D to emit light.

[0085] It can be understood that, in the light-emitting stage t3, the voltage value of the adjustment signal EM1(n) alternates between the first potential and the second potential. The time that the adjustment signal EM1(n) is at the first potential can be greater than, equal to or less than the time that the adjustment signal EM1(n) is at the second potential. Among them, the first potential is greater than the initial potential of the gate G of the driving transistor Td, and the second potential is less than the initial potential of the gate G of the driving transistor Td. When the adjustment signal EM1(n) jumps from the first potential to the second potential, the potential of the first node Q is less than the initial potential of the gate G of the driving transistor Td. The gate G of the driving transistor Td leaks and the potential decreases. When the adjustment signal EM1(n) jumps from the second potential to the first potential, the potential of the first node Q is greater than the initial potential of the gate G of the driving transistor Td. The gate potential of the driving transistor Td increases. In this way, it can be ensured that the gate potential of the driving transistor Td is basically maintained at the initial value under long-term display.

[0086] In addition, since the seventh transistor T7 is provided, in the light emitting stage t3 , the influence of the other potential of the source and the drain of the driving transistor Td on the gate potential of the driving transistor Td can be reduced.

[0087] See also Figure 4 , Figure 4 The second circuit diagram of the pixel circuit provided by the present application is shown in FIG. Figure 2 The difference of the pixel circuit 10 shown is that, in the present embodiment, the second transistor T2 is a dual-gate transistor. The first gate and the second gate of the second transistor T2 are both connected to the second scanning signal S2(n). One end of the coupling capacitor Cst is connected to the dual-gate node P of the second transistor T2. The other end of the coupling capacitor Cst is connected to the adjustment signal EM1(n).

[0088] It is understandable that the leakage current of a dual-gate transistor is smaller than that of a single-gate transistor. Therefore, in this embodiment, the second transistor T2 is set as a dual-gate transistor, which can further reduce the leakage at the gate G of the driving transistor Td and ensure the potential stability of the gate G of the driving transistor Td.

[0089] The driving timing of the pixel circuit 10 in this embodiment is similar to Figure 2 The driving timing of the pixel circuit 10 is the same as that of the pixel circuit 10, and the details can be referred to the above content, which will not be repeated here.

[0090] See also Figure 5 , Figure 5 The third circuit diagram of the pixel circuit provided in this application is shown in FIG. Figure 2 The difference of the pixel circuit 10 shown is that, in this embodiment, the threshold voltage compensation module 102 includes a second transistor T2 and a first capacitor Cst2.

[0091] The gate of the second transistor T2 is connected to the second scanning signal S2(n). One of the source and drain of the second transistor T2 and one end of the first capacitor Cst2 are connected to the gate G of the driving transistor Td. The other of the source and drain of the second transistor T2 is connected to the other of the source and drain of the driving transistor Td. The other end of the first capacitor Cst2 is connected to the first power supply signal VDD.

[0092] Specifically, in the embodiment of the present application, the second transistor T2 is a dual-gate transistor. The first gate and the second gate of the second transistor T2 are both connected to the second scanning signal S2(n). One end of the coupling capacitor Cst is connected to the dual-gate node P of the second transistor T2. The other end of the coupling capacitor Cst is connected to the adjustment signal EM1(n).

[0093] The pixel circuit 10 provided in the present application uses a pixel circuit with a 7T1C (7 transistors and 1 capacitor) structure to control the light-emitting device D, uses fewer components, has a simple and stable structure, and saves costs.

[0094] Further, in the embodiment of the present application, the first initialization module 103 includes a third transistor T3. The control signal connected to the gate of the third transistor T3 is the fourth scanning signal S2(n-1). One of the source and the drain of the third transistor T3 is connected to the first initialization signal V1. The other of the source and the drain of the third transistor T3 is connected to the gate of the driving transistor Td.

[0095] The third transistor T3 is a dual-gate transistor. The pixel circuit 10 further includes a second capacitor Cst3. One end of the second capacitor Cst3 is connected to the dual-gate node E of the third transistor T3. The other end of the second capacitor Cst3 is connected to the first initial signal V1.

[0096] The embodiment of the present application sets the second capacitor Cst3 to clamp the potential of the double gate node E of the third transistor T3, further reducing the leakage at the gate G of the driving transistor Td. In addition, the other end of the second capacitor Cst3 is connected to the first initial signal V1, and the first initial signal V1 is reused, which can simplify the signal complexity in the pixel circuit 10.

[0097] In the embodiment of the present application, the second initialization module 105 is connected to the fifth scanning signal S1(n+1) and the second initialization signal V2, and is connected to the first electrode of the light-emitting device D. The second initialization module 105 includes a sixth transistor T6. The gate of the sixth transistor T6 is connected to the fifth scanning signal S1(n+1). One of the source and the drain of the sixth transistor T6 is connected to one of the source and the drain of the driving transistor Td. The other of the source and the drain of the sixth transistor T6 is connected to the second initialization signal V2. The second initialization signal V2 can be the same signal as the first initialization signal V1.

[0098] See also Figure 6 , Figure 6 for Figure 5 The timing diagram of the pixel circuit shown in FIG. The light-emitting control signal EM(n), the adjustment signal EM1(n), the first scanning signal S1(n), the second scanning signal S2(n), the fourth scanning signal S2(n-1) and the fifth scanning signal S1(n+1) are combined to correspond to the first reset stage t1, the threshold voltage compensation stage t2, the second reset stage t3 and the light-emitting stage t4. That is, within one frame time, the driving control timing of the pixel circuit 10 provided in the embodiment of the present application includes the first reset stage t1, the threshold voltage compensation stage t2, the second reset stage t3 and the light-emitting stage t4.

[0099] In the first reset phase t1, the fourth scanning signal S2(n-1) is at a low potential. The first scanning signal S1(n), the second scanning signal S2(n), the fifth scanning signal S1(n+1) and the light emitting control signal EM(n) are all at a high potential. At this time, the first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5 and the sixth transistor T6 are all turned off. The third transistor T3 is turned on. The first initial signal V1 is output to the gate G of the driving transistor Td through the third transistor T3. The potential of the gate G of the driving transistor Td is reset to the potential of the first initial signal V1.

[0100] In the threshold voltage compensation stage t2, the first scanning signal S1(n) and the second scanning signal S2(n) are both at low potential. The fourth scanning signal S2(n-1), the fifth scanning signal S1(n+1) and the light emitting control signal EM(n) are all at high potential. At this time, the third transistor T3, the fourth transistor T4 and the fifth transistor T5 are all turned off. The first transistor T1 and the second transistor T2 are both turned on. The data signal Da is written to the gate G of the driving transistor Td through the first transistor T1, the driving transistor Td and the second transistor T2. When the potential of the gate G of the driving transistor Td is charged to Vdata-Vth, the driving transistor Td is turned off, and the potential of the gate G of the driving transistor Td no longer rises. The first capacitor C1 stores the potential of the gate G of the driving transistor Td.

[0101] In the second reset stage t3, the fifth scanning signal S1(n+1) is at a low potential, and the light-emitting control signal EM(n), the first scanning signal S1(n), the second scanning signal S2(n) and the fourth scanning signal S2(n-1) are all at a high potential. The sixth transistor T6 is turned on. The potential of the first electrode of the light-emitting device D is reset to the potential of the second initial signal V2. This ensures that the light-emitting device D does not emit light in the threshold voltage compensation stage t2.

[0102] In the light-emitting stage t4, the light-emitting control signal EM(n) is at a low potential, and the first scanning signal S1(n), the second scanning signal S2(n), the fourth scanning signal S2(n-1) and the fifth scanning signal S1(n+1) are all at a high potential. At this time, the first transistor T1, the second transistor T2, the third transistor T3 and the sixth transistor T6 are all turned off. The driving transistor Td, the fourth transistor T4 and the fifth transistor T5 are all turned on. The driving transistor Td generates a driving current corresponding to the data signal Da through the potential of the gate. The driving current flows to the light-emitting device D through the turned-on fourth transistor T4, the driving transistor Td and the fifth transistor T5, driving the light-emitting device D to emit light.

[0103] It can be understood that, in the light-emitting stage t4, the voltage value of the adjustment signal EM1(n) alternates between the first potential and the second potential. The time that the adjustment signal EM1(n) is at the first potential can be greater than, equal to or less than the time that the adjustment signal EM1(n) is at the second potential. Among them, the first potential is greater than the initial potential of the gate G of the driving transistor Td, and the second potential is less than the initial potential of the gate G of the driving transistor Td. When the adjustment signal EM1(n) jumps from the first potential to the second potential, the potential of the double gate node P of the second transistor T2 is less than the initial potential of the gate G of the driving transistor Td. The gate of the driving transistor Td leaks and the potential decreases. When the adjustment signal EM1(n) jumps from the second potential to the first potential, the potential of the double gate node P of the second transistor T2 is greater than the initial potential of the gate G of the driving transistor Td. The gate potential of the driving transistor Td increases. In this way, it can be ensured that the gate potential of the driving transistor Td is basically maintained at the initial value under long-term display.

[0104] See also Figure 7 , Figure 7 This is a fourth circuit diagram of a pixel circuit provided by the present application. Figure 5 The difference of the pixel circuit 10 shown is that, in this embodiment, one end of the coupling capacitor Cst is connected to the double gate node E of the third transistor T3. The other end of the coupling capacitor Cst is connected to the adjustment signal EM1(n).

[0105] Furthermore, one end of the second capacitor Cst3 is connected to the double gate node P of the second transistor T2, and the other end of the second capacitor Cst3 is connected to the first initial signal V1.

[0106] In the embodiment of the present application, by connecting one end of the coupling capacitor Cst to the double gate node E of the third transistor T3, the leakage of the gate G of the driving transistor Td through the third transistor T3 can be reduced. In addition, by setting the second capacitor Cst3 to be connected to the double gate node Q of the second transistor T2, the potential of the double gate node Q of the second transistor T2 can be clamped, and the leakage at the gate G of the driving transistor Td can be further reduced.

[0107] The driving timing of the pixel circuit 10 in this embodiment is similar to Figure 5 The driving timing of the pixel circuit 10 is the same as that of the pixel circuit 10, and the details can be referred to the above content, which will not be repeated here.

[0108] See also Figure 8 , Figure 8 This is a fifth circuit diagram of the pixel circuit provided by the present application. Figure 1 The difference of the pixel circuit 10 shown is that, in this embodiment, the coupling capacitor Cst1 is a variable capacitor.

[0109] Specifically, the constant capacitor is usually a parallel plate capacitor. The variable capacitor is evolved from the transistor. Figure 8 As shown, the gate of the transistor is connected to the adjustment signal EM1(n), and the source and drain of the transistor are short-circuited together and connected to the first node Q. The source and drain of the transistor are made of semiconductor material. When the gate potential is changed, the capacitance will change due to the difference in the accumulation of hole carriers at the semiconductor interface.

[0110] In the embodiment of the present application, the coupling capacitor Cst1 is set as a variable capacitor evolved from a transistor, which can be formed by the same process together with other transistors in the pixel circuit 10. In addition, since the capacitance will change when the potential of the adjustment signal EM1(n) is changed, the coupling effect is superimposed, and the potential of the first node Q can be better pulled up or down.

[0111] In an embodiment of the present application, the first scan signal S1(n), the third scan signal S1(n-1) and the fifth scan signal S1(n+1) are generated by a group of GOA (Gate Driver on Array, array substrate gate drive technology) circuits. The second scan signal S2(n) and the fourth scan signal S2(n-1) are generated by a group of GOA circuits. The first scan signal Scan1(n) and the second scan signal Scan2(n) can be generated by two groups of GOA or one group of GOA circuits. Among them, the GOA circuit is a technology well known to those skilled in the art and will not be described in detail here.

[0112] In an embodiment of the present application, when driven at a low frequency, the second scanning signal S2(n) and the fourth scanning signal S2(n-1) are set to corresponding low-frequency scanning, such as 60 Hz. The first scanning signal S1(n), the third scanning signal S1(n-1) and the fifth scanning signal S1(n+1) maintain high-frequency scanning, such as 120 Hz. The data signal Da is designed to be a high-potential signal in the vertical blank period interval, and one of the source and drain of the driving transistor Td can be connected to the bias signal at a high frequency. This reduces the threshold voltage offset of the driving transistor Td when it is in a bias state for a long time at a low frequency, further improving the display quality.

[0113] In addition, the light control signal EM(n) and the adjustment signal EM1(n) are each generated by a set of GOA circuits. Within one frame time, the first potential and the second potential of the adjustment signal EM1(n) can be set arbitrarily according to the actual application. The light control signal EM(n) is a high-frequency signal, and performs high-low level conversion within one frame time. Among them, the light control signal EM(n) is at a high level for a very short time, and only a brief black insertion is performed.

[0114] See also Fig. 9 , Fig. 9 The present invention also provides a display panel 100, comprising a plurality of pixel units 11 arranged in an array, each pixel unit 11 comprising the above-mentioned pixel circuit 10, and the above description of the pixel circuit 10 may be referred to for details, which will not be repeated here.

[0115] In the embodiment of the present application, the display panel 100 may be an AMOLED (Active-Matrix Organic Light-Emitting Diode) display panel.

[0116] For details, please refer to Fig.10 , Fig.10 A schematic diagram of the brightness change of the display panel provided in the present application. The dotted line C represents the target brightness of the display panel 100 within a frame display cycle. Curve A represents the change trend of the brightness of the display panel 100 within a frame display cycle when the first initialization module is set to be connected to the gate of the driving transistor in the prior art. Curve B represents the change trend of the brightness of the display panel 100 in the embodiment of the present application within a frame display cycle.

[0117] Depend on Fig.10It can be seen that within a frame display cycle, the brightness change of the display panel 100 in the prior art is ΔL', which is relatively large. Within a frame display cycle, the brightness change of the display panel 100 of the present application fluctuates around the target brightness. Under low-frequency driving, the luminous time is longer, and the display of the display panel 100 within a frame display cycle is more uniform.

[0118] In the display panel 100 provided in the present application, a new pixel circuit 10 is designed, a coupling capacitor is added to the pixel circuit 10, and in the light-emitting stage, the time occupied by the first potential and the second potential of the adjustment signal is adjusted to ensure that the gate potential of the driving transistor is basically maintained at the initial value under long-term display. Therefore, when driving at a low frequency, the potential stability of the gate of the driving transistor is improved, flicker is reduced, and the display quality is improved.

[0119] The above is a detailed introduction to a pixel circuit and a display panel provided in an embodiment of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for technical personnel in this field, according to the idea of ​​the present application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A pixel circuit, characterized in that: include: A light emitting device, one end of which is connected to a first power signal, and the other end of which is connected to a second power signal; a data signal writing module, the data signal writing module receiving the first scanning signal and the data signal and outputting the data signal in response to the first scanning signal; A driving transistor, one of a source and a drain of the driving transistor is connected to the data signal writing module; A threshold voltage compensation module, the threshold voltage compensation module is connected to the second scanning signal and the first power supply signal, and is connected to the other of the source and the drain of the driving transistor and the gate of the driving transistor; A first initialization module, the first initialization module receives a control signal and a first initialization signal, and is connected to the gate of the driving transistor; A light-emitting control module, which receives a light-emitting control signal and is connected in series between the first power signal and the second power signal; as well as A coupling capacitor, one end of which is connected to the adjustment signal, and the other end of which is connected to the first initialization module or the threshold voltage compensation module; The threshold voltage compensation module includes a second transistor, a seventh transistor and a first capacitor; Among them, the gate of the second transistor is connected to the second scanning signal, one of the source and the drain of the second transistor and one end of the first capacitor are connected to the gate of the driving transistor, the other of the source and the drain of the second transistor and one of the source and the drain of the seventh transistor are connected to the first node, the other of the source or the drain of the seventh transistor is connected to the other of the source and the drain of the driving transistor, the gate of the seventh transistor is connected to the first scanning signal, and the other end of the first capacitor is connected to the first power supply signal.

2. The pixel circuit according to claim 1, characterized in that: One end of the coupling capacitor is connected to the first node, and the other end of the coupling capacitor is connected to the adjustment signal.

3. The pixel circuit according to claim 1, characterized in that: The second transistor is a dual-gate transistor, and the first gate and the second gate of the second transistor are both connected to the second scanning signal; one end of the coupling capacitor is connected to the dual-gate node of the second transistor, and the other end of the coupling capacitor is connected to the adjustment signal.

4. The pixel circuit according to claim 1 or 2, characterized in that: The first initialization module includes a third transistor, a gate of the third transistor is connected to the control signal, one of a source and a drain of the third transistor is connected to the first initialization signal, and the other of the source and the drain of the third transistor is connected to the first node.

5. The pixel circuit according to claim 1, characterized in that: The threshold voltage compensation module includes a second transistor and a first capacitor; Among them, the gate of the second transistor is connected to the second scanning signal, one of the source and the drain of the second transistor and one end of the first capacitor are connected to the gate of the driving transistor, the other of the source and the drain of the second transistor is connected to the other of the source and the drain of the driving transistor, and the other end of the first capacitor is connected to the first power supply signal.

6. The pixel circuit according to claim 5, characterized in that: The second transistor is a dual-gate transistor, and the first gate and the second gate of the second transistor are both connected to the second scanning signal; one end of the coupling capacitor is connected to the dual-gate node of the second transistor, and the other end of the coupling capacitor is connected to the adjustment signal.

7. The pixel circuit according to claim 6, characterized in that: The first initialization module includes a third transistor, a gate of the third transistor is connected to a control signal, one of a source and a drain of the third transistor is connected to the first initialization signal, and the other of the source and the drain of the third transistor is connected to the gate of the driving transistor; The third transistor is a dual-gate transistor, and the pixel circuit further includes a second capacitor, one end of the second capacitor is connected to the dual-gate node of the third transistor, and the other end of the second capacitor is connected to the first initial signal.

8. The pixel circuit according to claim 5, characterized in that: The first initialization module includes a third transistor, a gate of the third transistor is connected to the control signal, one of a source and a drain of the third transistor is connected to the first initialization signal, and the other of the source and the drain of the third transistor is connected to the gate of the driving transistor; The third transistor is a dual-gate transistor, one end of the coupling capacitor is connected to the dual-gate node of the third transistor, and the other end of the coupling capacitor is connected to the adjustment signal.

9. The pixel circuit according to claim 8, characterized in that: The second transistor is a dual-gate transistor, and both the first gate and the second gate of the second transistor are connected to the second scanning signal; The pixel circuit further includes a second capacitor, one end of the second capacitor is connected to the dual gate node of the second transistor, and the other end of the second capacitor is connected to the first initial signal.

10. The pixel circuit according to claim 1, characterized in that: The pixel circuit further includes a second initialization module, wherein the second initialization module includes a sixth transistor; The gate of the sixth transistor is connected to the first scanning signal, one of the source and the drain of the sixth transistor is connected to the other of the source and the drain of the driving transistor, and the other of the source and the drain of the sixth transistor is connected to the second initial signal.

11. The pixel circuit according to claim 1, characterized in that: The light emitting control module comprises a first light emitting control unit and a second light emitting control unit, wherein the first light emitting control unit comprises a fourth transistor; and the second light emitting control unit comprises a fifth transistor; The gate of the fourth transistor and the gate of the fifth transistor are both connected to the light-emitting control signal, one of the source and the drain of the fourth transistor is connected to the first power supply signal, and the other of the source and the drain of the fourth transistor is connected to one of the source and the drain of the driving transistor; one of the source and the drain of the fifth transistor is connected to the first electrode of the light-emitting device, and the other of the source and the drain of the fifth transistor is connected to the other of the source and the drain of the driving transistor.

12. The pixel circuit according to claim 1, characterized in that: The coupling capacitor is a variable capacitor.

13. A display panel, characterized in that: The display panel comprises a plurality of pixel units arranged in an array, and each of the pixel units comprises the pixel circuit according to any one of claims 1 to 12.

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