Topcon solar cell, preparation method thereof, battery pack and photovoltaic system
By introducing a nanocrystalline silicon layer on the back of the TOPCon solar cell, the problem of p-atom diffusion in the n-type doped polycrystalline silicon layer is solved, thereby improving the performance and efficiency of the cell.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- ZHEJIANG AIKO SOLAR ENERGY TECH CO LTD
- Filing Date
- 2022-06-23
- Publication Date
- 2026-07-03
Smart Images
Figure CN115101604B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of solar cell technology, and in particular to a TOPCon solar cell, its preparation method, cell module, and photovoltaic system. Background Technology
[0002] Currently, TOPCon solar cells (tunneling oxide passivated contact solar cells) typically use n-type silicon wafers. Their back-side structure usually consists of a silicon oxide layer as a tunneling layer, followed by an n-type doped polycrystalline silicon layer (n+Poly-Si layer), with an Ag metal electrode layer on the outermost layer. The silicon oxide tunneling layer prevents direct contact between the semiconductor and the metal electrode, reducing recombination at the cell surface and minimizing electron collection losses. The n+Poly-Si undergoes high-temperature crystallization, causing band bending on the silicon wafer surface, blocking minority carriers, promoting majority carrier tunneling, and achieving carrier separation at the interface. This entire structure constitutes a passivated contact for selective carrier collection. However, in related technologies, during fabrication, p atoms in the n+Poly-Si layer can diffuse into the silicon wafer because the silicon oxide layer, acting as a tunneling layer, cannot completely block them, leading to increased defects and open-circuit voltage loss. Summary of the Invention
[0003] This invention provides a TOPCon solar cell and its preparation method, cell module and photovoltaic system, aiming to solve the technical problem in the prior art that p atoms in the n-type doped polycrystalline silicon layer of TOPCon solar cells diffuse into the silicon wafer because the silicon oxide layer, which serves as a tunneling layer, cannot completely block them, leading to increased defects and loss of open-circuit voltage.
[0004] The present invention is implemented as follows: the TOPCon solar cell in the embodiment of the present invention includes a silicon wafer and a first silicon oxide layer, a nanocrystalline silicon layer, a second silicon oxide layer, an n-type doped polycrystalline silicon layer and a back metal electrode sequentially stacked on the back of the silicon wafer. The back metal electrode is in conductive contact with the n-type doped polycrystalline silicon layer. The nanocrystalline silicon layer is used to prevent phosphorus atoms in the n-type doped polycrystalline silicon layer from diffusing into the first silicon oxide layer and the silicon wafer.
[0005] Furthermore, the thickness of the nanocrystalline silicon layer is 3nm-7nm.
[0006] Furthermore, the thickness of the first silicon oxide layer is 0.5nm-1.5nm.
[0007] Furthermore, the thickness of the second silicon oxide layer is 0.5nm-1.5nm.
[0008] Furthermore, the front side of the silicon wafer is sequentially provided with a p-type doped polycrystalline silicon layer, a passivation layer, an anti-reflection layer, and a front metal electrode, wherein the front metal electrode penetrates the anti-reflection layer and the passivation layer and makes conductive contact with the p-type doped polycrystalline silicon layer.
[0009] This invention also provides a method for preparing a TOPCon solar cell, the method comprising:
[0010] Texturing of silicon wafers;
[0011] A first silicon oxide layer is prepared on the back side of the silicon wafer;
[0012] A nanocrystalline silicon layer is prepared on the first silicon oxide layer;
[0013] A second silicon oxide layer is prepared on the nanocrystalline silicon layer;
[0014] An n-type doped polycrystalline silicon layer is prepared on the second silicon oxide layer;
[0015] A back metal electrode is fabricated on the n-type doped polysilicon layer, and the back metal electrode is in conductive contact with the n-type doped polysilicon layer.
[0016] Furthermore, the step of preparing a nanocrystalline silicon layer on the first silicon oxide layer includes:
[0017] A hydrogenated amorphous silicon layer is deposited on the first silicon oxide layer;
[0018] The silicon wafer is subjected to high-temperature annealing to convert the hydrogenated amorphous silicon layer into the nanocrystalline silicon layer.
[0019] Furthermore, the silicon wafer is subjected to high-temperature annealing at a temperature of 900℃-950℃.
[0020] Furthermore, after the step of texturing the silicon wafer and before the step of preparing a first silicon oxide layer on the back side of the silicon wafer, the preparation method further includes:
[0021] A p-type doped polycrystalline silicon layer is deposited on the front side of the silicon wafer;
[0022] After the step of preparing an n-type doped polycrystalline silicon layer on the second silicon oxide layer, the preparation method further includes:
[0023] A passivation layer and an antireflection layer are sequentially deposited on the front side of the silicon wafer;
[0024] A front metal electrode is formed on the front side of the silicon wafer, the front metal electrode penetrating the passivation layer and the antireflection layer to make conductive contact with the p-type doped polysilicon layer.
[0025] The present invention also provides a battery assembly comprising a plurality of TOPCon solar cells as described in the embodiments of the present invention.
[0026] The present invention also provides a photovoltaic system comprising the above-described battery module.
[0027] The beneficial effects achieved by this invention are:
[0028] By providing a nanocrystalline silicon layer between the two silicon oxide layers on the back side, the nanocrystalline silicon layer can effectively block phosphorus atoms in the n-type doped polycrystalline silicon layer to prevent p atoms from diffusing into the first silicon oxide layer and the silicon wafer. This solves the technical problem in the prior art where p atoms in the n-type doped polycrystalline silicon layer of TOPCon solar cells diffuse into the silicon wafer because the silicon oxide layer, which is a tunneling layer, cannot completely block them, leading to increased defects and loss of open-circuit voltage.
[0029] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description
[0030] Figure 1 This is a schematic diagram of the photovoltaic system provided by the present invention;
[0031] Figure 2 This is a schematic diagram of the battery assembly provided by the present invention;
[0032] Figure 3 This is a schematic diagram of the structure of the TOPCon solar cell provided by the present invention;
[0033] Figure 4 This is a schematic flowchart of the method for preparing TOPCon solar cells provided by the present invention;
[0034] Figure 5 This is another schematic diagram of the process for preparing TOPCon solar cells provided by the present invention;
[0035] Figure 6 This is another schematic diagram of the process for preparing the TOPCon solar cell provided by the present invention.
[0036] Explanation of key component symbols:
[0037] Photovoltaic system 1000, battery module 200, TOPCon solar cell 100, silicon wafer 10, first silicon oxide layer 20, nanocrystalline silicon layer 30, second silicon oxide layer, n-type doped polycrystalline silicon layer 50, back metal electrode 60, p-type doped polycrystalline silicon layer 70, passivation layer 80, anti-reflection layer 90, front metal electrode 110. Detailed Implementation
[0038] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the invention, and should not be construed as limiting the invention. Furthermore, it should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
[0039] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," etc., indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of the stated features. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.
[0040] The following disclosure provides numerous different embodiments or examples for implementing various structures of the invention. To simplify the disclosure, specific examples of components and arrangements are described below. These are merely examples and are not intended to limit the invention. Furthermore, reference numerals and / or letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or arrangements discussed. In addition, examples of various specific processes and materials are provided in this invention, but those skilled in the art will recognize the application of other processes and / or the use of other materials.
[0041] In related technologies, during the fabrication of TOPcon solar cells, p atoms in the n-type doped polycrystalline silicon layer (i.e., n+Poly-Si layer) diffuse into the silicon wafer because the silicon oxide layer, which serves as a tunneling layer, cannot completely block them, leading to increased defects and loss of open-circuit voltage.
[0042] In this invention, a nanocrystalline silicon layer is provided between the two silicon oxide layers on the back side. The nanocrystalline silicon layer can effectively block phosphorus atoms in the n-type doped polycrystalline silicon layer 50 to prevent p atoms from diffusing into the first silicon oxide layer 20 and the silicon wafer 10. This solves the technical problem in the prior art that p atoms in the n-type doped polycrystalline silicon layer of TOPCon solar cells will diffuse into the silicon wafer due to the inability of the silicon oxide layer, which is a tunneling layer, to completely block them, resulting in increased defects and loss of open-circuit voltage.
[0043] Example 1
[0044] Please see Figure 1 and Figure 2 The photovoltaic system 1000 of the present invention may include the battery module 200 in the embodiments of the present invention, and the battery module 200 in the embodiments of the present invention may include a plurality of TOPCon solar cells 100 in the embodiments of the present invention.
[0045] Please see Figure 3 The TOPCon solar cell 100 (tunneling oxide passivated contact solar cell) in this embodiment of the invention includes a silicon wafer 10 and a first silicon oxide layer 20, a nanocrystalline silicon layer 30, a second silicon oxide layer 40, an n-type doped polycrystalline silicon layer 50, and a back metal electrode 60 sequentially stacked on the back side of the silicon wafer 10. The back metal electrode 60 is in conductive contact with the n-type doped polycrystalline silicon layer 50. The nanocrystalline silicon layer 30 is used to block phosphorus atoms in the n-type doped polycrystalline silicon layer 50 from diffusing into the first silicon oxide layer 20 and the silicon wafer 10.
[0046] In the TOPCon solar cell 100, cell module 200, and photovoltaic system 1000 of this embodiment, the nanocrystalline silicon layer 30 is used to block phosphorus atoms in the n-type doped polycrystalline silicon layer 50 from diffusing into the silicon oxide layer and the silicon wafer 10. Thus, a nanocrystalline silicon layer 30 is provided between the two silicon oxide layers on the back side. The nanocrystalline silicon layer 30 can effectively block phosphorus atoms in the n-type doped polycrystalline silicon layer 50 to prevent phosphorus atoms from diffusing into the first silicon oxide layer 20 and the silicon wafer 10, thereby avoiding increased defects and loss of open-circuit voltage.
[0047] Specifically, in this embodiment of the invention, the silicon wafer 10 can be an n-type silicon wafer 10, the n-type doped polycrystalline silicon layer 50 is a phosphorus (p) doped polycrystalline silicon layer, and the back metal electrode 60 can be an aluminum electrode. The back metal electrode 60 can be a metal backplate that completely covers the n-type doped polycrystalline silicon layer 50, or it can be composed of multiple spaced electrodes. Multiple TOPCon solar cells 100 in the battery module 200 can be connected in series or in parallel to form a battery string, thereby achieving series or parallel current output. For example, the battery cells can be connected in series by using solder strips.
[0048] It is understood that, in embodiments of the present invention, the battery assembly 200 may further include a metal frame, a backsheet, photovoltaic glass, and an encapsulant film (not shown). The encapsulant film may be attached to the front and back of the solar cell, and may be a transparent colloid with good light transmittance and aging resistance. For example, the encapsulant film may be an EVA film or a POE film, and the specific choice may be made according to the actual situation, without limitation.
[0049] Photovoltaic glass can be applied to the encapsulating film on the front of solar cells. This photovoltaic glass can be ultra-clear glass, possessing high light transmittance, high transparency, and superior physical, mechanical, and optical properties. For example, ultra-clear glass can achieve a light transmittance of over 80%, protecting the solar cells while minimizing impact on their efficiency. Simultaneously, the encapsulating film bonds the photovoltaic glass and the solar cells together, providing sealing, insulation, and waterproofing / moisture protection for the solar cells.
[0050] The backsheet can be attached to the adhesive film on the back of the solar cell. The backsheet protects and supports the solar cell, providing reliable insulation, water resistance, and aging resistance. Multiple backsheet options are available, typically including tempered glass, acrylic glass, aluminum alloy TPT composite film, etc., and the specific choice depends on the specific circumstances and is not limited here. The backsheet, solar cell, adhesive film, and photovoltaic glass together form a unit mounted on a metal frame. The metal frame serves as the main external support structure for the entire battery module 200, providing stable support and installation for the module. For example, the battery module 200 can be installed at the desired location using the metal frame.
[0051] Furthermore, in this invention, the photovoltaic system 1000 can be applied to photovoltaic power plants, such as ground-mounted power plants, rooftop power plants, and floating power plants. It can also be applied to equipment or devices that utilize solar energy for power generation, such as user solar power supplies, solar streetlights, solar cars, and solar buildings. Of course, it is understood that the application scenarios of the photovoltaic system 1000 are not limited to these; that is, the photovoltaic system 1000 can be applied in all fields that require solar energy for power generation. Taking a photovoltaic power generation system grid as an example, the photovoltaic system 1000 may include a photovoltaic array, a combiner box, and an inverter. The photovoltaic array may be an array combination of multiple battery modules 200. For example, multiple battery modules 200 can form multiple photovoltaic arrays. The photovoltaic array is connected to the combiner box, which can collect the current generated by the photovoltaic array. The collected current flows through the inverter and is converted into AC power required by the mains power grid before being connected to the mains power grid to achieve solar power supply.
[0052] In an embodiment of the present invention, the nanocrystalline silicon layer can be formed by first depositing a hydrogenated amorphous silicon layer and then crystallizing it by high-temperature annealing.
[0053] Please see Figure 3 Furthermore, in some embodiments, the thickness of the nanocrystalline silicon layer 30 may be 3nm-7nm.
[0054] Thus, setting the thickness of the nanocrystalline silicon layer 30 in the range of 3nm-7nm can effectively block the diffusion of phosphorus atoms. It can also avoid the nanocrystalline silicon layer 30 being too thin, which would lead to uneven deposition and some local areas (such as local holes) not having the nanocrystalline silicon layer 30 and thus failing to block the diffusion of p atoms. At the same time, it can also avoid the nanocrystalline silicon layer 30 being too thick, which would increase costs and affect the tunneling efficiency.
[0055] Specifically, in this invention, the thickness of the nanocrystalline silicon layer 30 can be 3nm, 4nm, 5nm, 6nm, 7nm, or any value between 3nm and 7nm. The preferred thickness of the nanocrystalline silicon layer 30 is 5nm, but this is not specifically limited. It should be noted that in this invention, the nanocrystalline silicon layer 30 has the function of minority carrier passage; that is, after minority carriers tunnel through the first silicon oxide layer 20, they can smoothly pass through the nanocrystalline silicon layer 30 and the second silicon oxide layer 40.
[0056] Implementation 2
[0057] Please see Figure 3 In this invention, the thickness of the first silicon oxide layer 20 can be 0.5nm-1.5nm.
[0058] Thus, setting the thickness of the first silicon oxide layer 20 in the range of 0.5nm-1.5nm can avoid the first silicon oxide layer 20 being too thin, which would result in more local pores and thus increase the leakage current. At the same time, it can also avoid the tunneling efficiency being reduced due to excessive thickness.
[0059] Specifically, in this invention, the first silicon oxide layer 20 can be formed on the back side of the silicon wafer 10 by deposition. For example, the first silicon oxide layer 20 can be deposited on the back side of the silicon wafer 10 using LPCVD (low-pressure chemical vapor deposition) or PECVD (plasma-enhanced chemical vapor deposition). The thickness of the first silicon oxide layer 20 can be 0.5 nm, 1 nm, 1.5 nm, or any value between 0.5 nm and 1.5 nm. The thickness of the first silicon oxide layer 20 is preferably 1 nm, but no specific limitation is made here.
[0060] Furthermore, in some embodiments, the thickness of the second silicon oxide layer 40 may also be 0.5nm-1.5nm.
[0061] Thus, setting the thickness of the second silicon oxide layer 40 within the range of 0.5nm-1.5nm avoids unevenness during fabrication due to an excessively thin layer, while also preventing reduced tunneling efficiency and increased costs due to an excessively thick layer. Simultaneously, the presence of the second silicon oxide layer 40 also protects the nanocrystalline silicon layer 30, ensuring its phosphorus atom blocking efficiency and preventing damage to the nanocrystalline silicon layer 30 during subsequent deposition of the n-type doped polycrystalline silicon layer 50.
[0062] Specifically, in this invention, the first silicon oxide layer 20 can be formed on the back side of the silicon wafer 10 by deposition. For example, the first silicon oxide layer 20 can be deposited on the back side of the silicon wafer 10 using LPCVD or PECVD. The nanocrystalline silicon layer 30 can be formed by first depositing a hydrogenated amorphous silicon layer using LPCVD or PECVD, and then converting it into a nanocrystalline silicon layer 30 by high-temperature annealing. In addition, the second silicon oxide layer 40 and the n-type doped polycrystalline silicon layer 50 can also be deposited using LPCVD or PECVD.
[0063] In this embodiment, similar to the first silicon oxide layer 20, the thickness of the second silicon oxide layer 40 can be any value between 0.5nm, 1nm, 1.5nm or 3nm-7nm. The thickness of the first silicon oxide layer 20 is preferably 1nm, but no specific limitation is made here.
[0064] Furthermore, in this invention, both the first silicon oxide layer 20 and the second silicon oxide layer 40 are tunneling layers, with an overall thickness between 1 nm and 3 nm. This ensures that the thickness of the entire tunneling layer on the back side of the silicon wafer 10 is neither too thin, leading to increased porosity and leakage, nor too thick, causing a significant decrease in tunneling efficiency. In other words, in this embodiment, the second silicon oxide layer 40 is positioned to protect the nanocrystalline silicon layer 30 while ensuring efficient blocking of phosphorus atoms, thus maintaining overall tunneling efficiency.
[0065] Furthermore, in some embodiments, the thickness of the n-type doped polysilicon layer 50 can be 100nm-120nm.
[0066] Thus, setting the thickness of the n-type doped polysilicon layer 50 in the range of 100nm-120nm can avoid the increase in manufacturing cost caused by excessive thickness and reduce the current loss caused by parasitic absorption of the n-type doped polysilicon layer 50. At the same time, it can also avoid the problem of poor uniformity caused by excessive thickness.
[0067] Example 3
[0068] Please continue reading. Figure 3In an embodiment of the present invention, the front side of the silicon wafer 10 may be provided with a p-type doped polysilicon layer 70, a passivation layer 80, an anti-reflection layer 90 and a front metal electrode 110 in sequence. The front metal electrode 110 penetrates the anti-reflection layer 90 and the passivation layer 80 and makes conductive contact with the diffusion layer.
[0069] Thus, the passivation layer 80 and the antireflection layer 90 can effectively passivate the front side of the silicon wafer 10 to improve the conversion efficiency of the solar cell, while also reducing the reflection of sunlight to improve efficiency.
[0070] Specifically, in this embodiment, the p-type doped polycrystalline silicon layer 70 can be a boron-doped polycrystalline silicon layer. It can be obtained by first depositing a polycrystalline silicon layer on the front side of the silicon wafer 10, and then performing boron diffusion on the front side of the silicon wafer 10; alternatively, it can be obtained by first depositing a p-type doped amorphous silicon layer on the front side of the silicon wafer 10, and then crystallizing it through high-temperature annealing; or it can be obtained by directly depositing a boron-doped polycrystalline silicon layer on the front side of the silicon wafer 10. No specific limitations are imposed here. The passivation layer 80 can be an aluminum oxide film layer, which can be prepared using ALD (atomic layer deposition) equipment. The antireflection layer 90 can be a silicon nitride film layer, which can be formed by LPCVD or PECVD deposition. The front metal electrode 110 can be a silver electrode.
[0071] Furthermore, in some embodiments, the thickness of the passivation layer 80 can be 1nm-30nm, preferably 2nm-6nm.
[0072] Thus, setting the thickness of the passivation layer 80 within the above range can ensure that the film layer has a good passivation effect while making the film layer more uniform, avoiding the phenomenon of unevenness caused by the film layer being too thin, and also avoiding the phenomenon of increased cost caused by the film layer being too thick, as well as avoiding the phenomenon that the front metal electrode 110 cannot burn through the film layer.
[0073] Furthermore, in some embodiments, the thickness of the antireflection layer 90 is 10nm-200nm.
[0074] Thus, setting the thickness of the antireflection layer 90 within the above range can ensure that the film has a low reflectivity while making the film preparation more uniform. It can also avoid the increased cost caused by an excessively thick film and the phenomenon that the front metal electrode 110 cannot be burned through.
[0075] Example 4
[0076] Please see Figure 3 and Figure 4 This embodiment provides a method for manufacturing a TOPCon solar cell 100. The TOPCon solar cell 100 of this invention can be manufactured by the manufacturing method described in this embodiment. The manufacturing method of this invention may include the following steps:
[0077] S10: Texturing silicon wafer 10;
[0078] S20: A first silicon oxide layer 20 is prepared on the back side of the silicon wafer 10;
[0079] S30: A nanocrystalline silicon layer 30 is prepared on the first silicon oxide layer 20;
[0080] S40: A second silicon oxide layer 40 is prepared on the nanocrystalline silicon layer 30;
[0081] S50: An n-type doped polycrystalline silicon layer 50 is prepared on the second silicon oxide layer 40;
[0082] S60: A back metal electrode 60 is fabricated on an n-type doped polysilicon layer 50, and the back metal electrode 60 is in conductive contact with the n-type doped polysilicon layer 50.
[0083] The TOPCon solar cell 100 manufactured by the method described in this embodiment of the invention includes a silicon wafer 10 and a first silicon oxide layer 20, a nanocrystalline silicon layer 30, a second silicon oxide layer 40, an n-type doped polycrystalline silicon layer 50, and a back metal electrode 60 sequentially stacked on the back side of the silicon wafer 10. The back metal electrode 60 is in conductive contact with the n-type doped polycrystalline silicon layer 50. The nanocrystalline silicon layer 30 is used to prevent phosphorus atoms in the n-type doped polycrystalline silicon layer 50 from diffusing into the first silicon oxide layer 20 and the silicon wafer 10. Thus, a nanocrystalline silicon layer 30 is provided between the two silicon oxide layers on the back side. The nanocrystalline silicon layer 30 can effectively block phosphorus atoms in the n-type doped polycrystalline silicon layer 50 to avoid phosphorus atoms diffusing into the first silicon oxide layer 20 and the silicon wafer 10, which would cause increased defects and loss of open-circuit voltage.
[0084] Specifically, in one possible embodiment, the silicon wafer 10 can be an n-type monocrystalline silicon wafer or an n-type polycrystalline silicon wafer with high resistivity. Before texturing, the silicon wafer 10 can be polished using an alkaline solution. In step S10, during texturing, the silicon wafer 10 can be immersed in an alkaline solution (e.g., KOH) to etch the front and back sides of the silicon wafer 10 to form a pyramidal textured surface. In steps S20 and S40, PECVD can be used to deposit the first silicon oxide layer 20. In step S50, LPCVD or PECVD can be used to directly deposit the n-type doped polycrystalline silicon. Alternatively, a polycrystalline silicon layer can be deposited first, followed by phosphorus diffusion, or n-type doped amorphous silicon can be deposited first, followed by high-temperature annealing to transform it into an n-type doped polycrystalline silicon layer 50. In step S60, aluminum paste can be used to directly form a back metal electrode 60 on the back side of the silicon wafer 10 through screen printing and high-temperature sintering.
[0085] Further, please refer to Figure 5In some embodiments, step S30 may include the following steps:
[0086] S31: Deposit a hydrogenated amorphous silicon layer on the first silicon oxide side;
[0087] S32: High-temperature annealing is performed on silicon wafer 10 to convert the hydrogenated amorphous silicon layer into a nanocrystalline silicon layer.
[0088] Thus, the method of first depositing a hydrogenated amorphous silicon layer and then converting it into a more stable nanocrystalline silicon layer through high-temperature degradation is relatively simple.
[0089] Specifically, in such embodiments, the hydrogenated amorphous silicon layer can be formed by LPCVD or PECVD deposition, and the high-temperature annealing temperature can be 900℃-950℃. This can avoid the hydrogenated amorphous silicon layer not being able to crystallize completely due to the temperature being too low, and can also avoid the waste of energy due to the temperature being too high, as well as the damage to the nanocrystalline silicon layer 30 due to the temperature being too high.
[0090] Furthermore, in some embodiments, after step S10 and before step S20, the preparation method may further include:
[0091] S70: A p-type doped polysilicon layer 70 is deposited on the front side of silicon wafer 10.
[0092] Thus, a p-type emitter can be formed by directly depositing a p-type doped polysilicon layer 70, which is relatively simple. At the same time, directly depositing the p-type doped polysilicon layer 70 can avoid the need for additional process steps to remove the plating and borosilicate glass that would occur during diffusion.
[0093] Specifically, in such an embodiment, a p-type doped polycrystalline silicon layer 70 doped with a boron source can be directly deposited using PECVD or LPCVD.
[0094] Furthermore, after step S50, the preparation method in this embodiment of the invention may further include:
[0095] S80: A passivation layer 80 and an anti-reflection layer are sequentially deposited on the front side of the silicon wafer 10;
[0096] S90: A front metal electrode 110 is formed on the front side of the silicon wafer 10. The front metal electrode 110 penetrates the passivation layer 80 and the anti-reflection layer to make conductive contact with the p-type doped polysilicon layer 70.
[0097] Specifically, in step S80, the passivation layer 80 can be an aluminum oxide film layer, which can be deposited by an ALD device, and the antireflection layer 90 can be a silicon nitride film layer, which can be deposited by PECVD or LPCVD.
[0098] It should be noted that in the illustrated example, step S80 is performed after step S50 and before step S60, and step S90 is performed before step S60. It is understood that in other embodiments, step S90 may also be performed after step S60 or steps S90 and S60 may be performed simultaneously. That is, the back metal electrode 60 and the front metal electrode 110 may be prepared simultaneously or one may be prepared first and then the other. The specific order is not limited here. In addition, the back metal electrode 60 may be formed by screen printing and sintering aluminum paste, and the front metal electrode 110 may be formed by screen printing and sintering silver paste.
[0099] In the description of this specification, references to terms such as "some embodiments," "illustrative embodiments," "examples," "specific examples," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with the described embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.
[0100] Furthermore, the above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.
Claims
1. A TOPCon solar cell, characterized in that, The device includes a silicon wafer and a first silicon oxide layer, a nanocrystalline silicon layer, a second silicon oxide layer, an n-type doped polycrystalline silicon layer, and a back metal electrode sequentially stacked on the back side of the silicon wafer. The back metal electrode is in conductive contact with the n-type doped polycrystalline silicon layer. The nanocrystalline silicon layer is used to prevent phosphorus atoms in the n-type doped polycrystalline silicon layer from diffusing into the first silicon oxide layer and the silicon wafer. The thickness of the nanocrystalline silicon layer is 3nm-7nm.
2. The TOPCon solar cell according to claim 1, characterized in that, The thickness of the first silicon oxide layer is 0.5nm-1.5nm.
3. The TOPCon solar cell according to claim 1, characterized in that, The thickness of the second silicon oxide layer is 0.5nm-1.5nm.
4. The TOPCon solar cell according to claim 1, characterized in that, The front side of the silicon wafer is provided with a p-type doped polycrystalline silicon layer, a passivation layer, an anti-reflection layer and a front metal electrode in sequence. The front metal electrode penetrates the anti-reflection layer and the passivation layer and makes conductive contact with the p-type doped polycrystalline silicon layer.
5. A method for preparing a TOPCon solar cell, characterized in that, include: Texturing of silicon wafers; A first silicon oxide layer is prepared on the back side of the silicon wafer; A nanocrystalline silicon layer is prepared on the first silicon oxide layer; the thickness of the nanocrystalline silicon layer is 3nm-7nm. A second silicon oxide layer is prepared on the nanocrystalline silicon layer; An n-type doped polycrystalline silicon layer is prepared on the second silicon oxide layer; A back metal electrode is fabricated on the n-type doped polysilicon layer, and the back metal electrode is in conductive contact with the n-type doped polysilicon layer.
6. The method for preparing a TOPCon solar cell according to claim 5, characterized in that, The step of preparing a nanocrystalline silicon layer on the first silicon oxide layer includes: A hydrogenated amorphous silicon layer is deposited on the first silicon oxide layer; The silicon wafer is subjected to high-temperature annealing to convert the hydrogenated amorphous silicon layer into the nanocrystalline silicon layer.
7. The method for preparing a TOPCon solar cell according to claim 5, characterized in that, The silicon wafer is subjected to high-temperature annealing at a temperature of 900℃-950℃.
8. The method for preparing a TOPCon solar cell according to claim 5, characterized in that, After the step of texturing the silicon wafer and before the step of preparing a first silicon oxide layer on the back side of the silicon wafer, the preparation method further includes: A p-type doped polycrystalline silicon layer is deposited on the front side of the silicon wafer; After the step of preparing an n-type doped polycrystalline silicon layer on the second silicon oxide layer, the preparation method further includes: A passivation layer and an antireflection layer are sequentially deposited on the front side of the silicon wafer; A front metal electrode is formed on the front side of the silicon wafer, the front metal electrode penetrating the passivation layer and the antireflection layer to make conductive contact with the p-type doped polysilicon layer.
9. A battery assembly, characterized in that, Includes the TOPCon solar cell as described in any one of claims 1-4.
10. A photovoltaic system, characterized in that, Includes the battery assembly as described in claim 9.