Power supply system and leakage detection device thereof

Abstract

The present invention discloses a power supply system and a leakage detection device thereof, the device comprising an over-voltage and under-voltage detection circuit and a leakage detection circuit; the over-voltage and under-voltage detection circuit comprises a sampling circuit, a signal comparison circuit and an adjustable inverse time control circuit connected in sequence; the leakage detection circuit comprises a filtering circuit, an amplification processing circuit, a signal detection circuit and a delay circuit connected in sequence; the input end of the sampling circuit is connected to the power supply end of the power supply system; the output end of the adjustable inverse time control circuit is connected to the delay circuit; the input end of the filtering circuit is connected to a current transformer, and the current transformer is sleeved on the power supply end of the power supply system; the output end of the delay circuit is connected to an alarm module and / or a drive execution module. The present invention can monitor the leakage current size or overvoltage / undervoltage state in real time, and has an adaptive inverse time delay control function.

Description

Technical Field

[0001] The present invention belongs to the technical field of power supply protection, and in particular relates to a power supply system and a leakage detection device thereof. Background Art

[0002] 50 / 60Hz frequency AC power is widely used in industry, agriculture, transportation, national defense, enterprises, hospitals, schools and residents. In order to ensure the safety of life and property, leakage detection circuits or devices are required to be installed in AC power supply systems at all levels and in residents' household electricity supply, so as to effectively detect leakage or electric shock accidents, cut off the power supply in time, and prevent safety accidents from happening.

[0003] However, most of the leakage detection circuits or devices currently used do not have overvoltage or undervoltage detection functions, or the overvoltage and undervoltage sampling accuracy is insufficient, and the anti-interference ability is poor, which can easily cause system misjudgment. When overvoltage or undervoltage occurs in the AC power supply system of the power grid, it is very easy to cause damage to power supply facilities and loads, and even cause fires and personal life safety accidents due to the inability to detect it in time and accurately, which poses a huge safety hazard.

[0004] In addition, almost all leakage protectors or leakage detection devices drive the actuator to cut off the power supply through a fixed delay action time after detecting that the leakage current value reaches the leakage current threshold, and do not have the inverse time limit function of automatically adjusting the delay action time according to the action current value. For example, CN107658846A: can only realize the A-type leakage detection function, has a set fixed delay function but does not have an adaptive inverse time limit function and over- and under-voltage detection function; another example is CN101552160A: can only realize leakage detection and basic delay functions and drive the release device to cut off the load; another example is CN106159890A: can only realize the basic leakage detection function, does not have over- and under-voltage detection and does not have the inverse time limit function of automatically and intelligently adjusting the delay action time according to the action current value.

[0005] Therefore, when there is a sudden and abnormally large leakage current accident or abnormal fluctuation of the AC power supply voltage, it is impossible to accurately predict the fault and risk size, and take measures in advance to eliminate the hidden dangers in time, so that the leakage protector or leakage detection device cannot detect the fault leakage current in time or effectively and cut off the power supply, and there are certain safety hazards in the power supply facilities or loads. Summary of the invention

[0006] The object of the present invention is to provide a power supply system and a leakage detection device thereof, so as to solve the problems that the existing leakage detection device has no over-voltage or under-voltage detection function or has low over-voltage or under-voltage detection accuracy, and cannot adaptively adjust the delayed action time.

[0007] The present invention solves the above technical problems through the following technical solutions: a leakage detection device for a power supply system, comprising an over-voltage and under-voltage detection circuit and a leakage detection circuit; the over-voltage and under-voltage detection circuit comprises a sampling circuit, a signal comparison circuit and an adjustable inverse time control circuit connected in sequence; the leakage detection circuit comprises a filtering circuit, an amplification processing circuit, a signal detection circuit and a delay circuit connected in sequence;

[0008] The input end of the sampling circuit is connected to the power supply end of the power supply system; the output end of the adjustable inverse time control circuit is connected to the delay circuit; the input end of the filter circuit is connected to the current transformer, and the current transformer is sleeved on the power supply end of the power supply system; the output end of the delay circuit is connected to the alarm module and / or the drive execution module;

[0009] The adjustable inverse time control circuit controls the start of the delay device in the delay circuit according to the overvoltage signal and undervoltage signal collected by the sampling circuit, and at the same time, the leakage signal output by the signal detection circuit controls the start of the delay counter in the delay circuit, thereby realizing an intelligent adaptive inverse time delay control function.

[0010] Furthermore, the sampling circuit includes a rectifier circuit and a step-down voltage divider circuit connected to each other, the rectifier circuit is used to collect the industrial frequency voltage signal at the power supply end of the power supply system and rectify the industrial frequency voltage signal into a smooth DC high voltage signal, and the step-down voltage divider circuit is used to convert the DC high voltage signal into an overvoltage signal and an undervoltage signal.

[0011] Furthermore, the signal comparison circuit includes a first voltage comparator, a second voltage comparator, a first AD converter, a second AD converter and a logic circuit; the positive input terminal of the first voltage comparator is connected to the overvoltage output terminal of the sampling circuit, and the negative input terminal of the first voltage comparator is connected to the overvoltage reference signal V REF_OV The negative input terminal of the second voltage comparator is connected to the undervoltage output terminal of the sampling circuit, and the positive input terminal of the second voltage comparator is connected to the undervoltage reference signal V REF_UV Connection; the output end of the first voltage comparator is connected to the logic circuit through a first AD converter, and the output end of the second voltage comparator is connected to the logic circuit through a second AD converter.

[0012] Further, the logic circuit includes a first latch, a second latch and multiple first OR gates; the output end of the first AD converter is connected to the input end of the first latch, and the enable end of the first AD converter is connected to the enable end of the first latch; the output end of the second AD converter is connected to the input end of the second latch, and the enable end of the second AD converter is connected to the enable end of the second latch; the number of the first OR gates is the same as the number of output bits of the first latch and the second latch, and the i-th output bit of the first latch and the i-th output bit of the second latch are connected to the input end of the i-th first OR gate, where i=0,1,…,n, and n is the number of output bits of the first latch or the second latch.

[0013] Furthermore, the adjustable inverse time control circuit includes a current regulating circuit formed by connecting multiple current branches in parallel, a current limiting resistor RA, a charging capacitor CA and a third voltage comparator A3, one end of the current regulating circuit is connected to the positive input end of the third voltage comparator A3 and the positive electrode of the charging capacitor CA through the current limiting resistor RA, and the negative input end of the third voltage comparator A3 is connected to the reference voltage V REF Each of the current branches is composed of a MOS switch and a current source in series, and the number of the current branches is the same as the number of output bits of the logic circuit in the signal comparison circuit.

[0014] Furthermore, the current magnitudes of the current sources in the multiple current branches increase exponentially in sequence.

[0015] Further, the delay circuit includes a fourth voltage comparator, a fifth voltage comparator, a sixth voltage comparator, a seventh voltage comparator, a data selector, a first delay counter, a second delay counter, a third delay counter, a fourth delay counter, a clock oscillator, a delay device and a second OR gate; the positive input terminals of the fourth voltage comparator, the fifth voltage comparator, the sixth voltage comparator and the seventh voltage comparator are all connected to the output terminal of the signal detection circuit, and the negative input terminals of the fourth voltage comparator, the fifth voltage comparator, the sixth voltage comparator and the seventh voltage comparator are respectively connected to the reference voltage V REF1 , reference voltage V REF2 , reference voltage V REF3 and reference voltage V REF4The output ends of the fourth voltage comparator, the fifth voltage comparator, the sixth voltage comparator and the seventh voltage comparator are respectively connected to the input end of the data selector; the output end of the data selector is respectively connected to the first delay counter, the second delay counter, the third delay counter and the fourth delay counter; the clock oscillator is respectively connected to the first delay counter, the second delay counter, the third delay counter, the fourth delay counter and the delay device; the input end of the delay device is connected to the output end of the adjustable inverse time control circuit; the output ends of the first delay counter, the second delay counter, the third delay counter, the fourth delay counter and the delay device are respectively connected to the input end of the second OR gate.

[0016] Furthermore, V REF1 >V REF2 >V REF3 >V REF4 .

[0017] Preferably, the delay time of the first delay counter is less than the delay time of the second delay counter, less than the delay time of the third delay counter, and less than the delay time of the fourth delay counter.

[0018] Further, when the input of the first delay counter is at a high level, the first delay counter works, and after the delay time of the first delay counter ends, the alarm module and / or the driving execution module are controlled to act;

[0019] When the input of the first delay counter is at a low level and the input of the second delay counter is at a high level, the second delay counter works, and controls the alarm module and / or the drive execution module to act after the delay time of the second delay counter ends;

[0020] When the inputs of the first delay counter and the second delay counter are both at low levels and the input of the third delay counter is at a high level, the third delay counter works, and controls the alarm module and / or the drive execution module to act after the delay time of the third delay counter ends;

[0021] When the inputs of the first delay counter, the second delay counter and the third delay counter are all at low levels and the input of the fourth delay counter is at a high level, the fourth delay counter works, and controls the alarm module and / or the drive execution module to act after the delay time of the fourth delay counter ends;

[0022] When the inputs of the first delay counter, the second delay counter, the third delay counter and the fourth counter are all at low level, the first delay counter, the second delay counter, the third delay counter and the fourth counter do not work.

[0023] Based on the same inventive concept, the present invention also provides a power supply system, comprising the leakage detection device as described above.

[0024] Beneficial Effects

[0025] Compared with the prior art, the advantages of the present invention are:

[0026] The present invention provides a power supply system and a leakage detection device thereof, which integrates high-precision leakage detection and over-voltage / under-voltage detection functions, and can monitor the leakage current size or overvoltage / undervoltage status in real time; at the same time, the device has an intelligent adaptive inverse time delay control function, which can realize external adjustment of the delay time. When the rated leakage signal is reached or an effective over-voltage / undervoltage status is detected, the inverse time delay is intelligently and adaptively realized according to the leakage signal size or the over-voltage / undervoltage degree, and functions such as alarm, drive output to cut off power supply or load are realized, which is conducive to pre-elimination and processing, and eliminates the risk of power safety accidents, and further improves and strengthens the protective function of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the technical solution of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only one embodiment of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0028] Figure 1 is a structural block diagram of a leakage detection device in an embodiment of the present invention;

[0029] Figure 2 is a schematic diagram of a rectifier circuit in an embodiment of the present invention;

[0030] Figure 3 is a schematic diagram of a voltage-step-down and voltage-dividing circuit in an embodiment of the present invention;

[0031] Figure 4 is a schematic diagram of a signal comparison circuit in an embodiment of the present invention;

[0032] Figure 5 is a schematic diagram of a logic circuit in an embodiment of the present invention;

[0033] Figure 6 It is a schematic diagram of an adjustable inverse time control circuit in an embodiment of the present invention;

[0034] Figure 7 It is a schematic diagram of a delay circuit in an embodiment of the present invention. DETAILED DESCRIPTION

[0035] The following is a clear and complete description of the technical solutions in the present invention in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0036] The technical solution of the present application is described in detail with specific embodiments below. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described in detail in some embodiments.

[0037] like Figure 1 As shown, a leakage detection device for a power supply system provided by an embodiment of the present invention includes an over-voltage and under-voltage detection circuit and a leakage detection circuit; the over-voltage and under-voltage detection circuit includes a sampling circuit, a signal comparison circuit and an adjustable inverse time control circuit connected in sequence; the leakage detection circuit includes a filtering circuit, an amplification processing circuit, a signal detection circuit and a delay circuit connected in sequence; the input end of the sampling circuit is connected to the power supply end of the power supply system; the output end of the adjustable inverse time control circuit is connected to the delay circuit; the input end of the filtering circuit is connected to a current transformer, and the current transformer is set on the power supply end of the power supply system, that is, the current transformer is set on the neutral line and the live line of the power supply system. When leakage occurs, the vector sum of the current passing through the neutral line and the live line is not zero, and a corresponding current will be induced on the secondary coil, which is detected by the current transformer; the output end of the delay circuit is connected to an alarm module and / or a drive execution module. The alarm module includes an alarm drive circuit and an alarm, and the drive execution module includes a drive circuit and an actuator.

[0038] The sampling circuit includes a rectifier circuit and a step-down voltage divider circuit connected to each other. The rectifier circuit is used to collect the power frequency voltage signal at the power supply end of the power supply system and rectify the power frequency voltage signal into a smooth DC high voltage signal (180V~270V DC high voltage signal). Figure 2 As shown, the industrial frequency voltage signal is a conventional 220V / 50HZ AC signal; the DC high voltage signal is much larger than the weak current system, such as 12V or 5V DC supply voltage range, so it is necessary to step down the DC high voltage signal through a step-down voltage divider circuit to a weak current system, such as 5V voltage range, and set appropriate overvoltage detection points and undervoltage detection points on the step-down voltage divider circuit to generate overvoltage signals OVI and undervoltage signals UVI as output signals of the sampling circuit, and provide them to the signal comparison circuit as its input signal. The step-down voltage divider circuit is used to convert the DC high voltage signal into an overvoltage signal and an undervoltage signal, such as Figure 3As shown, an overvoltage detection point and an undervoltage detection point are provided on the step-down voltage divider circuit, and the undervoltage detection point and the overvoltage detection point are connected to the positive input terminal of the first voltage comparator A1 and the negative input terminal of the second voltage comparator A2 respectively.

[0039] like Figure 4 As shown, the signal comparison circuit includes a first voltage comparator A1, a second voltage comparator A2, a first AD converter, a second AD converter and a logic circuit; the positive input terminal of the first voltage comparator A1 is connected to the overvoltage output terminal (i.e., the overvoltage detection point) of the sampling circuit, and the negative input terminal of the first voltage comparator A1 is connected to the overvoltage reference signal V REF_OV The negative input terminal of the second voltage comparator A2 is connected to the undervoltage output terminal (ie, the undervoltage detection point) of the sampling circuit, and the positive input terminal of the second voltage comparator A2 is connected to the undervoltage reference signal V REF_UV The output end of the first voltage comparator A1 is connected to the logic circuit through the first AD converter, and the output end of the second voltage comparator A2 is connected to the logic circuit through the second AD converter. The overvoltage signal OVI (actually the voltage value of the overvoltage signal) output by the sampling circuit is greater than the overvoltage reference signal V REF_OV When the overvoltage signal OVI is higher than the undervoltage reference voltage (actually the overvoltage reference voltage), the first voltage comparator A1 outputs a high level, the first AD converter works and converts the overvoltage signal OVI into a first digital signal and inputs it into the logic circuit; the undervoltage signal UVI output by the sampling circuit is less than the undervoltage reference signal V REF_UV When , the second voltage comparator A2 outputs a high level, the second AD converter works and converts the undervoltage signal UVI into a second digital signal which is input into the logic circuit; in the logic circuit, the first digital signal and the second digital signal perform a logic operation to obtain a digital control signal.

[0040] When the enable terminal of the AD converter is at a low level, the AD converter does not work and has no output; when the enable terminal of the AD converter is at a high level, the AD converter works and outputs a digital signal.

[0041] In a specific embodiment of the present invention, Figure 5As shown, the logic circuit includes a first latch, a second latch and a plurality of first OR gates, the first digital signal (8-bit data INA0-INA7) output by the first AD converter is used as the input signal of the first latch (8 bits), and the enable signal of the first AD converter is used as the latch enable and output enable control signal of the first latch; when the first AD converter is enabled, the overvoltage signal is converted into a first digital signal and the first latch is enabled to latch and synchronously output the first digital signal input by the first AD converter; the second digital signal (8-bit data INB0-INB7) output by the second AD converter is used as the input signal of the second latch (8 bits), and the enable signal of the second AD converter is used as the latch enable and output enable control signal of the second latch; when the second AD converter is enabled, the undervoltage signal is converted into a second digital signal and the second latch is enabled to latch and synchronously output the second digital signal input by the second AD converter. The number of the first OR gates is the same as the number of output bits of the first latch and the second latch. The i-th output bit of the first latch and the i-th output bit of the second latch are connected to the input end of the i-th first OR gate, i=0,1,2,3,4,5,6,7 (the number of output bits in this embodiment is 8), and the corresponding output bits of the first latch and the second latch are output (D0-D7) after the OR logic operation and used as the switch control signal of the adjustable inverse time control circuit to control the charging current of the charging capacitor CA and realize the inverse time delay function. Exemplarily, the 0th output bit OUTA0 of the first latch and the 0th output bit OUTB0 of the second latch are output D0 after the first OR gate operation, and D0 is used as the control signal of MOS0 in the adjustable inverse time control circuit.

[0042] like Figure 6 As shown, the adjustable inverse time control circuit includes a current regulating circuit composed of 8 current branches connected in parallel, a current limiting resistor RA, a charging capacitor CA and a third voltage comparator A3. One end of the current regulating circuit is connected to the positive input end of the third voltage comparator A3 and the positive electrode of the charging capacitor CA through the current limiting resistor RA, and the negative input end of the third voltage comparator A3 is connected to the reference voltage V REF Each current branch has a MOS switch MOS i and a current source S i The currents of the eight current sources connected in series, i = 0, 1, 2, 3, 4, 5, 6, 7, increase in order (from left to right or from right to left) by exponential times of 2. For example, let the 0th current source S0 be I S (2 0 ) current source, then the first current source S1 is 2I S (2 1 ) current source, the second current source S2 is 4I S (2 2) current source, the third current source S3 is 8I S (2 3 ) current source, the fourth current source S4 is 16I S (2 4 ) current source, the fifth current source S5 is 32I S (2 5 ) current source, the sixth current source S6 is 64I S (2 6 ) current source, the seventh current source S7 is 128I S (2 7 ) current source of size; the opening and closing of 8 MOS switches (MOS0~MOS7) are controlled by the outputs D0-D7 of the logic circuit respectively (the gate of the MOS switch is connected to the output of the logic circuit).

[0043] When a certain output D of the logic circuit i When (D0-D7) is at a low level, the corresponding MOS switch is turned off, and the corresponding current source will not charge the charging capacitor CA through the current limiting resistor RA. i When (D0-D7) is at a high level, the corresponding MOS switch is closed, and the corresponding current source charges the charging capacitor CA with a constant current through the current limiting resistor RA. Each current branch works independently and does not affect each other. Therefore, the D0-D7 control signal jointly determines the size of the charging current of the charging capacitor CA through the current limiting resistor RA. The eight MOS switches (MOS0-MOS7) are respectively connected to the current limiting resistor RA, and the other end of RA is connected to the positive end of the charging capacitor CA. The negative end of the charging capacitor CA is grounded. The connection end of the current limiting resistor RA and the charging capacitor CA serves as the positive input end of the third voltage comparator A3, and is connected to the reference voltage value V of the negative input end of the third voltage comparator A3. REF The output terminal of the third voltage comparator A3 is connected to the input terminal of the delay circuit. When the positive terminal voltage of the charging capacitor CA is lower than the reference voltage V REF When the output terminal of the third voltage comparator A3 is low level, the delay device in the delay circuit does not start; when the positive terminal voltage value of the charging capacitor CA is higher than the reference voltage value V REF When the third voltage comparator A3 outputs a high level, the delay device in the delay circuit starts a fixed short delay operation. After the fixed short delay ends, the delay device outputs a signal to drive the alarm device to alarm and / or drive the actuator to act. Since the charging current of the charging capacitor CA is controlled by the opening and closing of the MOS switch controlled by D0-D7, the charging current determines the positive end of the charging capacitor CA is charged from 0V to a voltage higher than the reference voltage V REFtime, thus realizing the delay control function of the D0-D7 control adjustable inverse time control circuit. By controlling the charging current to control the delay circuit to adaptively set the delay time, since the output signal D0-D7 of the logic circuit is directly related to the overvoltage amplitude or undervoltage amplitude, the larger the overvoltage amplitude or undervoltage amplitude, the larger the charging current, and the charging reaches the reference voltage value V REF On the contrary, when the overvoltage amplitude is smaller or the undervoltage amplitude is smaller, the charging current is smaller and the charging reaches the reference voltage value V REF The longer the time is, the more intelligent adaptive inverse time function of the delay device in the delay circuit is realized.

[0044] like Figure 7 As shown, the delay circuit includes a fourth voltage comparator A4, a fifth voltage comparator A5, a sixth voltage comparator A6, a seventh voltage comparator A7, a data selector MUX, a first delay counter, a second delay counter, a third delay counter, a fourth delay counter, a clock oscillator, a delay device and a second OR gate; the positive input terminals of the fourth voltage comparator A4, the fifth voltage comparator A5, the sixth voltage comparator A6 and the seventh voltage comparator A7 are all connected to the output terminal of the signal detection circuit, and the negative input terminals of the fourth voltage comparator A4, the fifth voltage comparator A5, the sixth voltage comparator A6 and the seventh voltage comparator A7 are respectively connected to the corresponding reference voltage V REF1 ~V REF4 The output ends of the fourth voltage comparator A4, the fifth voltage comparator A5, the sixth voltage comparator A6, and the seventh voltage comparator A7 are respectively connected to the input end of the data selector MUX, and the output end of the data selector MUX is respectively connected to the first delay counter, the second delay counter, the third delay counter, and the fourth delay counter; the output ends of the first delay counter, the second delay counter, the third delay counter, the fourth delay counter, the clock oscillator, and the delay are respectively connected to the input end of the second OR gate.

[0045] The clock oscillator generates a reference clock for timing control and counting, and a delay clock reference; the delay device is used to control the start of the drive circuit and / or a fixed short delay circuit before the alarm after the over-voltage and under-voltage reverse time delay ends. The delay device is provided with a reference clock by the clock oscillator, and then realizes a short delay function after frequency division and counting; the first delay counter to the fourth delay counter are all based on the reference clock signal provided by the clock oscillator, and realize delay functions of different times through counting and frequency division. The delay time of the first delay counter is less than the delay time of the second delay counter, the delay time of the second delay counter is less than the delay time of the third delay counter, and the delay time of the third delay counter is less than the delay time of the fourth delay counter. The start enable terminals of the first delay counter to the fourth delay counter are respectively connected to the four output terminals of the data selector MUX, the output terminals of the fourth voltage comparator A4 to the seventh voltage comparator A7 are respectively connected to the four input terminals of the data selector MUX, the positive input terminals of the fourth voltage comparator A4 to the seventh voltage comparator A7 are respectively connected to the leakage signal output by the signal detection circuit, and the negative input terminals of the fourth voltage comparator A4 to the seventh voltage comparator A7 are respectively connected to the reference voltage V REF1 ~V REF4 , where V REF1 >V REF2 >V REF3 >V REF4 When the leakage signal at the positive input of the fourth voltage comparator A4 to the seventh voltage comparator A7 is less than the reference voltage at its negative input, the voltage comparator outputs a low level. When the leakage signal at the positive input of the fourth voltage comparator A4 to the seventh voltage comparator A7 is greater than the reference voltage at its negative input, the voltage comparator outputs a high level. Exemplarily, when the leakage signal at the positive input of the fourth voltage comparator A4 is less than the reference voltage V at its negative input, REF1 When the leakage signal at the positive input terminal of the fourth voltage comparator A4 is greater than the reference voltage V at its negative input terminal, the fourth voltage comparator A4 outputs a low level. REF1, the fourth voltage comparator A4 outputs a high level. The output signals of the fourth voltage comparator A4 to the seventh voltage comparator A7 are DLYA_en, DLYB_en, DLYC_en, and DLYD_en, respectively, and serve as the input signal of the data selector MUX. When DLYA_en is a high level, no matter what the levels of DLYB_en, DLYC_en, and DLYD_en are, the data selector MUX outputs an enable signal to control the operation of the first delay counter, and the delay count ends to enable the drive circuit and / or the alarm drive circuit to output, thereby causing the actuator to act and / or the alarm to sound an alarm; when DLYA_en is a low level, if DLYB_en is a high level, the data selector MUX outputs an enable signal to control the operation of the second delay counter, and the delay count ends to enable the drive circuit and / or the alarm drive circuit to output, thereby causing the actuator to act and / or the alarm to sound an alarm; when DLYA_en and DLYB_en are both low levels, if DLYC_en is a high level, the data selector The MUX output enable signal controls the operation of the third delay counter, and the output of the enable drive circuit and / or the alarm drive circuit is enabled when the delay count ends, thereby causing the actuator to operate and / or the alarm to alarm; when DLYA_en, DLYB_en, and DLYC_en are all low levels, if DLYD_en is high, the data selector MUX outputs an enable signal to control the operation of the fourth delay counter, and the output of the enable drive circuit and / or the alarm drive circuit is enabled when the delay count ends, thereby causing the actuator to operate and / or the alarm to alarm; when DLYA_en, DLYB_en, DLYC_en, and DLYD_en are all low levels, the data selector MUX outputs are all low levels, and the first delay counter to the fourth delay counter do not operate. Through the delay circuit, leakage detection can realize the inverse time limit function, and the larger the leakage signal, the shorter the delay time. The output of the delay device, the first delay counter, the second delay counter, the third delay counter and the fourth delay counter control the start of the alarm drive circuit and / or the drive circuit through the second OR gate operation. Any output of the delay device, the first delay counter, the second delay counter, the third delay counter and the fourth delay counter can trigger the second OR gate output, thereby controlling the start of the alarm drive circuit and / or the drive circuit and realizing the delayed action of the alarm device and / or the actuator.

[0046] When leakage signal, overvoltage or undervoltage is detected, the inverse time delay function may be triggered. When the inverse time delay timing ends, a high level is output as the input signal of the alarm drive circuit and / or drive circuit, triggering the alarm and / or the actuator to act, such as triggering the release to trip and cut off the load power supply to protect it from damage.

[0047] The current transformer collects the leakage signal, and the filter circuit is used to filter out the high-frequency interference signal in the leakage signal. The weak leakage signal provided by the filter circuit is then amplified by the amplification processing circuit; the signal detection circuit filters the amplified leakage signal to remove the high-frequency noise signal and other non-effective AC components other than the normal 50HZ AC signal, and performs rectification to flip the negative half-cycle signal of the AC leakage signal into a symmetrical positive half-cycle signal to achieve differential to single-ended output.

[0048] What is disclosed above is only a specific implementation mode of the present invention, but the protection scope of the present invention is not limited thereto. Any technician familiar with the technical field can easily think of changes or modifications within the technical scope disclosed in the present invention, which should be covered within the protection scope of the present invention.

Claims

1. A leakage detection device for a power supply system, characterized in that: It includes an over-voltage and under-voltage detection circuit and a leakage detection circuit; the over-voltage and under-voltage detection circuit includes a sampling circuit, a signal comparison circuit and an adjustable inverse time control circuit connected in sequence; the leakage detection circuit includes a filtering circuit, an amplification processing circuit, a signal detection circuit and a delay circuit connected in sequence; The input end of the sampling circuit is connected to the power supply end of the power supply system; the output end of the adjustable inverse time control circuit is connected to the delay circuit; the input end of the filter circuit is connected to the current transformer, and the current transformer is sleeved on the power supply end of the power supply system; the output end of the delay circuit is connected to the alarm module and / or the drive execution module; The adjustable inverse time control circuit controls the start of the delay device in the delay circuit according to the overvoltage signal or undervoltage signal collected by the sampling circuit, and controls the start of the delay counter in the delay circuit according to the leakage signal output by the signal detection circuit; The adjustable inverse time control circuit includes a current regulating circuit formed by connecting multiple current branches in parallel, a current limiting resistor, a charging capacitor and a third voltage comparator. One end of the current regulating circuit is connected to the positive input end of the third voltage comparator and the positive electrode of the charging capacitor through the current limiting resistor. The negative input end of the third voltage comparator is connected to the reference voltage V REF Each of the current branches is composed of a MOS switch and a current source connected in series, and the number of the current branches is the same as the number of output bits of the logic circuit in the signal comparison circuit; The delay circuit includes a fourth voltage comparator, a fifth voltage comparator, a sixth voltage comparator, a seventh voltage comparator, a data selector, a first delay counter, a second delay counter, a third delay counter, a fourth delay counter, a clock oscillator, a delay device and a second OR gate; the positive input terminals of the fourth voltage comparator, the fifth voltage comparator, the sixth voltage comparator and the seventh voltage comparator are all connected to the output terminal of the signal detection circuit, and the negative input terminals of the fourth voltage comparator, the fifth voltage comparator, the sixth voltage comparator and the seventh voltage comparator are respectively connected to the reference voltage V REF1 , reference voltage V REF2 , reference voltage V REF3 and reference voltage V REF4 The output ends of the fourth voltage comparator, the fifth voltage comparator, the sixth voltage comparator and the seventh voltage comparator are respectively connected to the input end of the data selector; the output end of the data selector is respectively connected to the first delay counter, the second delay counter, the third delay counter and the fourth delay counter; the clock oscillator is respectively connected to the first delay counter, the second delay counter, the third delay counter, the fourth delay counter and the delay device; the input end of the delay device is connected to the output end of the adjustable inverse time control circuit; the output ends of the first delay counter, the second delay counter, the third delay counter, the fourth delay counter and the delay device are respectively connected to the input end of the second OR gate.

2. The leakage detection device according to claim 1, characterized in that: The sampling circuit includes a rectifier circuit and a step-down voltage divider circuit connected to each other. The rectifier circuit is used to collect the power frequency voltage signal at the power supply end of the power supply system and rectify the power frequency voltage signal into a smooth DC high voltage signal. The step-down voltage divider circuit is used to convert the DC high voltage signal into an overvoltage signal and an undervoltage signal.

3. The leakage detection device according to claim 1, characterized in that: The signal comparison circuit includes a first voltage comparator, a second voltage comparator, a first AD converter, a second AD converter and a logic circuit; the positive input terminal of the first voltage comparator is connected to the overvoltage output terminal of the sampling circuit, and the negative input terminal of the first voltage comparator is connected to the overvoltage reference signal V REF_OV The negative input terminal of the second voltage comparator is connected to the undervoltage output terminal of the sampling circuit, and the positive input terminal of the second voltage comparator is connected to the undervoltage reference signal V REF_UV Connection; the output end of the first voltage comparator is connected to the logic circuit through a first AD converter, and the output end of the second voltage comparator is connected to the logic circuit through a second AD converter.

4. The leakage detection device according to claim 3, characterized in that: The logic circuit includes a first latch, a second latch and a plurality of first OR gates; the output end of the first AD converter is connected to the input end of the first latch, and the enable end of the first AD converter is connected to the enable end of the first latch; the output end of the second AD converter is connected to the input end of the second latch, and the enable end of the second AD converter is connected to the enable end of the second latch; the number of the first OR gates is the same as the number of output bits of the first latch and the second latch, and the first latch of the first latch is connected to the enable end of the second latch; i The first output bit and the second latch i The output bit is i The input terminals of the first OR gate are connected, where i =0,1,…, n , n is the number of output bits of the first latch or the second latch.

5. The leakage detection device according to claim 1, characterized in that: The current magnitudes of the current sources in the multiple current branches increase exponentially in sequence.

6. The leakage detection device according to claim 1, characterized in that: V REF1 >V REF2 >V REF3 >V REF4 。 7. The leakage detection device according to claim 1, characterized in that: The delay time of the first delay counter is less than the delay time of the second delay counter, less than the delay time of the third delay counter, and less than the delay time of the fourth delay counter.

8. The leakage detection device according to any one of claims 1 to 7, characterized in that: When the input of the first delay counter is at a high level, the first delay counter works, and controls the alarm module and / or the drive execution module to act after the delay time of the first delay counter ends; When the input of the first delay counter is at a low level and the input of the second delay counter is at a high level, the second delay counter works, and controls the alarm module and / or the drive execution module to act after the delay time of the second delay counter ends; When the inputs of the first delay counter and the second delay counter are both at low levels and the input of the third delay counter is at a high level, the third delay counter works, and controls the alarm module and / or the drive execution module to act after the delay time of the third delay counter ends; When the inputs of the first delay counter, the second delay counter and the third delay counter are all at low levels and the input of the fourth delay counter is at a high level, the fourth delay counter works, and controls the alarm module and / or the drive execution module to act after the delay time of the fourth delay counter ends; When the inputs of the first delay counter, the second delay counter, the third delay counter and the fourth counter are all at low level, the first delay counter, the second delay counter, the third delay counter and the fourth counter do not work.

9. A power supply system, characterized in that: The invention comprises the leakage detection device according to any one of claims 1 to 8.

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