Chip control circuits, systems and chips

Abstract

The embodiments of the present application provide a chip control circuit, system and chip, which relate to the field of semiconductor technology. The chip control circuit includes: a storage unit for receiving update data; a signal conversion unit, the input end of the signal conversion unit is signal-connected to the output end of the storage unit, the control end of the signal conversion unit is signal-connected to the control unit, and the signal conversion unit is used to convert the update data into a serial data stream; a signal selection unit, the input end of the signal selection unit is signal-connected to the output end of the signal conversion unit, the output end of the signal selection unit is used to connect to an input / output interface, and the signal selection unit is used to select target data from the serial data stream and send the target data to the input / output interface. The technical problem of the poor flexibility of the current SoC chip is solved, and the technical effect of improving the flexibility of the SoC chip is achieved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular, to a chip control circuit, system and chip. Background Art

[0002] The integration of SoC chips (System on Chip) is getting higher and higher, and the coordination and stability of various IPs inside the chip are also getting higher. For most IPs in SoC chips, from simple low-speed IPs such as UART, I2C, SPI to high-speed IPs such as DDR, PCIE, etc., a certain number of registers are defined inside the IP, and then these registers are configured and programmed by software to control the IP to enter different working modes or states, and finally generate the expected digital signals to meet the requirements of IP protocol transmission.

[0003] During the use of SoC chips, some software may update the hardware functions or put forward new requirements for the system application layer. However, at this time, the chip has been taped out and its pre-configured functions and IPs are fixed and can no longer be updated.

[0004] Therefore, the flexibility of current SoC chips is relatively poor. Summary of the invention

[0005] In order to solve the above technical problems, a chip control circuit, system and chip are provided in the embodiments of the present application.

[0006] A first aspect of an embodiment of the present application provides a chip control circuit, including:

[0007] A storage unit, used for receiving update data;

[0008] A signal conversion unit, wherein an input end of the signal conversion unit is signal-connected to an output end of the storage unit, a control end of the signal conversion unit is signal-connected to a control unit, and the signal conversion unit is used to convert the update data into a serial data stream;

[0009] A signal selection unit, wherein the input end of the signal selection unit is signal-connected to the output end of the signal conversion unit, the output end of the signal selection unit is used to connect to the input / output interface, and the signal selection unit is used to select target data from the serial data stream and send the target data to the input / output interface.

[0010] In an optional embodiment of the present application, the signal conversion unit includes:

[0011] Register body;

[0012] The signal generator based on direct memory access is arranged in the register body shown, the input end of the signal generator is connected to the output end of the storage unit, the control end of the signal generator is connected to the control unit, and the signal generator is used to convert the update data into a serial data stream.

[0013] In an optional embodiment of the present application, the signal selection unit includes:

[0014] A data interface, the input end of the data interface is signal-connected to the output end of the signal conversion unit;

[0015] A signal selector, wherein the control end of the signal selector is used to connect to the control unit shown, the input end of the signal selector is signal-connected to the output end of the data interface, the output end of the signal selector is signal-connected to the input / output interface, and the signal selector is used to determine target data from the serial data stream according to the control signal sent by the control unit, and send the target data to the input / output interface.

[0016] In an optional embodiment of the present application, the number of data interfaces is multiple.

[0017] In an optional embodiment of the present application, the storage unit includes multiple storage devices.

[0018] In an optional embodiment of the present application, the storage device is at least one of a random access memory, a double rate synchronous dynamic random access memory, and a register.

[0019] In an optional embodiment of the present application, the chip control circuit further includes:

[0020] A memory selector, wherein the input end of the memory selector is respectively connected to the signals of a plurality of memory devices, the output end of the memory selector is connected to the signal conversion unit signal, and the memory selector is used to select a target memory device that generates target data from the plurality of memory devices.

[0021] In an optional embodiment of the present application, the memory selector is a high-speed bus.

[0022] A second aspect of an embodiment of the present application provides a chip control system, including:

[0023] A chip control circuit as in any one of the above items;

[0024] The control unit has an output end connected to a control end signal of a signal conversion unit in a chip control circuit. The control unit is used to generate a control signal and control the signal conversion unit to convert the update data into a serial data stream based on the control signal.

[0025] According to a third aspect of the embodiments of the present application, a chip is provided, including:

[0026] substrate;

[0027] Chip control system as above;

[0028] The input / output interface is arranged on the substrate and is connected to the input terminal signal of the signal selection unit in the chip control system.

[0029] The chip control circuit is configured with a storage unit, a signal conversion unit, and a signal selection unit. When the internal signal of the SoC chip needs to be updated, the update data is written to the storage unit, and then the signal conversion unit can convert the update data into serial data. The signal selection unit selects the target data from the serial data stream and sends the target data to the input / output interface, thereby realizing interaction with other chips. Due to the programmability of the update data in the storage unit, that is, the SoC chip can flexibly update the update data in the storage unit 100, so that the SoC chip can output signal data in any format, so that the SoC chip can interact with any type of chip, thereby solving the technical problem of poor flexibility of the current SoC chip and achieving the technical effect of improving the flexibility of the SoC chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0031] Figure 1 It is a schematic diagram of the existing chip control circuit;

[0032] Figure 2 An overall schematic diagram of a chip control circuit and related devices provided in one embodiment of the present application;

[0033] Figure 3 An overall schematic diagram of a chip control circuit and related devices provided in one embodiment of the present application;

[0034] Figure 4 An overall schematic diagram of a chip control circuit and related devices provided in one embodiment of the present application;

[0035] Figure 5 An overall schematic diagram of a chip control circuit and related devices provided in one embodiment of the present application;

[0036] Figure 6 A circuit diagram of a chip control system provided by one embodiment of the present application;

[0037] Figure 7 A schematic diagram of a chip circuit provided for one embodiment of the present application.

[0038] In the figure:

[0039] 10. Chip control circuit; 100. Storage unit; 200. Signal conversion unit; 210. Register body; 220. Signal generator; 300. Signal selection unit; 310. Data interface; 320. Signal selector; 400. Memory selector; 20. Chip control system; 21. Control unit; 30. Chip; 31. Input / output interface. DETAILED DESCRIPTION

[0040] In order to make the purpose, technical solutions and advantages of the present application more clearly understood, the chip control circuit, system and chip of the present application are further described in detail below through embodiments and in combination with the accompanying drawings. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0041] The serial numbers assigned to the components herein, such as "first", "second", etc., are only used to distinguish the objects described and do not have any order or technical meaning. The "connection" and "coupling" mentioned in this application, unless otherwise specified, include direct and indirect connections (couplings). In the description of this application, it should be understood that the orientation or position relationship indicated by the terms "upper", "lower", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", etc. are based on the orientation or position relationship shown in the accompanying drawings, which is only for the convenience of describing this application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation to this application.

[0042] In the present application, unless otherwise clearly specified and limited, a first feature being “above” or “below” a second feature may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, a first feature being “above”, “above”, and “above” a second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. A first feature being “below”, “below”, and “below” a second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.

[0043] See also Figure 1At present, the internal control circuit of the SoC chip includes a processor 101, several IP registers 102, and an IO interface 103 (input / output interface) corresponding to each IP. Once the chip is taped out, the internal IP type is fixed, and the signal type for interacting with other chips is also fixed and cannot be changed. The chip control circuit 10 provided in the embodiment of the present application is applied to the SoC chip to provide a data update path for the SoC chip. Even after the SoC chip is taped out, its IP type, signal type, data, etc. can be updated in real time according to actual conditions.

[0044] In the process of implementing this application, the inventor found that the current SoC chip has poor flexibility. In view of the above problem, a chip control circuit is provided in the embodiment of this application to solve the technical problem that the current SoC chip has poor flexibility.

[0045] See also Figure 2 , an embodiment of the present application provides a chip control circuit 10, including: a storage unit 100, a signal conversion unit 200, and a signal selection unit 300.

[0046] The storage unit 100 is used to receive update data. The update data can be signal data for interacting or driving with other chips 30, IP data for updating IP types, or test data for internal or external testing, etc., which are not exhaustive here, and can be configured in real time by developers, etc. according to actual conditions. However, it should be explained that the update data refers to data that updates or adds additional data to the existing data inside the chip 30. The form of the data to be updated can be a serial data stream or a parallel data stream, and the embodiment of the present application does not make any limitation. The storage unit 100 is used to receive the update data, and store or cache the update data for subsequent processing units to read and process. The storage unit 100 can be various types of memory, register, etc. The storage unit 100 can be an existing storage device inside the chip 30, or a new storage device additionally configured on the existing basis of the SoC chip, etc., and the embodiment of the present application does not make any specific limitation.

[0047] The input end of the signal conversion unit 200 is connected to the output end of the storage unit 100 by signal, and the control end of the signal conversion unit 200 is connected to the control unit 21 by signal. The signal conversion unit 200 is used to convert the update data into a serial data stream. The signal conversion unit 200 converts the update data into a serial data stream to facilitate the subsequent signal selection unit 300 to select the target data actually needed from the data to be updated. The signal conversion unit 200 can be a data converter or a signal generator 220, etc., and the embodiment of the present application is not specifically limited. It only needs to realize the function of converting the update data into serial data. It needs to be explained that serial data is opposite to parallel data. Serial data refers to data in which each data bit is transmitted in sequence during the transmission process, that is, the data is transmitted one by one in sequence, and each data bit occupies a fixed time length. Parallel data is data transmitted simultaneously by each data bit. The embodiment of the present application converts the update data into a serial data stream, which can greatly improve the accuracy and reliability of selecting the target data from the update data.

[0048] The input end of the signal selection unit 300 is connected to the output end of the signal conversion unit 200, and the output end of the signal selection unit 300 is used to connect the input / output interface 31. The signal selection unit 300 is used to select target data from the serial data stream and send the target data to the input / output interface 31. The target data refers to the data selected from the current update data and actually used for interaction, testing, etc. with other chips 30. The signal selection unit 300 can be an independent signal selector 320, or a signal path controlled by the control unit 21, and the target data is selected from the current serial data through the control signal of the control unit 21.

[0049] The following is a brief introduction to the working principle of the chip control circuit 10 provided in the embodiment of the present application:

[0050] In actual work, the staff writes the update data that needs to be updated for the SoC chip to the storage unit 100, and the storage unit 100 caches or stores the update data. The signal conversion unit 200 converts the update data, which may be parallel data, into, for example, single-bit serial data, and the signal selection unit 300 selects the target data that it actually needs from the serial data, and transmits the target data through the IO interface to achieve interaction with other chips 30.

[0051] The chip control circuit 10 provided in the embodiment of the present application is configured with a storage unit 100, a signal conversion unit 200, and a signal selection unit 300. When it is necessary to update the internal signal of the SoC chip, the update data is written to the storage unit 100, and then the signal conversion unit 200 can convert the update data into serial data, and the signal selection unit 300 selects the target data from the serial data stream and sends the target data to the input / output interface 31, thereby realizing interaction with other chips 30. Due to the programmability of the update data in the storage unit 100, that is, the SoC chip can flexibly update the update data in the storage unit 100, so that the SoC chip can output signal data in any format, so that the SoC chip can interact with any type of chip 30, thereby solving the technical problem of poor flexibility of the current SoC chip and achieving the technical effect of improving the flexibility of the SoC chip.

[0052] See also Figure 3 In an optional embodiment of the application, the signal conversion unit 200 includes: a register body 210 and a signal generator 220 .

[0053] The register body 210 refers to a device used to provide a matrix for the signal generator 220. The register body 210 can be any type of register such as a general register, a control register, a segment register, etc. It only needs to provide a matrix for the signal generator 220 and perform data caching functions. The embodiment of the present application does not make specific limitations.

[0054] The signal generator 220 (Signal Generation Device, SGDEV for short) based on direct memory access is set in the register body 210 shown. The input end of the signal generator 220 is connected to the output end signal of the storage unit 100, and the control end of the signal generator 220 is connected to the control unit 21 for signaling. The signal generator 220 is used to convert the update data into a serial data stream. The signal generator 220 in the embodiment of the present application is based on direct memory access (DMA) transmission. The signal generator 220 can be used as a common control end to read any updated data mapped to or written into the system memory space, that is, the above-mentioned storage unit 100, and then the update data is converted into a serial single-bit data stream in units of one bit or several bits, so as to facilitate the subsequent signal selection unit 300 to select the current data, which can greatly improve the efficiency of target data selection, thereby improving the data processing efficiency of the SoC chip in the embodiment of the present application.

[0055] Direct memory access allows hardware devices of different speeds to exchange data without relying on a large number of interrupt loads in the central processor, thereby avoiding the central processor from copying all data from the source to the temporary register and then writing them back to the new place to affect other work processes of the central processor. Therefore, the embodiment of the present application can avoid the occurrence of such a situation while realizing data conversion by setting the signal generator 220 for direct memory access, thereby improving the working efficiency of the SoC chip.

[0056] See also Figure 4 In an optional embodiment of the application, the signal selection unit 300 includes: a data interface 310 and a signal selector 320.

[0057] The input end of the data interface 310 is signal-connected to the output end of the signal conversion unit 200, and is used to receive the serial data stream output by the signal conversion unit 200. The data interface 310 can be a pin, a tube pin, or other data interface 310 similar to AGP, PCI-E, USB, etc., and this embodiment does not make specific limitations.

[0058] The control end of the signal selector 320 is used to connect to the control unit 21 , the input end of the signal selector 320 is signal-connected to the output end of the data interface 310 , and the output end of the signal selector 320 is signal-connected to the input / output interface 31 .

[0059] In the working state, the serial data stream enters the signal selector 320 in sequence. The signal selector 320 is used to determine the target data from the serial data stream according to the control signal sent by the control unit 21, and send the target data to the IO interface so that the IO interface can interact with other chips 30. The signal selector 320 can be a GPIO (general purpose input / output, general input / output interface 31) switch. The control unit 21 controls the GPIO switch to achieve selective connection of the target data in the serial data stream. The operation is simple and convenient, and the target data selection efficiency is higher and the error rate is lower, which further improves the data processing efficiency and reliability of the SoC chip.

[0060] In an optional embodiment of the application, the number of interfaces of the data interface 310 is multiple, and different data interfaces 310 correspond to different types of data or signals. Correspondingly, the signal selector 320 can selectively pass the target data from the serial data stream by simply controlling the on and off of each data interface 310. This avoids the problem of selecting from a large amount of data, improves the selection efficiency of the target data, and further improves the data processing efficiency of the SoC chip.

[0061] In an optional embodiment of the application, the storage unit 100 includes multiple storage devices, and different types of data or signals are stored in different storage devices, so that the signal conversion unit 200 can directly read the corresponding data from the storage unit 100 according to the data type, which greatly saves the time of selective data reading, thereby improving the data processing efficiency of the SoC chip. At the same time, different types of data are configured in different storage devices. Under the premise of performance permission, the signal conversion unit 200 can simultaneously read data of various types of updated data in several storage devices, which greatly improves the efficiency of data processing and further improves the data processing efficiency of the SoC chip.

[0062] In an optional embodiment of the application, the storage device is at least one of a random access memory (RAM), a register (REG), and a double data rate synchronous dynamic random access memory (DDR). Among them, RAM and REG can meet the storage of different types of memory data, and DDR is an external editable memory. Therefore, the embodiment of the disclosure can update the data or signal in the SoC chip from multiple dimensions of internal memory and external memory, greatly broadening the way to update data in the SoC chip and further improving its data update efficiency.

[0063] Please attend Figure 5 In an optional embodiment of the application, the chip control circuit 10 also includes: a memory selector 400.

[0064] The input end of the memory selector 400 is respectively connected to the signals of multiple memory devices, and the output end of the memory selector 400 is connected to the signal conversion unit 200. The memory selector 400 is used to select a target memory device that generates target data from multiple memory devices. For example, for an IP or signal of high-speed data transmission, the path between the DDR and the signal conversion unit 200 is connected, and the high-speed transmission update data stored in the DDR is transmitted to the signal conversion unit 200, and so on. The embodiments of the present application are provided with a memory selector 400, which can control the signal conversion unit 200 to selectively access each memory device, and selectively connect the path between the corresponding memory device and the signal conversion unit 200, which can greatly reduce the number of samples of the signal conversion unit 200 to be selected for update data when reading the signal, thereby improving the data reading efficiency of the signal conversion unit 200, and further improving the data processing efficiency of the SoC chip.

[0065] In an alternative embodiment of the present invention, the memory selector 400 is a high-speed bus.

[0066] Generally, a high-speed bus (Bus fabric) is configured in the chip 30. The embodiment of the present application directly configures the high-speed bus in the existing chip 30 as a memory selector 400, and directly selects each memory device through the high-speed bus without the need to configure other memory selectors 400. This greatly reduces the cost of the chip control circuit 10 while ensuring that the chip control circuit 10 corresponds to the memory selection function.

[0067] In an optional embodiment of the application, the above-mentioned signal conversion unit 200 and signal selection unit 300 are both bidirectional processing units, that is, the signal selection unit 300 can select target data from the serial data stream output from the signal conversion unit 200 and send it to the IO interface. Similarly, the signal selection unit 300 can also select the target data required by the SoC chip from the data stream input through the IO interface; correspondingly, the signal conversion unit 200 can convert the data in the storage unit 100 into a serial data stream and transmit it to the signal selection unit 300 for selection. Similarly, the signal conversion unit 200 can also convert the target data selected by the signal selection unit 300 from the data stream connected to the IO interface into parallel data and store it in the storage unit 100, thereby saving the storage space of the storage unit 100. That is, the chip control circuit 10 provided in the embodiment of the present application is a bidirectional conversion and control circuit, which can greatly improve the compatibility and flexibility of the SoC chip.

[0068] See also Figure 6 In another embodiment of the present application, a chip control system 20 is provided, including: a chip control circuit 10 and a control unit 21.

[0069] As for the chip control circuit 10 in any of the above embodiments, the beneficial effects of the chip control circuit 10 have been described in detail in the above embodiments and will not be repeated here.

[0070] The output end of the control unit 21 is connected to the control end signal of the signal conversion unit 200 in the chip control circuit 10. The control unit 21 is used to generate a control signal and control the signal conversion unit 200 to convert the update data into a serial data stream based on the control signal. The control unit 21 can be a processor in the SoC chip or an additionally configured control device. The control unit 21 controls the operation of the signal conversion unit 200, for example, converting the update data into a serial data stream in a preset format to adapt to the signal format of different chips 30 that interact with the SoC chip, thereby improving the compatibility of the SoC chip.

[0071] See also Figure 7 In another embodiment of the present application, a chip 30 is provided, comprising: a substrate ( Figure 7 ), chip control system 20 and input / output interface 31.

[0072] The substrate is used to provide a carrier for the chip control system 20, etc. The substrate can be any type of substrate such as a PBGA (Plastic BGA) substrate, a CBGA (Ceramic BGA) substrate, a FCBGA (FilpChip BGA) substrate, a TBGA (Tape BGA) substrate, etc., and the embodiment of the present application does not make any specific limitations.

[0073] The beneficial effects of the chip control system 20 have been described in detail in the above embodiments and will not be repeated here.

[0074] The input / output interface 31 is an IO interface, which is arranged on the substrate and is connected to the input signal of the signal selection unit 300 in the chip control system 20, and transmits the target data selected by the signal selection unit 300 to other chips 30 to realize signal interaction with other signals.

[0075] The chip 30 provided in the embodiment of the present application can interact with chips 30 of any communication form or format, greatly improving the compatibility of the SoC chip.

[0076] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0077] The above embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.

Claims

1. A chip control circuit, characterized in that: include: A storage unit, used for receiving update data; A signal conversion unit, wherein the input end of the signal conversion unit is signal-connected to the output end of the storage unit, the control end of the signal conversion unit is signal-connected to the control unit, and the signal conversion unit is used to convert the update data into a serial data stream; the signal conversion unit includes a signal generator based on direct memory access; the input end of the signal generator is signal-connected to the output end of the storage unit, the control end of the signal generator is signal-connected to the control unit, and the signal generator is used to convert the update data into a serial data stream; the signal generator reads any update data mapped to or written into the system access memory space as a common control end, and then converts the update data into a serial single-bit data stream in units of one bit or several bits; A signal selection unit, wherein an input end of the signal selection unit is signal-connected to an output end of the signal conversion unit, an output end of the signal selection unit is used to connect to an input / output interface, and the signal selection unit is used to select target data from the serial data stream and send the target data to the input / output interface; A control unit, wherein an output end of the control unit is signal-connected to a control end of the signal conversion unit, and the control unit is used to generate a control signal and control the signal conversion unit to convert the update data into a serial data stream based on the control signal; the control unit is a processor in the SoC chip; A memory selector, wherein the input end of the memory selector is respectively connected to the plurality of memory devices in the storage unit by signal, and the output end of the memory selector is connected to the signal conversion unit by signal, and the memory selector is used to select a target memory device that generates the target data from the plurality of memory devices, and the memory selector controls the signal conversion unit to selectively access each memory device, and selectively connects a path between the corresponding memory device and the signal conversion unit; If it is an IP or signal for high-speed data transmission, the path between the DDR and the signal conversion unit is connected, and the update data for high-speed transmission stored in the DDR is transmitted to the signal conversion unit.

2. The chip control circuit according to claim 1, characterized in that: The signal conversion unit comprises: Register body; A signal generator based on direct memory access is arranged in the register body, the input end of the signal generator is signal-connected to the output end of the storage unit, the control end of the signal generator is signal-connected to the control unit, and the signal generator is used to convert the update data into a serial data stream.

3. The chip control circuit according to claim 1, characterized in that: The signal selection unit comprises: A data interface, an input end of the data interface being signal-connected to an output end of the signal conversion unit; A signal selector, wherein the control end of the signal selector is used to connect to the control unit, the input end of the signal selector is signal-connected to the output end of the data interface, the output end of the signal selector is signal-connected to the input / output interface, and the signal selector is used to determine the target data from the serial data stream according to the control signal sent by the control unit, and send the target data to the input / output interface.

4. The chip control circuit according to claim 3, characterized in that: The data interface has multiple interfaces.

5. The chip control circuit according to claim 1, characterized in that: The storage unit includes a plurality of storage devices.

6. The chip control circuit according to claim 5, characterized in that: The memory device is at least one of a random access memory, a double rate synchronous dynamic random access memory, and a register.

7. The chip control circuit according to claim 1, characterized in that: The memory selector is a high-speed bus.

8. A chip control system, characterized in that: include: A chip control circuit as described in any one of claims 1 to 7.

9. A chip, characterized in that: include: substrate; The chip control system as claimed in claim 8; The input / output interface is arranged on the substrate and is connected to the input terminal signal of the signal selection unit in the chip control system.

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