Methods of microelectronic device formation and related microelectronic devices, memory devices, and electronic systems

Abstract

The present application relates to microelectronic device formation methods and related microelectronic devices, memory devices, and electronic systems. A microelectronic device formation method includes forming a first stack structure including alternating levels of insulative structures and other insulative structures; forming strings of memory cells through the first stack structure; forming a second stack structure over the first stack structure; forming a first custom reticle specific to an observed amount of pillar bowing within the first stack structure; forming openings extending through the second stack structure and over some of the strings of memory cells using the first custom reticle, wherein a center of the openings over the strings of memory cells is at least substantially aligned with a center of an uppermost surface of the strings of memory cells in a direction of the observed pillar bowing; and forming upper pillars extending through the second stack structure and over some of the strings of memory cells.

Description

[0001] Priority Claim

[0002] This application claims the benefit of the filing date of U.S. Patent Application No. 17 / 205,954, filed March 18, 2021, entitled “METHODS OF FORMING MICROELECTRONIC DEVICES, AND RELATED MICROELECTRONIC DEVICES, MEMORY DEVICES, AND ELECTRONIC SYSTEMS”. Technical Field

[0003] This disclosure generally relates to the field of microelectronic device design and fabrication, in various embodiments. More specifically, this disclosure relates to methods of forming microelectronic devices, and to related microelectronic devices, memory devices, and electronic systems. Background Technology

[0004] A persistent goal of the microelectronics industry is to increase the memory density (e.g., the number of memory cells per memory die) of memory devices, such as non-volatile memory devices (e.g., NAND flash memory devices). One way to increase memory density in non-volatile memory devices is to utilize vertical memory array (also known as “three-dimensional (3D) memory arrays”) architectures. A conventional vertical memory array comprises vertical memory strings extending through openings in one or more stacks (e.g., stacked structures) containing conductive structures and dielectric material layers. Each vertical memory string may contain at least one selection device series-coupled to a series combination of vertically stacked memory cells. Compared to structures with conventional planar (e.g., two-dimensional) transistor arrangements, this configuration allows for a greater number of switching devices (e.g., transistors) to be located in cells (i.e., the length and width of the active surface consumed) of the die region by constructing the array upwards (e.g., vertically) on the die.

[0005] Vertical memory array architectures typically include electrical connections between conductive structures of layers in a stack of memory devices (e.g., a stacked structure) and access lines (e.g., bit lines), allowing memory cells in the vertical memory array to be uniquely selected for write, read, or erase operations. One method of forming such electrical connections involves forming a so-called “step” (or “step”) structure at the edges (e.g., horizontal ends) of the layers in the stack of memory devices. The step structure includes individual “steps” defining contact areas of conductive structures, on which conductive contact structures can be positioned to provide electrical pathways for the conductive structures.

[0006] With the development of vertical memory array technology, memory density has been increased by forming memory devices in a multi-stack configuration (e.g., dual-stack). For example, in a conventional dual-stack configuration, some vertical memory strings are located in an upper stack (e.g., upper stack structure), while additional vertical memory strings are located in a lower stack below the upper stack (e.g., lower stack structure). The vertical memory strings in the upper stack can be electrically coupled to the additional vertical memory strings in the lower stack (e.g., through conductive interconnect structures), or the vertical memory strings in the upper stack can be electrically isolated from the additional vertical memory strings in the lower stack (e.g., through an intermediate dielectric material). Unfortunately, with the increase in feature package density and the decrease in the margin of forming errors, conventional memory device forming methods and associated configurations lead to undesirable stresses (e.g., access line contacts exceeding etch stress), defects (e.g., access line contact vias), and current leakage (e.g., select gate current leakage, access line current leakage), which degrade the desired memory device performance, reliability, and durability.

[0007] Another ongoing goal in the microelectronics device manufacturing industry is to improve device performance, such as 3D NAND memory devices, by reducing the resistance and / or capacitance of word lines. However, efforts to reduce the resistance and / or capacitance of word lines can negatively impact other aspects of device design and manufacturing, such as causing pin bending in regions adjacent to stepped structures within the device. Therefore, designing and manufacturing microelectronic devices with reduced resistance and / or capacitance and no pin bending, such as 3D NAND memory devices, remains a challenge. Summary of the Invention

[0008] Embodiments of this disclosure include a method of forming a microelectronic device. The method includes: forming a first stacked structure comprising alternating layers of insulating structures and other insulating structures; forming a memory cell string comprising channel material extending through the first stacked structure; forming a second stacked structure above the first stacked structure, comprising alternating layers of additional insulating structures and other additional insulating structures, based at least in part on post bending observed within the first stacked structure; forming a first custom marker specific to the observed post bending; forming openings extending through the second stacked structure and above some of the memory cell strings using the first custom marker, wherein the center of the openings above the memory cell strings is substantially aligned with the center of the uppermost surface of the memory cell string, at least in the direction of the observed post bending; forming upper posts extending through the second stacked structure and above some of the memory cell strings; and forming a slot structure between some adjacent upper posts, the slot structure exhibiting a nonlinear shape, based at least in part on the observed post bending.

[0009] Some embodiments of this disclosure include a microelectronic device. The microelectronic device includes: a stacked structure comprising a vertically alternating sequence of conductive and insulating structures arranged in layers, the stacked structure being divided into block structures separated from each other by slot structures; lower guide pillars extending vertically through the block structures of the stacked structure, the lower guide pillars exhibiting guide pillar bending in a first direction, each of the lower guide pillars having a lowermost surface and an uppermost surface not vertically aligned with the lowermost surface of the guide pillar; an additional stacked structure vertically overlying the stacked structure and comprising a vertically alternating sequence of additional conductive and insulating structures arranged in additional layers; and upper guide pillars extending through the additional stacked structure and vertically overlying the lower guide pillars, each upper guide pillar having a lowermost surface and an uppermost surface, wherein the center of the lowermost surface of each upper guide pillar is aligned in the first direction with the center of the uppermost surface of the corresponding guide pillar.

[0010] Additional embodiments of this disclosure include a microelectronic device comprising: a memory cell string extending through a first stacked structure comprising alternating conductive and insulating structures, the memory cell string comprising at least a dielectric material and a channel material extending vertically through the first stacked structure; a second stacked structure vertically overlying the first stacked structure; upper posts extending through the second stacked structure and vertically overlying the memory cell string; a rigid mask material located above the second stacked structure; elliptical openings extending through the rigid mask material, each elliptical opening vertically overlapping at least a portion of a corresponding upper post of the upper posts; elliptical conductive contacts formed within the elliptical openings, each elliptical conductive contact contacting a corresponding upper post of the upper posts; and access lines electrically contacting the elliptical conductive contacts, wherein the elliptical cross-section of the elliptical conductive contacts has a principal axis extending in a direction perpendicular to the extension direction of the access lines.

[0011] Embodiments of this disclosure include an electronic system. The electronic system includes: an input device; an output device; a processor device operatively coupled to the input device and the output device; and a memory device operatively coupled to the processor device and including a microelectronic device structure. The microelectronic device structure includes: a string of memory cells extending through a stacked structure comprising alternating layers of insulating and conductive structures, the string of memory cells exhibiting post bending in a first direction; an upper post located within an additional stacked structure comprising alternating layers of additional insulating and conductive structures, the center of the lowest portion of the upper post being substantially aligned in the first direction with the corresponding center of the uppermost portion of the string of memory cells; slot structures extending at least partially through the stacked structure, the slot structures exhibiting nonlinear shapes; elliptical conductive contacts contacting the uppermost portion of the upper post, the elliptical cross-section of the elliptical conductive contacts having a principal axis extending in the first direction; and access lines electrically contacting the elliptical conductive contacts and extending in a second direction perpendicular to the first direction. Attached Figure Description

[0012] Figures 1A to 1X This is a simplified cross-sectional view illustrating a method for forming a microelectronic device structure according to an embodiment of the present disclosure. Figure 1A , Figure 1C , Figure 1D , Figures 1F to 1J , Figure 1L , Figure 1M , Figure 10 and Figure 1P ) and top view ( Figure 1B , Figure 1E , Figure 1K and Figure 1N );

[0013] Figure 2 This is a partial cross-sectional perspective view of a microelectronic device according to an embodiment of the present disclosure;

[0014] Figure 3 This is a block diagram of an electronic system according to embodiments of the present disclosure; and

[0015] Figure 4 This is a block diagram of a processor-based system according to an embodiment of the present disclosure. Detailed Implementation

[0016] The illustrations included herein are not intended to be actual views of any particular system, microelectronic structure, microelectronic device, or its integrated circuit, but are merely idealized representations for describing the embodiments herein. Common elements and features in the figures may retain the same numerical designations, but for ease of following the illustrations, the reference numerals begin with the figure number that introduces the element or provides the most complete description of the element.

[0017] The following description provides specific details, such as material composition, shape, and size, to provide a sufficient description of embodiments of this disclosure. However, those skilled in the art will understand that embodiments of this disclosure can be practiced without these specific details. In practice, embodiments of this disclosure can be practiced in conjunction with conventional microelectronic device manufacturing techniques used in the industry. Furthermore, the description provided below does not form a complete process flow for manufacturing microelectronic devices (e.g., memory devices, such as 3D NAND flash memory devices). The structures described below do not form a complete microelectronic device. Only those process actions and structures necessary for understanding embodiments of this disclosure are described in detail below. Additional actions for forming a complete microelectronic device according to the structures can be performed using conventional manufacturing techniques.

[0018] The diagrams presented herein are for illustrative purposes only and are not intended to be actual views of any particular material, component, structure, device, or system. Shapes depicted in the diagrams are expected to vary due to, for example, manufacturing techniques and / or tolerances. Therefore, the embodiments described herein should not be construed as limited to the specific shapes or areas shown, but rather include deviations in shape, for example, due to manufacturing processes. For instance, an area shown or described as box-shaped may have coarse and / or non-linear characteristics, and an area shown or described as circular may contain some coarse and / or linear characteristics. Furthermore, acute angles shown may be rounded, and vice versa. Therefore, the areas shown in the figures are schematic in nature, and their shapes are not intended to illustrate the precise shape of the areas and do not limit the scope of the claims. The diagrams are not necessarily drawn to scale. Additionally, common elements between the diagrams may retain the same numerical designations.

[0019] As used herein, “memory device” means and includes, but is not limited to, microelectronic devices that exhibit memory functionality. In other words, by way of non-limiting example only, the term “memory device” includes not only memory (e.g., volatile memory, such as DRAM; non-volatile memory, such as NAND memory), but also application-specific integrated circuits (ASICs) (e.g., system-on-a-chip (SoC)), microelectronic devices with combinational logic and memory, and graphics processing units (GPUs) incorporating memory.

[0020] As used herein, the terms “vertical,” “longitudinal,” “horizontal,” and “lateral” refer to the principal plane of the structure and are not necessarily defined by the Earth’s gravitational field. A “horizontal” or “lateral” direction is generally parallel to the principal plane of the structure, while a “vertical” or “longitudinal” direction is generally perpendicular to the principal plane of the structure. The principal plane of the structure is defined by the surfaces of the structure that have a relatively large area compared to the other surfaces of the structure. Referring to the figures, a “horizontal” or “lateral” direction may be perpendicular to the indicated “Z” axis and parallel to the indicated “X” axis and / or parallel to the indicated “Y” axis; and a “vertical” or “longitudinal” direction may be parallel to the indicated “Z” axis, perpendicular to the indicated “X” axis, and perpendicular to the indicated “Y” axis.

[0021] As used herein, features described as “adjacent” to each other (e.g., areas, structures, devices) refer to and include features that are most closely (e.g., closest to) each other and have the disclosed identifiers (or more identifiers). Additional features (e.g., additional areas, additional structures, additional devices) that do not match the disclosed identifiers (or more identifiers) of “adjacent” features may be positioned between “adjacent” features. In other words, “adjacent” features may be positioned directly adjacent to each other such that no other features intervene between “adjacent” features; or “adjacent” features may be positioned indirectly adjacent to each other such that at least one feature having an identifier other than the identifier associated with at least one “adjacent” feature is positioned between “adjacent” features. Thus, features described as “vertically adjacent” to each other refer to and include features that are most closely (e.g., closest to) each other and have the disclosed identifiers (or more identifiers). Furthermore, features described as “horizontally adjacent” to each other refer to and include features that are most closely (e.g., closest to) each other and have the disclosed identifiers (or more identifiers).

[0022] As used herein, spatial relation terms such as “below,” “under,” “lower,” “bottom,” “above,” “upper,” “top,” “front,” “rear,” “left,” “middle,” and “right” are used for convenience to describe the relationship between one element or feature and another element(s) as shown in the figures. Unless otherwise specified, spatial relation terms inherently cover different orientations of material other than those depicted in the figures. For example, if the material in the figures is reversed, the element described as being “below,” “under,” “lower,” or “bottom” of other elements or features will be oriented “above” or “top” of said other elements or features. Thus, the term “below” may encompass both above and below orientations, depending on the context in which the term is used, as will be apparent to those skilled in the art. Material may be oriented in other ways (e.g., rotated 90 degrees, inverted, flipped), and the spatial relation descriptors used herein may be interpreted accordingly.

[0023] As used herein, the singular forms “a” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0024] As used in this article, “and / or” includes any and all combinations of one or more of the associated listed items.

[0025] As used herein, the term “configuration” refers to the size, shape, material composition, orientation, and arrangement of at least one feature (e.g., at least one structure, at least one area, at least one device) that facilitates the operation of said at least one feature in a predetermined manner.

[0026] As used herein, the phrase “coupled to” refers to structures that are operatively connected to each other, for example by direct ohmic connection or by indirect connection (e.g., by means of another structure) electrical connection.

[0027] As used herein, the term "generally" with respect to a given parameter, characteristic, or condition means and includes the degree to which a given parameter, characteristic, or condition conforms to a degree of variability (e.g., within acceptable tolerances) as would be understood by one of ordinary skill in the art. By way of example, depending on the specific parameter, characteristic, or condition being generally satisfied, the parameter, characteristic, or condition may satisfy at least 90.0%, at least 95.0%, at least 99.0%, at least 99.9%, or even 100.0%.

[0028] As used herein, the term "about" or "approximately" with respect to a particular parameter includes the value, and those skilled in the art will understand that the degree of variation relative to the value is within an acceptable tolerance for the particular parameter. For example, "about" or "approximately" with respect to a value may include additional values ​​that are within 90.0% to 110.0% of the value, such as 95.0% to 105.0%, 97.5% to 102.5%, 99.0% to 101.0%, 99.5% to 100.5%, or 99.9% to 100.1%.

[0029] As used herein, the term "homogeneous" means that the relative number of elements contained in a feature (e.g., material, structure) does not vary across different parts of the feature (e.g., different horizontal sections, different vertical sections). Conversely, as used herein, the term "heterogeneous" means that the relative number of elements contained in a feature (e.g., material, structure) varies across different parts of the feature. If a feature is heterogeneous, then the number of one or more elements contained in the feature may vary abruptly (e.g., abruptly) across different parts of the feature, or it may vary continuously (e.g., gradually, such as linearly, parabolically) across different parts of the feature. For example, a feature may be composed of at least two different materials and contain a stack of two different materials.

[0030] Unless otherwise indicated, the materials described herein can be formed using conventional techniques, including but not limited to spin coating, blanket coating, chemical vapor deposition (CVD), atomic layer deposition (ALD), plasma-enhanced ALD, physical vapor deposition (PVD) (including sputtering, evaporation, ionization PVD, and / or plasma-enhanced CVD), or epitaxial growth. Alternatively, the material can be grown in situ. Depending on the specific material to be formed, the technique used for depositing or growing the material can be selected by a person skilled in the art. Unless the context otherwise indicates, the removal of the material can be achieved by any suitable technique, including but not limited to etching (e.g., dry etching, wet etching, vapor phase etching), ion milling, abrasive planarization (e.g., chemical mechanical planarization), or other known methods. The etching chemistry and etching conditions used to etch the desired material can be selected by a person skilled in the art.

[0031] As used herein, the term "insulating material" includes one or more of the following: at least one dielectric oxide material (e.g., silicon oxide (SiO2)). x Phosphorus silicate glass, borosilicate glass, borosilicate-phosphorus silicate glass, fluorosilicate glass, alumina (AlO) x ), Hafnium oxide (HfO) x ), niobium oxide (NbO) x Titanium oxide (TiO) x Zirconium oxide (ZrO) x ), tantalum oxide (TaO) x ) and magnesium oxide (MgO) x One or more of the following), at least one dielectric nitride material (e.g., silicon nitride (SiN) y ()), at least one dielectric oxide nitride material (e.g., silicon oxynitride (SiO) x N y And at least one dielectric carbon oxynitride material (e.g., silicon carbon oxynitride (SiO2)). x C z Ny This document contains one or more of the chemical formulas “x”, “y”, and “z” (e.g., SiO2). x AlO x HfO x NbO x TiO x SiN y SiO x N y SiO x C z N y A chemical formula represents a material containing “x” atoms of one element, “y” atoms of another element, and “z” atoms of an additional element (if present) relative to each atom of another element (e.g., Si, Al, Hf, Nb, Ti). Because chemical formulas represent relative atomic ratios and non-strict chemical structures, insulating structures can include one or more stoichiometric compounds and / or one or more non-stoichiometric compounds, and the values ​​of “x,” “y,” and “z” (if present) can be integers or non-integers. As used herein, the term “non-stoichiometric compound” means and includes compounds composed of an element whose composition cannot be expressed by a well-defined ratio of natural numbers and violates the law of definite proportions.

[0032] As used herein, the term "conductive material" includes one or more of the following: metals (e.g., tungsten (W), titanium (Ti), molybdenum (Mo), niobium (Nb), vanadium (V), hafnium (Hf), tantalum (Ta), chromium (Cr), zirconium (Zr), iron (Fe), ruthenium (Ru), osmium (Os), cobalt (Co), rhodium (Rh), iridium (Ir), nickel (Ni), palladium (Pa), platinum (Pt), copper (Cu), silver (Ag), gold (Au), aluminum (Al)); alloys (e.g., Co Basic alloys, Fe-based alloys, Ni-based alloys, Fe and Ni-based alloys, Co and Ni-based alloys, Fe and Co-based alloys, Co and Ni and Fe-based alloys, Al-based alloys, Cu-based alloys, Magnesium (Mg)-based alloys, Ti-based alloys, steel, low-carbon steel, stainless steel); containing metallic materials (e.g., metal nitrides, metal silicides, metal carbides, metal oxides); including titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN), iridium oxide (IrO). x ), Ruthenium oxide (RuO) x Materials comprising at least one of the following alloys: conductive doped semiconductor materials (e.g., conductive doped polysilicon, conductive doped germanium (Ge), conductive doped silicon germanium (SiGe)); polysilicon; other materials exhibiting conductivity; or combinations thereof.

[0033] As used herein, the terms "lead misalignment" or "lead bending" refer to a deviation of the central longitudinal axis of a lead structure in a microelectronic device architecture from an ideal, true vertical central longitudinal axis. As a non-limiting example, a lead may be tilted or bent, deviating from its true vertical orientation. For instance, the bottom portion of a lead may be ideally positioned and formed therein, but due to lead bending, the top portion of the lead may not be vertically aligned with the bottom surface of the lead.

[0034] Embodiments of this disclosure include microelectronic device structures (e.g., memory devices), and related microelectronic devices (e.g., memory devices), electronic systems, and methods. In some embodiments, the microelectronic device structures of this disclosure include: a string of memory cells (e.g., posts) extending through a stacked structure comprising alternating layers of insulating and conductive structures, the string of memory cells exhibiting post bending in a first direction; an upper post located within an additional stacked structure comprising alternating layers of additional insulating and conductive structures, the center of the lowermost surface of the uppermost post being substantially aligned in the first direction with the corresponding center of the uppermost surface of the string of memory cells; a slot structure extending at least partially through the stacked structure, the slot structures exhibiting nonlinear shapes; an elliptical conductive contact contacting the uppermost surface of the uppermost post, the elliptical cross-section of the elliptical conductive contact having a principal axis extending in the first direction; and an access line electrically contacting the elliptical conductive contact and extending in a second direction perpendicular to the first direction.

[0035] Embodiments of this disclosure include forming openings therein with one or more custom markings to form upper guide pillars. The openings may be formed to accommodate guide pillar bending exhibited by a string of memory cells (e.g., guide pillars within a stacked structure). Additionally, embodiments of this disclosure include forming elliptical openings within a rigid mask material above the upper guide pillars, where elliptical conductive contacts are formed, using custom markings. The size and shape of the ellipse defined by the elliptical contacts may be determined at least in part by the observed guide pillar bending of the string of memory cells (e.g., guide pillars within a stacked structure) to accommodate (e.g., compensate for) the observed degree of guide pillar bending. In some embodiments, the custom markings may be formed in real-time (i.e., designed and manufactured). For example, the custom markings may be formed during the process of forming the microelectronic device structure based on observed guide pillar bending of the microelectronic device structure. In other embodiments, the custom markings may be formed for observed and / or anticipated guide pillar misalignment and / or guide pillar bending amounts, and the custom markings may be selected from the formed custom markings and used to form the openings and elliptical openings of the microelectronic device structure. For example, custom markings can be selected based on observed post misalignment and / or post bending and / or based on expected post misalignment and / or post bending within the microelectronic device structure.

[0036] Forming openings and / or elliptical openings in a microelectronic device structure using custom markings based on observed post misalignment and / or post bending can be more advantageous than conventional microelectronic device structure formation methods. For example, compared to conventional methods and structures that exhibit post misalignment and / or post bending, forming openings and / or elliptical openings in a microelectronic device structure using custom markings based on observed post misalignment and / or post bending can improve the overlap between the post and the upper post structure. Therefore, the electrical connection between the post and the upper post structure can be improved.

[0037] Furthermore, compared to conventional methods and structures that exhibit lead misalignment and / or lead bending, using custom markings to form openings and / or elliptical openings in the microelectronic device structure based on observed lead misalignment and / or lead bending can improve the overlap between the elliptical conductive contacts and the upper lead structure, and thus improve the electrical connection between the elliptical conductive contacts and the upper lead structure. Additionally, using custom markings to form elliptical openings based on observed lead misalignment and / or lead bending can improve the overlap between the elliptical conductive contacts and access lines (e.g., bit lines), which may have a fixed position within the microelectronic device structure, even if the microelectronic device structure exhibits lead misalignment and / or lead bending. For example, compared to the annular shape in conventional structures exhibiting lead misalignment and / or lead bending, the elliptical shape of the elliptical openings and elliptical conductive contacts improves the overlap between the elliptical conductive contacts and the access lines (e.g., bit lines). In view of the foregoing, by accommodating and / or compensating for the bending of the guide pillars within the microelectronic device structure, the number of dummy guide pillars (e.g., dummy guide pillar regions) within the microelectronic device structure can be reduced relative to conventional structures.

[0038] Figures 1A-1X A method for forming a microelectronic device structure according to an embodiment of the present disclosure is shown. Figure 1A This is a simplified partial cross-sectional view of a microelectronic device structure 100 according to an embodiment of the present disclosure. Figure 1B yes Figure 1A A top view of the structure 100 of the microelectronic device. Figure 1A The cross section passes through Figure 1B The cross-section line AA is cut off. The microelectronic device structure 100 may include a stacked structure 101, which includes a vertical (e.g., in the Z direction) alternating sequence of insulating structures 104 and other insulating structures 106 arranged in layers 102. Each of the layers 102 may respectively include a level of insulating structure 104, which is directly vertically adjacent (e.g., adjacent) to a level of other insulating structure 106. The insulating structure 104 of the stacked structure 101 may also be referred to herein as "insulating material", and the other insulating structures 106 of the stacked structure 101 may also be referred to herein as "other insulating materials".

[0039] In some embodiments, the number (e.g., quantity) of layers 102 in the stacked structure 101 may range from 32 layers 102 to 256 layers 102. In some embodiments, the stacked structure 101 comprises 128 layers 102. However, this disclosure is not limited thereto, and the stacked structure 101 may comprise a different number of layers 102. Additionally, in some embodiments, the stacked structure 101 may comprise: a first stacked structure vertically overlying the source structure 103 and comprising layers 102 including insulating structures 104 and other insulating structures 106; and a second stacked structure above the first stacked structure, the second stacked structure comprising layers 102 including insulating structures 104 and other insulating structures 106. In some such embodiments, the first stacked structure may be separated from the second stacked structure by an inter-stack region. For example, the stacked structure 101 may comprise a dual-stack 3D NAND device (e.g., a 3D NAND flash memory device). In some embodiments, the stacked structure 101 may be referred to herein as a stacked structure or a first stacked structure.

[0040] The layers of the insulating structure 104 may be formed of and contain at least one dielectric material, such as one or more of the following: oxide materials (e.g., silicon dioxide (SiO2)), phosphosilicate glass, borosilicate glass, borosilicate-phosphosilicate glass, fluorosilicate glass, titanium dioxide (TiO2), hafnium dioxide (HfO2), zirconium dioxide (ZrO2), tantalum oxide (TaO2), magnesium oxide (MgO), and aluminum oxide (Al2O3). In some embodiments, the insulating structure 104 is formed of and contains silicon dioxide.

[0041] Other insulating structures 106 may be formed and comprised of insulating materials different from insulating structures 104 and exhibiting etch selectivity with respect to them. In some embodiments, other insulating structures 106 are formed and comprised of nitride materials (e.g., silicon nitride (Si3N4)) or oxide nitride materials (e.g., silicon oxynitride). In some embodiments, other insulating structures 106 are formed and comprised of silicon nitride.

[0042] The stacked structure 101 may be formed above the source structure 103 (e.g., source material, source plate). The source structure 103 may be formed from and include: for example, a semiconductor material doped with one or more P-type conductive materials (e.g., polysilicon doped with at least one P-type dopant, such as one or more of boron, aluminum, and gallium), or a semiconductor material doped with one or more N-type conductive materials (e.g., polysilicon doped with at least one N-type dopant, such as one or more of arsenic, phosphorus, antimony, and bismuth). Although Figure 1AThe stacked structure 101 has been described and shown as being contained directly above (e.g., on) the source structure 103, but this disclosure is not limited thereto. In other embodiments, the stacked structure 101 is covered by an additional layer 102 including an insulating structure 104 and other insulating structures 106 and separated from the stacked structure 101 by at least one dielectric material.

[0043] The dielectric material 108 may be located above the uppermost layer in layer 102. The dielectric material 108 may be formed of and contain an electrically insulating material, such as one or more of the following: phosphosilicate glass (PSG), borosilicate glass (BSG), fluorosilicate glass (FSG), borosilicate glass (BPSG), and silicon dioxide. In some embodiments, the dielectric material 108 may contain the same material composition as the insulating structure 104. In some embodiments, the dielectric material 108 is formed of and contains silicon dioxide.

[0044] Material posts 110 (e.g., cell posts, memory posts) may extend vertically (e.g., in the Z direction) through the stack structure 101. As will be described herein, the material of the posts 110 may form memory cells (e.g., memory cell strings). Posts 110 (e.g., lower posts 110) may each include an insulating material 112, a channel material 114 horizontally adjacent to the insulating material 112, a tunneling dielectric material (also referred to as "tunneling dielectric") 116 horizontally adjacent to the channel material 114, a memory material 118 horizontally adjacent to the tunneling dielectric material 116, and a dielectric barrier material (also referred to as "charge barrier material") 120 horizontally adjacent to the memory material 118. The dielectric barrier material 120 may be horizontally adjacent to one of the other insulating structures 106 of one layer 102 in the stack structure 101. The channel material 114 can be horizontally inserted between the insulating material 112 and the tunnel dielectric material 116; the tunnel dielectric material 116 can be horizontally inserted between the channel material 114 and the memory material 118; the memory material 118 can be horizontally inserted between the tunnel dielectric material 116 and the dielectric barrier material 120; and the dielectric barrier material 120 can be horizontally inserted between the memory material 118 and a layer of other insulating structures 106.

[0045] The insulating material 112 may be formed of and comprise an electrically insulating material, such as phosphosilicate glass (PSG), borosilicate glass (BSG), fluorosilicate glass (FSG), borosilicate glass (BPSG), silicon dioxide, titanium dioxide, zirconium dioxide, hafnium dioxide, tantalum oxide, magnesium oxide, aluminum oxide, niobium oxide, molybdenum oxide, strontium oxide, barium oxide, yttrium oxide, nitride materials (e.g., silicon nitride (Si3N4)), nitrogen oxides (e.g., silicon oxynitride), dielectric carbonitride materials (e.g., silicon carbonitride (SiCN)), dielectric carbonoxynitride materials (e.g., silicon carbonoxynitride (SiOCN)), or combinations thereof. In some embodiments, the insulating material 112 is formed of and comprises silicon dioxide.

[0046] The channel material 114 may be formed from and include one or more of the following: semiconductor materials (at least one elemental semiconductor material, such as polycrystalline silicon; at least one III-V composite semiconductor material, at least one II-VI composite semiconductor material, at least one organic semiconductor material, GaAs, InP, GaP, GaN, other semiconductor materials), and oxide semiconductor materials. In some embodiments, the channel material 114 comprises amorphous silicon or polycrystalline silicon. In some embodiments, the channel material 114 is formed from and includes doped semiconductor materials.

[0047] The tunnel dielectric material 116 may be formed of and contain a dielectric material, capable of performing charge tunneling through the dielectric material under suitable electrical bias conditions, such as by hot carrier injection or charge transfer induced by Fowler-Nordheim tunneling. As a non-limiting example, the tunnel dielectric material 116 may be formed of and contain one or more of the following: silicon oxide, silicon nitride, silicon oxynitride, dielectric metal oxides (e.g., aluminum oxide and hafnium oxide), dielectric metal oxynitrides, dielectric metal silicates, alloys thereof, and / or combinations thereof. In some embodiments, the tunnel dielectric material 116 may contain silicon dioxide. In other embodiments, the tunnel dielectric material 116 is formed of and contains silicon oxynitride.

[0048] Memory material 118 may include charge-trapping material or conductive material. Memory material 118 may be formed from and contain one or more of the following: silicon nitride, silicon oxynitride, polycrystalline silicon (doped polycrystalline silicon), conductive material (tungsten, molybdenum, tantalum, titanium, platinum, ruthenium and their alloys, or metal silicides such as tungsten silicide, molybdenum silicide, tantalum silicide, titanium silicide, nickel silicide, cobalt silicide, or combinations thereof), semiconducting material containing at least one elemental semiconductor element or at least one synthetic semiconductor material, polycrystalline or amorphous semiconductor material, conductive nanoparticles (e.g., ruthenium nanoparticles), or metal dots. In some embodiments, memory material 118 is formed from and contains silicon nitride.

[0049] The dielectric barrier material 120 may be formed of and contain a dielectric material, such as one or more of oxides (e.g., silicon dioxide), nitrides (silicon nitride), and oxynitrides (silicon oxynitride) or another material. In some embodiments, the dielectric barrier material 120 is formed of and contains silicon oxynitride.

[0050] In some embodiments, the tunnel dielectric 116, the memory material 118, and the dielectric barrier material 120 may be co-formed and comprise structures configured to trap charges, such as oxide-nitride-oxide (ONO) structures. In some such embodiments, the tunnel dielectric 116 is formed of and comprises silicon dioxide, the memory material 118 is formed of and comprises silicon nitride, and the dielectric barrier material 120 is formed of and comprises silicon dioxide.

[0051] refer to Figure 1B Some guide posts 110 may be aligned with each other (e.g., in the Y direction), while other guide posts 110 may be offset from each other (e.g., in the Y direction). The guide posts 110 may be arranged in a so-called braided pattern (e.g., a hexagonal close-packed arrangement), which can promote increased density of guide posts 110 (and the resulting string of memory cells) in the stacked structure 101. The guide posts 110 may be arranged in rows 107 extending in a first horizontal (e.g., lateral) direction (e.g., in the X direction) and columns 109 extending in a second horizontal direction (e.g., in the Y direction). In some embodiments, the guide posts 110 in columns 109 may be laterally offset relative to the guide posts 110 in adjacent (e.g., neighboring) columns 109 (e.g., in each of the X and Y directions). Additionally, the guide posts 110 of every other column 109 may be horizontally aligned (e.g., in the Y direction). Similarly, the guide posts 110 of row 107 may be horizontally offset relative to the guide posts 110 in adjacent (e.g., neighboring) rows 107 (e.g., in each of the X and Y directions). Additionally, the guide posts 110 of every other row 107 may be horizontally aligned (e.g., in the X direction).

[0052] refer to Figure 1C After the guide post 110 is formed, a portion of the guide post 110 may be removed, causing the guide post 110 to be recessed relative to the uppermost surface of the dielectric material 108. In some embodiments, a portion of the insulating material and the channel material 114 may be recessed vertically lower than other components of the guide post 110 (e.g., in the Z direction) than the other components (e.g., tunnel dielectric material 116, memory material 118, dielectric barrier material 120).

[0053] In some embodiments, conductive material 122 may be formed within the recess to form a so-called “conductive plug structure.” Conductive material 122 may be formed of and comprise polysilicon or another conductive material, which is formulated relative to dielectric material 108 and exhibits etch selectivity relative to one or more materials in the post 110 in some embodiments. In some embodiments, conductive material 122 is formed of and comprises polysilicon. In some embodiments, conductive material 122 is electrically connected to (e.g., in electrical communication with) channel material 114. In some embodiments, conductive material 122 may comprise doped polysilicon. In some embodiments, conductive material 122 is doped with one or more n-type dopants, such as phosphorus. In some embodiments, conductive material 122 is lightly doped d (e.g., at a concentration of about 1 x 10⁻⁶). 18 (atoms / cubic centimeter). Alternatively, in some embodiments, the insulating material may be formed within the recess. In such embodiments, the insulating material may then be perforated to form a connection with the channel material 114.

[0054] After the conductive material 122 is formed, the microelectronic device structure 100 may undergo a chemical mechanical planarization (CMP) process to remove the conductive material from the outer surface of the recess (e.g., on the upper surface of the dielectric material 108).

[0055] Also refer to Figures 1D-1F After the conductive material 122 is formed, another stacked structure 105 (e.g., upper stacked structure, selected gate drain (SGD) stacked structure) may be formed on top of the stacked structure 101 (which may also be referred to herein as a "second stacked structure"). Figure 1D Is it through Figure 1E A simplified cross-sectional view of the microelectronic device structure 100 taken by the cross-section line DD. Figure 1E This is a top view of a portion of the microelectronic device structure 100, showing the corresponding... Figure 1B The portion of the microelectronic device structure 100 located at frame E. Figure 1E In the diagram, the guide pillars 110 are shown in dashed lines, indicating that they are located below the upper surface of the microelectronic device structure 100. Figure 1F Is it through Figure 1EA simplified partial cross-sectional view of the microelectronic device structure 100, taken through the cross-section line FF. It has been confirmed that the cross-section taken through the second line FF will contain, relative to... Figure 1D The guide post 110 is narrowed; however, Figure 1D and 1F The guide post 110 in the figure is shown as the same, so as to better illustrate the structure of the guide post 110.

[0056] refer to Figure 1D and 1F Other stacked structures 105 may comprise alternating layers of insulating structures 104 and additional insulating structures 106 formed over etch-stop material 125. These alternating layers of insulating structures 104 and additional insulating structures 106 may be arranged as layer 124. The dielectric material 108 between stacked structures 101 and other stacked structures 105 may be referred to as inter-stack region 111. Other stacked structures 105 may include an uppermost insulating structure 129, which has a greater thickness in the vertical direction (e.g., in the Z direction) than the other insulating structures 104 of the other stacked structures 105.

[0057] The etch stop material 125 may be formed of and comprise a material exhibiting etch selectivity relative to insulating structure 104 and other insulating structures 106. In some embodiments, the etch stop material 125 may comprise a carbon-containing material (e.g., silicon carbonitride (SiCN)). In some such embodiments, the etch stop material 125 may facilitate an improvement in the electric field in the channel region adjacent to the etch stop material 125 during use and operation of the microelectronic device structure 100. In some embodiments, the microelectronic device structure 100 may not include the etch stop material 125 between the stacked structure 101 and other stacked structures 105. In some such embodiments, a dielectric material 108 may be interposed between the stacked structure 101 and other stacked structures 105.

[0058] Special Reference Figure 1F Due to manufacturing limitations, the stacked structure 101 and its guide pillars 110 (e.g., the lower guide pillar) may exhibit guide pillar misalignment or bending, causing the central longitudinal axis of the guide pillars 110 of the microelectronic device structure 100 to deviate from an ideal, true vertical central longitudinal axis. As a non-limiting example, the guide pillars 110 may be tilted or bent, deviating from their true vertical orientation. For example, the bottom portion of a given guide pillar 110 may be ideally positioned and formed therein, but due to guide pillar bending, the top portion of a given guide pillar 110 may not be vertically aligned with the bottom surface of the guide pillar. In some embodiments, the stacked structure 101 and its guide pillars 110 may exhibit guide pillar misalignment or bending in a direction indicated as the "guide pillar bending direction" (e.g., the Y direction). To better illustrate alignment, Figure 1FThe guide post 110 is shown to have a true vertical orientation; however, it should be understood that the guide post 110 of the microelectronic device structure 100 may exhibit guide post misalignment or guide post bending as described herein.

[0059] After the other stacked structures 105 are formed, a first opening 126 and a second opening 127 (collectively referred to as openings 126, 127) may be formed through the other stacked structures 105 to the conductive material 122. The first opening 126 and the second opening 127 may be formed using markers (e.g., chromium etching on a glass plate). For example, markers (not shown) defining the arrangement of the first opening 126 and the second opening 127 may be used to pattern, for example, a rigid mask structure (e.g., an etch-stop material) using an exposure device having the arrangement of the first opening 126 and the second opening 127, and the rigid mask structure may be used to transfer (e.g., etch) the pattern of the first opening 126 and the second opening 127 through the other stacked structures 105 to define the first opening 126 and the second opening 127 in the other stacked structures 105.

[0060] In some embodiments, the markings used to form the first opening 126 and the second opening 127 may include a first custom marking. Specifically, the first custom marking may include progressive markings designed and manufactured at least in part based on the formation progress of the microelectronic device structure 100 and its components (e.g., guide pillars 110). For example, the first custom marking may include a pattern customized (e.g., designed) to compensate for guide pillar misalignment and / or guide pillar bending exhibited relative to actual vertical guide pillars within the microelectronic device structure 100 (e.g., at the interface between stacked structures 101 and other stacked structures 105).

[0061] In some embodiments, the first custom markings may be designed and manufactured at least in part based on received data regarding the microelectronic device structure 100 (referred to herein as "structure data"). In some embodiments, the structure data may be received from a wafer testing system. For example, previously manufactured microelectronic device structures and / or the current microelectronic device structure 100 may be tested, evaluated, and / or analyzed using conventional methods to identify post misalignment and / or post bending. As a non-limiting example, through testing and analysis, the first custom markings may be designed and manufactured based on data received regarding the microelectronic device structure 100. Figure 1A-1CDuring the formation of the described microelectronic device structure 100, guide post misalignment and / or guide post bending are observed in one or more previously manufactured microelectronic device structures and / or the current microelectronic device structure 100. The observed guide post misalignment and / or guide post bending can be represented in received structural data, and a first custom marker can be designed, manufactured, and / or otherwise provided at least in part based on the observed guide post misalignment and / or guide post bending. Furthermore, the first custom marker can be designed, manufactured, and / or otherwise provided during the formation of the first opening 126 and the second opening 127 to compensate for (e.g., offset) the observed guide post misalignment and / or guide post bending. Therefore, the upper guide post structure 135 is formed therein using the first custom marker. Figure 1I The first opening 126 and the second opening 127 of the microelectronic device structure 100 can improve the physical and electrical connections between the elements of other stacked structures 105 and stacked structures 101, as described in more detail below.

[0062] Still referencing Figure 1D-1F In some embodiments, the degree of misalignment and / or bending of the guide post observed in the X and / or Y directions (e.g., the misalignment and / or bending exhibited by guide post 110 and / or conductive material relative to the true vertical orientation) is considered. Figure 1E As indicated, the pattern of the first custom marking line may be designed, manufactured, and / or otherwise provided in the X and / or Y directions (e.g., adjusted relative to a marking line used for true vertical orientation (referred to herein as a "non-custom marking line")) during the formation of the first opening 126 and the second opening 127 to counteract observed guide post misalignment and / or guide post bending. For example, the pattern of the first custom marking line may be adjusted relative to a non-custom marking line (e.g., a glass-on-glass chrome ("COG") line) by the same or similar amount to counteract the observed guide post misalignment and / or guide post bending. As a non-limiting example, if a guide post bending of approximately 55 nm in the Y direction is observed between stacked structure 101 and other stacked structures 105 (e.g., at the interface between stacked structure 101 and other stacked structures 105), then the pattern of the first custom marking line used to form the first opening 126 and the second opening 127 may be adjusted relative to the non-custom marking line in the Y direction by approximately 55 nm. Although this document describes specific amounts of guide post misalignment and / or bending, this disclosure is not limited thereto; rather, a first custom guideline may be designed and manufactured to compensate for observed amounts of guide post misalignment and / or bending.

[0063] In some embodiments, the entire pattern of the first custom marking can be adjusted as a whole based on individual guide post misalignment and / or guide post bending observed within the microelectronic device structure 100 during manufacturing. In other embodiments, each portion of the pattern of the first custom marking representing a block of the microelectronic device structure 100 can be adjusted individually during manufacturing based on guide post misalignment and / or guide post bending observed within the guide posts of the corresponding block of the microelectronic device structure 100. In additional embodiments, each portion of the pattern of the first custom marking representing a region of the microelectronic device structure 100 (e.g., an edge region, a middle region, etc.) can be adjusted individually during manufacturing based on guide post misalignment and / or guide post bending observed within the guide posts of the corresponding region of the microelectronic device structure 100. In still other embodiments, each portion of the pattern of the first custom marking representing the first opening 126 or the second opening 127 can be adjusted individually during manufacturing based on guide post misalignment and / or guide post bending observed within the corresponding guide post of the microelectronic device structure 100.

[0064] In view of the foregoing, since the first custom marking is designed, manufactured and / or otherwise provided based on guide post misalignment and / or guide post bending observed within the microelectronic device structure 100, the first opening 126 and the second opening 127 may also be designed, manufactured and / or otherwise provided based on guide post misalignment and / or guide post bending observed within the microelectronic device structure 100.

[0065] In some embodiments, the first custom marker can be formed in real time (i.e., designed and manufactured). For example, structural data may be received, and the first custom marker may be formed during the process of forming the microelectronic device structure 100. In other embodiments, the custom marker may be formed for observed and / or anticipated lead misalignment and / or lead bending, and the first custom marker may be selected from the formed custom marker and used to form the first opening 126 and the second opening 127 of the microelectronic device structure 100. For example, the first custom marker may be selected based on observed lead misalignment and / or lead bending in the structural data and / or based on anticipated lead misalignment and / or lead bending within the microelectronic device structure 100.

[0066] In some embodiments, the first opening 126 and the second opening 127 may be formed via a first custom marking such that the central axis 180 of the first opening 126 and the second opening 127 is at least substantially horizontally aligned with the central axis 181 of the corresponding conductive material 122 and / or the guide post 110 at the interface between the guide post 110 and the first opening 126 and the second opening 127 in at least one direction (e.g., the Y direction). Figure 1F As shown in the image.

[0067] Additionally, in some embodiments, the central axis 180 of the first opening 126 is offset relative to the central axis 181 of the guide post 110 in the X direction, and the central axis 180 of the second opening 127 is aligned with the central axis 181 of the guide post 110 in the X direction, such as... Figure 1D As shown in the diagram. In other embodiments, the second opening 127 is horizontally offset relative to the center of the base post 110 in the X direction, but the degree of offset is less than that of the first opening 126. As will be described herein, the first opening 126 may be adjacent to (e.g., located in the vicinity of) a slot structure that divides the block structure of the microelectronic device structure 100 into one or more sub-block structures.

[0068] refer to Figure 1E In some embodiments, a first opening 126 is arranged in column 109 (e.g., extending in the Y direction), and a second opening 127 is arranged in column 109 horizontally adjacent to the column 109 of the first opening 126. In some such embodiments, the first opening 126 may be horizontally aligned with other first openings 126 in the same column 109 (e.g., in the X direction), and the second opening 127 may be horizontally aligned with other second openings 127 in the same column 109 (e.g., in the X direction).

[0069] After forming the first opening 126 and the second opening 127, a padding material 128 may be formed over the surfaces (e.g., sidewalls) of the first opening 126 and the second opening 127. The padding material 128 may be formed of and contain an insulating material, such as one or more of the materials described above with reference to insulating material 112. In some embodiments, the padding material 128 may contain silicon dioxide. In some embodiments, after forming the padding material 128, the padding material 128 may undergo so-called “penetration etching” to remove a portion of the padding material 128 and expose a portion of the conductive material 122. In some embodiments, a portion of the conductive material 122 may also be removed.

[0070] Now for reference Figure 1G and 1H The channel material 130 can be formed above the side of the pad material 128 and can be electrically connected to the channel material 114 through the conductive material 122. Figure 1G From and Figure 1D A simplified cross-sectional view of the microelectronic device structure 100 from the same perspective. Figure 1H From and Figure 1FA simplified cross-sectional view of the microelectronic device structure 100 from the same perspective. The channel material 130 may include one or more of the materials described above with reference to channel material 114. In some embodiments, the channel material 130 may contain the same material composition as channel material 114. In some embodiments, the channel material 130 may extend substantially continuously from channel material 114. Because the channel material 130 may contain the same material composition as channel material 114 and is electrically connected to channel material 114 via conductive material 122, channel material 114, conductive material 122, and channel material 130 may be collectively referred to as the channel region as used herein.

[0071] refer to Figure 1I and 1J After the channel material 130 is formed, an insulating material 134 can be formed between the channel materials 130 in the remaining portions of the openings 126, 127 to form a first upper guide post structure 135 and a second upper guide post structure 137 in the respective first opening 126 and second opening 127. Figure 1I From and Figure 1D A simplified cross-sectional view of the microelectronic device structure 100 from the same perspective. Figure 1J From and Figure 1F A simplified cross-sectional view of the microelectronic device structure 100 from the same perspective. Insulating material 134 may be vertically overlaid (e.g., in the Z direction) on channel material 130, for example, vertically overlaid on the horizontal extension of channel material 130 above conductive material 122.

[0072] The insulating material 134 may be formed from and comprise one or more of the materials described above with reference to insulating material 112. In some embodiments, the insulating material 134 may comprise a material composition substantially the same as that of insulating material 112. In some embodiments, the insulating material 134 may comprise silicon dioxide. In some embodiments, the microelectronic device structure 100 undergoes a planarization process, such as a CMP process, after the insulating material 134 is formed.

[0073] In view of the foregoing, since the central axis 180 of the first opening 126 and the second opening 127 is at least substantially horizontally aligned with the central axis 181 of the corresponding conductive material 122 and / or the guide post 110 at the interface between the guide post 110 and the first opening 126 and the second opening 127 in at least one direction (e.g., the Y direction), the first upper guide post structure 135 and the second upper guide post structure 137 (e.g., the center of the first upper guide post structure 135 and the second upper guide post structure 137) can also be at least substantially horizontally aligned with the central axis 181 of the corresponding conductive material 122 and / or the guide post 110 at the interface between the guide post 110 and the upper guide post structures 135, 137 in at least one direction (e.g., the Y direction). Figure 1J As shown in the image.

[0074] In some embodiments, the first upper guide post structure 135 may be horizontally offset (e.g., in the X direction) relative to the center of the guide post 110 of the vertical foundation (e.g., in the Z direction). The second upper guide post structure 137 may be horizontally aligned with the center of the guide post 110 of the vertical foundation (e.g., in the Z direction) (e.g., in each of the X and Y directions). In some embodiments, the second upper guide post structure 137 may be horizontally offset relative to the center of the vertical foundation guide post 110, but the offset is less than the horizontal offset of the first upper guide post structure 135 relative to the vertical foundation guide post 110.

[0075] Now for reference Figure 1K and 1L After the insulating material 134 is formed, at least a portion of the insulating material 134 may optionally be recessed from the upper guide post structures 135, 137 to form a recess. Figure 1K From and Figure 1D A simplified cross-sectional view of the microelectronic device structure 100 from the same perspective. Figure 1L From and Figure 1F A simplified cross-sectional view of the microelectronic device structure 100 from the same perspective. Recesses may be filled with additional channel material to form a horizontal extension 136 of channel material 130. The additional channel material may include the same material composition as channel material 130.

[0076] Common Reference Figure 1M and Figure 1N After the horizontal extension 136 of the channel material 130 is formed, the groove 133 can be formed through other stacked structures 105 and stacked structures 101. Figure 1M Is it through Figure 1NThe image shows a simplified partial cross-sectional view of the microelectronic device structure 100 taken by the cross-sectional line MM. The trench 133 may be referred to herein as a so-called "replacement gate" trench, through which other insulating structures 106 are subsequently removed. In some embodiments, the trench 133 is exposed at at least a portion of the source structure 103.

[0077] refer to Figure 1N The microelectronic device structure 100 may include slots 133 that are horizontally spaced apart from each other (e.g., in the X direction) by a plurality of columns 109 of guide pillars 110 and upper guide pillar structures 135, 137. The microelectronic device structure 100 may be divided into block structures 140 between horizontally adjacent (e.g., in the X direction) slots 133. Although Figure 1N Only one block structure 140 is shown, but it should be understood that the microelectronic device structure 100 may contain several block structures 140. As will be described herein, a block structure 140 may be divided into one or more sub-block structures.

[0078] Return to reference Figure 1M After trench 133 is formed, other insulating structures 106 of the stacked structure 101 can be removed through trench 133 as part of a so-called "gate replacement" or "gate persistence" process. As a non-limiting example, other insulating structures 106 can be removed by exposing them to one or more etchants (e.g., wet etchants) including phosphoric acid, sulfuric acid, hydrochloric acid, nitric acid, or another material. In some embodiments, other insulating structures 106 are removed by exposing them to a so-called "wet nitride stripe" including phosphoric acid. In some embodiments, other insulating structures 106 of the stacked structure 101 and other stacked structures 105 can be removed through trench 133 substantially simultaneously.

[0079] Common Reference Figure 10 and 1P After removing other insulation structures 106 ( Figure 1M Subsequently, conductive structures 142 may be formed between adjacent insulating structures 104 at positions corresponding to previous positions of other insulating structures 106, to form a stacked structure 101 comprising layers 144 having alternating levels of insulating structures 104 and conductive structures 142, and another stacked structure 105 comprising layers 144 having alternating levels of insulating structures 104 and additional conductive structures 145 (which may include the same material composition as conductive structures 142). For clarity, the insulating structures 104 of the other stacked structures 105 may be referred to herein as additional insulating structures 104. Figure 10 From and Figure 1M A simplified cross-sectional view of the microelectronic device structure 100 from the same perspective. Figure 1P From and Figure 1LA simplified cross-sectional view of the microelectronic device structure 100 from the same perspective. The conductive structure 142 of the stacked structure 101 can be used as a local word line structure (e.g., local or word line). Additional conductive structures 145 of other stacked structures 105 can be used as select gate structures, such as select gate drain (SGD) structures.

[0080] The conductive structure 142 and the additional conductive structure 145 may each be formed of and contain a conductive material, such as at least one conductive material, such as tungsten, titanium, nickel, platinum, rhodium, ruthenium, iridium, aluminum, copper, molybdenum, silver, gold, metal alloys, metallic materials (e.g., metal nitrides, metal silicides, metal carbides, metal oxides), including titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN), iridium oxide (IrO). x ), Ruthenium oxide (RuO) x The materials comprising at least one of the alloys, conductive doped semiconductor materials (e.g., conductive doped silicon, conductive doped germanium, conductive doped silicon-germanium, etc.), polycrystalline silicon, other materials exhibiting electrical conductivity, or combinations thereof. In some embodiments, conductive structure 142 and additional conductive structure 145 may comprise tungsten.

[0081] In some embodiments, the conductive structure 142 may include a conductive liner material (not shown) surrounding the conductive structure 142 (e.g., between the conductive structure 142 and the insulating structure 104). Additionally, an additional conductive structure 145 may include a conductive liner material (not shown) surrounding the additional conductive structure 145 (e.g., between the additional conductive structure 145 and the insulating structure 104). The conductive liner material may include, for example, a seed material, from which the conductive structure 142 and the additional conductive structure 145 may be formed. The conductive liner material may be formed from and include, for example, a metal (e.g., titanium, tantalum), a metal nitride (e.g., tungsten nitride, titanium nitride, tantalum nitride), or another material. In some embodiments, the conductive liner material may include titanium nitride.

[0082] The formation of conductive structure 142 can form a string 160 of memory cells 162. The memory cells 162 in the string 160 can be located at the intersection of post 110 and conductive structure 142, and can each include a portion of post 110 and a portion of conductive structure 142. Vertically adjacent memory cells 162 in the string 160 can be separated from each other by a layer in insulating structure 104.

[0083] After forming conductive structure 142 and additional conductive structure 145, trench 133 can be filled with dielectric material 146. Dielectric material 146 can extend through other stacked structures 105 and 101. Therefore, dielectric material 146 can connect adjacent (e.g., neighboring) block structures 140 of the microelectronic device structure 100. Figure 1N They are physically separated.

[0084] The dielectric material 146 may include one or more of the materials described above with reference to the insulating material 112. In some embodiments, the dielectric material 146 may have a material composition substantially the same as that of the insulating material 112. In some embodiments, the dielectric material 146 may comprise silicon dioxide.

[0085] Now for joint reference Figure 1Q - Figure 1S After the trench 133 is filled with dielectric material 146, an additional trench 148 may be formed through layers 144 of other stacked structures 105 having alternating levels of insulating structure 104 and additional conductive structure 145. In some embodiments, the additional trench 148 is formed by sequentially removing layers 144 of insulating structure 104 and additional conductive structure 145. Figure 1Q yes Figure 1R A simplified cross-sectional view of the microelectronic device structure 100 is obtained by cutting through the cross-section line QQ. Figure 1S yes Figure 1R An enlarged top view of the microelectronic device structure 100, depicting... Figure 1R Region S.

[0086] In some embodiments, the additional slot 148 terminates within the bottommost layer of the layers 144 of the other stacked structures 105. In some such embodiments, the additional conductive structure 145 of the bottommost layer 144 of the other stacked structures 105 may be substantially continuous within the block structure 140 and may be continuous, for example, with the conductive structure 142 of the stacked structure 101. In contrast, the additional slot 148 may divide the additional conductive structure 145 of the layers 144 of the other stacked structures 105 (other than the bottommost layer 144) into distinct portions, such that the additional conductive structure 145 is not substantially continuous within the block structure 140. Instead, such additional conductive structure 145 may be divided by the additional slot 148.

[0087] In some embodiments, the lowermost additional conductive structure 145 may include a so-called "dummy" word line structure. When using and operating the microelectronic device structure 100, a voltage may be applied to the lowermost additional conductive structure 145, which may facilitate improved current flow through the channel material 130 horizontally adjacent to the lowermost additional conductive structure 145 and through the inter-stack region 111. Consecutive lowermost additional conductive structures 145 may facilitate voltage application at locations near substantially all first upper post structures 135 and second upper post structures 137 within the block structure 140. Additionally, in some embodiments, the uppermost conductive structure 142 of the stack structure 101 may include a dummy word line structure. Similarly, the application of voltage to the uppermost conductive structure 142 may facilitate improved current flow through the channel material 130 adjacent to the inter-stack region 111.

[0088] Continue to refer to Figure 1Q - Figure 1S The additional slot 148 may extend vertically over at least a portion of each post 110 adjacent to the additional slot 148 (e.g., in the Z direction). The additional slot 148 may be sized and shaped to facilitate electrical isolation of the additional conductive structure 145 and may be physically spaced apart from the upper post structures 135, 137.

[0089] The additional slot 148 may exhibit a so-called "woven" pattern, wherein the additional slot 148 is not defined by a generally straight line (e.g., extending in the Y direction). Instead, the additional slot 148 may be configured to extend between adjacent columns of the guide post 110 and the upper guide post structure 135, and may exhibit a non-linear shape (e.g., a wave-like and / or sinusoidal shape) to at least partially conform to the layout (e.g., shape) of the string 160 of the memory cells 162 and the first upper guide post structure 135. For example, the additional slot 148 may include a crest region 165 (e.g., a protruding region) extending in a direction away from the horizontally adjacent (e.g., in the X direction) guide post 110 and upper guide post structure 137, and may include a corresponding trough region 167 (e.g., a recessed region) horizontally adjacent (e.g., in the X direction) to the crest region 165.

[0090] As mentioned above Figure 1D-1F As described, the first custom marking can be used to counteract and / or compensate for post misalignment and / or post bending within the microelectronic device structure 100. Similarly, the formation of the additional slot 148 can be customized and / or performed based at least in part on observed post misalignment and / or post bending within the microelectronic device structure 100. As a non-limiting example, the formation of the additional slot 148 can be customized (e.g., shifted) based at least in part on observed post misalignment and / or post bending, such that the center 185 of the trough region 167 (e.g., recessed region) of the additional slot 148 ( Figure 1S In the Y direction, it is at least substantially horizontally aligned with the central axis 187 of the upper guide post structure 135, which is horizontally adjacent to the additional slot 148, such as... Figure 1R and 1S As depicted in the text.

[0091] As a non-limiting example, the formation of the additional slot 148 can be customized in a manner similar to that of the first custom marker, as described above. Figure 1D-1FAs described above. Specifically, the position of the additional slot 148 in the Y direction (or the direction of observed post misalignment and / or post bending) (e.g., the position of the crest region 165 and the trough region 167) can be determined and / or designed, at least in part, based on post misalignment and / or post bending observed according to the structural data described above. For example, if a post bending of approximately 55 nm in the Y direction is observed at the interface between stacked structure 101 and other stacked structures 105, then the position of the additional slot 148 in the Y direction can be determined and / or designed to differ from an ideal position (e.g., an ideal position within a microelectronic device structure where no post misalignment and / or post bending is present) by approximately 55 nm in the Y direction. For instance, the positions of the crest region 165 and the trough region 167 can be adjusted by approximately 55 nm in the Y direction such that the trough region 167 is at least substantially horizontally aligned with the central axis 187 of the upper post structure 135 horizontally adjacent to the additional slot 148 in the Y direction. In some embodiments, the position of the additional slot 148 in one or more directions may be customized by the same amount as the positions of the first opening 126 and the second opening 127 in those directions. In other embodiments, the position of the additional slot 148 in one or more directions may be customized by a different amount than the positions of the first opening 126 and the second opening 127 in those directions. In view of the foregoing, a progressive approach can be used to form the additional slot 148 of the microelectronic device structure 100.

[0092] In view of the foregoing, the position of the additional slot 148 in one or more directions may be determined at least in part based on observed guide post misalignment and / or guide post bending. In an additional embodiment, the XY plane (e.g., Figure 1R The shape and / or pattern (e.g., the shape of a braided pattern) of the additional slot 148 (as depicted in the view) may be determined at least in part based on observed guide post misalignment and / or guide post bending. For example, the frequency, wavelength, and amplitude of the braided pattern may be determined at least in part based on observed guide post misalignment and / or guide post bending. In other embodiments, the location and shape of the additional slot 148 may both be determined at least in part based on observed guide post misalignment and / or guide post bending. After the location and / or shape of the additional slot 148 are determined, the additional slot 148 may be formed via any conventional process.

[0093] Additional slot 148 may be located at a horizontally offset (e.g., non-concentric) first upper guide pillar structure 135 and a corresponding string 160 of memory cell 162 directly below the first upper guide pillar structure 135 (e.g., the first upper guide pillar structure 135 is formed by a first opening 126). Figure 1IThe additional slots 148 can be formed with a larger horizontal dimension by forming the first upper guide pillar structure 135 adjacent to (e.g., adjacent to) the additional slots 148, without being too close to or requiring the removal of portions of the upper guide pillar structure 135. Furthermore, the weave pattern of the additional slots 148 and the horizontal offset of the first upper guide pillar structure 135 facilitate the formation of block structures 140 with relatively smaller horizontal dimensions between the slots 133 compared to conventional microelectronic devices. For example, in conventional microelectronic devices, additional slots can be formed through some upper guide pillar structures (e.g., columns of upper guide pillar structures), thereby reducing the total number of upper guide pillar structures that can fit within a given horizontal dimension between adjacent slots 148.

[0094] refer to Figure 1R The additional slot 148 can divide the block structure 140 into sub-block structures 150, each sub-block structure being confined within a horizontal boundary between adjacent additional slots 148.

[0095] Now for joint reference Figure 1T-1V After the additional groove 148 is formed, the additional groove 148 can be filled with dielectric material 152. Figure 1T From and Figure 1Q A simplified cross-sectional view of the microelectronic device structure 100 from the same perspective. Figure 1U From and Figure 1P Another simplified cross-sectional view of the microelectronic device structure 100 from the same perspective. Figure 1V This is a magnified top view of the microelectronic device structure 100, and is in comparison with... Figure 1S Depicted from the same perspective. Additionally, one or more materials and structures are used... Figure 1V The inner portions are shown as transparent and / or removed to better depict the vertical alignment of the components of the microelectronic device structure 100. Dielectric material 152 may comprise one or more of the materials described above with reference to dielectric material 146. In some embodiments, dielectric material 152 may comprise substantially the same material composition as dielectric material 146. In some embodiments, dielectric material 152 may comprise silicon dioxide.

[0096] After the dielectric material 152 is formed within the additional trench 148, the dielectric material 152 located outside the additional trench 148 can be removed, for example, by subjecting the microelectronic device structure 100 to a CMP process. An etch-stop material 154 (e.g., a hard mask material) may be formed over the microelectronic device structure 100. The etch-stop material 154 may include one or more of the materials described above with reference to etch-stop material 125. In some embodiments, the etch-stop material 154 may contain substantially the same material composition as the etch-stop material 125. In some embodiments, the etch-stop material 154 may contain a carbon-containing material (e.g., silicon carbonitride (SiCN)).

[0097] Continue to refer to Figure 1T-1V An elliptical opening 156 can be formed through the etch-stop material 154 to expose the upper portion of each upper guide post structure 135, such as at least the upper surface of the horizontal extension 136 of the channel material 130 of the upper guide post structure 135.

[0098] Similar to the above about Figure 1D-1F The first opening 126 and the second opening 127 described herein, and the elliptical opening 156, can be formed using markings (e.g., chromium etching on a glass plate). For example, markings (not shown) designed for forming elliptical openings can be used to pattern, for example, an etch-stopping material 154 via an exposed device having the arrangement and shape of the elliptical opening 156. In other words, markings can be used to form the elliptical opening 156 through the etch-stopping material 154.

[0099] Furthermore, the markings used to form the elliptical opening 156 may include a second custom marking. For example, the second marking may include a progressive marking designed and manufactured (i.e., custom-made) at least in part based on the formation progress of the microelectronic device structure 100 and its components (e.g., guide pillars 110). Specifically, the second custom marking may include a pattern custom-made (e.g., designed) to compensate for and / or counteract guide pillar misalignment and / or guide pillar bending exhibited within the stacked structure 101 and / or other stacked structures 105. For example, the second custom marking may include a pattern custom-made to form an elliptical opening that allows the formation of contact with the corresponding upper guide pillar structure 135 (e.g., the upper surface of the horizontal extension 136 of the channel material 130 of the upper guide pillar structure 135) and the subsequently formed access line 191. Figure 1X The elliptical conductive contact 158 ​​of both (e.g., forming an electrical connection with them) Figure 1W The access lines have a fixed position and orientation within the microelectronic device structure 100, even if the microelectronic device structure 100 exhibits guide post misalignment and / or guide post bending. For example, a second custom marking may include a custom-designed line to form across the uppermost surface of the upper guide post structure 135 and a corresponding access line 191. Figure 1X A pattern of elliptical openings at a horizontal distance between ) .

[0100] In some embodiments, the second custom marking may be at least partially based on the above regarding Figure 1D-1FThe received structural data is described for customization. For example, as discussed above, guide post misalignment and / or guide post bending may be observed in one or more previously manufactured microelectronic device structures and / or the current microelectronic device structure 100, and structural data indicating observed guide post misalignment and / or guide post bending may be received and used to customize a second customized marker. Specifically, the second customized marker may be designed, manufactured, and / or otherwise provided based at least in part on the observed guide post misalignment and / or guide post bending. In some embodiments, the second customized marker may be designed, manufactured, and / or otherwise provided to form a vertical line that at least partially overlaps with the formed upper guide post structure 135 and a vertical line that overlaps with the subsequently formed access line 191. Figure 1X The elliptical opening 156 at least partially overlaps with the position of the access line 191 (formed later in the microelectronic device structure 100). Figure 1X An elliptical conductive contact 158 ​​is formed between the upper guide pillar structure 135 of the microelectronic device structure 100 and the upper guide pillar structure 135 of the microelectronic device structure 100. Figure 1W When the second custom-designed guideline is designed, manufactured, and / or otherwise provided to form an elliptical opening 156, it compensates for and / or counteracts observed guide post misalignment and / or guide post bending. Therefore, the use of the second custom-designed guideline improves the relationship between the first upper guide post structure 135 and the second upper guide post structure 137 of the microelectronic device structure 100 and the access line 191. Figure 1X The connections between ) are described in more detail below.

[0101] Still referencing Figure 1T-1V Based on the observed misalignment and / or bending of the guide posts in the X and / or Y directions (e.g., misalignment and / or bending of guide post 110 relative to a completely vertical orientation), the pattern of the second custom marking line can be designed, manufactured, and / or otherwise provided. Specifically, the pattern of the second custom marking line can be designed, manufactured, and / or otherwise provided to form an elliptical opening 156 of a specific size. For example, the principal axis and minor axis of the ellipse defined by the elliptical opening 156 can be determined based on the observed misalignment and / or bending of the guide posts. As a non-limiting example, the observed misalignment and / or bending of the guide posts in the Y direction can at least partially determine the principal axis of the ellipse defined by the corresponding elliptical opening 156. For instance, the greater the observed misalignment and / or bending of the guide posts in the Y direction, the larger the principal axis of the ellipse can be, thereby ensuring the upper guide post structure 135 of the microelectronic device structure 100 and the subsequently formed access line 191 (… Figure 1X The two are connected via elliptical conductive contacts 158 formed within corresponding elliptical openings 156. Figure 1WThe contact between the lead post and the access line 191 is determined by the lead post misalignment and / or lead post bending observed in the X direction. Similarly, the amount of lead post misalignment and / or lead post bending observed in the X direction can at least partially determine the minor axis of the ellipse defined by the corresponding elliptical opening 156. For example, the greater the lead post misalignment and / or lead post bending observed in the X direction, the larger the minor axis can be, thereby ensuring the upper lead post structure 135 of the microelectronic device structure 100 and the subsequently formed access line 191. Figure 1X The two are connected via elliptical conductive contacts 158 formed within corresponding elliptical openings 156. Figure 1W ) contact.

[0102] In some embodiments, the principal axis of the ellipse defined by the elliptical opening 156 may extend in the same direction as the word line structure (e.g., conductive structures 142, 145) of the microelectronic device structure 100. For example, the principal axis of the ellipse defined by the elliptical opening 156 may extend perpendicular to the access line 191 of the microelectronic device structure 100. Figure 1X The ellipse extends in the direction of its extension. Furthermore, the minor axis of the ellipse defined by the elliptical opening 156 may extend in the access line 191 of the microelectronic device structure 100. Figure 1X The ellipse extends in the same direction as the extension. For example, the minor axis of the ellipse defined by the elliptical opening 156 may extend in a direction perpendicular to the extension direction of the word line structure (e.g., conductive structures 142, 145) of the microelectronic device structure 100.

[0103] In some embodiments, the second custom marker can be formed in real time (i.e., designed and manufactured). For example, structural data may be received, and the second custom marker may be formed during the process of forming the microelectronic device structure 100. In other embodiments, the custom marker may be formed for observed and / or typical lead misalignment and / or lead bending amounts, and the second custom marker may be selected from the formed custom marker and used to form the elliptical opening 156 of the microelectronic device structure 100. For example, the second custom marker may be selected based on observed lead misalignment and / or lead bending in the structural data and / or based on expected lead misalignment and / or lead bending within the microelectronic device structure 100.

[0104] In some embodiments, the center of the ellipse defined by the elliptical opening 156 may be offset relative to the central axis of both the guide post 110 and the upper guide post structure 135 in one or more of the Y and X directions. Additionally, the center of the ellipse defined by the elliptical opening 156 may be offset relative to the ideal central axis of both the guide post 110 and the upper guide post structure 135 in one or more of the Y and X directions.

[0105] Now for reference Figure 1W and 1XAfter forming the elliptical opening 156, elliptical conductive contacts 158 (e.g., elliptical conductive contacts 158 having an elliptical cross-section in the XY plane) can be formed above and electrically communicated with the channel material 130, and are at least partially within the elliptical opening 156. As mentioned above, the elliptical conductive contacts 158 can be electrically coupled to access lines 191 (e.g., bit lines) configured to selectively couple to strings 160 of memory cells 162. Figure 1X Additionally, the elliptical conductive contact 158 ​​may be formed at least partially within the elliptical opening 156, and thus the elliptical conductive contact 158 ​​may have an elliptical cross-section in the XY plane.

[0106] The elliptical conductive contact 158 ​​may include a conductive material, such as one or more of the materials described above with reference to the conductive structure 142. In some embodiments, the elliptical conductive contact 158 ​​may contain substantially the same material composition as the conductive structure 142. In some embodiments, the elliptical conductive contact 158 ​​may contain tungsten.

[0107] Common Reference Figure 1A-1X Forming a first opening 126 and a second opening 127 using a first custom marking based on observed guide post misalignment and / or guide post bending, customizing an additional groove 148 based on observed guide post misalignment and / or guide post bending, and forming an elliptical opening 156 using a second custom marking based on observed guide post misalignment and / or guide post bending are advantageous compared to conventional methods of forming microelectronic device structures 100. For example, compared to conventional methods and structures that exhibit guide post misalignment and / or guide post bending, forming the first opening 126 and the second opening 127 using a first custom marking based on observed guide post misalignment and / or guide post bending can improve the overlap between the guide post 110 and the upper guide post structure 135. Therefore, the electrical connection between the guide post 110 and the upper guide post structure 135 can be improved.

[0108] Furthermore, compared to conventional methods and structures that demonstrate guide post misalignment and / or guide post bending, customizing the additional groove 148 based on observed guide post misalignment and / or guide post bending can reduce interference between the additional groove 148 and the upper guide post structure 135. Additionally, customizing the additional groove 148 based on observed guide post misalignment and / or guide post bending can improve the orientation of the additional groove 148 relative to the upper guide post structure 135.

[0109] Furthermore, compared to conventional methods and structures that demonstrate post misalignment and / or post bending, forming an elliptical opening 156 using a second custom marker based on observed post misalignment and / or post bending improves the overlap between the elliptical conductive contact 158 ​​and the upper post structure 135, and thus improves the electrical connection between the elliptical conductive contact 158 ​​and the upper post structure 135. Additionally, forming an elliptical opening 156 using a second custom marker based on observed post misalignment and / or post bending improves the overlap between the elliptical conductive contact 158 ​​and the access line 191 (e.g., a bit line), which has a fixed position within the microelectronic device structure 100, even when the microelectronic device structure 100 exhibits post misalignment and / or post bending. For example, the offset position of the elliptical opening 156 and the elliptical conductive contact 158 ​​relative to the annular shape and the offset position of the elliptical opening 156 relative to the upper guide post structure 135 (e.g., in the Y direction (i.e., the direction of guide post bending)) improves the overlap between the elliptical conductive contact 158 ​​and the access line 191 (e.g., bit line).

[0110] Still for reference Figure 1A-1X Compared to conventional methods and structures, the methods and embodiments described herein reduce the dummy pillar region of the microelectronic device structure 100 because the overlap between the lead post 110 and the upper lead post structure 135 is improved by using a first custom marker, the overlap between the elliptical conductive contact 158 ​​and the upper lead post structure 135 is improved, and the overlap between the elliptical conductive contact 158 ​​and the access line 191 is improved. Specifically, dummy pillars are typically included within the microelectronic device structure 100 to mitigate or reduce lead post bending. Therefore, because lead post bending is accommodated in the embodiments described herein, the dummy pillar region of the microelectronic device structure 100 can be significantly reduced or eliminated. As a non-limiting example, in a microelectronic device structure exhibiting a lead post bending of 55 nm, the dummy pillar region can be reduced to approximately 5 μm. Reducing the dummy pillar region of the microelectronic device structure 100 can also improve array efficiency and result in more competitive (e.g., smaller) microelectronic device structure (e.g., die) sizes.

[0111] Furthermore, because the aforementioned improvements are achieved via custom markings, the methods and embodiments described herein can be implemented with minimal additional cost compared to conventional methods and structures. Additionally, the elliptical shape of the elliptical conductive contact 158 ​​can be verified and tested using conventional microelectronic device structure testing and analysis methods.

[0112] Furthermore, the "braided" pattern of the additional trench 148 and the horizontal offset of the first upper post structure 135 in the X direction facilitate improved operation of the microelectronic device structure 100. For example, the select gate structure formed by the additional conductive structure 145 exhibits improved threshold voltage characteristics compared to conventional microelectronic devices. Additionally, compared to conventional microelectronic device structures, the additional conductive structure 145 can exhibit improved electrical characteristics because it is formed via trench 133 (rather than via additional trench 148). Furthermore, compared to conventional microelectronic device structures, the additional conductive structure 145 exhibits fewer voids (e.g., tungsten voids) because it is formed via another stacked structure 105 including the additional conductive structure 145 and other insulating structures 104 (rather than via a stacked structure including polysilicon or another sacrificial material as in conventional microelectronic device structures). This results in improved conductivity (and lower resistance).

[0113] although Figures 1A to 1X Memory cell 162 with a specific structure and configuration has been described and shown, but this disclosure is not limited thereto. In some embodiments, memory cell 162 may include a so-called "MONOS" (metal-oxide-nitride-oxide-semiconductor) memory cell. In additional embodiments, memory cell 162 includes a so-called "TANOS" (tantalum nitride-aluminum oxide-nitride-oxide-semiconductor) memory cell or a so-called "BETANOS" (band / barrier engineered TANOS) memory cell, each of which is a subset of MONOS memory cells. In other embodiments, memory cell 162 includes a so-called "floating gate" memory cell as a charge storage structure, comprising a floating gate (e.g., a metal floating gate). The floating gate may be horizontally positioned between the central structure of string 160 and conductive structure 142.

[0114] In some embodiments, the electrical connection of the channel material 114 to the channel material 130 via the conductive material 122 can facilitate performance improvements in the microelectronic device structure 100. For example, the current between the channel material 114 and the channel material 130 can be enhanced by the conductive material 122 because current can flow along several paths through the conductive material 122 between the channel material 114 and the channel material 130 (due to the size and shape of the conductive material 122). Additionally, the concentration of dopant within the conductive material 122 can be controlled to promote improved current flow between the channel material 114 and the channel material 130.

[0115] Figure 2This is a partially sectional perspective view showing a portion of a microelectronic device 201 (e.g., a memory device, such as a dual-stack 3D NAND flash memory device) including a microelectronic device structure 200. The microelectronic device structure 200 may be substantially similar to that in the previous references. Figure 1W and 1X The microelectronic device structure 100 described after the processing stage. For example... Figure 2 As shown, the microelectronic device structure 200 may include a stepped structure 220 that defines the connection of the access line 206 to the conductive layer 205 (e.g., a conductive layer, conductive plate, such as conductive structure 142). Figure 1W and 1X The contact area of ​​the microelectronic device structure 200 may include memory cells 203 (e.g., memory cell 162) coupled in series with each other. Figure 1W and 1X The vertical string 207 (e.g., string 160) Figure 1W and 1X The vertical string 207 may extend vertically (e.g., in the Z direction) orthogonally to the conductive line and conductive layer 205, such as data line 202, source layer 204 (e.g., source structure 103). Figure 1W and 1X ), conductive layer 205, access line 206, first select gate 208 (e.g., upper select gate, drain select gate (SGD), or other stacked structures 105). Figure 1W and 1X Additional conductive structure 145 ( Figure 10 Selection line 209 and second selection gate 210 (e.g., lower selection gate, source selection gate (SGS)). Selection gate 208 may be horizontally (e.g., in the Y direction) divided into multiple blocks 232 (e.g., block structure 140). Figure 1R They pass through groove 230 (e.g., formed in groove 133). Figure 1Q , Figure 1R Dielectric material 146 () inside Figure 1Q , Figure 1R ) and 148 additional slots Figure 1W and 1X ) dielectric material 152 ( Figure 1W and 1X The additional slots 148 are horizontally (e.g., in the Y direction) separated from each other. As described above, referring to the microelectronic device structure 100, the additional slots 148 are relative to the first upper guide pillar structure 135. Figure 1W and 1X ) and oval conductive contact 158 ​​( Figure 1W and 1X The size, shape, and orientation of the gate can help form a first-choice gate 208 that exhibits relatively improved characteristics.

[0116] Vertical conductive contacts 211 can electrically couple components to each other, as shown. For example, select line 209 can be electrically coupled to first select gate 208, and access line 206 can be electrically coupled to conductive layer 205. Microelectronic device 201 may also include a control unit 212 positioned under the memory array, which may include control logic configured to control various operations of other features of microelectronic device 201 (e.g., vertical strings 207 of memory cells 203). As a non-limiting example, control unit 212 may include one or more (e.g., each) of the following: a charge pump (e.g., V... CCP Charge pump, V NEGWL Charge pumps, DVC2 charge pumps), delay-locked loop (DLL) circuit systems (e.g., ring oscillators), V dd Regulators, drivers (e.g., string drivers), decoders (e.g., local stack decoders, column decoders, row decoders), sense amplifiers (e.g., equalization (EQ) amplifiers, isolation (ISO) amplifiers, NMOS sense amplifiers (NSA), PMOS sense amplifiers (PSA)), repair circuitry (e.g., column repair circuitry, row repair circuitry), I / O devices (e.g., local I / O devices), memory test devices, MUX, error checking and correction (ECC) devices, self-refresh / wear-out equalization devices, and other chip / stack control circuitry. For example, control unit 212 may be electrically coupled to data line 202, source layer 204, access line 206, first select gate 208, and second select gate 210. In some embodiments, control unit 212 includes complementary metal-oxide-semiconductor (CMOS) circuitry. In such embodiments, control unit 212 may be characterized as having an "array-under-CMOS" ("CuA") configuration.

[0117] The first selection gate 208 may extend horizontally in a first direction (e.g., the X direction) and may be coupled to a corresponding first group of vertical strings 207 at a first end (e.g., the upper end) of the vertical strings 207 of the memory cells 203. The second selection gate 210 may be formed in a substantially flat configuration and may be coupled to the vertical strings 207 at a second opposite end (e.g., the lower end) of the vertical strings 207 of the memory cells 203.

[0118] Data lines 202 (e.g., bit lines) may extend horizontally in a second direction (e.g., in the Y direction) at an angle (e.g., perpendicular to) to a first direction extending from the first select gate 208. Data lines 202 may be coupled to a corresponding second set of vertical strings 207 at a first end (e.g., the upper end) of the vertical string 207. The first set of vertical strings 207 coupled to the corresponding first select gate 208 may share a specific vertical string 207 with the second set of vertical strings 207 coupled to the corresponding data lines 202. Therefore, a specific vertical string 207 at the intersection of a specific first select gate 208 and a specific data line 202 can be selected. Thus, the first select gate 208 can be used to select a memory cell 203 in the vertical string 207 of the memory cell 203.

[0119] Conductive layer 205 (e.g., word lines, word line boards, such as conductive structure 142) Figure 1P The conductive layers 205 can extend in the corresponding horizontal plane. The conductive layers 205 can be stacked vertically such that each conductive layer 205 is coupled to all vertical strings 207 of the memory cells 203, and the vertical strings 207 of the memory cells 203 extend vertically through the stack of conductive layers 205. The conductive layers 205 can be coupled to or can form the control gate of the memory cell 203 coupled to the conductive layer 205. Each conductive layer 205 can be coupled to one memory cell 203 in a specific vertical string 207 of the memory cell 203.

[0120] The first selection gate 208 and the second selection gate 210 can be used to select a specific vertical string 207 of memory cells 203 between a specific data line 202 and the source layer 204. Thus, a specific memory cell 203 can be selected and electrically coupled to the data line 202 by operating (e.g., by selecting) the first selection gate 208, the second selection gate 210, and the conductive layer 205 appropriately coupled to the specific memory cell 203.

[0121] The stepped structure 220 can be configured to provide an electrical connection between the access line 206 and the conductive layer 205 via vertical conductive contacts 211. In other words, a specific level in the conductive layer 205 can be selected via an access line 206 electrically connected to a corresponding vertical conductive contact 211, which is electrically connected to the specific conductive layer 205.

[0122] Data line 202 can be connected via conductive contact structure 234 (e.g., conductive contact). Figure 1X Electrically coupled to vertical string 207.

[0123] Microelectronic devices including microelectronic devices (e.g., microelectronic device 201) and microelectronic device structures including upper guide post structures 135, 137 formed via custom markings, additional slots 148 displaying a braided pattern, and elliptical conductive contacts 158 formed via custom markings (e.g., microelectronic device structures 100, 200) can be used in embodiments of the electronic systems disclosed herein. For example, Figure 3 This is a block diagram of an electronic system 303 according to an embodiment of the present disclosure. The electronic system 303 may include, for example, a computer or computer hardware component, a server or other networking hardware component, a cellular phone, a digital camera, a personal digital assistant (PDA), a portable media (e.g., music) player, a Wi-Fi or cellular-enabled tablet computer (e.g., or Tablet computers, e-books, navigation devices, etc. Electronic system 303 includes at least one memory device 305. Memory device 305 may include, for example, the microelectronic device architecture previously described herein (e.g., microelectronic device architecture 100, 200) or previously referenced... Figures 1A to 1X and Figure 2 The described embodiment is a microelectronic device (e.g., microelectronic device 201) including an additional slot 148, a first upper guide post structure 135 and a second upper guide post structure 137 and an elliptical conductive contact 158.

[0124] The electronic system 303 may further include at least one electronic signal processor device 307 (generally referred to as a “microprocessor”). The electronic signal processor device 307 may optionally include the microelectronic devices or microelectronic device structures previously described herein (e.g., previously referenced...). Figures 1A to 1P and Figure 2 The embodiments described are of the microelectronic device 201 or one or more of the microelectronic device structures 100, 200. The electronic system 303 may further include one or more input devices 309 for a user to input information into the electronic system 303, such as a mouse or other pointing device, keyboard, touchpad, button, or control panel. The electronic system 303 may further include one or more output devices 311 for outputting information (e.g., visual or audio output) to the user, such as a monitor, display, printer, audio output jack, speaker, etc. In some embodiments, the input device 309 and output device 311 may include a single touchscreen device that can simultaneously input information into the electronic system 303 and output visual information to the user. The input device 309 and output device 311 may be electrically connected to one or more of the memory device 305 and the electronic signal processor device 307.

[0125] refer to Figure 4The present invention describes a processor-based system 400. The processor-based system 400 may include various microelectronic devices and microelectronic device structures manufactured according to embodiments of the present disclosure (e.g., microelectronic devices and microelectronic device structures including one or more of microelectronic device 201 or microelectronic device structures 100, 200). The processor-based system 400 may be any of various types, such as a computer, pager, cellular phone, personal assistant, control circuitry, or other electronic device. The processor-based system 400 may include one or more processors 402, such as microprocessors, for controlling system functions and request processing within the processor-based system 400. The processor 402 and other sub-components of the processor-based system 400 may include microelectronic devices and microelectronic device structures manufactured according to embodiments of the present disclosure (e.g., microelectronic devices and microelectronic device structures including one or more of microelectronic device 201 or microelectronic device structures 100, 200).

[0126] The processor-based system 400 may include a power source 404 operatively connected to the processor 402. For example, if the processor-based system 400 is a portable system, the power source 404 may include one or more of the following: a fuel cell, a power scavenging device, a permanent battery, a replaceable battery, and a rechargeable battery. The power source 404 may also include an AC adapter; thus, the processor-based system 400 can be plugged into, for example, a wall socket. The power source 404 may also include a DC adapter, allowing the processor-based system 400 to be plugged into, for example, a vehicle cigarette lighter or a vehicle power port.

[0127] Depending on the functions performed by the processor-based system 400, various other devices may be coupled to the processor 402. For example, a user interface 406 may be coupled to the processor 402. The user interface 406 may include input devices such as buttons, switches, keyboards, light pens, mice, digitizers and styluses, touchscreens, voice recognition systems, microphones, or combinations thereof. A display 408 may also be coupled to the processor 402. The display 408 may include an LCD display, a SED display, a CRT display, a DLP display, a plasma display, an OLED display, an LED display, a 3D projector, an audio display, or combinations thereof. Furthermore, an RF subsystem / baseband processor 410 may also be coupled to the processor 402. The RF subsystem / baseband processor 410 may include antennas coupled to an RF receiver and an RF transmitter (not shown). One or more communication ports 412 may also be coupled to the processor 402. Communication port 412 can be used to couple to one or more peripheral devices 414, such as modems, printers, computers, scanners or cameras, or to networks, such as local area networks, remote area networks, intranets or the Internet.

[0128] Processor 402 can control processor-based system 400 by implementing software programs stored in memory. The software programs may include, for example, operating systems, database software, drafting software, word processing software, media editing software, or media playback software. Memory is operatively coupled to processor 402 to store various programs and facilitate their execution. For example, processor 402 may be coupled to system memory 416, which may include one or more of the following: spin torque transfer magnetic random access memory (STT-MRAM), magnetic random access memory (MRAM), dynamic random access memory (DRAM), static random access memory (SRAM), particle orbital memory, and other known memory types. System memory 416 may include volatile memory, non-volatile memory, or combinations thereof. System memory 416 is typically large enough to store dynamically loaded application programs and data. In some embodiments, system memory 416 may include semiconductor devices, such as the microelectronic devices and microelectronic device structures described above (e.g., microelectronic device 201 and microelectronic device structures 100, 200), or combinations thereof.

[0129] Processor 402 may also be coupled to non-volatile memory 418, which does not mean that system memory 416 must be volatile. Non-volatile memory 418 may include one or more of the following: STT-MRAM, MRAM, read-only memory (ROM) such as EPROM, resistive read-only memory (RROM), and flash memory to be used in conjunction with system memory 416. The size of non-volatile memory 418 is typically chosen to be just large enough to store any required operating system, applications, and fixed data. In addition, non-volatile memory 418 may include mass storage, such as disk drive memory, such as a hybrid drive containing resistive memory or other types of non-volatile solid-state memory. Non-volatile memory 418 may include microelectronic devices, such as the microelectronic devices and microelectronic device structures described above (e.g., microelectronic device 201 and microelectronic device structures 100, 200), or combinations thereof.

[0130] Therefore, according to embodiments of this disclosure, an electronic system includes: an input device; an output device; a processor device operatively coupled to the input device and the output device; and a memory device operatively coupled to the processor device and including at least one microelectronic device. The at least one microelectronic device includes: a string of memory cells extending through a stacked structure comprising alternating layers of insulating and conductive structures, the string of memory cells exhibiting post bending in a first direction; an upper post located within an additional stacked structure comprising alternating layers of additional insulating and conductive structures, the center of the lowermost surface of the upper post being substantially aligned in the first direction with a corresponding center of the uppermost surface of the string of memory cells; a slot structure extending at least partially through the stacked structure, the slot structures exhibiting nonlinear shapes; an elliptical conductive contact contacting the uppermost surface of the upper post, the elliptical cross-section of the elliptical conductive contact having a principal axis extending in the first direction; and an access line electrically contacting the elliptical conductive contact and extending in a second direction perpendicular to the first direction.

[0131] Embodiments of this disclosure include a method of forming a microelectronic device. The method includes: forming a first stacked structure comprising alternating layers of insulating structures and other insulating structures; forming a memory cell string comprising channel material extending through the first stacked structure; forming a second stacked structure above the first stacked structure, comprising alternating layers of additional insulating structures and other additional insulating structures, based at least in part on post bending observed within the first stacked structure; forming a first custom marker specific to the observed post bending; forming openings extending through the second stacked structure and above some of the memory cell strings using the first custom marker, wherein the center of the openings above the memory cell strings is substantially aligned with the center of the uppermost surface of the memory cell string, at least in the direction of the observed post bending; forming upper posts extending through the second stacked structure and above some of the memory cell strings; and forming a slot structure between some adjacent upper posts, the slot structure exhibiting a nonlinear shape, based at least in part on the observed post bending.

[0132] Some embodiments of this disclosure include a microelectronic device. The microelectronic device includes: a stacked structure comprising a vertically alternating sequence of conductive and insulating structures arranged in layers, the stacked structure being divided into block structures separated from each other by slot structures; lower guide pillars extending vertically through the block structures of the stacked structure, the lower guide pillars exhibiting guide pillar bending in a first direction, each of the lower guide pillars having a lowermost surface and an uppermost surface not vertically aligned with the lowermost surface of the guide pillar; an additional stacked structure vertically overlying the stacked structure and comprising a vertically alternating sequence of additional conductive and insulating structures arranged in additional layers; and upper guide pillars extending through the additional stacked structure and vertically overlying the lower guide pillars, each upper guide pillar having a lowermost surface and an uppermost surface, wherein the center of the lowermost surface of each upper guide pillar is aligned in the first direction with the center of the uppermost surface of the corresponding guide pillar.

[0133] Additional embodiments of this disclosure include a microelectronic device comprising: a memory cell string extending through a first stacked structure comprising alternating conductive and insulating structures, the memory cell string comprising at least a dielectric material and a channel material extending vertically through the first stacked structure; a second stacked structure vertically overlying the first stacked structure; upper posts extending through the second stacked structure and vertically overlying the memory cell string; a rigid mask material located above the second stacked structure; elliptical openings extending through the rigid mask material, each elliptical opening vertically overlapping at least a portion of a corresponding upper post of the upper posts; elliptical conductive contacts formed within the elliptical openings, each elliptical conductive contact contacting a corresponding upper post of the upper posts; and access lines electrically contacting the elliptical conductive contacts, wherein the elliptical cross-section of the elliptical conductive contacts has a principal axis extending in a direction perpendicular to the extension direction of the access lines.

[0134] Embodiments of this disclosure include an electronic system. The electronic system includes: an input device; an output device; a processor device operatively coupled to the input device and the output device; and a memory device operatively coupled to the processor device and including a microelectronic device structure. The microelectronic device structure includes: a string of memory cells extending through a stacked structure comprising alternating layers of insulating and conductive structures, the string of memory cells exhibiting post bending in a first direction; an upper post located within an additional stacked structure comprising alternating layers of additional insulating and conductive structures, the center of the lowest portion of the upper post being substantially aligned in the first direction with the corresponding center of the uppermost portion of the string of memory cells; slot structures extending at least partially through the stacked structure, the slot structures exhibiting nonlinear shapes; elliptical conductive contacts contacting the uppermost portion of the upper post, the elliptical cross-section of the elliptical conductive contacts having a principal axis extending in the first direction; and access lines electrically contacting the elliptical conductive contacts and extending in a second direction perpendicular to the first direction.

[0135] Embodiments of this disclosure further include:

[0136] Example 1. A microelectronic device comprising: a stacked structure including a vertically alternating sequence of conductive and insulating structures arranged in layers, the stacked structure being divided into block structures separated from each other by slot structures; lower guide pillars extending vertically through the block structures of the stacked structure, the lower guide pillars exhibiting guide pillar bending in a first direction, each of the lower guide pillars having a lowermost surface and an uppermost surface not vertically aligned with the lowermost surface of the lower guide pillar; an additional stacked structure vertically overlying the stacked structure and including a vertically alternating sequence of additional conductive and insulating structures arranged in additional layers; and upper guide pillars extending through the additional stacked structure and vertically overlying the lower guide pillars, each upper guide pillar having a lowermost surface and an uppermost surface, wherein the center of the lowermost surface of each upper guide pillar is aligned in the first direction with the center of the uppermost surface of the corresponding lower guide pillar.

[0137] Example 2. The microelectronic device according to Example 1 further includes: an additional trench structure comprising a dielectric material extending through at least a portion of the additional stacked structure and subdividing each of the block structures into sub-block structures, the additional trench structure being horizontally adjacent to some of the upper post.

[0138] Example 3. The microelectronic device according to Example 2, wherein each of the additional slot structures displays a woven pattern.

[0139] Example 4. The microelectronic device according to Example 2, wherein each of the additional slot structures includes a crest region and a trough region, and wherein the trough region is at least substantially aligned with the center of the adjacent upper guide post.

[0140] Example 5. A microelectronic device according to any one of Examples 1-4, further comprising: a rigid mask material formed over the additional stacked structure; elliptical openings extending through the rigid mask material, wherein each elliptical opening vertically overlaps at least a portion of a corresponding upper guide post in the upper guide post; elliptical conductive contacts formed within the elliptical openings; and access lines electrically contacting the elliptical conductive contacts.

[0141] Example 6. The microelectronic device according to Example 5, wherein the elliptical cross-section of the elliptical conductive contact has a main axis extending in a direction perpendicular to the extension direction of the access line.

[0142] Example 7. The microelectronic device according to Example 5, wherein the elliptical cross-section of the elliptical conductive contact has a minor axis extending in the extension direction of the access line.

[0143] Example 8. A microelectronic device according to any one of Examples 1-7, wherein the lower guide pillars form a memory cell string, each memory cell string comprising a channel material extending vertically through the stacked structure.

[0144] Example 9. The microelectronic device according to Example 8, wherein each of the upper guide pillars further includes another channel material extending vertically through the additional stack structure and electrically connected to the channel material of the corresponding memory cell string.

[0145] Example 10. The microelectronic device according to Example 9, wherein the channel material is electrically coupled to the other channel material through a conductive material.

[0146] Example 11. A microelectronic device according to any one of Examples 1-10, wherein the lower guide post exhibits a certain guide post bending amount in the first direction, and wherein the central longitudinal axis of the upper guide post is offset from the center of the lowermost surface of the lower guide post by the guide post bending amount.

[0147] Example 12. A method of forming a microelectronic device, the method comprising: forming a first stacked structure including alternating layers of insulating structures and other insulating structures; forming a string of memory cells including a channel material extending through the first stacked structure; forming a second stacked structure above the first stacked structure including alternating layers of additional insulating structures and additional other insulating structures; forming a first custom marker specific to the observed post bending amount based at least in part on post bending amount observed within the first stacked structure; forming openings extending through the second stacked structure and above some of the memory cell strings using the first custom markers, wherein the center of the openings above the memory cell strings is at least substantially aligned with the center of the uppermost surface of the memory cell strings in the direction of the observed post bending amount; forming upper posts extending through the second stacked structure and above some of the memory cell strings; and forming a groove structure between some adjacent upper posts, the groove structure exhibiting a nonlinear shape, based at least in part on the observed post bending amount.

[0148] Example 13. The method according to Example 12, further comprising: forming a rigid mask material over the second stacked structure; forming a second custom marker specific to the observed guide post bending amount based at least in part on the observed guide post bending amount within the first stacked structure; forming elliptical openings through the rigid mask material using the second custom markers, wherein each elliptical opening vertically overlaps at least a portion of a corresponding upper guide post in the upper guide post and at least a portion of a desired profile of an access line; forming elliptical conductive contacts within the elliptical openings; and forming an access line electrically contacting the elliptical conductive contacts.

[0149] Example 14. The method according to Example 13, wherein forming the elliptical opening through the rigid mask material includes forming the elliptical opening having a main axis extending in a direction perpendicular to the extension direction of the access line.

[0150] Example 15. The method according to Example 13, wherein forming the elliptical opening through the rigid mask material includes forming the elliptical opening having a short axis extending in the extension direction of the access line.

[0151] Example 16. The method according to any of Examples 12-15, wherein forming a groove structure between some adjacent upper guide posts includes forming the groove structure to display a woven pattern.

[0152] Example 17. The method according to Example 16 further includes forming the groove structure having crest regions and trough regions, and aligning the trough regions of the groove structure at least substantially with the center of the upper guide post.

[0153] Example 18. The method according to any of Examples 12-17 further includes forming an additional channel material through the upper guide post, the additional channel material being electrically connected to the channel material of the memory cell string to form a channel region comprising the channel material and the additional channel material.

[0154] Example 19. A microelectronic device comprising: a memory cell string extending through a first stacked structure comprising alternating conductive and insulating structures, the memory cell string comprising at least a dielectric material and a channel material extending vertically through the first stacked structure; a second stacked structure vertically overlying the first stacked structure; upper posts extending through the second stacked structure and vertically overlying the memory cell string; a rigid mask material located above the second stacked structure; elliptical openings extending through the rigid mask material, each elliptical opening vertically overlapping at least a portion of a corresponding upper post of the upper posts; elliptical conductive contacts formed within the elliptical openings, each elliptical conductive contact contacting a corresponding upper post of the upper posts; and access lines electrically contacting the elliptical conductive contacts, wherein the elliptical cross-section of the elliptical conductive contacts has a principal axis extending in a direction perpendicular to the extension direction of the access lines.

[0155] Example 20. The microelectronic device according to Example 19, wherein the memory cell string exhibits post bending in a first direction.

[0156] Example 21. The microelectronic device according to Example 20, wherein the center of the lowest surface of the upper guide post is at least substantially aligned with the center of the uppermost surface of the memory cell string in the first direction.

[0157] Example 22. A microelectronic device according to any of Examples 19-21, further comprising an additional trench structure including a dielectric material extending through at least a portion of the second stacked structure and subdividing the block structure of the microelectronic device into sub-block structures, the additional trench structure being horizontally adjacent to some of the upper guide pillars.

[0158] Example 23. The microelectronic device according to Example 22, wherein each of the additional slot structures includes a crest region and a trough region, and wherein the trough region is at least substantially aligned with the center of the adjacent upper guide post.

[0159] Example 24. An electronic system comprising: an input device; an output device; a processor device operatively coupled to the input device and the output device; and a memory device operatively coupled to the processor device and including at least one microelectronic device structure, the at least one microelectronic device structure comprising: a memory cell string extending through a stacked structure comprising alternating layers of insulating and conductive structures, the memory cell string exhibiting post bending in a first direction; an upper post located within an additional stacked structure comprising alternating layers of additional insulating and conductive structures, the center of the lowermost portion of the upper post being substantially aligned in the first direction with the corresponding center of the uppermost portion of the memory cell string; a slot structure extending at least partially through the stacked structure, the slot structures exhibiting nonlinear shapes; an elliptical conductive contact contacting the uppermost portion of the upper post, the elliptical cross-section of the elliptical conductive contact having a principal axis extending in the first direction; and an access line electrically contacting the elliptical conductive contact and extending in a second direction perpendicular to the first direction.

[0160] Example 25. The electronic system according to Example 24, wherein the memory device includes a multi-stack 3D NAND flash memory device.

[0161] Specific embodiments have been illustrated by way of example in the accompanying drawings and described in detail herein, but this disclosure is readily subject to various modifications and alternatives. However, this disclosure is not limited to the specific forms disclosed. Rather, this disclosure is intended to cover all modifications, equivalents, and alternatives that fall within the scope of the appended claims and their legal equivalents.

Claims

1. A microelectronic device comprising: A stacked structure comprising a vertically alternating sequence of conductive and insulating structures arranged in layers, the stacked structure being divided into block structures separated from each other by slot structures; The lower guide post extends vertically through the block structure of the stacked structure, the lower guide post exhibits guide post curvature in a first direction, and each of the lower guide posts has a lowermost surface and an uppermost surface that is not vertically aligned with the lowermost surface of the lower guide post. An additional stacked structure, which is vertically superimposed on the stacked structure and includes a vertically alternating sequence of additional conductive structures and additional insulating structures arranged as additional layers; as well as Upper guide posts extend through the additional stacked structure and vertically overlay the lower guide posts. Each upper guide post has a lowermost surface and an uppermost surface, wherein the center of the lowermost surface of each upper guide post is aligned in the first direction with the center of the uppermost surface of the corresponding lower guide post.

2. The microelectronic device according to claim 1, further comprising: An additional slot structure comprising dielectric material extending through at least a portion of the additional stack structure and subdividing each of the block structures into sub-block structures, the additional slot structure being horizontally adjacent to some of the upper guide posts.

3. The microelectronic device of claim 2, wherein each of the additional slot structures displays a woven pattern.

4. The microelectronic device of claim 2, wherein each of the additional slot structures includes a crest region and a trough region, and wherein the trough region is at least substantially aligned with the center of the adjacent upper guide post.

5. The microelectronic device according to claim 1, further comprising: A rigid mask material is formed over the additional stacked structure; An elliptical opening extending through the rigid mask material, wherein each elliptical opening vertically overlaps at least a portion of a corresponding upper guide post in the upper guide post; An elliptical conductive contact is formed within the elliptical opening; and The access line is in electrical contact with the elliptical conductive contact.

6. The microelectronic device of claim 5, wherein the elliptical cross-section of the elliptical conductive contact has a principal axis extending in a direction perpendicular to the extension direction of the access line.

7. The microelectronic device of claim 5, wherein the elliptical cross-section of the elliptical conductive contact has a minor axis extending in the direction of extension of the access line.

8. The microelectronic device of claim 1, wherein the lower guide pillar forms a memory cell string, each of the memory cell strings comprising a channel material extending vertically through the stacked structure.

9. The microelectronic device of claim 8, wherein each of the upper guide pillars further comprises another channel material extending vertically through the additional stack structure and electrically connected to the channel material of the corresponding memory cell string.

10. The microelectronic device of claim 9, wherein the channel material is electrically coupled to the other channel material via a conductive material.

11. The microelectronic device according to any one of claims 1 to 10, wherein the lower guide post exhibits a guide post bending amount in the first direction, and wherein the central longitudinal axis of the upper guide post is offset from the center of the lowermost surface of the lower guide post by the guide post bending amount.

12. A method for forming a microelectronic device, the method comprising: Forming a first stacked structure comprising alternating layers of insulating structures and other insulating structures; Forming a string of memory cells comprising a channel material extending through the first stacked structure; A second stacked structure, comprising alternating layers of additional insulating structures and other additional insulating structures, is formed above the first stacked structure; A first custom datum line specific to the observed guide post bending amount is formed, based at least in part on the guide post bending amount observed within the first stacked structure. The first custom markings are used to form openings that extend through the second stack structure and above some of the memory cell strings, wherein the center of the opening above the memory cell strings is at least substantially aligned with the center of the uppermost surface of the memory cell strings in the direction of the observed guide post bending. Forming upper guide pillars that extend through the second stacked structure and above some of the memory cell strings; as well as Based at least in part on the observed guide post bending, a groove structure is formed between some adjacent upper guide posts, the groove structure exhibiting a nonlinear shape.

13. The method of claim 12, further comprising: A rigid mask material is formed above the second stacked structure; A second custom datum line, specific to the observed guide post bending amount, is formed, based at least in part on the observed guide post bending amount within the first stacked structure. The second custom marking line is used to form an elliptical opening through the rigid mask material, wherein each elliptical opening vertically overlaps at least a portion of the corresponding upper guide post in the upper guide post and at least a portion of the expected profile of the access line. An elliptical conductive contact is formed within the elliptical opening; and An access line is formed that makes electrical contact with the elliptical conductive contact.

14. The method of claim 13, wherein forming the elliptical opening through the rigid mask material comprises forming the elliptical opening having a main axis extending in a direction perpendicular to the extension direction of the access line.

15. The method of claim 13, wherein forming the elliptical opening through the rigid mask material comprises forming the elliptical opening having a short axis extending in the extension direction of the access line.

16. The method of claim 12, wherein forming a groove structure between some adjacent upper guide posts includes forming the groove structure to display a woven pattern.

17. The method of claim 16, further comprising forming the groove structure having crest regions and trough regions, and aligning the trough regions of the groove structure at least substantially with the center of the upper guide post.

18. The method according to any one of claims 12 to 17, further comprising forming an additional channel material through the upper guide post, the additional channel material being electrically connected to the channel material of the memory cell string to form a channel region comprising the channel material and the additional channel material.

19. A microelectronic device comprising: A memory cell string extending through a first stacked structure comprising alternating conductive and insulating structures, the memory cell string comprising at least a dielectric material and a channel material extending vertically through the first stacked structure; The second stacked structure is vertically superimposed on the first stacked structure; The upper guide post extends through the second stacking structure and vertically covers the memory cell string; A rigid mask material is located above the second stacked structure; Elliptical openings extending through the rigid mask material, each elliptical opening vertically overlapping at least a portion of a corresponding upper guide post in the upper guide post; Elliptical conductive contacts are formed within the elliptical opening, each elliptical conductive contact contacting a corresponding upper guide post in the upper guide post; and The access line is in electrical contact with the elliptical conductive contact. The elliptical cross-section of the elliptical conductive contact has a main axis extending in a direction perpendicular to the extension direction of the access line.

20. The microelectronic device of claim 19, wherein the memory cell string exhibits post bending in a first direction.

21. The microelectronic device of claim 20, wherein the center of the lowest surface of the upper post is at least substantially aligned with the center of the uppermost surface of the memory cell string in the first direction.

22. The microelectronic device of claim 19, further comprising an additional trench structure including a dielectric material extending through at least a portion of the second stacked structure and subdividing the block structure of the microelectronic device into sub-block structures, the additional trench structure being horizontally adjacent to some of the upper post.

23. The microelectronic device of claim 22, wherein each of the additional slot structures includes a crest region and a trough region, and wherein the trough region is at least substantially aligned with the center of the adjacent upper guide post.

24. An electronic system comprising: Input device; Output device; A processor device operatively coupled to the input device and the output device; as well as A memory device operatively coupled to the processor device and including at least one microelectronic device structure, the at least one microelectronic device structure comprising: A memory cell string that extends through a stacked structure comprising alternating layers of insulating and conductive structures, the memory cell string exhibiting post bending in a first direction; The upper guide post is located within an additional stacked structure comprising alternating layers of additional insulating and additional conductive structures, the center of the lowermost portion of the uppermost portion of the uppermost portion of the memory cell string being substantially aligned in the first direction with the corresponding center of the uppermost portion of the memory cell string. The slot structures extend at least partially through the additional stacked structures, each exhibiting a nonlinear shape; An elliptical conductive contact contacts the uppermost portion of the upper guide post, the elliptical cross-section of the elliptical conductive contact having a principal axis extending in the first direction; and Access lines are electrically connected to the elliptical conductive contacts and extend in a second direction perpendicular to the first direction.

25. The electronic system of claim 24, wherein the memory device comprises a multi-stack 3D NAND flash memory device.

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