A synchronous rectification integrated circuit and a control method thereof

Abstract

A synchronous rectification integrated circuit and a control method thereof, comprising a power device, a power supply circuit, a capacitor and an amplifier circuit packaged on the same chip, the chip further comprising a power device drain port and a power device source port; the gate of the power device is connected to the output of the amplifier circuit, the source is connected to the power device source port, and the drain is connected to the power device drain port; one end of the power supply circuit is connected to the power device drain port, the other end is connected to the positive electrode of the capacitor and the positive terminal of the internal power supply of the amplifier circuit, the negative electrode of the capacitor is connected to the power device source port, the non-inverting input terminal of the amplifier circuit and the negative terminal of the internal power supply of the amplifier circuit respectively, and the inverting input terminal of the amplifier circuit is connected to the power device drain port. The amplifier circuit drives the gate of the power device to control its conduction and cutoff, and adjusts the conduction impedance in real time according to the current size, thereby improving the conversion efficiency and reducing the switching loss.

Description

Technical Field

[0001] This invention belongs to the field of synchronous current conversion circuit technology, specifically relating to a synchronous rectification integrated circuit and its control method. Background Technology

[0002] In common circuits, the application of environmentally friendly and high-efficiency power supplies is becoming increasingly widespread. Switching power supplies are used most frequently among power supplies. The rectifier diodes used in common switching power supplies have relatively low efficiency. Synchronous rectification circuits can replace diode rectification, thereby achieving higher efficiency. Improved circuit efficiency makes power supplies greener and more environmentally friendly.

[0003] Traditional synchronous rectification circuits rely on comparators to detect the voltage at the drain terminal of a MOSFET. When the voltage reaches the turn-on threshold, the gate of the MOSFET is pulled high to the power supply voltage to turn on the MOSFET. Then, when the drain voltage reaches the turn-off threshold, the gate of the MOSFET is pulled low to turn off the MOSFET.

[0004] Since current continues to flow during turn-off, it will freewheel through the body diode of the MOS transistor after turn-off, causing the drain voltage to become negative again. AC-to-DC converters relying on primary-side feedback (PSR) need to deliberately avoid sampling at the turn-off time of the synchronous rectifier chip; otherwise, significant fluctuations in the sampled voltage will lead to loop instability, undoubtedly increasing the design complexity of primary-side feedback and reducing its reliability. Furthermore, because the diode forward voltage drop after turn-off is negative and below the turn-on threshold, it may still be below the threshold at the trough of voltage oscillation when the current reaches zero, creating a risk of false turn-on. Measures such as slope detection, minimum turn-on time, and turn-off time limits need to be implemented in the design to avoid false operation, but this undoubtedly increases the design complexity and limits the frequency range of applications.

[0005] Under light load or no-load operating conditions, the current through synchronous rectification becomes very small. When the MOSFET turns on, the voltage across it drops rapidly, reaching the turn-off threshold, causing the MOSFET to turn off quickly after a brief period of on-time. This characteristic introduces additional switching losses and electromagnetic interference, which is detrimental to optimizing standby power consumption. Although some synchronous rectification designs incorporate load detection, they do not switch upon detecting a light load, allowing the MOSFET's body diode to freewheel. While this reduces electromagnetic interference, the large freewheeling voltage drop of the body diode is also detrimental to standby power consumption optimization and requires consideration of the application scenario, limiting its application scope.

[0006] Prior art document 1 (CN112421970A) discloses a synchronous rectification device and its control method, including a synchronous rectifier diode, a drive control circuit, a Vcc capacitor, and a charging circuit. It utilizes a reverse voltage applied to the synchronous rectification device to charge the Vcc capacitor through the charging circuit. When the Vcc capacitor voltage is detected to rise to its upper limit value Vcc_H, charging of the Vcc capacitor stops; when the Vcc voltage is detected to drop to its lower limit value Vcc_L, charging of the Vcc capacitor begins, so that the switching transistor of the charging circuit operates in an intermittent and fully conducting state. The drawback of prior art document 1 is that the charging circuit requires detection of the Vcc capacitor voltage, and the detection circuit inevitably consumes power from Vcc; simultaneously, the Vcc voltage fluctuates from Vcc_H to Vcc_L, adversely affecting system stability. The shortcomings of prior art document 1 are that... Figure 5 It is evident that the Vcc charge / discharge cycle is 7 times the switching cycle. Since the common AC-to-DC switching frequency is around 75kHz, it can be deduced that the Vcc charge / discharge cycle is approximately 11kHz, which is within the audio range. This may result in sound waves that are perceptible to the human ear in the end product, affecting user experience and product competitiveness.

[0007] In summary, existing synchronous rectification circuits are complex in design, have many control circuit components, and it is difficult to solve the matching problem between the on-resistance of power devices and the application current. They also suffer from high switching losses, and voltage fluctuations lead to poor system stability and are not conducive to optimizing standby power consumption, resulting in a very narrow application range for a single synchronous rectification integrated circuit. Summary of the Invention

[0008] To address the shortcomings of existing technologies, including the complexity of common rectifier circuit designs, the large number of control circuit components, and the difficulty in matching the on-resistance of power devices with the application current, which results in a narrow application range for synchronous rectifier integrated circuits, the present invention aims to provide a synchronous rectifier integrated circuit.

[0009] The present invention adopts the following technical solution:

[0010] A synchronous rectification integrated circuit includes power devices, power supply circuits, capacitors, and amplifier circuits packaged on the same chip.

[0011] The chip also includes a power device drain port 5 and a power device source port 6; the gate of the power device is connected to the output terminal of the amplifier circuit, the source is connected to the power device source port 6, and the drain is connected to the power device drain port 5.

[0012] One end of the power supply circuit is connected to the drain port 5 of the power device, and the other end is connected to the positive terminal of the capacitor and the positive terminal of the internal power supply of the amplifier circuit. The negative terminal of the capacitor is connected to the source port 6 of the power device, the non-inverting input terminal of the amplifier circuit and the negative terminal of the internal power supply of the amplifier circuit, respectively. The inverting input terminal of the amplifier circuit is connected to the drain port 5 of the power device.

[0013] The power device is a MOSFET.

[0014] When the voltage at the drain port 5 of the power device is higher than the positive terminal voltage of the internal power supply of the amplifier circuit, the power supply circuit supplies power to the positive terminal of the internal power supply of the amplifier circuit, and the capacitor connected to the positive terminal of the internal power supply of the amplifier circuit is charged; when the voltage at the drain port 5 of the power device is lower than the positive terminal voltage of the internal power supply of the amplifier circuit, the power supply circuit is turned off and does not work, and the capacitor supplies power to the amplifier circuit.

[0015] The power supply circuit includes a first power supply circuit composed of a first JFET device and a first diode, wherein the gate of the first JFET device is connected to the source port 6 of the power device, the drain of the first JFET device is connected to the negative terminal of the first diode, and the source is connected to the positive terminal of the internal power supply of the amplifier circuit; the positive terminal of the first diode is connected to the drain port 5 of the power device.

[0016] The power supply circuit also includes a second power supply circuit consisting of a second JFET device 21 and a second diode 22.

[0017] A power supply port 7 is set in the chip. The power supply port 7 is connected to the anode of the second diode of the second power supply circuit. The gate of the second JFET device is connected to the source port 6 of the power device. The drain is connected to the negative terminal of the second diode. The source is connected to the positive terminal of the internal power supply of the amplifier circuit.

[0018] The amplifier circuit is equipped with an offset voltage Vos. When the voltage at the drain port 5 of the power device is continuously higher than the voltage difference Vs-Vos between the voltage at the source port 6 of the power device and the offset voltage, the amplifier circuit pulls down the gate voltage of the power device, and the power device is turned off. When the voltage at the drain port 5 of the power device is continuously lower than the voltage difference Vs-Vos between the voltage at the source port 6 of the power device and the offset voltage, the amplifier pulls up the gate voltage of the power device, and the power device is turned on.

[0019] When the current is between 0 and Vos / Rdson1, the amplifier circuit adjusts the gate voltage of the power device in real time according to the relationship between the voltage at the drain port 5 of the power device and Vs-Vos, thereby adjusting the on-resistance of the power device so that the product of its on-resistance and current is equal to the offset voltage Vos.

[0020] Rdson1 refers to the on-resistance when the gate voltage of the power device is equal to the positive terminal voltage of the internal power supply of the amplifier circuit.

[0021] The amplifier circuit adjusts the offset voltage by configuring tail current sources; the amplifier circuit specifically includes MOS devices 0 to 15 and tail current sources 0 to 5.

[0022] The inverting input of the amplifier circuit is connected to two series-connected MOS devices, the 12th and 14th, and bias current is provided through the 5th tail current source; the source of the 12th MOS device is connected to the source of the 1st MOS device and the source of the 3rd MOS device.

[0023] The non-inverting input of the amplifier circuit is connected to two series-connected MOS devices, number 15 and 13, and bias current is provided through the fourth tail current source; the source of the 13th MOS device is connected to the sources of the 4th and 6th MOS devices.

[0024] The gate and drain of the 3rd MOS device are connected to the gate of the 2nd MOS device, respectively, and bias current is provided through the 0th tail current source; the drain of the 2nd MOS device is connected to the source of the 11th MOS device, and the source of the 2nd MOS device is connected to the source of the 7th MOS device; the drain of the 7th MOS device is connected to the drain and gate of the 9th MOS device and the gate of the 8th MOS device, and the gate of the 7th MOS device is connected to the gate and drain of the 4th MOS device and the 3rd tail current source; the negative terminal of the internal power supply of the amplifier circuit is connected to the source of the 9th MOS device, the source of the 8th MOS device, the drain of the 0th MOS device, and the 1st tail current source;

[0025] The drain and gate of the 1st MOS device are connected to the first tail current source and the gate of the 0th MOS device; the source of the 0th MOS device is connected to the source of the 5th MOS device; the drain of the 5th MOS device is connected to the drain and gate of the 10th MOS device and the gate of the 11th MOS device; the gate of the 5th MOS device is connected to the gate and drain of the 6th MOS device and is provided with bias current through the second tail current source; the positive terminal of the internal power supply of the amplifier circuit is connected to the source of the 11th MOS device and the source of the 10th MOS device;

[0026] The output of the amplifier circuit is connected to the drain of the 11th MOS device and the drain of the 8th MOS device.

[0027] A synchronous rectification integrated circuit control method:

[0028] The power supply circuit supplies power to the positive terminal of the amplifier circuit's internal power supply: when the voltage at terminal 5 of the power device's drain port is higher than the voltage at the positive terminal of the amplifier circuit's internal power supply, the power supply circuit supplies power to the amplifier circuit, and the capacitor connected to the positive terminal of the amplifier circuit's internal power supply is charged; when the voltage at terminal 5 of the power device's drain port is lower than the voltage at the positive terminal of the amplifier circuit's internal power supply, the power supply circuit is turned off and does not work, and the capacitor supplies power to the amplifier circuit.

[0029] The amplifier circuit is equipped with an offset voltage Vos. When the voltage Vd at the drain port 5 of the power device is continuously higher than the voltage difference Vs-Vos between the voltage Vs at the source port 6 of the power device and the offset voltage, the amplifier circuit pulls down the gate voltage of the power device, and the power device is turned off. When the voltage at the drain port 5 of the power device is continuously lower than the voltage difference Vs-Vos between the voltage Vs at the source port 6 of the power device and the offset voltage, the amplifier pulls up the gate voltage of the power device, and the power device is turned on.

[0030] Among them, when When the amplifier circuit adjusts the gate voltage of the power device to control the product of Rdson1 and I to equal the offset voltage Vos, where I represents the current value between the drain port 5 and the source port 6 of the power device, and Rdson1 represents the on-resistance of the power device.

[0031] The beneficial effects of this invention are that, compared with the prior art, it achieves smooth zero-current turn-off and conduction voltage control through the negative feedback characteristics of the amplifier, which is closer to the characteristics of an ideal diode. Therefore, there is no risk of malfunction in the traditional solution, nor is there a minimum switching time limitation. Thus, there is no problem of limiting the application frequency range in the traditional solution, and it has good versatility and adaptability to various power supply systems.

[0032] The beneficial effects of this invention also include: the synchronous rectification integrated circuit uses an amplifier circuit to drive the gate of the power device to control its on / off state, and can adjust the on-resistance in real time according to the current magnitude. It replaces the on-voltage drop of the rectifier diode with the reference voltage input to the amplifier, improving conversion efficiency, reducing switching losses, and solving the matching problem between the on-resistance of the power device and the application current. It is a highly efficient and versatile synchronous rectification circuit. The synchronous rectification circuit of this application has a simple design and wide applicability. In this application, the power supply circuit does not have a detection circuit; instead, it uses the inherent characteristics of the JFET device to complete the feedback. Furthermore, the internal power supply voltage of the amplifier circuit will not experience artificially set fluctuations, nor will it pose a risk of generating additional audio frequencies. Attached Figure Description

[0033] Figure 1 This is a schematic diagram of the structure of a synchronous rectification integrated circuit according to the present invention;

[0034] Figure 2 This is a schematic diagram of the first power supply circuit according to an embodiment of the present invention;

[0035] Figure 3 This is a schematic diagram of a synchronous rectifier integrated circuit including a second power supply circuit, according to Embodiment 2 of the present invention;

[0036] Figure 4This is a schematic diagram of the second power supply circuit according to an embodiment of the present invention.

[0037] Figure 5 This is a schematic diagram of the preferred amplifier circuit of Embodiment 3 of the present invention;

[0038] Figure 6 This is a schematic diagram of the circuit principle of Embodiment 4 of the present invention;

[0039] The diagram is labeled as follows: 1. Power supply circuit; 11. First JFET device; 12. First diode; 2. Second power supply circuit; 21. Second JFET device; 22. Second diode; 3. Amplifier circuit; 4. Power device; 30-315. MOS device; 40-45. Tail current source; 5. Drain port of power device; 6. Source port of power device; 7. Power supply port; 8. First resistor; 9. Second resistor. Detailed Implementation

[0040] The present application will be further described below with reference to the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solutions of the present invention, and should not be construed as limiting the scope of protection of the present application.

[0041] As attached Figure 1 This application discloses a synchronous rectification integrated circuit, including a power device 4, a power supply circuit 1, a capacitor, and an amplifier circuit 3 packaged on the same chip. The chip also includes a drain port 5 and a source port 6 for the power device. The gate of the power device 4 is connected to the output terminal of the amplifier circuit 3, the source is connected to the source port 6, and the drain is connected to the drain port 5. One end of the power supply circuit is connected to the drain port 5, and the other end is connected to the positive terminal of the capacitor and the positive terminal of the internal power supply of the amplifier circuit. The negative terminal of the capacitor is connected to the source port 6, the non-inverting input terminal of the amplifier circuit, and the negative terminal of the internal power supply of the amplifier circuit. The inverting input terminal of the amplifier circuit is connected to the drain port 5. The power device is a MOSFET. The drain port 5 is used to detect the drain of the power device, and the source port 6 is used to detect the source of the power device. The capacitor suppresses voltage fluctuations of the internal power supply by storing and releasing electrical energy.

[0042] like Figure 2 The schematic diagram of the first power supply circuit of this embodiment of the invention shown includes a first power supply circuit composed of a first JFET device 11 and a first diode 12. The gate of the first JFET device 11 is connected to the source port 6 of the power device, the drain of the first JFET device 11 is connected to the negative terminal of the first diode 12, and the source is connected to the positive terminal of the internal power supply of the amplifier circuit. The positive terminal of the first diode is connected to the drain port 5 of the power device. The first power supply circuit is used to charge the amplifier circuit.

[0043] Preferably, the power supply circuit of this application may further include a second power supply circuit, such as... Figure 3 The schematic diagram of the synchronous rectifier integrated circuit of Embodiment 2 of the present invention shown includes a second power supply circuit, wherein the schematic diagram of the second power supply circuit 2 is as follows. Figure 4 As shown, the power supply circuit also includes a second power supply circuit 2 composed of a second JFET device 21 and a second diode 22. A power supply port 7 is provided on the chip, connected to the anode of the second diode 22. The gate of the second JFET device 21 is connected to the source port 6 of the power device, its drain is connected to the cathode of the second diode 22, and its source is connected to the positive terminal of the amplifier circuit's internal power supply. The second power supply circuit 2 supplies power to the chip; it supplies power to the chip when the pin of the power supply port 7 has power supply capability, preventing insufficient power supply to the power supply circuit connected to the drain port 5 of the power device.

[0044] When the voltage at terminal 5 of the drain of the power device is higher than the positive terminal of the internal power supply of the amplifier circuit, the power supply circuit supplies power to the amplifier circuit, and the capacitor connected to the positive terminal of the internal power supply of the amplifier circuit is charged; when the voltage at terminal 5 of the drain of the power device is lower than the positive terminal of the internal power supply of the amplifier circuit, the power supply circuit is turned off and does not work, and the capacitor supplies power to the amplifier circuit. Figure 1 and attached Figure 2 VCC in the diagram represents the positive terminal of the internal power supply of the amplifier circuit.

[0045] In this embodiment, the power supply circuit 1 is connected to the drain port 5 and source port 6 of the power device and the internal power supply. The amplifier circuit is powered by the voltage difference between the voltage Vd at the drain port 5 and the voltage Vs at the source port 6 of the power device. In this example, a JFET (junction field-effect transistor) device and a diode are used. The gate of the first JFET device 11 is connected to the source port 6 of the power device, the drain is connected to the negative terminal of the first diode 12, and the source is connected to the positive terminal of the internal power supply of the amplifier circuit. The positive terminal of the first diode 12 is connected to the drain port 5 of the power device. When the positive terminal voltage of the internal power supply of the amplifier circuit is lower than the threshold voltage of the first JFET device 11, the channel of the JFET is turned on. If the voltage at the drain port 5 of the power device is higher than the positive terminal voltage of the internal power supply of the amplifier circuit, current can flow from the drain port 5 of the power device through the channel of the first diode 11 and the first JFET device 12 into the positive terminal of the internal power supply of the amplifier circuit to charge the amplifier circuit. If the voltage at the drain port 5 of the power device is lower than the positive terminal voltage of the internal power supply of the amplifier circuit, the first diode 12 is reverse-biased to prevent the current from flowing out to the drain port 5 of the power device. When the positive terminal voltage of the internal power supply of the amplifier circuit is higher than the threshold voltage of the first JFET device 11, the channel of the JFET is pinched off, and current cannot flow through the first JFET device 11, preventing the positive terminal voltage of the internal power supply of the amplifier circuit from rising further. The amplifier circuit adjusts the offset voltage by configuring tail current sources; the amplifier circuit specifically includes the 1st to 16th MOS devices and the 1st to 6th tail current sources. The positive terminal of the amplifier circuit's internal power supply is the internal power supply VCC shown in the attached diagram. The negative terminal of the internal power supply is connected to the source port 6 of the power device. The non-inverting input terminal is connected to the drain port 5 of the power device, the inverting input terminal is connected to the source port 6 of the power device, and the output terminal is connected to the gate of the power device. This amplifier can have a fixed or adjustable offset voltage.

[0046] The amplifier circuit structure in this embodiment is as follows: Figure 5 As shown, the + and - terminals represent the non-inverting and inverting input terminals of the amplifier circuit, respectively, with Vout being the output terminal. The positive terminal of the amplifier circuit's internal power supply is the node containing the top horizontal line, and the negative terminal is the node containing the bottom horizontal line. The offset voltage of this amplifier can be adjusted by configuring the tail current sources 44 and 45.

[0047] The amplifier circuit specifically includes MOS devices 0 to 15 and tail current sources 0 to 5. The inverting input terminal of the amplifier circuit is connected to two series-connected MOS devices 314 and 312, and bias current is provided through tail current source 45. The source of MOS device 312 is connected to the source of MOS device 31 and MOS device 33.

[0048] The non-inverting input terminal of the amplifier circuit is connected to two series-connected MOS devices 315 and 313, and bias current is provided through the fourth tail current source 44; the source of the 13th MOS device 313 is connected to the source of the 4th MOS device 34 and the 6th MOS device 36.

[0049] The gate and drain of the third MOS device 33 are respectively connected to the gate of the second MOS device 32, and bias current is provided through the 0th tail current source 40; the drain of the second MOS device 32 is connected to the source of the 11th MOS device 311, and the source of the second MOS device 32 is connected to the source of the 7th MOS device 37; the drain of the 7th MOS device 37 is connected to the drain and gate of the 9th MOS device 39 and the gate of the 8th MOS device 38, and the gate of the 7th MOS device 37 is connected to the gate and drain of the 4th MOS device 34 and the 3rd tail current source 43; the negative terminal of the internal power supply of the amplifier circuit is connected to the source of the 9th MOS device 39, the source of the 8th MOS device 38, the drain of the 0th MOS device 30 and the 1st tail current source 41;

[0050] The drain and gate of the first MOS device 31 are connected to the first tail current source 41 and the gate of the 0th MOS device 30; the source of the 0th MOS device 30 is connected to the source of the 5th MOS device 35; the drain of the 5th MOS device 35 is connected to the drain and gate of the 10th MOS device 310 and the gate of the 11th MOS device 311; the gate of the 5th MOS device 35 is connected to the gate and drain of the 6th MOS device 36 and is provided with bias current through the second tail current source 42; the positive terminal of the internal power supply of the amplifier circuit is connected to the source of the 11th MOS device 311 and the source of the 10th MOS device 310;

[0051] The output of the amplifier circuit is connected to the drain of the 11th MOS device 311 and the drain of the 8th MOS device 38.

[0052] Power devices can be MOSFETs with low on-resistance; capacitors can be surface-mount capacitors or ceramic capacitors.

[0053] The power supply circuit supplies power to the amplifier circuit. When the voltage Vd at the drain port 5 of the power device is higher than the positive terminal voltage of the amplifier circuit's internal power supply, the power supply circuit supplies power to the amplifier circuit, and the capacitor connected to the positive terminal of the amplifier circuit's internal power supply is charged. When the voltage at the drain port 5 of the power device is lower than the positive terminal voltage of the amplifier circuit's internal power supply, the power supply circuit is turned off and does not work, and the capacitor supplies power to the amplifier circuit. Alternatively, charge pump technology can be used. When there is a voltage difference between the voltage Vd at the drain port 5 of the power device and the voltage Vs at the source port 6 of the power device, the charge between the drain port 5 and the source port 6 of the power device is transferred to the internal power supply to continue supplying power, thus maintaining continuous conduction for a long time.

[0054] This synchronous rectifier integrated circuit simulates the unidirectional conduction characteristics of a diode through an amplifier, which is designed to have an offset voltage Vos.

[0055] For ease of explanation, the on-resistance when the gate voltage of the MOS is equal to the internal power supply VCC voltage is defined as Rdson1, and Vs-Vos represents the voltage difference between the source port 6 voltage Vs and the offset voltage of the power device.

[0056] When the voltage at the drain port 5 of the power device remains higher than Vs-Vos, the amplifier pulls down the gate voltage of the MOS, the MOS is turned off, no current flows, simulating the cutoff characteristics of a diode.

[0057] When the voltage at drain port 5 of the power device remains below Vs-Vos, the amplifier pulls up the gate voltage of the MOS transistor, turning it on and allowing current to flow, simulating the conduction characteristics of a diode. Note that the current flows from source port 6 of the power device into drain port 5, so the voltage at drain port 5 is negative relative to the voltage at source port 6.

[0058] Specifically, when the current is between 0 and Vos / Rdson1, the amplifier circuit adjusts the gate voltage of the MOS transistor in real time based on the relationship between the voltage Vd at the drain port 5 of the power device and Vs-Vos. This adjusts the on-resistance of the MOS transistor, ensuring that the product of the on-resistance and the current equals the offset voltage Vos. Specifically, when a decrease in current causes the voltage Vd at the drain port 5 of the power device to be higher than Vs-Vos, the gate voltage is lowered to increase the MOS impedance, thus maintaining the product of the on-resistance and the current equal to the offset voltage Vos. Conversely, when an increase in current causes the voltage Vd at the drain port 5 of the power device to be lower than Vs-Vos, the gate voltage is raised to decrease the MOS impedance, thus maintaining the product of the on-resistance and the current equal to the offset voltage Vos. The negative feedback loop formed by the amplifier ensures that Vd = Vs-Vos, simulating the unidirectional conduction characteristic of a diode.

[0059] The circuit structure in Example 4 can also be as follows: Figure 6 As shown: The inverting input of the amplifier circuit is connected to two additional resistors to set the offset voltage. Specifically, the inverting input of the amplifier circuit is connected to the first resistor 8 and the second resistor 9. The other end of the first resistor 8 is connected to the positive terminal of the internal power supply of the amplifier circuit, and the second resistor 9 is connected to the drain of the power device. Then the set offset voltage Vos = VINT * R9 / R8, where VINT is the difference between the voltage at the positive terminal of the internal power supply of the amplifier circuit and the voltage at the source port 6 of the power device, R9 is the resistance value of the second resistor 9, and R8 is the resistance value of the first resistor.

[0060] Those skilled in the art can improve conversion efficiency by setting an appropriate offset voltage Vos. For example, in a discontinuous mode flyback power supply system, to set the gate voltage of the MOS to be pulled down in the latter part of the conduction interval, the offset voltage Vos needs to be set to the product of the MOS current value Ir and Rdson1 when it is desired to start pulling down the MOS gate, i.e., Vos = Rdson1 * Ir, in order to achieve a trade-off between conduction loss and turn-off loss.

[0061] Because of the amplifier's negative feedback loop, the gate voltage is adjusted as needed, eliminating the need for a switching synchronous rectifier circuit to pull the gate voltage up to the power supply voltage, thus reducing switching losses.

[0062] This application also provides a control method for a synchronous rectifier integrated circuit, specifically including:

[0063] The power supply circuit supplies power to the positive terminal of the amplifier circuit's internal power supply: when the voltage at terminal 5 of the power device's drain port is higher than the voltage at the positive terminal of the amplifier circuit's internal power supply, the power supply circuit supplies power to the amplifier circuit, and the capacitor connected to the positive terminal of the amplifier circuit's internal power supply is charged; when the voltage at terminal 5 of the power device's drain port is lower than the voltage at the positive terminal of the amplifier circuit's internal power supply, the power supply circuit is turned off and does not work, and the capacitor supplies power to the amplifier circuit.

[0064] The amplifier circuit is equipped with an offset voltage Vos. When the voltage Vd at the drain port 5 of the power device is continuously higher than the voltage difference Vs-Vos between the voltage Vs at the source port 6 of the power device and the offset voltage, the amplifier circuit pulls down the gate voltage of the power device, and the power device is turned off. When the voltage at the drain port 5 of the power device is continuously lower than the voltage difference Vs-Vos between the voltage Vs at the source port 6 of the power device and the offset voltage, the amplifier pulls up the gate voltage of the power device, and the power device is turned on.

[0065] Among them, when In this process, the amplifier circuit adjusts the gate voltage of the power device to ensure that the product of Rdson1 and I equals the offset voltage Vos. Here, I represents the current between the drain port 5 and source port 6 of the power device, and Rdson1 represents the on-resistance of the power device. Even when a MOS with a very small on-resistance Rdson1 is used in applications with very low current, this invention can still guarantee that its on-state voltage drop is Vos. This is highly beneficial for feedback in primary-side feedback AC-to-DC conversion systems that rely on on-state voltage drop, improving feedback accuracy and load regulation. It also solves the matching problem between the on-resistance of the power device and the application current, reducing selection difficulty and demonstrating strong versatility.

[0066] The beneficial effects of this invention are that, compared with the prior art, it achieves smooth zero-current turn-off and conduction voltage control through the negative feedback characteristics of the amplifier, which is closer to the characteristics of an ideal diode. Therefore, there is no risk of malfunction in the traditional solution, nor is there a minimum switching time limitation. Thus, there is no problem of limiting the application frequency range in the traditional solution, and it has good versatility and adaptability to various power supply systems.

[0067] The beneficial effects of this invention also include: the synchronous rectification integrated circuit uses an internal amplifier to drive the gate of the power device to control its on / off state and can adjust the on-resistance in real time according to the current magnitude. It replaces the on-voltage drop of the rectifier diode with the reference voltage input to the amplifier, improving conversion efficiency, reducing switching losses, and solving the matching problem between the on-resistance of the power device and the application current. This is a highly efficient and versatile synchronous rectification circuit.

[0068] The applicant of this invention has provided a detailed description of the embodiments of the invention in conjunction with the accompanying drawings. However, those skilled in the art should understand that the above embodiments are merely preferred embodiments of the invention. The detailed description is only intended to help readers better understand the spirit of the invention and is not intended to limit the scope of protection of the invention. On the contrary, any improvements or modifications made based on the inventive spirit of the invention should fall within the scope of protection of the invention.

Claims

1. A synchronous rectification integrated circuit, comprising a power device, a power supply circuit, a capacitor, and an amplifier circuit packaged on the same chip, characterized in that: The chip also includes a power device drain port (5) and a power device source port (6); the gate of the power device is connected to the output terminal of the amplifier circuit, the source is connected to the power device source port (6), and the drain is connected to the power device drain port (5). One end of the power supply circuit is connected to the drain port (5) of the power device, and the other end is connected to the positive terminal of the capacitor and the positive terminal of the internal power supply of the amplifier circuit. The negative terminal of the capacitor is connected to the source port (6) of the power device, the non-inverting input terminal of the amplifier circuit and the negative terminal of the internal power supply of the amplifier circuit, respectively. The inverting input terminal of the amplifier circuit is connected to the drain port (5) of the power device. The amplifier circuit is equipped with an offset voltage Vos. When the voltage at the drain port (5) of the power device is continuously higher than the voltage difference Vs-Vos between the voltage Vs at the source port (6) of the power device and the offset voltage Vos, the amplifier circuit pulls down the gate voltage of the power device, and the power device is turned off. When the voltage at the drain port (5) of the power device is continuously lower than the voltage difference Vs-Vos between the voltage Vs at the source port (6) of the power device and the offset voltage Vos, the amplifier pulls up the gate voltage of the power device, and the power device is turned on. When the current I between the drain port (5) and the source port (6) of the power device is between 0 and Vos / Rdson1, the amplifier circuit adjusts the gate voltage of the power device in real time according to the relationship between the voltage at the drain port (5) and Vs-Vos, thereby adjusting the on-resistance of the power device so that the product of its on-resistance and current is equal to the offset voltage Vos. Rdson1 refers to the on-resistance when the gate voltage of the power device is equal to the positive terminal voltage of the internal power supply of the amplifier circuit.

2. The synchronous rectification integrated circuit according to claim 1, characterized in that: The power device is a MOSFET.

3. The synchronous rectification integrated circuit according to claim 2, characterized in that: When the voltage at the drain port (5) of the power device is higher than the positive terminal voltage of the internal power supply of the amplifier circuit, the power supply circuit supplies power to the positive terminal of the internal power supply of the amplifier circuit, and the capacitor connected to the positive terminal of the internal power supply of the amplifier circuit is charged; when the voltage at the drain port (5) of the power device is lower than the positive terminal voltage of the internal power supply of the amplifier circuit, the power supply circuit is turned off and does not work, and the capacitor supplies power to the amplifier circuit.

4. A synchronous rectification integrated circuit according to claim 3, characterized in that: The power supply circuit includes a first power supply circuit composed of a first JFET device (11) and a first diode (12), wherein the gate of the first JFET device is connected to the source port (6) of the power device, the drain of the first JFET device is connected to the negative terminal of the first diode, and the source is connected to the positive terminal of the internal power supply of the amplifier circuit; the positive terminal of the first diode is connected to the drain port (5) of the power device.

5. A synchronous rectification integrated circuit according to claim 4, characterized in that: The power supply circuit also includes a second power supply circuit (2) consisting of a second JFET device (21) and a second diode (22).

6. A synchronous rectification integrated circuit according to claim 5, characterized in that: The chip is set with a power supply port (7). The pin of the power supply port (7) is connected to the anode of the second diode (22) of the second power supply circuit (2). The gate of the second JFET device (21) is connected to the source port (6) of the power device. The drain is connected to the negative terminal of the second diode (22). The source is connected to the positive terminal of the power supply inside the amplifier circuit.

7. A synchronous rectification integrated circuit according to claim 6, characterized in that: The amplifier circuit adjusts the offset voltage by configuring a tail current source; the amplifier circuit specifically includes MOS devices 0 to 15 and tail current sources 0 to 5.

8. A synchronous rectification integrated circuit according to claim 7, characterized in that: The inverting input of the amplifier circuit is connected to two series-connected 12th and 14th MOS devices (314, 312), and bias current is provided through the 5th tail current source (45); the source of the 12th MOS device (312) is connected to the source of the 1st MOS device (31) and the 3rd MOS device (33); The non-inverting input of the amplifier circuit is connected to two series-connected 15th and 13th MOS devices (315, 313), and bias current is provided through the fourth tail current source (44); the source of the 13th MOS device (313) is connected to the source of the 4th MOS device (34) and the 6th MOS device (36); The gate and drain of the 3rd MOS device (33) are connected to the gate of the 2nd MOS device (32) respectively, and bias current is provided through the 0th tail current source (40); the drain of the 2nd MOS device (32) is connected to the source of the 11th MOS device (311), and the source of the 2nd MOS device (32) is connected to the source of the 7th MOS device (37); the drain of the 7th MOS device (37) is connected to the drain and gate of the 9th MOS device (39) and the gate of the 8th MOS device (38), and the gate of the 7th MOS device (37) is connected to the gate and drain of the 4th MOS device (34) and the 3rd tail current source (43); the negative terminal of the internal power supply of the amplifier circuit is connected to the source of the 9th MOS device (39), the source of the 8th MOS device (38), the drain of the 0th MOS device (30), and the 1st tail current source (41). The drain and gate of the 1st MOS device (31) are connected to the first tail current source (41) and the gate of the 0th MOS device (30); the source of the 0th MOS device (30) is connected to the source of the 5th MOS device (35); the drain of the 5th MOS device (35) is connected to the drain and gate of the 10th MOS device (310) and the gate of the 11th MOS device (311); the gate of the 5th MOS device (35) is connected to the gate and drain of the 6th MOS device (36) and is provided with bias current through the second tail current source (42); the positive terminal of the internal power supply of the amplifier circuit is connected to the source of the 11th MOS device (311) and the source of the 10th MOS device (310); The output of the amplifier circuit is connected to the drain of the 11th MOS device (311) and the drain of the 8th MOS device (38).

9. A synchronous rectification integrated circuit control method, based on a synchronous rectification integrated circuit according to any one of claims 1-8, characterized in that: The power supply circuit supplies power to the positive terminal of the internal power supply of the amplifier circuit: when the voltage at the drain port (5) of the power device is higher than the voltage at the positive terminal of the internal power supply of the amplifier circuit, the power supply circuit supplies power to the amplifier circuit, and the capacitor connected to the positive terminal of the internal power supply of the amplifier circuit is charged; when the voltage at the drain port (5) of the power device is lower than the voltage at the positive terminal of the internal power supply of the amplifier circuit, the power supply circuit is turned off and does not work, and the capacitor supplies power to the amplifier circuit. The amplifier circuit is equipped with an offset voltage Vos. When the voltage Vd at the drain port (5) of the power device is continuously higher than the voltage difference Vs-Vos between the voltage Vs at the source port (6) of the power device and the offset voltage Vos, the amplifier circuit pulls down the gate voltage of the power device, and the power device is turned off. When the voltage at the drain port (5) of the power device is continuously lower than the voltage difference Vs-Vos between the voltage Vs at the source port (6) of the power device and the offset voltage Vos, the amplifier pulls up the gate voltage of the power device, and the power device is turned on. Among them, when At that time, the amplifier circuit adjusts the gate voltage of the power device to control The product of I and I equals the offset voltage Vos, where I represents the current value between the drain port (5) and the source port (6) of the power device. This represents the on-resistance when the gate voltage of the power device equals the positive terminal voltage of the internal power supply of the amplifier circuit.

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