Fault detection methods and equipment for storage units

Abstract

This disclosure provides a method and apparatus for fault detection of storage cells. The method includes: writing first data to each storage cell in the storage array according to their address order; performing the data read / write process M times, including: after waiting for a preset time, reading second data to each storage cell in the address order and writing third data backwards, where M is an integer greater than or equal to 2; and determining whether a data retention fault exists in the storage cell based on the first data, second data, and third data. The preset waiting time is a necessary condition for a data retention fault to occur in the storage cell. That is, within the preset waiting time, the storage cell may experience leakage, leading to a data retention fault. This allows for the detection of data retention faults in as many storage cells as possible, improving the test coverage and accuracy of data retention fault detection.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a method and apparatus for fault detection of a memory cell. Background Technology

[0002] DRAM (Dynamic Random Access Memory) is a type of internal memory that includes at least one memory array. Each memory array consists of M rows and N columns of memory cells, and each memory cell can store one bit of data, either "1" or "0". Thus, a memory array can store M × N bits of data. It can be seen that the capacity of DRAM is related to the number of memory cells. The storage of data in a memory cell is achieved by storing electrical charge through a storage capacitor; the amount of charge is related to the amount of data stored.

[0003] However, leakage in the storage capacitors can lead to data loss, meaning the storage unit has a data retention failure. How to detect data retention failures in storage units is a pressing technical problem that needs to be solved. Summary of the Invention

[0004] This disclosure provides a method and apparatus for detecting faults in a storage unit, in order to detect data retention faults in the storage unit.

[0005] In a first aspect, embodiments of this disclosure provide a fault detection method for a storage cell, the method comprising:

[0006] Write the first data to each storage cell in the storage array one by one according to the address order of each storage cell in the storage array;

[0007] The data read and write process is executed M times. The data read and write process includes: after waiting for a preset time, reading each storage unit in the storage array one by one according to the address order of each storage unit to obtain the second data, and writing the third data back to the storage unit. The preset time of some or all of the data read and write processes is greater than 0, and M is an integer greater than or equal to 2.

[0008] Based on the first data, the second data, and the third data, determine whether the storage unit has a data retention fault.

[0009] In some implementations, the first data corresponding to different storage units may be the same or different, and the third data corresponding to different storage units may be the same or different during a single data read / write operation.

[0010] In some implementations, the first data is different from the third data written in the first reverse write, and the third data is different in two consecutive reverse writes.

[0011] In some implementations, each data read / write process includes: reading second data multiple times and / or writing third data backwards multiple times.

[0012] In some implementations, it also includes:

[0013] Before performing the first data read / write process, the preset duration of the first data read / write process is determined based on the first data, and different first data correspond to different preset durations;

[0014] Before performing the Nth data read / write process, the preset duration of the Nth data read / write process is determined based on the third data of the (N-1)th data read / write process. Different third data correspond to different preset durations, and N is greater than or equal to 2 and less than or equal to M.

[0015] In some implementations, the data read / write process with a preset duration greater than 0 includes: a first data read / write process executed after writing data "1" to the storage unit, and a second data read / write process executed after writing data "0" to the storage unit.

[0016] In some implementations, before the preset waiting time, the method further includes:

[0017] The target voltage is determined based on the last data written to the storage unit before the data read / write process. When the data is "1", the target voltage is a low-level voltage, and when the data is "0", the target voltage is a high-level voltage.

[0018] The target voltage is applied to the target plate of the storage capacitor of the storage cell. The target voltage is a necessary condition for the data retention fault. The target plate is the plate of the storage capacitor that is not connected to the transistor of the storage cell.

[0019] In some implementations, writing the third data back to the storage unit includes:

[0020] When the number of reverse writes is less than M, the third data is reverse written to the storage unit.

[0021] In some implementations, determining whether the storage unit has a data retention fault based on the first data, the second data, and the third data includes:

[0022] Based on the second data read in the first reading and the first data, determine whether the storage unit has a data retention fault; and / or,

[0023] Based on the second data read on the Nth time and the third data written back on the N-1th time, it is determined whether the storage unit has a data retention fault, where N is an integer greater than or equal to 2 and less than or equal to M.

[0024] In some implementations, determining whether the storage unit has a data retention fault based on the second data read in the first reading and the first data includes:

[0025] If the second data read for the first time is inconsistent with the first data, it is determined that the corresponding storage unit has a data retention failure;

[0026] If the second data read for the first time is consistent with the first data, then it is determined that the corresponding storage unit does not have a data retention fault.

[0027] In some implementations, determining whether the storage unit has a data retention fault based on the second data read for the Nth time and the third data written back for the (N-1)th time includes:

[0028] If the second data read on the Nth time is inconsistent with the third data written on the (N-1)th time, then it is determined that the corresponding storage unit has a data retention fault.

[0029] If the second data read on the Nth time is consistent with the third data written on the (N-1)th time, then it is determined that the corresponding storage unit does not have a data retention fault.

[0030] Secondly, embodiments of this disclosure provide a fault detection device for a storage cell, comprising:

[0031] The first data writing module is used to write first data to each storage cell in the storage array one by one according to the address order of each storage cell in the storage array;

[0032] The read / write execution module is used to execute the data read / write process M times. The data read / write process includes: after waiting for a preset time, reading each storage unit in the storage array one by one according to the address order of each storage unit to obtain the second data, and writing the third data back to the storage unit. The preset time of some or all of the data read / write processes is greater than 0, and M is an integer greater than or equal to 2.

[0033] The fault detection module is used to determine whether the storage unit has a data retention fault based on the first data, the second data, and the third data.

[0034] In some implementations, the first data corresponding to different storage units may be the same or different, and the third data corresponding to different storage units may be the same or different during a single data read / write operation.

[0035] In some implementations, the first data is different from the third data written in the first reverse write, and the third data is different in two consecutive reverse writes.

[0036] In some implementations, each data read / write process includes: reading second data multiple times and / or writing third data backwards multiple times.

[0037] In some implementations, it also includes:

[0038] The first preset duration determination module is used to determine the preset duration of the first data read / write process based on the first data before performing the first data read / write process. Different first data correspond to different preset durations.

[0039] The second preset duration determination module is used to determine the preset duration of the Nth data read / write process based on the third data of the (N-1)th data read / write process before performing the Nth data read / write process. Different third data correspond to different preset durations, and N is greater than or equal to 2 and less than or equal to M.

[0040] In some implementations, the data read / write process with a preset duration greater than 0 includes: a first data read / write process executed after writing data "1" to the storage unit, and a second data read / write process executed after writing data "0" to the storage unit.

[0041] In some embodiments, the apparatus further includes:

[0042] The target voltage determination module is used to determine the target voltage based on the last data written to the storage unit before the data read / write process. When the data is "1", the target voltage is a low-level voltage, and when the data is "0", the target voltage is a high-level voltage.

[0043] A target voltage application module is used to apply the target voltage to the target plate of the storage capacitor of the storage cell. The target voltage is a necessary condition for the data retention fault. The target plate is the plate of the storage capacitor that is not connected to the transistor of the storage cell.

[0044] In some implementations, the read / write execution module is further configured to:

[0045] During the process of writing the third data back to the storage unit, the third data is written back to the storage unit when the number of writes is less than M.

[0046] In some implementations, the fault detection module is further used for:

[0047] Based on the second data read in the first reading and the first data, determine whether the storage unit has a data retention fault; and / or,

[0048] Based on the second data read on the Nth time and the third data written back on the N-1th time, it is determined whether the storage unit has a data retention fault, where N is an integer greater than or equal to 2 and less than or equal to M.

[0049] In some implementations, the fault detection module is further used for:

[0050] In the process of determining whether the storage unit has a data retention fault based on the second data read in the first reading and the first data, if the second data read in the first reading is inconsistent with the first data, then it is determined that the corresponding storage unit has a data retention fault.

[0051] If the second data read for the first time is consistent with the first data, then it is determined that the corresponding storage unit does not have a data retention fault.

[0052] In some implementations, the fault detection module is further used for:

[0053] In the process of determining whether the storage unit has a data retention fault based on the second data read for the Nth time and the third data written back for the N-1th time, if the second data read for the Nth time and the third data written back for the N-1th time are inconsistent, then it is determined that the corresponding storage unit has a data retention fault.

[0054] If the second data read on the Nth time is consistent with the third data written on the (N-1)th time, then it is determined that the corresponding storage unit does not have a data retention fault.

[0055] Thirdly, embodiments of this disclosure also provide an electronic device, including: at least one processor and a memory;

[0056] The memory stores computer-executed instructions;

[0057] The at least one processor executes computer execution instructions stored in the memory, causing the electronic device to implement the method described in the first aspect.

[0058] Fourthly, embodiments of this disclosure also provide a computer-readable storage medium storing computer-executable instructions, which, when executed by a computing device, cause the computing device to implement the method described in the first aspect.

[0059] Fifthly, embodiments of this disclosure also provide a computer program product for performing the method described in the first aspect.

[0060] The storage cell fault detection method and apparatus provided in this disclosure, after at least one data write process in the March algorithm, waits for a preset time before proceeding with the data read process. This preset waiting time is a necessary condition for a data retention fault to occur in the storage cell; that is, within this preset waiting time, the storage cell may experience current leakage, leading to a data retention fault. In this way, data retention faults in all storage cells can be detected as much as possible, helping to improve the test coverage and accuracy of data retention fault detection. Attached Figure Description

[0061] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the embodiments of the present disclosure.

[0062] Figure 1 This is a schematic diagram illustrating the write order of a march process provided in an embodiment of this disclosure;

[0063] Figure 2 This is a flowchart of the steps of a fault detection method for a storage unit provided in an embodiment of this disclosure;

[0064] Figure 3 This is a schematic diagram of a fault detection method for a storage unit provided in an embodiment of this disclosure;

[0065] Figure 4 This is a schematic diagram of the structure of a fault detection device for a storage unit provided in an embodiment of this disclosure;

[0066] Figure 5 This is a structural block diagram of an electronic device provided in an embodiment of this disclosure.

[0067] The accompanying drawings have illustrated specific embodiments of the present disclosure, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the present disclosure in any way, but rather to illustrate the concepts of the present disclosure to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0068] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with those of this disclosure. Rather, they are merely examples of apparatuses and methods consistent with some aspects of the embodiments of this disclosure as detailed in the appended claims.

[0069] In the field of semiconductor technology, the presence of faults in memory cells can be tested by writing and reading data. For the same memory cell, if the data written to and read from the cell are the same, then the memory cell is considered to be fault-free. If the data written to and read from the cell are inconsistent, then the memory cell is considered to be faulty.

[0070] For a storage array containing multiple of the aforementioned storage units, embodiments of this disclosure can test the storage array using the march algorithm. The march algorithm is implemented through multiple march processes. In each march process, data is first written sequentially to all storage units of the storage array, and then data is read sequentially from each storage unit.

[0071] Figure 1 This is a schematic diagram illustrating the write order of a march process provided in an embodiment of this disclosure. (Refer to...) Figure 1 As shown, U1 to U25 are 25 memory cells in a memory array, with addresses from low to high. Therefore, during a march, data can be written to or read from memory cells U1 to U25 in the order of U1 to U25.

[0072] It is understood that the order of U1 to U25 is in ascending address order. In some implementations, data can also be written to U25 to U1 in descending address order, or data can be read from U25 to U1 in descending address order.

[0073] from Figure 1 As can be seen, the sequence of U1 to U25 writes or reads all memory cells on a bit line each time, and then reads the memory cells on the next bit line. In some implementations, all memory cells on a word line can be written or read each time, and then the memory cells on the next word line can be read.

[0074] As can be seen, for the same storage unit, the above multiple marching processes can obtain multiple pairs of written and read data. Therefore, based on these multiple pairs of written and read data, it can be determined whether the storage unit is faulty. If at least one pair of written and read data is inconsistent, then the storage unit is faulty. If all pairs of written and read data are consistent, then the storage unit is not faulty.

[0075] The march algorithm described above not only ensures that all memory units are tested, thus improving test coverage, but also allows for multiple march processes to test the same memory unit multiple times, which helps improve test accuracy.

[0076] To test for data retention failures, this embodiment of the disclosure waits for a preset time after at least one data write operation in the aforementioned March algorithm before performing a data read operation. This preset waiting time is a necessary condition for a storage unit to experience a data retention failure; that is, within this preset waiting time, the storage unit may experience current leakage, leading to a data retention failure. In this way, data retention failures in all storage units can be detected as much as possible, helping to improve the test coverage and accuracy for data retention failures.

[0077] Figure 2 This is a flowchart illustrating the steps of a fault detection method for a memory cell provided in this disclosure. The fault detection method for a memory cell in this disclosure can detect one memory array at a time. If multiple DRAM memory arrays need to be detected, then the fault detection method for the memory cell in this disclosure needs to be executed at least once for each memory array. Please refer to... Figure 2 The fault detection method for the aforementioned storage unit includes:

[0078] S101: Write the first data to each storage cell in the storage array one by one according to the address order of each storage cell in the storage array.

[0079] The address order here can be either ascending or descending, and this embodiment does not limit the specific setting of this order. In some implementations, the fault detection method of the storage unit can be performed at least once in ascending order of address, and then at least once in descending order of address, in order to better detect the fault of the storage unit.

[0080] In this embodiment of the disclosure, storage cells within the same storage array can correspond to the same data. When storage cells in the storage array correspond to the same first data, the write logic, read logic, and consistency judgment logic of different storage cells are all the same, which helps to reduce testing complexity.

[0081] It should be noted that when testing for data retention faults caused by coupling in memory cells, adjacent memory cells can be written with different first data. However, when testing for data retention faults unrelated to coupling, all memory cells can be written with the same first data. To write the first data to one of the memory cells, firstly, the word line of that memory cell is turned on to receive an activation signal, which is used to turn on the transistor of the memory cell. Then, the signal for the first data is received through the bit line, causing the sensing amplifier circuit to pull up the voltage of the bit line of that memory cell. Finally, the first plate of the memory cell is charged through the bit line to achieve the writing of the first data. After writing to the bit line, the transistor controlling the memory cell can be turned off to avoid accidental writing or reading from the memory cell.

[0082] S102: Execute the data read / write process M times. The data read / write process includes: after waiting for a preset time, reading each storage cell in the storage array one by one according to the address order of each storage cell to obtain the second data, and writing the third data back to the storage cell. The preset time of part or all of the data read / write process is greater than 0, and M is an integer greater than or equal to 2.

[0083] When M is greater than or equal to 2, the data read / write process is executed at least twice, meaning at least two reads and at least two writes. The second data read in the first read corresponds to the first data in S101, meaning that the presence of a data retention fault in the storage unit can be determined based on whether the second data and the corresponding first data are consistent. The data read in the Nth read corresponds to the third data written back during the (N-1)th data read / write process, meaning that the presence of a data retention fault in the storage unit can be determined based on whether the second data and the corresponding third data are consistent. No reads are performed after the third data written back last time, therefore the third data written back last time is not used when determining whether a data fault exists.

[0084] In some implementations, the third data corresponding to different storage units can be the same or different during a single data read / write operation. When the third data corresponding to different storage units is the same, the write-back logic, read logic, and consistency judgment logic of different storage units are all the same, which helps to reduce testing complexity.

[0085] When testing for data retention failures caused by coupling in storage cells, adjacent storage cells can be written with different third data. However, when testing for data retention failures unrelated to coupling, all storage cells can be written with the same third data.

[0086] In some implementations, the first data and the third data written in the first reverse write are different, and the third data in two consecutive reverse writes are different. That is, for the same storage unit, the data to be written can be switched continuously to better test the storage performance of the storage unit.

[0087] In some implementations, each data read / write process includes: reading second data multiple times and / or writing third data multiple times. The second data read multiple times can be the same, and the third data written multiple times can also be the same. In this way, the performance of the same storage unit under repeated read / write of the same data can be tested, which helps to improve the accuracy of the test.

[0088] The conventional process of writing third data to each of the above memory cells may include: first, pre-charging the bit line and complementary bit line of the memory cell so that the voltage of the bit line and complementary bit line reaches VCC / 2, where VCC is the logic voltage of data "1"; then, turning on the transistor of the memory cell through the word line of the memory cell, so that a path is formed between the bit line and the storage capacitor respectively connected to the transistor of the memory cell, so that the charge of the storage capacitor can be shared with the bit line, the voltage of the bit line changes, and the amount of voltage change is the voltage difference between the bit line and the complementary bit line; finally, after amplifying and sensing the voltage difference between the bit line and the complementary bit line, the data of the storage capacitor can be read from the voltage on the bit line.

[0089] In the present embodiment, since the transistor has already been turned on when reading the second data, it is not necessary to turn on the transistor again when writing the third data. This saves the time required to turn on the transistor, thereby saving test time and improving test efficiency.

[0090] In some implementations, the third data is written back to the storage unit during each of the above data read / write operations. In other implementations, the third data may not be written back to the storage unit during the last data read / write operation. Since there is no corresponding read process after the third data written back during the last data read / write operation, testing time can be saved and testing efficiency can be improved.

[0091] Specifically, before each execution of the fault detection method for the storage unit according to this embodiment of the present disclosure, the number of write-back attempts is initialized to 0, and the write-back attempt is incremented by 1 each time a write-back attempt is performed. When the number of write-back attempts is less than M, it is determined that the data read / write process is not the last one, so the third data can be written back to the storage unit, and the next data read / write process can continue. When the number of write-back attempts is greater than or equal to M, it is determined that the data read / write process is the last one, so the third data can be left unwritten to the storage unit, and the next data read / write process will not be executed, thus ending the data read / write cycle.

[0092] In some implementations, different waiting times can be corresponding to different data, which is equivalent to providing different leakage conditions for different data. This helps to match the preset time required for leakage with the charge of the data in the storage capacitor. While ensuring leakage, a smaller preset time can be selected as much as possible, which helps to save test time as much as possible while ensuring test accuracy.

[0093] After writing the first data and before performing the first data read / write process, the preset duration of the first data read / write process can be determined based on the first data. Different first data correspond to different preset durations. That is, the preset duration T1 of the first data read / write process when the first data written is "0" is different from the preset duration T2 of the first data read / write process when the first data written is "1".

[0094] After the (N-1)th data read / write process and before the Nth data read / write process, the preset duration of the Nth data read / write process is determined based on the third data from the (N-1)th data read / write process. Different third data correspond to different preset durations, where N is an integer greater than or equal to 2 and less than or equal to M. That is, the preset duration T3 for waiting during the Nth data read / write process when the third data written in the (N-1)th process is "0" is different from the preset duration T4 for waiting during the Nth data read / write process when the third data written in the (N-1)th process is "1".

[0095] As can be seen from S102, the preset duration of some or all data read / write processes in this embodiment of the present disclosure is greater than 0. That is, in some implementations, only a portion of the data read / write process actually waits. In this way, not only can the presence of data retention faults in the storage unit be tested, but the test time can also be shortened as much as possible, thereby improving test efficiency.

[0096] The aforementioned data read / write process with a preset duration greater than 0 may include: a first data read / write process executed after writing data "1" to the storage unit, and a second data read / write process executed after writing data "0" to the storage unit.

[0097] For example, if the first data written is "1", then the data in the storage unit is "1" before the first data read / write process is executed, thus the first data read / write process can be identified as the first data read / write process. Furthermore, if the first data written in the (N-1)th time is "0", then the data in the storage unit is "0" when the Nth data read / write process is executed, thus the Nth data read / write process can be identified as the second data read / write process.

[0098] For example, if the first data written is "0", then the data in the storage unit is "0" before the first data read / write process is executed, thus the first data read / write process can be identified as the second data read / write process. Furthermore, if the first data written in the (N-1)th time is "1", then the data in the storage unit is "1" when the Nth data read / write process is executed, thus the Nth data read / write process can be identified as the first data read / write process.

[0099] In some implementations, to detect data retention faults in the memory cell as accurately as possible, a leakage voltage condition can be provided to the storage capacitor of the memory cell. For example, before the preset waiting time in each data read / write process, a target voltage can be determined based on the last data written to the memory cell before the data read / write process. When the data is "1", the target voltage is a low-level voltage, and when the data is "0", the target voltage is a high-level voltage. The target voltage is applied to the target plate of the storage capacitor of the memory cell. The target voltage is a necessary condition for a data retention fault, and the target plate is the plate of the storage capacitor that is not connected to the transistor of the memory cell.

[0100] It is understandable that the storage capacitor has two plates. One plate, P1, is connected to the bit line via a transistor and is used to store data. The voltage of plate P1 is related to the stored data. The other plate, P2 (which is the target plate mentioned above), is not connected to the transistor.

[0101] When the data in the memory cell is "1", the voltage on P1 is the logic voltage of "1", which is a high-level voltage. At this time, applying a low-level voltage to P2 can create a voltage difference between P1 and P2. This voltage difference can cause P1 to leak as much as possible, thus causing a data retention fault in the memory cell and making it possible to detect data retention faults of the memory cell for the data "1" as much as possible.

[0102] When the data in the memory cell is "0", the voltage on P1 is the logic voltage of "0", which is a low-level voltage. At this time, applying a low-level voltage to P2 can create a voltage difference between P2 and P1. This voltage difference can cause P2 to leak as much as possible, thus causing a data retention fault in the memory cell, and can detect data retention faults of "0" data in the memory cell as much as possible.

[0103] S103: Based on the first data, the second data, and the third data, determine whether there is a data retention fault in the storage unit.

[0104] As can be seen from S102, when M is greater than or equal to 2, this embodiment of the present disclosure performs more than two writes and at least two reads. Therefore, for any read, to determine whether a storage cell has a data retention fault, it is necessary to compare the read data with the data in the storage cell before the read, that is, to compare it with the data of the last write before the read.

[0105] For the first read, determine whether the storage cell has a data retention fault based on the second data and the first data read in the first read; and / or, for the second and subsequent reads, determine whether the storage cell has a data retention fault based on the second data read in the Nth read and the third data written in the N-1th reverse read, where N is an integer greater than or equal to 2 and less than or equal to M.

[0106] Understandably, for the first read, if the second data read is inconsistent with the first data, it is determined that the corresponding storage unit has a data retention fault; if the second data read is consistent with the first data, it is determined that the corresponding storage unit does not have a data retention fault.

[0107] Accordingly, for the second and subsequent reads, if the second data read in the Nth read is inconsistent with the third data written in the (N-1)th read, then the corresponding storage unit is determined to have a data retention fault; if the second data read in the Nth read is consistent with the third data written in the (N-1)th read, then the corresponding storage unit is determined not to have a data retention fault.

[0108] Of course, for a given storage unit, if a data retention fault is determined to exist after at least one read, then the storage unit can be determined to have a data retention fault. If a data retention fault is determined to not exist after all reads, then the storage unit can be determined to have no data retention fault.

[0109] In some implementations, if a storage unit is found to have a data retention fault after the Nth read, it is not necessary to determine whether the storage unit has a data retention fault based on the N+1 to Mth reads. This can save test time and improve test efficiency.

[0110] It should be noted that after each read, the presence of a data retention fault in the storage unit can be determined based on the read data and the previously written data. Furthermore, after all reads, the presence of a data retention fault in the storage unit can be determined based on all read data and the corresponding previously written data.

[0111] Figure 3 This is a schematic diagram illustrating fault detection of a storage unit according to an embodiment of this disclosure. (Refer to...) Figure 3As shown, the storage cells of the storage array are detected for faults through a 6-march process.

[0112] During the first March process, write the first data "0" to all U1 to U25.

[0113] After waiting for the preset time, the second march process is executed. In the second march process, the second data is read from U1 to U25, and the third data "1" is written backwards.

[0114] After waiting for the preset time, the third march process is executed. During the third march process, the second data is read from U1 to U25, and the third data "0" is written backwards.

[0115] During the fourth march, the second data is read from U1 to U25, and the third data "1" is written backwards.

[0116] During the fifth March process, the second data is read from U1 to U25, and the third data "0" is reversed.

[0117] During the fifth march, the fourth data is read from U1 to U25.

[0118] It can be seen that, Figure 3 The fault detection process for the storage unit only waits for a preset time after the first and second March processes, which helps to save testing time as much as possible and improve testing efficiency. Furthermore, since the data previously written was "0" when the second March process reads it, a data retention fault for the storage unit containing "0" data can be detected after the second March process reads it. Since the data previously written was "1" when the third March process reads it, a data retention fault for the storage unit containing "1" data can be detected after the third March process. Thus, data retention faults for all data in the storage unit can be detected through just two March processes.

[0119] Figure 3 The first March process shown corresponds to step S101. The second March process and the preceding waiting preset duration constitute the first data read / write process executed in S102. The third March process and the preceding waiting preset duration constitute the second data read / write process executed in S102. These two data processes are the data read / write processes with a preset duration greater than 0 mentioned in S102. The fourth to sixth March processes constitute one data read / write process in S102. These three data read / write processes are the data read / write processes with a preset duration of 0.

[0120] from Figure 3 It can be seen from this that Figure 3 The test vector used in the March algorithm is March C-. Of course, in practical applications, other March test vectors can also be used, and this embodiment does not limit them.

[0121] It is understandable that the more times the above-mentioned waiting occurs, the higher the test coverage, but the longer the test duration. Therefore, in order to minimize the test duration in scenarios with high coverage, the embodiments of this disclosure employ the above-mentioned... Figure 3 The two waits shown ensure coverage and result in a shorter test duration compared to waiting for each march.

[0122] In summary, although the fault detection method for storage units provided in this disclosure has a longer test time compared to the traditional March algorithm, which cannot detect data retention faults, it has a shorter test time compared to the combination of the traditional March algorithm and a dedicated test process for data retention faults. Figure 3 The fault detection process shown is twice as long as the preset duration of the traditional MarchC algorithm.

[0123] Corresponding to the above method embodiments, Figure 4 This is a schematic diagram of a fault detection device for a storage unit provided in an embodiment of this disclosure. Please refer to... Figure 4 The fault detection device 200 for the aforementioned storage unit includes:

[0124] The first data writing module 201 is used to write first data to each storage cell in the storage array one by one according to the address order of each storage cell in the storage array.

[0125] The read / write execution module 202 is used to execute the data read / write process M times. The data read / write process includes: after waiting for a preset time, reading each storage unit in the storage array one by one according to the address order of each storage unit in the storage array to obtain the second data, and writing the third data back to the storage unit. The preset time of part or all of the data read / write process is greater than 0, and M is an integer greater than or equal to 2.

[0126] The fault detection module 203 is used to determine whether there is a data retention fault in the storage unit based on the first data, the second data, and the third data.

[0127] In some implementations, the first data corresponding to different storage units is the same, and the third data corresponding to different storage units is the same during a single data read / write operation.

[0128] In some implementations, the first data is different from the third data written in reverse for the first time, and the third data is different in two consecutive reverse writes.

[0129] In some implementations, each data read / write process includes: reading second data multiple times and / or writing third data multiple times.

[0130] In some implementations, it also includes:

[0131] The first preset duration determination module is used to determine the preset duration of the first data read / write process based on the first data before the first data read / write process is performed. Different first data correspond to different preset durations.

[0132] The second preset duration determination module is used to determine the preset duration of the Nth data read / write process based on the third data of the N-1th data read / write process before performing the Nth data read / write process. Different third data correspond to different preset durations, and N is an integer greater than or equal to 2 and less than or equal to M.

[0133] In some implementations, the data read / write process with a preset duration greater than 0 includes: a first data read / write process executed after writing data "1" to the storage unit, and a second data read / write process executed after writing data "0" to the storage unit.

[0134] In some embodiments, the apparatus further includes:

[0135] The target voltage determination module is used to determine the target voltage based on the last data written to the storage unit before the data read / write process, before waiting for a preset time. When the data is "1", the target voltage is a low-level voltage, and when the data is "0", the target voltage is a high-level voltage.

[0136] A target voltage application module is used to apply the target voltage to the target plate of the storage capacitor of the storage cell. The target voltage is a necessary condition for the data retention fault. The target plate is the plate of the storage capacitor that is not connected to the transistor of the storage cell.

[0137] In some implementations, the read / write execution module is also used for:

[0138] During the process of writing the third data back to the storage unit, the third data is written back to the storage unit when the number of writes is less than M.

[0139] In some implementations, the fault detection module is also used for:

[0140] Based on the second and first data read in the first reading, determine whether the storage unit has a data retention fault; and / or,

[0141] Based on the second data read in the Nth time and the third data written back in the (N-1)th time, determine whether there is a data retention fault in the storage unit, where N is an integer greater than or equal to 2 and less than or equal to M.

[0142] In some implementations, the fault detection module is also used for:

[0143] In the process of determining whether a storage unit has a data retention fault based on the second data and the first data read in the first reading, if the second data and the first data read in the first reading are inconsistent, it is determined that the corresponding storage unit has a data retention fault.

[0144] If the second data read in the first reading is consistent with the first data, then it is determined that there is no data retention fault in the corresponding storage unit.

[0145] In some implementations, the fault detection module is also used for:

[0146] In the process of determining whether a storage unit has a data retention fault based on the second data read in the Nth time and the third data written in the N-1th time, if the second data read in the Nth time and the third data written in the N-1th time are inconsistent, then it is determined that the corresponding storage unit has a data retention fault.

[0147] If the second data read in the Nth time is consistent with the third data written in the (N-1)th time, then it is determined that there is no data retention fault in the corresponding storage unit.

[0148] The above-described apparatus embodiment is an embodiment corresponding to the foregoing method embodiment, and has the same technical effects as the method embodiment. A detailed description of this apparatus embodiment can be found in the detailed description of the foregoing method embodiment, and will not be repeated here.

[0149] Figure 5 This is a structural block diagram of an electronic device provided in an embodiment of the present disclosure. The electronic device 600 includes a memory 602 and at least one processor 601.

[0150] Among them, memory 602 stores computer-executed instructions.

[0151] At least one processor 601 executes computer execution instructions stored in memory 602, causing electronic device 601 to implement the aforementioned fault detection method for the memory unit.

[0152] In addition, the electronic device may also include a receiver 603 and a transmitter 604, wherein the receiver 603 is used to receive information from other devices or equipment and forward it to the processor 601, and the transmitter 604 is used to send information to other devices or equipment.

[0153] This disclosure also provides a computer-readable storage medium storing computer-executable instructions, which enable the computing device to implement a fault detection method for the storage unit when the computing device executes the computer-executable instructions.

[0154] This disclosure also provides a computer program product for executing the fault detection method for the aforementioned storage unit.

[0155] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0156] The sequence numbers of the embodiments disclosed above are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0157] The above are merely preferred embodiments of the present disclosure and do not limit the patent scope of the present disclosure. Any equivalent structural or procedural transformations made based on the description and drawings of the present disclosure, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of the present disclosure.

Claims

1. A method of failure detection of a memory cell, the method comprising: The method comprises: writing first data to each storage unit in the storage array in sequence according to the address of each storage unit in the storage array; performing M times of data read-write processes, the data read-write process comprising: after waiting for a preset time, reading each storage unit in the storage array in sequence according to the address of each storage unit to obtain second data, and writing third data to each storage unit, the preset time of part or all of the data read-write processes being greater than 0, and M being an integer greater than or equal to 2; determining whether the storage unit has a data retention fault according to the first data, the second data and the third data; The method further comprises: before performing the first data read-write process, determining the preset time of the first data read-write process according to the first data, different first data corresponding to different preset times; Before performing the Nth data read-write process, determining the preset time of the Nth data read-write process according to the third data of the (N-1)th data read-write process, different third data corresponding to different preset times, N being greater than or equal to 2 and less than or equal to M.

2. The method of claim 1, wherein, The first data corresponding to different storage units is the same or different, and the third data corresponding to different storage units in one data read-write process is the same or different.

3. The method of claim 2, wherein, The first data and the third data written for the first time are different, and the third data written for adjacent times is different.

4. The method of claim 3, wherein, Each data read-write process comprises: multiple times of reading second data and / or multiple times of writing third data.

5. The method of claim 1, wherein, The data read-write process with a preset time greater than 0 comprises: a first data read-write process performed after writing data "1" to the storage unit, and a second data read-write process performed after writing data "0" to the storage unit.

6. The method of claim 1, wherein, Before the waiting for a preset time, the method further comprises: determining a target voltage according to the data last written to the storage unit before the data read-write process, the target voltage being a low-level voltage when the data is "1", and the target voltage being a high-level voltage when the data is "0"; applying the target voltage to a target plate of a storage capacitor of the storage unit, the target voltage being a necessary condition for the data retention fault, and the target plate being a plate of the storage capacitor not connected to a transistor of the storage unit.

7. The method according to any one of claims 1 to 4, characterized in that, The writing of third data to the storage unit comprises: writing third data to the storage unit when the number of times of writing is less than M.

8. The method according to any one of claims 1 to 4, characterized in that, The determination of whether the storage unit has a data retention fault according to the first data, the second data and the third data comprises: determining whether the storage unit has a data retention fault according to the first data and the second data read for the first time; and / or determining whether the storage unit has a data retention fault according to the second data read for the Nth time and the third data written for the (N-1)th time, N being an integer greater than or equal to 2 and less than or equal to M.

9. The method of claim 8, wherein, The determining whether the storage unit has the data retention failure according to the second data read in the first time and the first data comprises: If the second data read in the first time and the first data are inconsistent, it is determined that the corresponding storage unit has the data retention failure; If the second data read in the first time and the first data are consistent, it is determined that the corresponding storage unit does not have the data retention failure.

10. The method of claim 8, wherein, The determining whether the storage unit has the data retention failure according to the second data read in the Nth time and the third data written in the N-1th time comprises: If the second data read in the Nth time and the third data written in the N-1th time are inconsistent, it is determined that the corresponding storage unit has the data retention failure; If the second data read in the Nth time and the third data written in the N-1th time are consistent, it is determined that the corresponding storage unit does not have the data retention failure.

11. An electronic device, comprising: comprise: at least one processor and a memory; The memory stores computer-executable instructions; The at least one processor executes the computer-executable instructions stored in the memory, so that the electronic device implements the method of any one of claims 1 to 10.

12. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer-executable instructions, and when the computing device executes the computer-executable instructions, the computing device implements the method of any one of claims 1 to 10.

13. A computer program product, characterised in that, The computer program product is used to execute the method of any one of claims 1 to 10.

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