Light-emitting element and display device including the same

Abstract

A light-emitting element according to an embodiment of the present invention includes: a first semiconductor layer; an active layer disposed on the first semiconductor layer; a second semiconductor layer disposed on the active layer; a third semiconductor layer including a 3-1 semiconductor layer and a 3-2 semiconductor layer stacked on the second semiconductor layer; and a fourth semiconductor layer disposed on the 3-2 semiconductor layer. The third semiconductor layer is a tunnel junction layer. The sum of the thicknesses of the fourth semiconductor layer and the 3-2 semiconductor layer is different from the sum of the thicknesses of the second semiconductor layer and the 3-1 semiconductor layer.

Description

Technical Field

[0001] Various embodiments of the present disclosure relate to a light-emitting element and a display device having the light-emitting element. Background Art

[0002] Light-emitting diodes can have relatively long durability even under harsh environmental conditions and have excellent performance in terms of lifespan and brightness. Recently, research on technologies for applying such light-emitting diodes to various display devices has become significantly more active.

[0003] As part of such research, technologies for manufacturing light-emitting diodes having ultra-small sizes corresponding to the micron or nanometer scale using an inorganic crystal structure (e.g., a structure formed by growing a nitride-based semiconductor) are being developed. The light-emitting diodes can be formed to have a small enough size to form pixels of a display device, etc. The light-emitting diodes can be grown individually on a substrate, and the grown light-emitting diodes can be separated from the substrate and used to manufacture a display panel. Summary of the Invention

[0004] Technical Problem

[0005] Various embodiments of the present disclosure relate to a light-emitting element using a tunnel junction layer (or a third semiconductor layer), in which an active layer is disposed at a position adjacent to the middle portion of the light-emitting element with respect to the longitudinal direction, so that the light output efficiency can be enhanced.

[0006] Various embodiments of the present disclosure relate to a display device including the light-emitting element.

[0007] Technical Solution

[0008] A light-emitting element according to an embodiment of the present disclosure may include: a first semiconductor layer; an active layer disposed on the first semiconductor layer; a second semiconductor layer disposed on the active layer; a third semiconductor layer including a 3-1 semiconductor layer and a 3-2 semiconductor layer stacked on the second semiconductor layer; and a fourth semiconductor layer disposed on the 3-2 semiconductor layer. The third semiconductor layer may be a tunnel junction layer. The sum of the thicknesses of the fourth semiconductor layer and the 3-2 semiconductor layer may be different from the sum of the thicknesses of the second semiconductor layer and the 3-1 semiconductor layer.

[0009] In an embodiment of the present disclosure, the first semiconductor layer, the fourth semiconductor layer, and the 3-2 semiconductor layer may include n-type semiconductor layers doped with an n-type dopant. The second semiconductor layer and the 3-1 semiconductor layer may include p-type semiconductor layers doped with a p-type dopant.

[0010] In an embodiment of the present disclosure, the sum of the thicknesses of the fourth semiconductor layer and the 3-2 semiconductor layer may be greater than the sum of the thicknesses of the second semiconductor layer and the 3-1 semiconductor layer.

[0011] In an embodiment of the present disclosure, the 3-1 semiconductor layer may be doped with a p-type dopant having a concentration higher than that of the p-type dopant in the second semiconductor layer. The 3-2 semiconductor layer may be doped with an n-type dopant having a concentration higher than that of the n-type dopant in the first semiconductor layer and the fourth semiconductor layer.

[0012] In an embodiment of the present disclosure, the light-emitting element may further include: an insulating layer surrounding an outer circumferential surface of each of the first semiconductor layer, the active layer, the second semiconductor layer, the third semiconductor layer, and the fourth semiconductor layer.

[0013] In an embodiment of the present disclosure, a distance from a contact surface between the 3-1 semiconductor layer and the 3-2 semiconductor layer to an outer surface of the fourth semiconductor layer may be different from a distance from the contact surface to an outer surface of the first semiconductor layer with respect to one direction.

[0014] In an embodiment of the present disclosure, a distance from the contact surface to an outer surface of the fourth semiconductor layer may be less than a distance from the contact surface to an outer surface of the first semiconductor layer with respect to one direction.

[0015] In an embodiment of the present disclosure, based on a point corresponding to half of an entire length of the light-emitting element with respect to one direction, the contact surface may be disposed closer to the outer surface of the fourth semiconductor layer than the outer surface of the first semiconductor layer.

[0016] A display device according to an embodiment of the present disclosure may include: a substrate including a display area including a plurality of pixel areas and a non-display area surrounding at least one side of the display area; and pixels disposed in each of the pixel areas. Each pixel may include a first electrode and a second electrode spaced apart from each other on the substrate, and a plurality of light-emitting elements electrically connected to each of the first electrode and the second electrode.

[0017] In an embodiment of the present disclosure, each of the light-emitting elements may include: a first semiconductor layer, an active layer, a second semiconductor layer, a third semiconductor layer, and a fourth semiconductor layer sequentially stacked in one direction. The third semiconductor layer may be a tunnel junction layer. The third semiconductor layer may include a 3-1 semiconductor layer directly disposed on the second semiconductor layer and a 3-2 semiconductor layer disposed between the 3-1 semiconductor layer and the fourth semiconductor layer.

[0018] In an embodiment of the present disclosure, a sum of thicknesses of the fourth semiconductor layer and the 3-2 semiconductor layer may be different from a sum of thicknesses of the second semiconductor layer and the 3-1 semiconductor layer.

[0019] In an embodiment of the present disclosure, the first semiconductor layer, the fourth semiconductor layer, and the 3-2 semiconductor layer may include an n-type semiconductor layer doped with an n-type dopant. The second semiconductor layer and the 3-1 semiconductor layer may include a p-type semiconductor layer doped with a p-type dopant.

[0020] In an embodiment of the present disclosure, the sum of the thicknesses of the 3-2 semiconductor layer and the fourth semiconductor layer sequentially stacked in one direction may be greater than the sum of the thicknesses of the second semiconductor layer and the 3-1 semiconductor layer sequentially stacked in one direction.

[0021] In an embodiment of the present disclosure, the 3-1 semiconductor layer may be doped with a p-type dopant having a concentration higher than the concentration of the p-type dopant in the second semiconductor layer. The 3-2 semiconductor layer may be doped with an n-type dopant having a concentration higher than the concentration of the n-type dopant in the first semiconductor layer and the fourth semiconductor layer.

[0022] In an embodiment of the present disclosure, the pixel may further include an insulating pattern disposed on one surface of each of the light-emitting elements. The insulating pattern may overlap with each of the light-emitting elements between the first electrode and the second electrode.

[0023] In an embodiment of the present disclosure, the distance from the contact surface between the 3-1 semiconductor layer and the 3-2 semiconductor layer to the outer surface of the fourth semiconductor layer in one direction may be less than the distance from the contact surface to the outer surface of the first semiconductor layer. Here, based on the point corresponding to half of the entire length of each of the light-emitting elements in one direction, the contact surface may be disposed closer to the outer surface of the fourth semiconductor layer than the outer surface of the first semiconductor layer.

[0024] In an embodiment of the present disclosure, the contact surface may be disposed between the point corresponding to half of the entire width of the surface of the insulating pattern in contact with each of the light-emitting elements in the longitudinal direction of each of the light-emitting elements and the point corresponding to one end of the surface.

[0025] In an embodiment of the present disclosure, the active layer of each of the light-emitting elements may include a first surface in contact with the first semiconductor layer in one direction, and a second surface opposite to the first surface and in contact with the second semiconductor layer. The first surface of the active layer may be disposed between the point corresponding to half of the entire width of the surface of the insulating pattern in contact with each of the light-emitting elements in the longitudinal direction of each of the light-emitting elements and the point corresponding to the other end of the surface.

[0026] In an embodiment of the present disclosure, the pixel may further include: a bank pattern disposed between the substrate and the first electrode and between the substrate and the second electrode; a first contact electrode connecting each of the light-emitting elements to the first electrode; and a second contact electrode connecting each of the light-emitting elements to the second electrode.

[0027] In an embodiment of the present disclosure, each of the light-emitting elements may include an insulating layer surrounding the outer peripheral surface of the first semiconductor layer, the outer peripheral surface of the active layer, the outer peripheral surface of the second semiconductor layer, the outer peripheral surface of the third semiconductor layer, and the outer peripheral surface of the fourth semiconductor layer, which are sequentially stacked in one direction. Here, the outer surface of the first semiconductor layer may not be covered by the insulating layer, and a part of the outer peripheral surface of the first semiconductor layer may not be covered by the insulating layer. The outer surface of the fourth semiconductor layer may not be covered by the insulating layer, and a part of the outer peripheral surface of the fourth semiconductor layer is not covered by the insulating layer.

[0028] In an embodiment of the present disclosure, the first contact electrode may be in direct contact with a part of the outer peripheral surface and the outer surface of the first semiconductor layer. The second contact electrode may be in direct contact with a part of the outer peripheral surface and the outer surface of the fourth semiconductor layer.

[0029] The display device in an embodiment of the present disclosure may include: a substrate, on which a plurality of pixels are disposed. Each of the pixels may include: a plurality of light-emitting elements disposed on the substrate; and a first electrode and a second electrode, the first electrode being electrically connected to one end of each of the light-emitting elements, the second electrode being electrically connected to the remaining end of each of the light-emitting elements, and the first electrode and the second electrode being spaced apart from each other.

[0030] In an embodiment of the present disclosure, each of the light-emitting elements may include: a first semiconductor layer, an active layer, a second semiconductor layer, a third semiconductor layer, and a fourth semiconductor layer stacked in one direction. The third semiconductor layer may be a tunnel junction layer and include a 3-1 semiconductor layer directly disposed on the second semiconductor layer and a 3-2 semiconductor layer disposed between the 3-1 semiconductor layer and the fourth semiconductor layer.

[0031] In an embodiment of the present disclosure, the same type of semiconductor layers are disposed at opposite ends of each of the light-emitting elements.

[0032] In an embodiment of the present disclosure, the distance from the contact surface between the 3-1 semiconductor layer and the 3-2 semiconductor layer to the outer surface of the fourth semiconductor layer may be less than the distance from the contact surface to the outer surface of the first semiconductor layer with respect to one direction.

[0033] In an embodiment of the present disclosure, a first semiconductor layer may be disposed at one of opposite ends of each of the light-emitting elements, and a fourth semiconductor layer may be disposed at the remaining end of opposite ends of each of the light-emitting elements. The first semiconductor layer and the fourth semiconductor layer may include an n-type semiconductor layer doped with an n-type dopant.

[0034] Advantageous Effects

[0035] Embodiments of the present disclosure may provide a light-emitting element in which, in a light-emitting stack pattern including a tunnel junction layer (or a third semiconductor layer), the sum of the thicknesses of the fourth semiconductor layer (n-type semiconductor layer) and the 3-2 junction semiconductor layer (high-concentration n-type semiconductor layer) is designed to be greater than the sum of the thicknesses of the second semiconductor layer (p-type semiconductor layer) and the 3-1 junction semiconductor layer (high-concentration p-type semiconductor layer), so that the efficiency of light emitted from the active layer can be enhanced.

[0036] In addition, embodiments of the present disclosure may provide a light-emitting element in which the active layer is disposed adjacent to the middle (or center) portion of the light-emitting element with respect to the longitudinal direction of the light-emitting element, so that the efficiency of light emitted from the active layer can be further enhanced.

[0037] In addition, embodiments of the present disclosure may provide a display device including a light-emitting device.

[0038] The effects of the present disclosure are not limited to the foregoing, and various other effects are expected herein. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 is a schematic perspective view showing a light-emitting element according to an embodiment of the present disclosure.

[0040] Figure 2 is a schematic cross-sectional view showing Figure 1 the light-emitting element.

[0041] Figures 3a to 3k is a cross-sectional view sequentially showing a method of manufacturing Figure 1 and Figure 2 the light-emitting element.

[0042] Figure 4 shows a display device according to an embodiment of the present disclosure, specifically, is a schematic plan view showing a display device using the light-emitting element shown in Figure 1 and Figure 2 as a light source.

[0043] Figures 5a to 5e is a circuit diagram showing various embodiments of the electrical connection relationship of components included in one pixel shown in Figure 4 .

[0044] Figure 6 is a schematic plan view showing Figure 4 one pixel among the pixels shown in

[0045] Figure 7 is a schematic plan view showing a pixel including components other than the first bank pattern and the second bank pattern Figure 6 of

[0046] Figure 8 is a cross-sectional view taken along line I-I' of Figure 6

[0047] Figures 9 to 11 is Figure 8 an enlarged cross-sectional view of part EA of

[0048] Figure 12 is a cross-sectional view taken along line II-II' of Figure 6

[0049] Figure 13 shows Figure 12 another embodiment of the first bank pattern shown in Figure 6 and is a cross-sectional view corresponding to line II-II' of

[0050] Figure 14 shows Figure 12 another embodiment of the second contact electrode shown in Figure 6 and is a cross-sectional view corresponding to line II-II' of

[0051] Figure 15 is a cross-sectional view taken along line III-III' of Figure 6 DETAILED DESCRIPTION

[0052] Since the present disclosure allows various changes and many embodiments, specific embodiments will be shown in the drawings and described in detail in the written description. However, this is not intended to limit the present disclosure to the specific modes of practice, and it should be understood that all changes, equivalents, and alternatives that do not depart from the technical scope of the present disclosure are included in the present disclosure.

[0053] ​​​Throughout the disclosure, in the various figures and embodiments of the disclosure, the same reference numerals denote the same components. For clarity of illustration, the dimensions of the elements in the figures may be exaggerated. It will be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the teachings of the disclosure, the first element discussed below may be referred to as the second element. Similarly, the second element may also be referred to as the first element. In the disclosure, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form.

[0054] It will also be understood that when the terms "comprising", "including", "having", etc. are used in this specification, it is stated that there are the stated features, wholes, steps, operations, elements, components and / or combinations thereof, but does not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or combinations thereof. In addition, in the case where a first component such as a layer, film, region or plate is disposed on a second component, the first component may not only be directly on the second component, but a third component may be disposed between the first component and the second component. Further, in the case where a first component such as a layer, film, region or plate is formed on a second component, the surface of the second component on which the first component is formed is not limited to the upper surface of the second component, but may include other surfaces such as the side surface or the lower surface of the second component. Conversely, in the case where a first component such as a layer, film, region or plate is under a second component, the first component may not only be directly under the second component, but a third component may be disposed between the first component and the second component.

[0055] It will be understood that when an element (e.g., a first element) is referred to as being (directly or indirectly) "coupled" / "coupled to" another element (e.g., a second element) or "connected" / "connected to" another element (e.g., a second element), the first element may be directly or via another element (e.g., a third element) coupled or connected / coupled to or connected to the second element. Conversely, it will be understood that when an element (e.g., a first element) is referred to as being "directly coupled" / "directly coupled to" another element (e.g., a second element) or "directly connected" / "directly connected to" another element (e.g., a second element), no other element (e.g., a third element) is disposed between the element and the other element.

[0056] To describe the present disclosure in detail, embodiments of the present disclosure and required details are described with reference to the accompanying drawings so that those of ordinary skill in the art to which the present disclosure pertains can easily practice the present disclosure. In addition, as long as not specifically mentioned in a sentence, the singular form may include the plural form.

[0057] Figure 1 is a schematic perspective view showing a light-emitting element according to an embodiment of the present disclosure, Figure 2 is Figure 1 a cross-sectional view of the light-emitting element.

[0058] Although Figure 1 and Figure 2 show a cylindrical light-emitting element LD, the type and / or shape of the light-emitting element LD according to the present disclosure are not limited thereto.

[0059] Referring to Figure 1 and Figure 2 , the light-emitting element LD may include a first semiconductor layer 11, a second semiconductor layer 13, and an active layer 12 disposed between the first semiconductor layer 11 and the second semiconductor layer 13. In addition, the light-emitting element LD may include a third semiconductor layer 15 disposed on the second semiconductor layer 13 and a fourth semiconductor layer 18 disposed on the third semiconductor layer 15.

[0060] In an embodiment of the present disclosure, the light-emitting element LD may include a light-emitting stack pattern 10 obtained by sequentially stacking a first semiconductor layer 11, an active layer 12, a second semiconductor layer 13, a third semiconductor layer 15, and a fourth semiconductor layer 18.

[0061] The light-emitting element LD may be formed in a shape extending in one direction. If the extending direction of the light-emitting element LD is defined as the longitudinal direction, the light-emitting element LD may have one end (or lower end) and the remaining end (or upper end) with respect to the extending direction. Any one of the first semiconductor layer 11 and the fourth semiconductor layer 18 may be disposed at one end (or lower end) of the light-emitting element LD, and the other of the first semiconductor layer 11 and the fourth semiconductor layer 18 may be disposed at the remaining end (or upper end) of the light-emitting element LD. For example, the first semiconductor layer 11 may be disposed at one end (or lower end) of the light-emitting element LD, and the fourth semiconductor layer 18 may be disposed at the remaining end (or upper end) of the light-emitting element LD.

[0062] The light-emitting element LD can have various shapes. For example, the light-emitting element LD can have a rod-shaped or strip-shaped form that extends in the longitudinal direction (i.e., has an aspect ratio greater than 1). In an embodiment of the present disclosure, the length L of the light-emitting element LD with respect to the longitudinal direction can be greater than its diameter (D or the width of the cross-section). The light-emitting element LD can include a light-emitting diode (LED) formed to have an ultra-small size (e.g., having a diameter D and / or a length L corresponding to the nanoscale or the microscale).

[0063] The diameter D of the light-emitting element LD can be generally in the range from 0.5 μm to 5 μm, and its length L can be generally in the range from 1 μm to 10 μm. However, the diameter D and the length L of the light-emitting element LD are not limited thereto. The size of the light-emitting element LD can be changed to meet the requirements (or design conditions) of the lighting device or the self-emitting display device to which the light-emitting element LD is applied.

[0064] The first semiconductor layer 11 can include, for example, at least one n-type semiconductor layer. For example, the first semiconductor layer 11 can include an n-type semiconductor layer containing any one of semiconductor materials such as InAlGaN, GaN, AlGaN, InGaN, AlN, and InN and doped with a first conductive dopant (or n-type dopant) such as Si, Ge, or Sn. However, the constituent material of the first semiconductor layer 11 is not limited thereto, and various other materials can be used to form the first semiconductor layer 11. In an embodiment of the present disclosure, the first semiconductor layer 11 can include a gallium nitride (GaN) semiconductor material doped with a first conductive dopant (or n-type dopant). For example, the first semiconductor layer 11 can include an n-type GaN semiconductor layer. With respect to the longitudinal direction L of the light-emitting element LD, the first semiconductor layer 11 can include an upper surface 11b in contact with the active layer 12 and a lower surface 11a exposed to the outside. The lower surface 11a of the first semiconductor layer 11 can correspond to one end (or the lower end) of the light-emitting element LD.

[0065] The active layer 12 can be disposed on the first semiconductor layer 11 and have a single quantum well structure or a multi-quantum well structure. For example, in the case where the active layer 12 has a multi-quantum well structure, the active layer 12 can be formed by periodically repeating the stacking of a barrier layer (not shown), a strain-enhanced layer, and a well layer, which are realized as a unit. The strain-enhanced layer can have a lattice constant smaller than that of the barrier layer, so that the strain (e.g., compressive strain) to be applied to the well layer can be further enhanced. However, the embodiment is not limited to the structure of the active layer 12.

[0066] The active layer 12 can emit light having a wavelength in the range of 400 nm to 900 nm and has a double heterostructure. In an embodiment of the present disclosure, a cladding layer (not shown) doped with a conductive dopant may be formed above or below the active layer 12 with respect to the longitudinal direction L of the light-emitting element LD. For example, the cladding layer may be formed of an AlGaN layer or an InAlGaN layer. In an embodiment, a material such as AlGaN or AlInGaN may be used to form the active layer 12, and in addition, various other materials may be used to form the active layer 12. The active layer 12 may include a first surface 12a in contact with the first semiconductor layer 11 and a second surface 12b in contact with the second semiconductor layer 13. The first surface 12a and the second surface 12b of the active layer 12 may face each other in the longitudinal direction L of the light-emitting element LD.

[0067] When an electric field having a specific voltage or a voltage greater than the specific voltage is applied between opposite ends of the light-emitting element LD, the light-emitting element LD can emit light by the recombination of electron-hole pairs in the active layer 12. Since the light emission of the light-emitting element LD can be controlled based on the foregoing principle, the light-emitting element LD can be used as a light source (light-emitting source) of various light-emitting devices including pixels of a display device.

[0068] The second semiconductor layer 13 may be disposed on the second surface 12b of the active layer 12 and includes a semiconductor layer of a type different from that of the first semiconductor layer 11. For example, the second semiconductor layer 13 may include at least one p-type semiconductor layer. For example, the second semiconductor layer 13 may include a p-type semiconductor layer containing any one of semiconductor materials such as InAlGaN, GaN, AlGaN, InGaN, AlN, and InN and doped with a second conductive dopant (or p-type dopant) such as Mg. However, the material of the second semiconductor layer 13 is not limited thereto, and various other materials may be used to form the second semiconductor layer 13. In an embodiment of the present disclosure, the second semiconductor layer 13 may include a gallium nitride (GaN) semiconductor material doped with a second conductive dopant (or p-type dopant). For example, the second semiconductor layer 13 may be formed of a p-type GaN semiconductor. With respect to the longitudinal direction L of the light-emitting element LD, the second semiconductor layer 13 may include a lower surface 13a in contact with the second surface 12b of the active layer 12 and an upper surface 13b in contact with the lower surface 15a of the third semiconductor layer 15.

[0069] In an embodiment of the present disclosure, the first semiconductor layer 11 and the second semiconductor layer 13 may have different thicknesses with respect to the longitudinal direction L of the light-emitting element LD. For example, with respect to the longitudinal direction L of the light-emitting element LD, the first semiconductor layer 11 may have a thickness greater than the thickness of the second semiconductor layer 13. Thus, as Figure 1 and Figure 2As shown, the active layer 12 of the light-emitting element LD may be disposed at a position closer to the upper surface 13b of the second semiconductor layer 13 than the lower surface 11a of the first semiconductor layer 11.

[0070] Although Figure 1 and Figure 2 it is shown that both the first semiconductor layer 11 and the second semiconductor layer 13 are implemented as single layers, the present disclosure is not limited thereto. In embodiments of the present disclosure, depending on the material of the active layer 12, both the first semiconductor layer 11 and the second semiconductor layer 13 may further include at least one layer, for example, a cladding layer and / or a tensile-strain-barrier reduction (TSBR) layer. The TSBR layer may be a strain-relief layer whose lattice structure is disposed between other semiconductor layers such that the strain-relief layer may be used as a buffer layer to reduce the difference in lattice constants. Although the TSBR layer may be implemented as a p-type semiconductor layer (such as p-GaInP, p-AlInP, or p-AlGaInP), the present disclosure is not limited thereto.

[0071] The third semiconductor layer 15 may be disposed and / or formed on the second semiconductor layer 13. The third semiconductor layer 15 may include a 3-1 semiconductor layer (or a 3-1 junction semiconductor layer) 16 and a 3-2 semiconductor layer (or a 3-2 junction semiconductor layer) 17. The third semiconductor layer 15 may have a thickness in the range of 2 nm to 100 nm in the longitudinal direction L of the light-emitting element LD, but the present disclosure is not limited thereto. Each of the 3-1 semiconductor layer 16 and the 3-2 semiconductor layer 17 may have a thickness in the range of 25 nm to 35 nm, but the present disclosure is not limited thereto. The 3-1 semiconductor layer 16 and the 3-2 semiconductor layer 17 may have the same thickness, but the present disclosure is not limited thereto. In an embodiment, the 3-1 semiconductor layer 16 and the 3-2 semiconductor layer 17 may have different thicknesses.

[0072] The 3-1 semiconductor layer 16 may be directly disposed on the upper surface 13b of the second semiconductor layer 13 in the longitudinal direction L of the light-emitting element LD and include a semiconductor layer of the same type as the second semiconductor layer 13. For example, the 3-1 semiconductor layer 16 may include at least one p-type semiconductor layer. For example, the 3-1 semiconductor layer 16 may include a p-type semiconductor layer doped with a second conductive dopant (or a p-type dopant) such as Mg or Zn, for example, including at least one semiconductor material (or substance) of GaN, InGaN, AlInGaN, and AlGaInP. In the case where the light-emitting element LD is configured to emit blue and / or green-based light, the 3-1 semiconductor layer 16 may include a semiconductor material (or substance) of AlInGaN. In the case where the light-emitting element LD is configured to emit red-based light, the 3-1 semiconductor layer 16 may include a semiconductor material (or substance) of AlGaInP.

[0073] The 3-1 semiconductor layer 16 may include a semiconductor material (or substance) doped with a second conductive dopant (or p-type dopant) having a concentration higher than that of the second conductive dopant (or p-type dopant) in the second semiconductor layer 13. In an embodiment, a portion of the 3-1 semiconductor layer 16 disposed on the second semiconductor layer 13 may have a graded dopant concentration within a range from the dopant concentration in the second semiconductor layer 13 to the desired dopant concentration in the 3-1 semiconductor layer 16, but the present disclosure is not limited thereto. With respect to the longitudinal direction L of the light-emitting element LD, the 3-1 semiconductor layer 16 may include a lower surface 16a in contact with the second semiconductor layer 13 and an upper surface 16b in contact with the 3-2 semiconductor layer 17. Here, the lower surface 16a of the 3-1 semiconductor layer 16 may be the lower surface 15a of the third semiconductor layer 15.

[0074] The 3-2 semiconductor layer 17 may be directly disposed on the upper surface 16b of the 3-1 semiconductor layer 16 with respect to the longitudinal direction L of the light-emitting element LD, include a semiconductor layer of a type different from that of the 3-1 semiconductor layer 16, and include a semiconductor layer of the same type as that of the first semiconductor layer 11. For example, the 3-2 semiconductor layer 17 may include at least one n-type semiconductor layer. For example, the 3-2 semiconductor layer 17 may include an n-type semiconductor layer doped with a first conductive dopant (or n-type dopant) such as Si, Ge, and for example, include at least one semiconductor material (or substance) selected from InGaN, GaN, AlGaInP, and AlInGaN. When the light-emitting element LD is configured to emit blue and / or green-based light, the 3-2 semiconductor layer 17 may include a semiconductor material (or substance) of AlInGaN. When the light-emitting element LD is configured to emit red-based light, the 3-2 semiconductor layer 17 may include a semiconductor material (or substance) of AlGaInP.

[0075] The 3-2 semiconductor layer 17 may include a semiconductor material (or substance) doped with a first conductive dopant (or n-type dopant) having a concentration higher than that of the first conductive dopant (or n-type dopant) in the first semiconductor layer 11. In an embodiment, the 3-2 semiconductor layer 17 may have a graded dopant concentration within a range from a maximum value close to the dopant concentration in the 3-1 semiconductor layer 16 to a minimum value close to the dopant concentration in the fourth semiconductor layer 18, but the present disclosure is not limited thereto. With respect to the longitudinal direction L of the light-emitting element LD, the 3-2 semiconductor layer 17 may include a lower surface 17a in contact with the 3-1 semiconductor layer 16 and an upper surface 17b in contact with the fourth semiconductor layer 18. Here, the upper surface 17b of the 3-2 semiconductor layer 17 may be the upper surface 15b of the third semiconductor layer 15.

[0076] In an embodiment of the present disclosure, the third semiconductor layer 15 formed by stacking different types of semiconductor layers may be a tunnel junction layer. The third semiconductor layer 15 (or tunnel junction layer) including the 3-1 semiconductor layer 16 and the 3-2 semiconductor layer 17 may be formed thin enough and doped enough such that a series of low voltage drops may occur when current is conducted in a reverse bias mode. The voltage drop applied to the third semiconductor layer 15 (or tunnel junction layer) may be generally in the range from 0.1 V to 1 V, but the present disclosure is not limited thereto.

[0077] In an embodiment, an intermediate layer (not shown) including InGaN, AlN, etc. may be disposed between the 3-1 semiconductor layer 16 and the 3-2 semiconductor layer 17. The intermediate layer may use the polarization field in group III nitrides to assist in the realignment of energy bands for tunneling. The aforementioned polarization effect may reduce the doping requirements in the 3-1 semiconductor layer 16 and the 3-2 semiconductor layer 17, and reduce the required tunneling distance. The composition of the intermediate layer may be different from that of each of the 3-1 semiconductor layer 16 and the 3-2 semiconductor layer 17, and is selected for the realignment of energy bands due to the polarization charges between other materials present in the group III nitride material system.

[0078] The fourth semiconductor layer 18 may be disposed on the third semiconductor layer 15 (or tunnel junction layer) in the longitudinal direction L of the light emitting element LD and in direct contact with the 3-2 semiconductor layer 17. The fourth semiconductor layer 18 may include a semiconductor layer of the same type as the 3-2 semiconductor layer 17. For example, the fourth semiconductor layer 18 may include at least one n-type semiconductor layer. For example, the fourth semiconductor layer 18 may include an n-type semiconductor layer doped with a first conductive dopant (or n-type dopant) such as Si, Ge, for example, including at least one semiconductor material (or substance) of InGaN, GaN, AlGaInP, and AlInGaN. The fourth semiconductor layer 18 may be used as an ohmic contact layer, but the present disclosure is not limited thereto.

[0079] The fourth semiconductor layer 18 may include a semiconductor material (or substance) doped with a first conductive dopant (or n-type dopant) having a concentration lower than that of the first conductive dopant (or n-type dopant) of the 3-2 semiconductor layer 17. Relative to the longitudinal direction L of the light emitting element LD, the fourth semiconductor layer 18 may include a lower surface 18a in contact with the upper surface 17b of the 3-2 semiconductor layer 17 and an upper surface 18b exposed to the outside.

[0080] In an embodiment of the present disclosure, the light-emitting stack pattern 10 may be provided and / or formed in a shape corresponding to the shape of the light-emitting element LD. For example, in the case where the light-emitting element LD is provided and / or formed in a cylindrical shape, the light-emitting stack pattern 10 may also be provided and / or formed in a cylindrical shape. In the case where the light-emitting stack pattern 10 has a cylindrical shape, the first semiconductor layer 11, the active layer 12, the second semiconductor layer 13, the third semiconductor layer 15 (or tunneling junction layer), and the fourth semiconductor layer 18 may all have a cylindrical shape.

[0081] The first semiconductor layer 11 may be provided at one end (or the lower end) of the light-emitting element LD with respect to the longitudinal direction L of the light-emitting element LD, and the fourth semiconductor layer 18 may be provided at the remaining end (or the upper end) of the light-emitting element LD. The light-emitting element LD may include a lower surface 11a of the first semiconductor layer 11 and an upper surface 18b of the fourth semiconductor layer 18 that are provided at opposite ends of the light-emitting element LD and are exposed to the outside. The lower surface 11a of the first semiconductor layer 11 and the upper surface 18b of the fourth semiconductor layer 18 may both be surfaces (e.g., outer surfaces) exposed to the outside such that the surface can contact an external conductive material and be electrically connected to the external conductive material. In an embodiment of the present disclosure, the lower surface 11a (or outer surface) of the first semiconductor layer 11 may be the lower surface LD_1 of the light-emitting element LD. The upper surface 18b (or outer surface) of the fourth semiconductor layer 18 may be the upper surface LD_2 of the light-emitting element LD.

[0082] In the case where the light-emitting element LD has a cylindrical shape, the lower surface 11a (outer surface) of the first semiconductor layer 11 and the upper surface 18b (or outer surface) of the fourth semiconductor layer 18 may both have a circular shape. In an embodiment, in the case where the light-emitting element LD has an elliptical cylindrical shape, the lower surface 11a (outer surface) of the first semiconductor layer 11 and the upper surface 18b (or outer surface) of the fourth semiconductor layer 18 may both have an elliptical shape. In an embodiment, in the case where the light-emitting element LD has a polygonal prism shape, the lower surface 11a (outer surface) of the first semiconductor layer 11 and the upper surface 18b (or outer surface) of the fourth semiconductor layer 18 may both have a polygonal shape.

[0083] In the case where the light-emitting stack pattern 10 is provided and / or formed in a shape corresponding to the shape of the light-emitting element LD, the light-emitting stack pattern 10 may have a length that is substantially similar or equal to the length L of the light-emitting element LD. In the following embodiments, the description will be made on the assumption that the length of the light-emitting stack pattern 10 is the same as the length L of the light-emitting element LD.

[0084] In an embodiment of the present disclosure, the light-emitting element LD may further include an insulating film 14 surrounding the outer peripheral surface of the light-emitting stack pattern 10. In an embodiment, the insulating film 14 may be omitted, or the insulating film 14 may be provided to cover only a part of the light-emitting stack pattern 10.

[0085] The insulating film 14 may include a transparent insulating material. For example, the insulating film 14 may include at least one insulating material selected from the group consisting of silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (AlO x ), titanium dioxide (TiO2), etc., but the present disclosure is not limited thereto. Various materials having insulating properties may be used.

[0086] The insulating film 14 may prevent a short circuit formed in the active layer 12 due to contact with a conductive material other than the first semiconductor layer 11 and the second semiconductor layer 13. In addition, due to the insulating film 14, the occurrence of defects on the surface of the light-emitting element LD can be minimized, thereby improving the lifetime and efficiency of the light-emitting element LD. In the case where a plurality of light-emitting elements LD are arranged in close contact with each other, the insulating film 14 may prevent an undesired short circuit from occurring between the light-emitting elements LD. Whether the insulating film 14 is provided or not is not limited as long as a short circuit between the active layer 12 and an external conductive material can be prevented.

[0087] The insulating film 14 may be formed and / or provided on the outer peripheral surface (or surface) of the light-emitting stack pattern 10 to surround at least the outer peripheral surface of the active layer 12, and may also surround the outer peripheral surface of each of the first semiconductor layer 11, the second semiconductor layer 13, the third semiconductor layer 15, and the fourth semiconductor layer 18. For ease of description, Figure 1 a part of the insulating film 14 has been removed is shown. The first semiconductor layer 11, the active layer 12, the second semiconductor layer 13, the third semiconductor layer 15 (or tunnel junction layer), and the fourth semiconductor layer 18 included in the light-emitting element LD may be surrounded by the insulating film 14.

[0088] In an embodiment of the present disclosure, the insulating film 14 may completely surround the outer peripheral surfaces of opposite ends of the light-emitting element LD including semiconductor layers of the same type, but the present disclosure is not limited thereto. In another embodiment, the insulating film 14 may surround only a part of the outer peripheral surface of the first semiconductor layer 11 and / or only a part of the outer peripheral surface of the fourth semiconductor layer 18.

[0089] The insulating film 14 may include a lower surface 14a parallel to the lower surface 11a (or outer surface) of the first semiconductor layer 11 in a direction crossing the longitudinal direction L of the light-emitting element LD, an upper surface 14b opposite to the lower surface 14a with respect to the longitudinal direction L, and a side surface 14c surrounding the outer peripheral surface of the light-emitting stack pattern 10. The lower surface 14a of the insulating film 14, the upper surface 14b of the insulating film 14, and the side surface 14c of the insulating film 14 may be connected to each other and continuous with each other. Here, the upper surface 14b of the insulating film 14 may be defined as an imaginary surface including the periphery of the upper end of the insulating film 14. The lower surface 14a of the insulating film 14 may be defined as an imaginary surface including the periphery of the lower end of the insulating film 14.

[0090] The lower surface 14a of the insulating film 14 may be disposed on the same surface (or the same line) as the lower surface 11a (or outer surface) of the first semiconductor layer 11. The upper surface 14b of the insulating film 14 may be disposed on the same surface (or the same line) as the upper surface 18b (or outer surface) of the fourth semiconductor layer 18. In some embodiments, the lower surface 14a of the insulating film 14 and the lower surface 11a (or outer surface) of the first semiconductor layer 11 may not always be disposed on the same surface (or the same line), and may be disposed on different surfaces (or different lines). Similarly, in some embodiments, the upper surface 14b of the insulating film 14 and the upper surface 18b (or outer surface) of the fourth semiconductor layer 18 may not always be disposed on the same surface (or the same line), and may be disposed on different surfaces (or different lines).

[0091] The first semiconductor layer 11, the active layer 12, the second semiconductor layer 13, the third semiconductor layer 15 (or tunneling junction layer), and the fourth semiconductor layer 18 sequentially stacked in the longitudinal direction L of the light-emitting element LD may have different thicknesses, but the present disclosure is not limited thereto.

[0092] In an embodiment of the present disclosure, based on the surface 15c (hereinafter referred to as the "contact surface") on which the upper surface 16b of the 3-1 semiconductor layer 16 and the lower surface 17a of the 3-2 semiconductor layer 17 are in contact with each other, different types of semiconductor layers may have different thicknesses. Specifically, with respect to the longitudinal direction L of the light-emitting element LD, a thickness d1 (hereinafter referred to as the "first thickness"), which is the sum of the thicknesses of the second semiconductor layer 13 and the 3-1 semiconductor layer 16 disposed below the contact surface 15c, may be different from a thickness d2 (hereinafter referred to as the "second thickness"), which is the sum of the thicknesses of the 3-2 semiconductor layer 17 and the fourth semiconductor layer 18 disposed above the contact surface 15c. For example, the second thickness d2 may be greater than the first thickness d1.

[0093] In an embodiment of the present disclosure, with respect to the longitudinal direction L of the light-emitting element LD, the thickness of the fourth semiconductor layer 18 provided at the upper end of the light-emitting element LD can be adjusted such that the second thickness d2 is greater than the first thickness d1. With respect to the longitudinal direction L of the light-emitting element LD, the fourth semiconductor layer 18 can have a thickness greater than the thickness of each of the second semiconductor layer 13 and the third semiconductor layer 15 and less than the thickness of the first semiconductor layer 11. However, the present disclosure is not limited thereto. In an embodiment, the fourth semiconductor layer 18 can have the same thickness as the first semiconductor layer 11.

[0094] With respect to the longitudinal direction L of the light-emitting element LD, the distance from the contact surface 15c to the upper surface LD_2 of the light-emitting element LD and / or the upper surface of the light-emitting stack pattern 10 can be different from the distance from the contact surface 15c to the lower surface LD_1 of the light-emitting element LD and / or the lower surface of the light-emitting stack pattern 10. For example, with respect to the longitudinal direction L of the light-emitting element LD, the distance from the contact surface 15c to the upper surface LD_2 of the light-emitting element LD and / or the upper surface of the light-emitting stack pattern 10 can be less than the distance from the contact surface 15c to the lower surface LD_1 of the light-emitting element LD and / or the lower surface of the light-emitting stack pattern 10. In other words, with respect to the longitudinal direction L of the light-emitting element LD, the distance from the contact surface 15c to the upper surface 18b (or outer surface) of the fourth semiconductor layer 18 can be less than the distance from the contact surface 15c to the lower surface 11a (or outer surface) of the first semiconductor layer 11. In an embodiment of the present disclosure, the contact surface 15c can be provided above a point corresponding to half of the entire length L of the light-emitting element LD and / or the light-emitting stack pattern 10 with respect to the longitudinal direction L of the light-emitting element LD. For example, based on the point corresponding to half of the entire length L of the light-emitting element LD with respect to the longitudinal direction L of the light-emitting element LD, the contact surface 15c can be provided closer to the upper surface 18b (or outer surface) of the fourth semiconductor layer 18 than the lower surface 11a (or outer surface) of the first semiconductor layer 11.

[0095] As described above, when the thickness d2 of the n-type semiconductor layer (e.g., the 3-2 semiconductor layer 17 and the fourth semiconductor layer 18) provided above the contact surface 15c with respect to the longitudinal direction L of the light-emitting element LD is greater than the thickness d1 of the p-type semiconductor layer (e.g., the 3-1 semiconductor layer 16 and the second semiconductor layer 13) provided below the contact surface 15c, and the contact surface 15c is provided adjacent to the upper surface 18b (or outer surface) of the fourth semiconductor layer 18 based on the point corresponding to half of the entire length L of the light-emitting element LD, the active layer 12 can be provided in the middle (or center) portion of the light-emitting element LD or provided adjacent to the middle (or center) portion of the light-emitting element LD.

[0096] The fourth semiconductor layer 18 can be provided and / or formed on the third semiconductor layer 15 (or tunnel junction layer) by a typical growth method. Here, by adjusting the growth conditions, a fourth semiconductor layer 18 having a specific level or greater thickness can be formed on the third semiconductor layer 15 (or tunnel junction layer). When the fourth semiconductor layer 18 has a specific level or greater thickness, the length L of the light-emitting element LD can increase with the thickness of the fourth semiconductor layer 18. Thus, the active layer 12 can be disposed substantially in the middle (or center) portion of the light-emitting element LD with respect to the longitudinal direction L of the light-emitting element LD, or disposed adjacent to the middle (or center) portion of the light-emitting element LD.

[0097] As described above, when the active layer 12 can be disposed substantially in the middle (or center) portion of the light-emitting element LD with respect to the longitudinal direction L of the light-emitting element LD or disposed adjacent to the middle (or center) portion of the light-emitting element LD, the light emitted from the active layer 12 can travel uniformly (or evenly) toward the opposite ends of the light-emitting element LD instead of being biased to one side. Thus, the intensity of the light emitted from the opposite ends of the light-emitting element LD can be uniform. Therefore, the optical efficiency of the light-emitting element LD can be enhanced.

[0098] When the active layer 12 is disposed at a position biased to one of the opposite ends of the light-emitting element LD instead of being disposed in the middle (or center) portion of the light-emitting element LD, the light emitted from the active layer 12 is focused on one end. In this case, the light emitted from the light-emitting element LD is biased to one side, and the light is output from the light-emitting element LD asymmetrically. In an embodiment of the present disclosure, the thickness d2 of the n-type semiconductor layer disposed above the contact surface 15c can be greater than the thickness d1 of the p-type semiconductor layer disposed below the contact surface 15c with respect to the longitudinal direction L of the light-emitting element LD, so that the active layer 12 can be disposed in the middle (or center) portion of the light-emitting element LD or disposed adjacent to the middle (or center) portion, whereby the light emitted from the active layer 12 can travel uniformly to the opposite ends of the light-emitting element LD. Therefore, according to the embodiment of the present disclosure, the light output efficiency of the light-emitting element LD can be enhanced.

[0099] In addition, in embodiments of the present disclosure, with respect to the longitudinal direction L of the light-emitting element LD, the first semiconductor layer 11 including an n-type semiconductor layer may be disposed at one end of the light-emitting element LD, and the fourth semiconductor layer 18 including an n-type semiconductor layer may be disposed at the remaining end of the light-emitting element LD. The n-type semiconductor layer may be disposed at opposite ends of the light-emitting element LD with respect to the longitudinal direction L of the light-emitting element LD, such that the electrical properties of the light-emitting element LD can be enhanced. Generally, the n-type semiconductor layer has material properties of high light transmittance and excellent electrical properties due to high electron mobility (or low resistance). Therefore, when the n-type semiconductor layer (e.g., the first semiconductor layer 11 and the fourth semiconductor layer 18) is disposed at opposite ends of the light-emitting element LD and a signal (or voltage) is applied to opposite ends of the light-emitting element LD, electron-hole pairs can be more quickly combined in the active layer 12 of the light-emitting element LD, such that the loss of light emitted from the active layer 12 can be minimized. Accordingly, the light output efficiency of the light-emitting element LD can be further enhanced.

[0100] The light-emitting element LD can be used as a light source for various display devices. The light-emitting element LD can be formed by a surface treatment process. For example, each light-emitting element LD can be surface-treated such that when a plurality of light-emitting elements LD are mixed with a fluid solution (or solvent) and then supplied to each emission region (e.g., the emission region of each pixel or the emission region of each sub-pixel), the light-emitting elements LD can be uniformly distributed instead of unevenly aggregating in the solution.

[0101] The light-emitting device including the above-described light-emitting element LD can be used not only in a display device but also in various devices having a light source. For example, in the case where a plurality of light-emitting elements LD are disposed in the pixel region of each pixel of a display panel, the light-emitting element LD can be used as a light source for the pixel. However, the application field of the light-emitting element LD is not limited to the above examples. For example, the light-emitting element LD can also be used in other types of devices having a light source (such as a lighting device).

[0102] Figures 3a to 3k sequentially shows the manufacturing Figure 1 and Figure 2 of the light-emitting element.

[0103] Referring to Figures 1 to 3a , a substrate 1 configured to support the light-emitting element LD is prepared.

[0104] The substrate 1 may be a GaAs, GaP, or InP substrate. The substrate 1 may be a wafer for epitaxial growth. The substrate 1 may include a ZnO substrate having a GaAs layer on its surface. In addition, a Ge substrate having a GaAs layer on its surface and a Si substrate having a GaAs layer on a Si wafer with a buffer layer disposed between the GaAs layer and the Si wafer may also be used.

[0105] A single crystal substrate formed by a known manufacturing method and being an article on the market can be used as Substrate 1. The material of Substrate 1 is not limited thereto as long as it satisfies the selectivity for manufacturing the light-emitting element LD and epitaxial growth can be smoothly performed.

[0106] The surface of Substrate 1 on which epitaxial growth is to be performed is desirably flat. The size and diameter of Substrate 1 can be changed according to the product to which Substrate 1 is to be applied, and it can be formed into a shape capable of reducing the bending phenomenon of the stacked structure caused by epitaxial growth. The shape of Substrate 1 is not limited to a circular shape, and it can have a polygonal shape such as a rectangular shape.

[0107] Subsequently, a sacrificial layer 3 is formed on Substrate 1. During the process of manufacturing the light-emitting element LD on Substrate 1, the sacrificial layer 3 can be provided between the light-emitting element LD and Substrate 1 so that the light-emitting element LD can be physically spaced apart from Substrate 1.

[0108] The sacrificial layer 3 can have various types of structures and can have a single-layer structure or a multi-layer structure. The sacrificial layer 3 can be a layer that will be removed in the final step of the process of manufacturing the light-emitting element LD. When the sacrificial layer 3 is removed, the layers provided above and below the sacrificial layer 3 can be separated from each other.

[0109] The sacrificial layer 3 can be formed of GaAs, AlAs, or AlGaAs.

[0110] A first semiconductor layer 11 is formed on the sacrificial layer 3. The first semiconductor layer 11 can be formed by epitaxial growth and can be formed by a method such as metalorganic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), vapor phase epitaxy (VPE), liquid phase epitaxy (LPE), etc. In an embodiment, an additional semiconductor layer (such as a buffer layer or an undoped semiconductor layer) for enhancing crystallinity can be further formed between the first semiconductor layer 11 and the sacrificial layer 3.

[0111] The first semiconductor layer 11 can include a semiconductor layer formed of a III (Ga, Al, In)-V (P, As) group and doped with a first conductive dopant (or n-type dopant) such as Si, Ge, and Sn. For example, the first semiconductor layer 11 can include at least one semiconductor material selected from GaP, GaAs, GaInP, and AlGaInP doped with Si. In other words, the first semiconductor layer 11 can include at least one n-type semiconductor layer.

[0112] Refer to Figures 1 to 3b, an active layer 12 can be formed on the first semiconductor layer 11. The active layer 12 can be a region where electrons and holes recombine with each other, and the recombination of electrons and holes can cause the energy level to transition to a lower energy level. Therefore, light with a wavelength corresponding to the energy level transition can be emitted. The active layer 12 can be formed on the first semiconductor layer 11, and the active layer 12 can have a single quantum well structure or a multiple quantum well structure. The position of the active layer 12 can be changed in various ways according to the type of the light-emitting element LD. In an embodiment of the present disclosure, the active layer 12 can be disposed in the middle (or center) portion of the light-emitting element LD with respect to the longitudinal direction L of the light-emitting element LD.

[0113] The active layer 12 can include at least one material among GaInP, AlGaInP, GaAs, AlGaAs, InGaAs, InGaAsP, InP, and InAs. The active layer 12 can emit light having a wavelength in the range of 400 nm to 900 nm. The active layer 12 can have a double heterostructure. In an embodiment, a cladding layer (not shown) doped with a conductive dopant can be further formed on the second surface 12b and / or the first surface 12a of the active layer 12. In an embodiment, a tensile strain barrier reduction (TSBR) layer can be further formed on the second surface 12b of the active layer 12. For example, the TSBR layer can be disposed between the second surface 12b of the active layer 12 and the lower surface 13a of the second semiconductor layer 13. In addition, in an embodiment, the TSBR layer can be disposed on the upper surface 17b of the 3-2 semiconductor layer 17 of the third semiconductor layer 15.

[0114] Referring to Figures 1 to 3c , a second semiconductor layer 13 is formed on the active layer 12. The second semiconductor layer 13 can include a semiconductor layer of a type different from that of the first semiconductor layer 11. The second semiconductor layer 13 can include a semiconductor layer formed of a III (Ga, Al, In)-V (P, As) group and doped with a second conductive dopant (or p-type dopant) such as Mg. For example, the second semiconductor layer 13 can include at least one semiconductor material among GaP, GaAs, GaInP, and AlGaInP doped with Mg. In other words, the second semiconductor layer 13 can include a p-type semiconductor layer.

[0115] Referring to Figures 1 to 3d , a 3-1 semiconductor layer 16 made of a semiconductor layer of the same type as that of the second semiconductor layer 13 can be formed on the second semiconductor layer 13. Thereafter, a 3-2 semiconductor layer 17 made of a semiconductor layer of a type different from that of the 3-1 semiconductor layer 16 is formed on the 3-1 semiconductor layer 16. The 3-1 semiconductor layer 16 and the 3-2 semiconductor layer 17 made of different types of semiconductor layers can form a third semiconductor layer 15 as a tunnel junction layer.

[0116] In an embodiment of the present disclosure, the 3-1 semiconductor layer 16 may be a p-type semiconductor layer and include a semiconductor material doped with a second conductive dopant (or p-type dopant) having a concentration higher than that of the second conductive dopant (or p-type dopant) of the second semiconductor layer 13. The 3-2 semiconductor layer 17 may be an n-type semiconductor layer and include a semiconductor material doped with a first conductive dopant (or n-type dopant) having a concentration higher than that of the first conductive dopant (or n-type dopant) of the first semiconductor layer 11.

[0117] Referring to Figures 1 to 3e , a fourth semiconductor layer 18 made of a semiconductor layer of the same type as the 3-2 semiconductor layer 17 is formed on the 3-2 semiconductor layer 17. The fourth semiconductor layer 18 may be an n-type semiconductor layer and include a semiconductor material doped with a first conductive dopant (or n-type dopant) having a concentration lower than that of the first conductive dopant (or n-type dopant) of the 3-2 semiconductor layer 17.

[0118] The fourth semiconductor layer 18 may be formed by epitaxial growth and may be formed by a method such as metal-organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), vapor phase epitaxy (VPE), liquid phase epitaxy (LPE), etc. When the fourth semiconductor layer 18 is formed on the 3-2 semiconductor layer 17, the fourth semiconductor layer 18 having a specific level or greater thickness may be formed on the 3-2 semiconductor layer 17 by adjusting growth conditions and the like.

[0119] The first semiconductor layer 11, the active layer 12, the second semiconductor layer 13, the third semiconductor layer 15 (or tunnel junction layer), and the fourth semiconductor layer 18 sequentially stacked on the substrate 1 may form a light-emitting stack 10'.

[0120] Referring to Figures 1 to 3f , a mask layer 20 is formed on the fourth semiconductor layer 18. The mask layer 20 may include an insulating layer (not shown) and a metal layer (not shown). The insulating layer may be formed on the fourth semiconductor layer 18. The insulating layer may be used as a mask for sequentially etching the light-emitting stack 10'. The insulating layer may be formed of an oxide or a nitride, for example, including silicon oxide (SiO x ), silicon nitride (SiN x ), etc. Although the insulating layer has a thickness in the range of 0.5 μm to 1.5 μm, the present disclosure is not limited thereto. The metal layer may include a metal such as chromium (Cr), but is not limited thereto. The metal layer may have a thickness in the range of 30 nm to 150 nm.

[0121] At least one fine pattern FP may be formed on the mask layer 20. The fine pattern FP may be formed using a polymer layer. The fine pattern FP may be formed by forming a polymer layer on the mask layer 20 and forming a pattern in the polymer layer at a nanoscale or microscale interval. Specifically, the fine pattern FP may be formed at a nanoscale or microscale interval by patterning the polymer layer on the mask layer 20 by a method such as photolithography, electron beam lithography, or nanoimprint lithography (NIL).

[0122] Referring Figures 1 to 3g , the mask pattern 20' is formed by patterning the mask layer 20 by using the fine pattern FP as a mask. The mask pattern 20' may be formed in a shape corresponding to the fine pattern FP. The mask pattern 20' may be used as an etching mask for forming the light-emitting stack pattern 10 by etching the light-emitting stack 10'. The fine pattern FP may be removed by a typical wet etching method, a dry etching method, or the like, but the present disclosure is not limited thereto, and the fine pattern FP may be removed by a typical removing method.

[0123] Referring Figures 1 to 3h , by performing an etching process via using the mask pattern 20' as an etching mask, a plurality of light-emitting stack patterns 10 are formed by patterning the light-emitting stack 10' at a nanoscale or microscale interval.

[0124] During the foregoing etching process, a region of the light-emitting stack 10' that does not correspond to the mask pattern 20' may be etched such that a groove HM exposing the region A of the first semiconductor layer 11 may be formed. A region of the light-emitting stack 10' corresponding to the mask pattern 20' is not etched.

[0125] The groove HM may have a shape that recesses from the upper surface 18b of the fourth semiconductor layer 18 of each light-emitting stack pattern 10 to the region A of the first semiconductor layer 11 in one direction (e.g., in the vertical direction).

[0126] A dry etching method such as a reactive ion etching (RIE) method, a reactive ion beam etching (RIBE) method, or an inductively coupled plasma reactive ion etching (ICP-RIE) method may be used as the etching method for forming the plurality of light-emitting stack patterns 10. Different from the wet etching method, the dry etching method may perform an anisotropic etching process and thus is suitable for forming the light-emitting stack pattern 10. In other words, the wet etching method may be performed with an isotropic etching scheme such that the target may be etched in all directions. In contrast, the dry etching method performs the etching process in such a way that the target is mainly etched in the depth direction to form the groove HM, whereby the groove HM may be formed in a desired pattern in terms of size, interval, etc.

[0127] In an embodiment of the present disclosure, each of the light-emitting stack patterns 10 may have a nanoscale or microscale size.

[0128] After performing the foregoing etching process, residues remaining on the light-emitting stack pattern 10, particularly residues of the mask pattern 20', can be removed by a typical wet etching method or dry etching method, but are not limited thereto. The residues can be removed by a typical removal method. Here, the mask pattern 20' (or residues) may include an etching mask, an insulating material, etc. required for performing the mask process.

[0129] Referring to Figures 1 to 3i , an insulating material layer 14' is formed on the light-emitting stack pattern 10 and the region A of the first semiconductor layer 11. The insulating material layer 14' may include an upper insulating material layer, a side insulating material layer, and a lower insulating material layer. The upper insulating material layer may completely cover each upper surface of the light-emitting stack pattern 10. Here, the upper surface of each of the light-emitting stack patterns 10 may correspond to the upper surface 18b (or outer surface) of the fourth semiconductor layer 18. In other words, the upper insulating material layer may completely cover the upper surface 18b of each fourth semiconductor layer 18 of the light-emitting stack pattern 10. The side insulating material layer may completely cover each side surface of the light-emitting stack pattern 10. The lower insulating material layer may completely cover the region A of the first semiconductor layer 11 exposed to the outside through the groove HM.

[0130] The upper insulating material layer, the side insulating material layer, and the lower insulating material layer may be connected to each other on the substrate 1 and may extend continuously with each other.

[0131] A method of applying an insulating material to the light-emitting stack pattern 10 attached to the substrate 1 may be used as a method of forming the insulating material layer 14', but the present disclosure is not limited thereto. The material used as the insulating material layer 14' may include any one or more selected from the group consisting of silicon oxide (SiO x ), silicon nitride (SiN x ), aluminum oxide (AlO x ), titanium dioxide (TiO2), etc., but the present disclosure is not limited thereto. For example, when the insulating material layer 14' includes aluminum oxide (AlO x ), the insulating material layer 14' can be formed by an atomic layer deposition (ALD) scheme, and a thin film can be formed through a chemical absorption and desorption process by supplying trimethylaluminum (TMA) and an H2O source in a pulsed form. The insulating material layer 14' may have a thickness in the range of 30 nm to 150 nm, but the present disclosure is not limited thereto.

[0132] Referring to Figures 1 to 3j , an insulating film 14 is formed by removing a part of the insulating material layer 14' formed on the substrate 1 through an etching process.

[0133] The upper and lower insulating material layers are removed by an etching process for forming the insulating film 14. Eventually, the insulating film 14 including only the side insulating material layer covering the side surfaces of each light-emitting stack pattern 10 can be formed. During the aforementioned etching process, the upper insulating material layer is removed such that the upper surface 18b of the fourth semiconductor layer 18 can be exposed. Here, the upper surface 14b of the insulating film 14 can be disposed and / or formed on the same surface (or the same line) as the surface (or line) of the upper surface 18b (or the outer surface) of the fourth semiconductor layer 18. In addition, the lower insulating material layer is removed by the aforementioned etching process such that the region A of the first semiconductor layer 11 can be exposed to the outside.

[0134] Multiple light-emitting elements LD including the light-emitting stack pattern 10 and the insulating film 14 surrounding the corresponding outer peripheral surfaces (or the corresponding surfaces) of the light-emitting stack pattern 10 can be finally formed by the aforementioned etching process. Here, the upper surface 18b (or the outer surface) of the fourth semiconductor layer 18 exposed to the outside can become the upper surface LD_2 of each of the light-emitting elements LD.

[0135] Refer to Figures 1 to 3k , the light-emitting element LD is separated from the substrate 1 by a physical peeling method including forming a space (not shown) between the light-emitting element LD and the substrate 1 and applying a small physical force or impact thereto. Here, the lower surface 11a of the first semiconductor layer 11 of each of the light-emitting elements LD can be exposed to the outside.

[0136] The method of separating the light-emitting element LD from the substrate 1 is not limited to the foregoing embodiments. In an embodiment, the light-emitting element LD can be separated from the substrate 1 by a laser lift-off (LLO) method using a laser, a chemical lift-off (CLO) method using an etchant solution, or the like.

[0137] In each of the light-emitting elements LD finally manufactured by the foregoing manufacturing process, the n-type semiconductor layers (the third-second semiconductor layer 17 and the fourth semiconductor layer 18) disposed above the contact surface 15c can have a thickness d2 greater than the thickness of the p-type semiconductor layers (the second semiconductor layer 13 and the third-first semiconductor layer 16) disposed below the contact surface 15c with respect to the longitudinal direction L of each light-emitting element LD.

[0138] In addition, each of the light-emitting elements LD finally formed by the foregoing manufacturing process can include an active layer 12 disposed in the middle (or center) portion of the light-emitting element LD or disposed adjacent to the middle (or center) portion with respect to the longitudinal direction L of each light-emitting element LD.

[0139] Figure 4 A display device according to an embodiment of the present disclosure is shown. Specifically, it shows the use of Figure 1 andFigure 2 Schematic plan view of a display device using the light-emitting element shown as a light source.

[0140] For illustrative purposes, Figure 4 The structure of the display device is schematically shown focusing on the display area where an image is displayed. In some embodiments, although not shown, at least one driver (e.g., a scan driver and a data driver) and / or multiple lines may be further provided in the display device.

[0141] Referring to Figures 1 to 4 , a display device according to an embodiment of the present disclosure may include a substrate SUB, a plurality of pixels PXL disposed on the substrate SUB and each including at least one light-emitting element LD, a driver disposed on the substrate SUB and configured to drive the pixels PXL, and a line assembly for connecting the pixels PXL to the driver.

[0142] The display device may be classified into a passive matrix type display device and an active matrix type display device according to the method of driving the light-emitting element LD. For example, in the case where the display device is implemented as an active matrix type, each of the pixels PXL may include a driving transistor configured to control the amount of current to be supplied to the light-emitting element LD, and a switching transistor configured to transmit a data signal to the driving transistor.

[0143] Recently, based on resolution, contrast, and operating speed, an active matrix type display device capable of selectively turning on each pixel PXL has become mainstream. However, the present disclosure is not limited thereto. For example, a passive matrix type display device in which the pixels PXL can be turned on in groups may also include components (e.g., a first electrode and a second electrode) for driving the light-emitting element LD.

[0144] The substrate SUB may include a display area DA and a non-display area NDA.

[0145] In an embodiment, the display area DA may be provided in the central area of the display device, and the non-display area NDA may be provided in the peripheral area of the display device so as to surround the display area DA. The positions of the display area DA and the non-display area NDA are not limited thereto, and their positions may vary.

[0146] The display area DA may be an area where pixels PXL for displaying an image are provided. The non-display area NDA may be an area where a driver configured to drive the pixels PXL and a part of the line assembly for connecting the pixels PXL to the driver are provided.

[0147] The display area DA can have various shapes. For example, the display area DA can have a closed polygon shape including straight edges. In another embodiment, the display area DA can have a circular shape and / or an elliptical shape including curved edges. In another embodiment, the display area DA can have various shapes such as a semi-circular shape and a semi-elliptical shape including straight edges and curved edges.

[0148] The non-display area NDA can be provided on at least one side of the display area DA. In an embodiment of the present disclosure, the non-display area NDA can surround the periphery (or edge) of the display area DA.

[0149] A line component connected to the pixel PXL and a driver connected to the line component and configured to drive the pixel PXL can be provided in the non-display area NDA.

[0150] The line component can electrically connect the driver to the pixel PXL. The line component can be a fan-out line connected to signal lines (e.g., scan lines, data lines, and emission control lines) connected to each pixel PXL to provide signals to the pixel PXL.

[0151] The substrate SUB can include a transparent insulating material to allow light transmission. The substrate SUB can be a rigid substrate or a flexible substrate.

[0152] One area on the substrate SUB can be set as the display area DA where the pixel PXL is provided, and another area on the substrate SUB can be set as the non-display area NDA. For example, the substrate SUB can include a display area DA including a plurality of pixel regions in which the corresponding pixel PXLs are formed and a non-display area NDA provided around the display area DA.

[0153] The pixel PXL can be provided in the display area DA on the substrate SUB. In an embodiment of the present disclosure, the pixel PXL can be arranged in the display area DA in a stripe or layout structure, but the present disclosure is not limited thereto.

[0154] Each of the pixel PXLs can include at least one light-emitting element LD configured to be driven in response to a corresponding scan signal and a corresponding data signal. The light-emitting element LD can have a small size corresponding to the micron level or the nanometer level, and can be connected in parallel to the light-emitting element provided adjacent thereto, but the present disclosure is not limited thereto. The light-emitting element LD can form a light source of each pixel PXL.

[0155] Each of the pixel PXLs can include at least one light source driven by a signal (e.g., a scan signal and a data signal) and / or a power source (e.g., a first driving power source and a second driving power source). For example, each of the pixel PXLs can include Figure 1 andFigure 2 The light-emitting element LD shown, for example, has at least one ultra-small light-emitting element LD with a small size in the range of nanometers to micrometers. However, in embodiments of the present disclosure, the type of the light-emitting element LD that can be used as a light source for each in the pixel PXL is not limited thereto.

[0156] In embodiments of the present disclosure, the color, type, and / or number of the pixels PXL are not particularly limited. For example, the color of the light emitted from each pixel PXL can be changed in various ways.

[0157] The driver can provide signals and power voltages to each of the pixels PXL through the line components, thereby controlling the operation of the pixels PXL.

[0158] The driver can include a scan driver configured to provide a scan signal to the pixels PXL through scan lines, an emission driver configured to provide an emission control signal to the pixels PXL through emission control lines, a data driver configured to provide data signals to the pixels PXL through data lines, and a timing controller. The timing controller can control the scan driver, the emission driver, and the data driver.

[0159] Figures 5a to 5e is a circuit diagram showing Figure 4 various embodiments of the electrical connection relationships of the components included in one pixel shown.

[0160] For example, Figures 5a to 5e shows other embodiments of the electrical connection relationships of the components included in the pixel PXL that can be used in an active display device. However, the type of the components included in the pixel PXL to which the embodiments of the present disclosure can be applied is not limited thereto.

[0161] In Figures 5a to 5e the definition of the term "pixel PXL" includes not only Figure 4 the components included in each of the pixels shown, but also the area where the components are disposed. In an embodiment, Figures 5a to 5e each pixel PXL shown can be any one of the pixels PXL disposed in Figure 4 the display device. The pixels PXL can have substantially the same or similar structures to each other.

[0162] Referring to Figures 1 to 4 and Figures 5a to 5e , each pixel (PXL, hereinafter referred to as "pixel") can include an emission unit EMU configured to generate light having a luminance corresponding to a data signal. The pixel PXL can also selectively include a pixel circuit 144 configured to drive the emission unit EMU.

[0163] In an embodiment, the emission unit EMU may include a plurality of light-emitting elements LD connected in parallel between a first power line PL1 to which a voltage of a first driving power supply VDD is to be applied and a second power line PL2 to which a voltage of a second driving power supply VSS is to be applied. For example, the emission unit EMU may include a first electrode EL1 (or “first alignment electrode”) connected to the first driving power supply VDD via a pixel circuit 144 and the first power line PL1, a second electrode EL2 (or “second alignment electrode”) connected to the second driving power supply VSS through the second power line PL2, and a plurality of light-emitting elements LD connected in parallel with each other in the same direction between the first electrode EL1 and the second electrode EL2. In an embodiment of the present disclosure, the first electrode EL1 may be an anode electrode, and the second electrode EL2 may be a cathode electrode.

[0164] In an embodiment of the present disclosure, each of the light-emitting elements LD included in the emission unit EMU may include a first end connected to the first driving power supply VDD through the first electrode EL1 and a second end connected to the second driving power supply VSS through the second electrode EL2. The first driving power supply VDD and the second driving power supply VSS may have different potentials. For example, the first driving power supply VDD may be set as a high-potential power supply, and the second driving power supply VSS may be set as a low-potential power supply. Here, during the emission period of the pixel PXL, the potential difference between the first driving power supply VDD and the second driving power supply VSS may be set to a value equal to or greater than the threshold voltage of the light-emitting element LD.

[0165] As described above, the light-emitting elements LD connected in parallel with each other in the same direction (e.g., in the forward direction) between the first electrode EL1 and the second electrode EL2 to which voltages having different potentials are respectively supplied may form respective effective light sources. The effective light sources may be aggregated to form the emission unit EMU of the pixel PXL.

[0166] The light-emitting elements LD of the emission unit EMU may emit light having a brightness corresponding to the driving current supplied thereto through the pixel circuit 144. For example, during each frame period, the pixel circuit 144 may supply a driving current corresponding to the gray level of the corresponding frame data to the emission unit EMU. The driving current supplied to the emission unit EMU may be divided into portions flowing into the respective light-emitting elements LD. Accordingly, each of the light-emitting elements LD may emit light having a brightness corresponding to the current applied thereto, such that the emission unit EMU may emit light having a brightness corresponding to the driving current.

[0167] Although Figures 5a to 5eAn embodiment is shown in which opposite ends of the light-emitting element LD are connected between the first driving power supply VDD and the second driving power supply VSS in the same direction, but the present disclosure is not limited thereto. In an embodiment, in addition to the light-emitting element LD forming each effective light source, the emission unit EMU may further include at least one ineffective light source. For example, as Figure 5d and Figure 5e shown, at least the reverse-biased light-emitting element LDr may be further connected between the first electrode EL1 and the second electrode EL2 of the emission unit EMU. The reverse-biased light-emitting element LDr and the light-emitting element LD forming the effective light source may be connected in parallel with each other between the first electrode EL1 and the second electrode EL2. Here, the reverse-biased light-emitting element LDr may be connected between the first electrode EL1 and the second electrode EL2 in a direction opposite to that of the light-emitting element LD. Even when a specific driving voltage (e.g., a forward-biased driving voltage) is applied between the first electrode EL1 and the second electrode EL2, the reverse-biased light-emitting element LDr remains deactivated. Therefore, current substantially does not flow through the reverse-biased light-emitting element LDr.

[0168] The pixel circuit 144 may be connected to the scan line Si and the data line Dj of the corresponding pixel PXL. For example, when the pixel PXL is disposed in the i-th row (i is a positive integer) and the j-th column (j is a positive integer) of the display area DA, the pixel circuit 144 of the pixel PXL may be connected to the i-th scan line Si and the j-th data line Dj of the display area DA. In an embodiment, as Figure 5a and Figure 5b shown, the pixel circuit 144 may include a first transistor T1, a second transistor T2, and a storage capacitor Cst. However, the structure of the pixel circuit 144 is not limited to the embodiments shown in Figure 5a and Figure 5b shown.

[0169] First, referring to Figure 5a , the pixel circuit 144 may include a first transistor T1, a second transistor T2, and a storage capacitor Cst.

[0170] The first terminal of the second transistor (T2; switching transistor) may be connected to the data line Dj, and its second terminal may be connected to the first node N1. Here, the first terminal and the second terminal of the second transistor T2 are different terminals. For example, when the first terminal is the source electrode, the second terminal is the drain electrode. The gate electrode of the second transistor T2 may be connected to the scan line Si.

[0171] When a scan signal having a voltage (e.g., a low voltage) for turning on the second transistor T2 is supplied from the scan line Si, the second transistor T2 is turned on to electrically connect the data line Dj to the first node N1. Here, a data signal corresponding to a corresponding frame is supplied to the data line Dj, whereby the data signal is transmitted to the first node N1. The data signal transmitted to the first node N1 may be charged into the storage capacitor Cst.

[0172] A first terminal of the first transistor (T1; driving transistor) may be connected to the first driving power supply VDD, and a second terminal thereof may be electrically connected to a first electrode EL1 of the light-emitting element LD. A gate electrode of the first transistor T1 may be connected to the first node N1. Thus, the first transistor T1 can control the amount of driving current to be supplied to the light-emitting element LD in response to the voltage of the first node N1.

[0173] One electrode of the storage capacitor Cst may be connected to the first driving power supply VDD, and a remaining electrode thereof may be connected to the first node N1. The storage capacitor Cst is charged with a voltage corresponding to the data signal supplied to the first node N1, and holds the charged voltage until a data signal of the next frame is supplied.

[0174] Figure 5a and Figure 5b both show a pixel circuit 144 including a second transistor T2 configured to transmit a data signal to the pixel PXL, a storage capacitor Cst configured to store the data signal, and a first transistor T1 configured to supply a driving current corresponding to the data signal to the light-emitting element LD.

[0175] However, the present disclosure is not limited thereto, and the structure of the pixel circuit 144 may be changed in various ways. For example, the pixel circuit 144 may further include at least one transistor element (a transistor element for compensating the threshold voltage of the first transistor T1, a transistor element for initializing the first node N1, and / or a transistor element for controlling the emission time of the light-emitting element LD), or other circuit elements (such as a boosting capacitor for raising the voltage of the first node N1).

[0176] In addition, although Figure 5a the transistors (e.g., the first transistor T1 and the second transistor T2) included in the pixel circuit 144 have been shown as P-type transistors, the present disclosure is not limited thereto. In other words, at least one of the first transistor T1 and the second transistor T2 included in the pixel circuit 144 may be implemented as an N-type transistor.

[0177] Refer to Figures 1 to 4 and Figure 5b, the first transistor T1 and the second transistor T2 according to an embodiment of the present disclosure can be implemented as N-type transistors. Except for some changes in the connection positions of components caused by the change in the type of transistor, Figure 5b The structure and operation of the pixel circuit 144 shown in Figure 5a are similar to the structure and operation of the pixel circuit 144 of

[0178] In an embodiment of the present disclosure, Figure 5b the pixel circuit 144 shown in Figure 5b may include a first transistor T1 and a second transistor T2 that are N-type transistors and a storage capacitor Cst. When the first transistor T1 and the second transistor T2 are implemented as N-type transistors, the emission unit EMU can be connected between the first driving power supply VDD and the pixel circuit 144 to ensure the stability of the storage capacitor Cst configured to be charged with a voltage corresponding to the data signal supplied to the first node N1. Here, the present disclosure is not limited thereto. In an embodiment, Figure 5b the emission unit EMU shown in Figure 5a and Figure 5b may be connected between the pixel circuit 144 and the second driving power supply VSS. In an embodiment of the present disclosure, the structure of the pixel circuit 144 is not limited to the embodiments shown in Figure 5b Figure 5c and Figure 5d For example, the pixel circuit 144 may be constructed in the same manner as the embodiments shown in Figure 5c and Figure 5d

[0179] As shown in Figure 5c and Figure 5d the pixel circuit 144 may be combined with the scan line Si and the data line Dj of the pixel PXL. For example, if the pixel PXL is set in the i-th row and the j-th column of the display area DA, the pixel circuit 144 of the pixel PXL may be connected to the i-th scan line Si and the j-th data line Dj of the display area DA.

[0180] In an embodiment, the pixel circuit 144 may also be connected to at least another scan line. For example, the pixel PXL set in the i-th row of the display area DA may also be connected to the (i - 1)-th scan line Si - 1 and / or the (i + 1)-th scan line Si + 1. In an embodiment, the pixel circuit 144 may be connected not only to the first driving power supply VDD and the second driving power supply VSS, but also to a third power supply. For example, the pixel circuit 144 may also be connected to the initialization power supply Vint.

[0181] The pixel circuit 144 may include a first transistor T1 to a seventh transistor T7 and a storage capacitor Cst.

[0182] One electrode (e.g., the source electrode) of the first transistor (T1; driving transistor) can be connected to the first driving power supply VDD via the fifth transistor T5, and its other electrode (e.g., the drain electrode) can be connected to one end of the light-emitting element LD via the sixth transistor T6. The gate electrode of the first transistor T1 can be connected to the first node N1. The first transistor T1 can control the driving current flowing between the first driving power supply VDD and the second driving power supply VSS via the light-emitting element LD in response to the voltage of the first node N1.

[0183] The second transistor (T2; switching transistor) can be connected between the j-th data line Dj connected to the pixel PXL and the source electrode of the first transistor T1. The gate electrode of the second transistor T2 can be connected to the i-th scan line Si connected to the pixel PXL. When a scan signal having a gate-on voltage (e.g., a low-level voltage) is supplied from the i-th scan line Si, the second transistor T2 can be turned on to electrically connect the j-th data line Dj to the source electrode of the first transistor T1. Therefore, when the second transistor T2 is turned on, the data signal supplied from the j-th data line Dj can be transmitted to the first transistor T1.

[0184] The third transistor T3 can be connected between the drain electrode of the first transistor T1 and the first node N1. The gate electrode of the third transistor T3 can be connected to the i-th scan line Si. When a scan signal having a gate-on voltage is supplied from the i-th scan line Si, the third transistor T3 can be turned on to electrically connect the drain electrode of the first transistor T1 to the first node N1.

[0185] The fourth transistor T4 can be connected between the first node N1 and the initialization power line to which the voltage of the initialization power supply Vint is to be applied. The gate electrode of the fourth transistor T4 can be connected to the previous scan line, e.g., the (i - 1)-th scan line Si-1. When a scan signal having a gate-on voltage is supplied to the (i - 1)-th scan line Si-1, the fourth transistor T4 can be turned on so that the voltage of the initialization power supply Vint can be transmitted to the first node N1. Here, the initialization power supply Vint can have a voltage equal to or less than the minimum voltage of the data signal.

[0186] The fifth transistor T5 can be connected between the first driving power supply VDD and the first transistor T1. The gate electrode of the fifth transistor T5 can be connected to the corresponding emission control line, e.g., the i-th emission control line Ei. The fifth transistor T5 can be turned off when an emission control signal having a gate-off voltage is supplied to the i-th emission control line Ei, and can be turned on in other cases.

[0187] The sixth transistor T6 can be connected between one end of the first transistor T1 and the light-emitting element LD. The gate electrode of the sixth transistor T6 can be connected to the i-th emission control line Ei. The sixth transistor T6 can be turned off when an emission control signal having a gate cut-off voltage is supplied to the i-th emission control line Ei, and can be turned on in other cases.

[0188] The seventh transistor T7 can be connected between the initialization power supply line and one end of the light-emitting element LD. The gate electrode of the seventh transistor T7 can be connected to any one of the scan lines of the subsequent group, for example, connected to the (i + 1)-th scan line Si+1. When a scan signal having a gate conduction voltage is supplied to the (i + 1)-th scan line Si+1, the seventh transistor T7 can be turned on, so that the voltage of the initialization power supply Vint can be supplied to one end of the light-emitting element LD.

[0189] The storage capacitor Cst can be connected between the first driving power supply VDD and the first node N1. The storage capacitor Cst can store a voltage corresponding to both the data signal applied to the first node N1 and the threshold voltage of the first transistor T1 during each frame period.

[0190] Although in Figure 5c and Figure 5d the transistors (e.g., the first transistor T1 to the seventh transistor T7) included in the pixel circuit 144 have been shown as P-type transistors, the present disclosure is not limited thereto. For example, at least one of the first transistor T1 to the seventh transistor T7 can be implemented as an N-type transistor.

[0191] In an embodiment of the present disclosure, the configuration of the pixel circuit 144 is not limited to Figures 5a to 5d the embodiment shown in Figure 5e For example, the pixel circuit 144 can be configured in the same manner as the embodiment shown in

[0192] As Figure 5e shown, the pixel circuit 144 can also be connected to the control line CLi and the sense line SENj. For example, the pixel circuit 144 of the pixel PXL provided in the i-th row and the j-th column of the display area DA can be connected to the i-th control line CLi and the j-th sense line SENj of the display area DA. In addition to Figure 5a and Figure 5b the first transistor T1 and the second transistor T2 shown in

[0193] The third transistor T3 is connected between the first transistor T1 and the sense line SENj. For example, one electrode of the third transistor T3 may be connected to a terminal (e.g., the source electrode) of the first transistor T1 that is connected to the first electrode EL1, and the other electrode of the third transistor T3 may be connected to the sense line SENj. In the case where the sense line SENj is omitted, the other electrode of the third transistor T3 may be connected to the data line Dj.

[0194] In an embodiment, the gate electrode of the third transistor T3 is connected to the control line CLi. In the case where the control line CLi is omitted, the gate electrode of the third transistor T3 may be connected to the scan line Si. The third transistor T3 may be turned on by a control signal having a gate conduction voltage (e.g., a high level) and supplied to the control line CLi during a specific sensing period, so that the sense line SENj and the first transistor T1 can be electrically connected to each other.

[0195] In an embodiment, the sensing period may be a period in which characteristic information (e.g., the threshold voltage of the first transistor T1, etc.) of each of the pixels PXL provided in the display area DA is extracted. During the above-mentioned sensing period, the first transistor T1 may be turned on by supplying a specific reference voltage for turning on the first transistor T1 to the first node N1 via the data line Dj and the second transistor T2, or by connecting each pixel PXL to a current source, etc. In addition, the third transistor T3 may be turned on by supplying a control signal having a gate conduction voltage to the third transistor T3, so that the first transistor T1 can be connected to the sense line SENj. Therefore, the characteristic information of each pixel PXL including the threshold voltage of the first transistor T1, etc. can be extracted through the sense line SENj. The extracted characteristic information may be used to convert image data to compensate for characteristic deviations between the pixels PXL.

[0196] Although Figure 5e an embodiment in which the first transistor T1 to the third transistor T3 are all N-type transistors is shown, the present disclosure is not limited thereto. For example, at least one of the first transistor T1 to the third transistor T3 may be implemented as a P-type transistor. In addition, although Figure 5e an embodiment in which the emission unit EMU is connected between the pixel circuit 144 and the second driving power source VSS is shown, the emission unit EMU may be connected between the first driving power source VDD and the pixel circuit 144. Additionally, a parasitic capacitance C may be formed between the first electrode EL1 and the second electrode EL2 of the emission unit EMU OLED .

[0197] Although Figures 5a to 5eAn embodiment is shown in which all light-emitting elements LD of each emission unit EMU are connected in parallel with each other, but the present disclosure is not limited thereto. In an embodiment, the emission unit EMU may include at least one series group including a plurality of light-emitting elements LD connected in parallel with each other. In other words, the emission unit EMU may have a series / parallel combined structure.

[0198] The structure of the pixel PXL to which the present disclosure can be applied is not limited to Figures 5a to 5e the embodiment shown in, and the corresponding pixel may have various structures. In an embodiment of the present disclosure, each pixel PXL may be configured in a passive light-emitting display device or the like. In this case, the pixel circuit 144 may be omitted, and opposite ends of the light-emitting element LD included in the emission unit EMU may be directly connected to the scan lines Si-1, Si, and Si+1, the data line Dj, the first power supply line PL1 to which the voltage of the first driving power supply VDD is to be applied, the second power supply line PL2 to which the voltage of the second driving power supply VSS is to be applied, and / or the control line.

[0199] Figure 6 is a schematic plan view showing Figure 4 one of the pixels shown in. Figure 7 is a schematic plan view showing a pixel including components other than the first bank pattern and the second bank pattern Figure 6 of. Figure 8 is a cross-sectional view taken along the line I-I' of Figure 6 of. Figures 9 to 11 is Figure 8 a magnified cross-sectional view of a partial EA of. Figure 12 is a cross-sectional view taken along the line II-II' of Figure 6 of. Figure 13 shows Figure 12 another embodiment of the first bank pattern shown in, and is a cross-sectional view corresponding to the line II-II' of Figure 6 of. Figure 14 shows Figure 12 another embodiment of the second contact electrode shown in, and is a cross-sectional view corresponding to the line II-II' of Figure 6 of. Figure 15 is a cross-sectional view taken along the line III-III' of Figure 6 of.

[0200] Figure 6 The pixels shown in may be any of the pixels shown in respectively. For example, Figures 5a to 5e the pixels shown in may be Figure 6 the pixels shown in. Figure 5a of.

[0201] In Figure 6 and Figure 7In the figure, for ease of description, illustrations of the transistors connected to the light-emitting elements and some signal lines connected to the transistors are omitted.

[0202] Although Figures 6 to 15 the structure of the pixel PXL is simply illustrated, for example, each electrode is shown as a single electrode layer and each insulating layer is shown as a single insulating layer, the present disclosure is not limited thereto.

[0203] In embodiments of the present disclosure, "components are provided and / or formed on the same layer (or referred to as the same layer)" may mean that the components are formed by the same process, and "components are provided and / or formed on different layers" may mean that the components are formed by different processes.

[0204] Furthermore, in embodiments of the present disclosure, the term "connected" between two components may mean being electrically connected to each other and physically connected to each other.

[0205] In addition, for illustrative purposes, Figures 8 to 15 only one first light-emitting element aligned between the first electrode and the second electrode among the light-emitting elements is shown, but the one first light-emitting element may replace Figure 6 and Figure 7 each of the multiple light-emitting elements shown in

[0206] Referring to Figures 1 to 4 、 Figure 5a 、 Figures 6 to 15 , a display device according to an embodiment of the present disclosure may include a substrate SUB, a signal line assembly, and a plurality of pixels PXL.

[0207] The substrate SUB may include a transparent insulating material to allow light transmission. The substrate SUB may be a rigid substrate or a flexible substrate.

[0208] For example, the rigid substrate may be one of a glass substrate, a quartz substrate, a glass-ceramic substrate, and a crystallized glass substrate.

[0209] The flexible substrate may be a film substrate or a plastic substrate including a polymer organic material. For example, the flexible substrate may include at least one of the following: polystyrene, polyvinyl alcohol, polymethyl methacrylate, polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, triacetate cellulose, and cellulose acetate propionate.

[0210] However, the material of the substrate SUB may be selected in various ways and includes, for example, fiber-reinforced plastic (FRP). During the process of manufacturing the display device, the material applied to the substrate SUB may be resistant to high processing temperatures (or heat-resistant).

[0211] The base SUB may include a display area DA including at least one pixel area PXA in which pixels PXL are provided, and a non-display area NDA provided around the display area DA.

[0212] In an embodiment, the pixels PXL may be arranged in a matrix shape and / or a stripe shape in the display area DA along a plurality of pixel rows extending in a first direction DR1 and a plurality of pixel columns extending in a second direction DR2 different from the first direction DR1 (e.g., intersecting the first direction DR1), but the present disclosure is not limited thereto. In an embodiment, the pixels PXL may be provided in the display area DA on the base SUB in various arrangements.

[0213] The pixel area PXA in which each pixel PXL is provided (or provided) may include an emission area EMA that emits light therefrom, and a peripheral area surrounding the periphery of the emission area EMA. In an embodiment of the present disclosure, the term "peripheral area" may include a non-emission area that does not emit light therefrom.

[0214] The signal line assembly may include a plurality of signal lines configured to transmit a signal (or voltage) to each pixel PXL. For example, the signal lines may include an i-th scan line Si configured to transmit a scan signal to each pixel PXL, a data line Dj configured to transmit a data signal to each pixel PXL, and power lines PL1 and PL2 configured to transmit driving power to each pixel PXL.

[0215] Each pixel PXL may include a pixel circuit layer PCL provided on the base SUB and including a pixel circuit 144, and a display element layer DPL including a plurality of light-emitting elements LD. The light-emitting elements LD may be provided in the emission area EMA in each of the pixel areas PXA provided in the pixels PXL.

[0216] For convenience of description, the pixel circuit layer PCL will be described first, and then the display element layer DPL will be described.

[0217] The pixel circuit layer PCL may include a buffer layer BFL, a pixel circuit 144 provided on the buffer layer BFL, and a passivation layer PSV provided on the pixel circuit 144.

[0218] The buffer layer BFL may prevent impurities from diffusing into the transistors T included in the pixel circuit 144. The buffer layer BFL may be an inorganic insulating layer formed of an inorganic material. The buffer layer BFL may include silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiON), and alumina (AlO x) at least one of the metal oxides. Although the buffer layer BFL can be implemented as a single-layer structure, the buffer layer BFL can be implemented as a multi-layer structure having at least two layers. In the case where the buffer layer BFL has a multi-layer structure, each layer can be formed of the same material or different materials. Depending on the material or process conditions of the substrate SUB, the buffer layer BFL can be omitted.

[0219] The pixel circuit 144 can include at least one transistor T and a storage capacitor Cst. The transistor T can include a driving transistor Tdr configured to control the driving current of the light-emitting element LD, and a switching transistor Tsw connected to the driving transistor Tdr. However, the present disclosure is not limited thereto. In addition to the driving transistor Tdr and the switching transistor Tsw, the pixel circuit 144 can further include circuit elements configured to perform other functions. In the following embodiments, the driving transistor Tdr and the switching transistor Tsw can be included in the term "transistor T" or "a plurality of transistors T". Here, the driving transistor Tdr can have the same configuration as the first transistor T1 described with reference to Figure 5a The switching transistor Tsw can have the same configuration as the second transistor T2 described with reference to Figure 5a described.

[0220] Each of the driving transistor Tdr and the switching transistor Tsw can include a transistor semiconductor pattern SCL, a gate electrode GE, a first terminal SE, and a second terminal DE. The first terminal SE can be a source electrode or a drain electrode, and the second terminal DE can be the other electrode. For example, in the case where the first terminal SE is a source electrode, the second terminal DE can be a drain electrode.

[0221] The transistor semiconductor pattern SCL can be provided and / or formed on the buffer layer BFL. The transistor semiconductor pattern SCL can include a first contact region in contact with the first terminal SE and a second contact region in contact with the second terminal DE. The region between the first contact region and the second contact region can be a channel region. The transistor semiconductor pattern SCL can be a semiconductor pattern formed of polysilicon, amorphous silicon, an oxide semiconductor, etc. The channel region can be a semiconductor pattern not doped with impurities and can be an intrinsic semiconductor. Each of the first contact region and the second contact region can be a semiconductor pattern doped with impurities.

[0222] The gate electrode GE can be provided and / or formed on the transistor semiconductor pattern SCL, and a gate insulating layer GI is disposed between the gate electrode GE and the transistor semiconductor pattern SCL.

[0223] The gate insulating layer GI can be an inorganic insulating layer including an inorganic material. For example, the gate insulating layer GI can include silicon nitride (SiN x )), silicon oxide (SiOx ) and at least one of metal oxides such as aluminum oxide (AlO x ). However, the material of the gate insulating layer GI is not limited to the materials of the foregoing embodiments. In an embodiment, the gate insulating layer GI may be implemented as an organic insulating layer including an organic material. Although the gate insulating layer GI may be implemented in a single-layer structure, the gate insulating layer GI may be implemented in a multi-layer structure having at least two layers.

[0224] The first terminal SE and the second terminal DE may respectively contact the first contact region and the second contact region of the transistor semiconductor pattern SCL through corresponding contact holes passing through the first interlayer insulating layer ILD1 and the gate insulating layer GI. For example, the first terminal SE may contact one of the first contact region and the second contact region of the transistor semiconductor pattern SCL. The second terminal DE may contact the other contact region of the first contact region and the second contact region of the transistor semiconductor pattern SCL.

[0225] The first interlayer insulating layer ILD1 may be an inorganic insulating layer including an inorganic material. For example, the first interlayer insulating layer ILD1 may include silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiON) and at least one of metal oxides such as aluminum oxide (AlO x ). The first interlayer insulating layer ILD1 may include a single layer or multiple layers. In an embodiment, the first interlayer insulating layer ILD1 may be an organic insulating layer including an organic material.

[0226] Although in the foregoing embodiments, the first terminal SE and the second terminal DE of each of the driving transistor Tdr and the switching transistor Tsw have been described as being electrically connected to separate electrodes of the transistor semiconductor pattern SCL through contact holes passing through the gate insulating layer GI and the first interlayer insulating layer ILD1, the present disclosure is not limited thereto. In an embodiment, the first terminal SE of each of the driving transistor Tdr and the switching transistor Tsw may be one of the first contact region and the second contact region adjacent to the channel region of the corresponding transistor semiconductor pattern SCL. The second terminal DE of each of the driving transistor Tdr and the switching transistor Tsw may be the other of the first contact region and the second contact region adjacent to the channel region of the corresponding transistor semiconductor pattern SCL. In this case, the second terminal DE of the driving transistor Tdr may be electrically connected to the light-emitting element LD of the corresponding pixel PXL through a separate connection member including a bridging electrode, a contact electrode, etc.

[0227] In an embodiment of the present disclosure, each of the transistors T included in the pixel circuit 144 may be formed of a low-temperature polysilicon (LTPS) thin-film transistor, but the present disclosure is not limited thereto. In some embodiments, each transistor may be implemented as an oxide semiconductor thin-film transistor. In addition, the case where each of the transistors T is shown as a thin-film transistor having a top-gate structure is shown, but the present disclosure is not limited thereto. In an embodiment, each of the transistors T may be a thin-film transistor having a bottom-gate structure.

[0228] In an embodiment, the transistors T included in the pixel circuit layer PCL may include not only the driving transistor Tdr and the switching transistor Tsw, but also additional transistors such as a transistor for compensating the threshold voltage of the driving transistor Tdr and a transistor for controlling the emission time of each of the light-emitting elements LD.

[0229] The storage capacitor Cst may include a lower electrode LE provided on the gate insulating layer GI and an upper electrode UE provided on the first interlayer insulating layer ILD1 and overlapping the lower electrode LE.

[0230] The lower electrode LE may be provided in the same layer as the gate electrode GE of the driving transistor Tdr and include the same material as the material of the gate electrode GE. In an embodiment, the lower electrode LE and the gate electrode GE of the driving transistor Tdr may be integrally formed with each other. In this case, the lower electrode LE may be regarded as a region of the gate electrode GE of the driving transistor Tdr. In another embodiment, the lower electrode LE may be provided as a component separated from the gate electrode GE of the driving transistor Tdr.

[0231] The upper electrode UE may overlap and cover the lower electrode LE. The capacitance of the storage capacitor Cst may be increased by increasing the overlapping area between the upper electrode UE and the lower electrode LE. The upper electrode UE may be electrically connected to the first power line PL1. Accordingly, the voltage of the first driving power supply VDD applied to the first power line PL1 may be transmitted to the upper electrode UE.

[0232] The second interlayer insulating layer ILD2 may be provided and / or formed on the storage capacitor Cst. The second interlayer insulating layer ILD2 may cover the storage capacitor Cst. The second interlayer insulating layer ILD2 may be an inorganic insulating layer including an inorganic material or an organic insulating layer including an organic material. In an embodiment, the second interlayer insulating layer ILD2 may include the same material as the material of the first interlayer insulating layer ILD1, but the present disclosure is not limited thereto. Although the second interlayer insulating layer ILD2 may be implemented as a single layer, it may be implemented as a multilayer including at least two layers.

[0233] The pixel circuit layer PCL may include a driving voltage line DVL disposed and / or formed on the second interlayer insulating layer ILD2. The driving voltage line DVL may have the same configuration as that of the second power line PL2 described with reference to Figure 5a . The voltage of the second driving power supply VSS may be applied to the driving voltage line DVL. The pixel circuit layer PCL may further include a first power line PL1 to which the voltage of the first driving power supply VDD is to be applied. The first power line PL1 may be disposed in the same layer as the layer of the driving voltage line DVL or in a layer different from the layer of the driving voltage line DVL. Although in the embodiments of the present disclosure, the driving voltage line DVL has been described as being disposed in the same layer as the layers of the first terminal SE and the second terminal DE of the driving transistor Tdr, the present disclosure is not limited thereto. In an embodiment, when the first terminal SE and the second terminal DE of the transistor T are contact regions adjacent to the channel region of the transistor semiconductor pattern SCL, the driving voltage line DVL may be disposed in the same layer as any one of the conductive layers in the conductive layer disposed in the pixel circuit layer PCL. In other words, the position of the driving voltage line DVL in the pixel circuit layer PCL may be changed in various ways according to the type of the transistor T.

[0234] The first power line PL1 may be electrically connected to a component (e.g., the first electrode EL1) of the display element layer DPL. The driving voltage line DVL may be electrically connected to a component (e.g., the second electrode EL2) of the display element layer DPL. The first power line PL1 and the driving voltage line DVL may respectively transmit an alignment signal (or alignment voltage) to the first electrode EL1 and the second electrode EL2 to align the light-emitting element LD in the pixel region PXA of each of the pixels PXL. After the light-emitting element LD has been aligned, both the first power line PL1 and the driving voltage line DVL may transmit corresponding driving power to each pixel PXL to drive the light-emitting element LD.

[0235] Each of the first power line PL1 and the driving voltage line DVL may include a conductive material. For example, each of the first power line PL1 and the driving voltage line DVL may have a single-layer structure formed of one or a combination selected from the group consisting of molybdenum (Mo), tungsten (W), aluminum neodymium (AlNd), titanium (Ti), aluminum (Al), silver (Ag), and their alloys, or may have a bilayer or multilayer structure formed of molybdenum (Mo), aluminum (Al), or silver (Ag) as a low-resistance material to reduce the line resistance.

[0236] The passivation layer PSV may be disposed and / or formed on the transistor T and the driving voltage line DVL.

[0237] The passivation layer PSV can be implemented in the form of an organic insulating layer, an inorganic insulating layer, or a structure including an organic insulating layer provided on an inorganic insulating layer. The inorganic insulating layer can include, for example, silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiON), and at least one of metal oxides such as aluminum oxide (AlO x ). The organic insulating layer can include, for example, at least one of polyacrylate resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin, and benzocyclobutene resin.

[0238] The passivation layer PSV can include a first contact hole CH1 that exposes a region of the driving transistor Tdr and a second contact hole CH2 that exposes a region of the driving voltage line DVL.

[0239] The display element layer DPL can be provided on the passivation layer PSV.

[0240] The display element layer DPL can include a first bank pattern BNK1 and a second bank pattern BNK2, a first electrode EL1 and a second electrode EL2, a first connection line CNL1 and a second connection line CNL2, a light-emitting element LD, and a first contact electrode CNE1 and a second contact electrode CNE2. In addition, the display element layer DPL can further include a first insulating layer INS1, a second insulating layer INS2, and a encapsulation layer ENC.

[0241] The first bank pattern BNK1 can be provided in an emission region EMA from which light will be emitted in a pixel region PXA of each pixel PXL. The first bank pattern BNK1 can be a support component that supports each of the first electrode EL1 and the second electrode EL2 so as to change the surface profile (or shape) of each of the first electrode EL1 and the second electrode EL2, such that light emitted from the light-emitting element LD can be guided in the image display direction of the display device.

[0242] The first bank pattern BNK1 may be disposed and / or formed between the passivation layer PSV and the first electrode EL1 and the second electrode EL2 in the emission area EMA of each pixel PXL. For example, the first bank pattern BNK1 may be uniformly disposed and / or formed between the passivation layer PSV and the first electrode EL1 and between the passivation layer PSV and the second electrode EL2. The first bank pattern BNK1 may include an inorganic insulating layer formed of an inorganic material or an organic insulating layer formed of an organic material. In an embodiment, the first bank pattern BNK1 may include an organic insulating layer having a single-layer structure and / or an inorganic insulating layer having a single-layer structure, but the present disclosure is not limited thereto. In an embodiment, the first bank pattern BNK1 may be implemented in the form of a multilayer structure formed by stacking at least one organic insulating layer and at least one inorganic insulating layer. However, the material of the first bank pattern BNK1 is not limited to the foregoing embodiments. In an embodiment, the first bank pattern BNK1 may include a conductive material.

[0243] The first bank pattern BNK1 may have a trapezoidal cross-section, the width of which decreases upward from one surface of the passivation layer PSV, but the present disclosure is not limited thereto. In an embodiment, as Figure 13 shown, the first bank pattern BNK1 may include a curved surface having a cross-section including a semi-elliptical shape, a semi-circular shape (or a hemispherical shape), etc. in which the width decreases upward from one surface of the passivation layer PSV. In a cross-sectional view, the shape of the first bank pattern BNK1 is not limited to the foregoing embodiments, and may be changed in various ways within a range in which the efficiency of light emitted from each of the light-emitting elements LD can be enhanced. The first bank patterns BNK1 adjacent to each other in the first direction DR1 may be disposed on the same surface of the passivation layer PSV and have the same height (or thickness).

[0244] In a plan view, the first bank pattern BNK1 may have a strip shape extending in the second direction DR2 (in the vertical direction), but the present disclosure is not limited thereto. The shape of the first bank pattern BNK1 may be changed in various ways.

[0245] The second bank pattern BNK2 may surround at least one side of the peripheral area of the pixel area PXA of each pixel PXL. The peripheral area may include a non-emission area from which light is not emitted.

[0246] The second bank pattern BNK2 may be a structure configured to define (or divide) the emission area EMA of each of the pixels PXL, and may be, for example, a pixel defining layer. The second bank pattern BNK2 may include at least one light-blocking material and / or reflective material to prevent light leakage defects in which light (or light rays) leaks between the pixels PXL. In an embodiment, a reflective material layer may be formed on the second bank pattern BNK2 to further enhance the efficiency of the light emitted from each of the pixels PXL. The second bank pattern BNK2 may be provided and / or formed in a layer different from the layer of the first bank pattern BNK1, but the present disclosure is not limited thereto. In an embodiment, the second bank pattern BNK2 may be provided and / or formed in the same layer as the layer of the first bank pattern BNK1. In an embodiment of the present disclosure, the second bank pattern BNK2 may be formed in a layer different from the layer of the first bank pattern BNK1 and provided on the first insulating layer INS1.

[0247] In a plan view, the first connection line CNL1 may extend in a first direction DR1 (e.g., “horizontal direction”) of each of the pixels PXL. The first connection line CNL1 may be provided and / or formed only in each pixel PXL to independently or individually drive each pixel PXL from adjacent pixels PXL and be electrically separated and / or physically separated from the first connection line CNL1 provided and / or formed in each of the adjacent pixels PXL. The first connection line CNL1 provided in each pixel PXL may be electrically connected to components (e.g., driving transistor Tdr) included in the pixel circuit layer PCL of the corresponding pixel PXL through a first contact hole CH1 passing through the passivation layer PSV.

[0248] In a plan view, the second connection line CNL2 may extend in a direction parallel to the direction in which the first connection line CNL1 extends. For example, the second connection line CNL2 may extend in the first direction DR1. The second connection line CNL2 may be provided in common for each pixel PXL and the pixel PXL adjacent thereto. Accordingly, a plurality of pixels PXL provided in the same pixel row in the first direction DR1 may be commonly connected to the second connection line CNL2. The second connection line CNL2 provided in each pixel PXL may be electrically connected to components (e.g., driving voltage line DVL) included in the pixel circuit layer PCL of the corresponding pixel PXL through a second contact hole CH2 passing through the passivation layer PSV. Accordingly, the voltage of the second driving power supply VSS applied to the driving voltage line DVL may be transmitted to the second connection line CNL2.

[0249] Each of the first electrode EL1 and the second electrode EL2 may be provided in the emission area EMA of each of the pixels PXL and extend in a second direction DR2. The first electrode EL1 and the second electrode EL2 may be provided on the same surface and spaced apart from each other.

[0250] The first electrode EL1 may include a 1-1 electrode EL1_1 and a 1-2 electrode EL1_2 branched from the first connection line CNL1 in the second direction DR2. The 1-1 electrode EL1_1, the 1-2 electrode EL1_2, and the first connection line CNL1 may be integrally formed and electrically connected and / or physically connected to each other. In the case where the first electrode EL1 and the first connection line CNL1 are integrally formed, the first connection line CNL1 may be a region of the first electrode EL1, or the first electrode EL1 may be a region of the first connection line CNL1. Here, the present disclosure is not limited thereto. In some embodiments, the first electrode EL1 and the first connection line CNL1 may be separately formed and electrically connected to each other through contact holes, connection members, etc. not shown.

[0251] The second electrode EL2 may branch from the second connection line CNL2 in the second direction DR2. The second electrode EL2 and the second connection line CNL2 may be integrally formed and electrically connected and / or physically connected to each other. In the case where the second electrode EL2 and the second connection line CNL2 are integrally formed, the second connection line CNL2 may be a region of the second electrode EL2, or the second electrode EL2 may be a region of the second connection line CNL2. However, the present disclosure is not limited thereto. In some embodiments, the second electrode EL2 and the second connection line CNL2 may be separately formed and electrically connected to each other through contact holes, connection members, etc. not shown.

[0252] The second electrode EL2 may be disposed between the 1-1 electrode EL1_1 and the 1-2 electrode EL1_2. The 1-1 electrode EL1_1 and the second electrode EL2 may be spaced apart from each other by a specific distance. The second electrode EL2 and the 1-2 electrode EL1_2 may be spaced apart from each other by a specific distance. In the emission region EMA of each of the pixels PXL, the distance between the 1-1 electrode EL1_1 and the second electrode EL2 and the distance between the second electrode EL2 and the 1-2 electrode EL1_2 may be the same as each other. Accordingly, the light-emitting element LD may be more uniformly aligned in the emission region EMA of each of the pixels PXL. However, the present disclosure is not limited thereto. In an embodiment, the distance between the 1-1 electrode EL1_1 and the second electrode EL2 and the distance between the second electrode EL2 and the 1-2 electrode EL1_2 may be different from each other.

[0253] Each of the first electrode EL1 and the second electrode EL2 may be disposed and / or formed on the first bank pattern BNK1 and have a surface profile corresponding to the shape of the first bank pattern BNK1. For example, each of the first electrode EL1 and the second electrode EL2 may include a protrusion corresponding to the first bank pattern BNK1 and a planar portion corresponding to one surface of the passivation layer PSV.

[0254] Each of the first electrode EL1 and the second electrode EL2 may be formed of a material having a predetermined reflectivity such that light emitted from each of the light-emitting elements LD travels in the image display direction of the display device. Each of the first electrode EL1 and the second electrode EL2 may be made of a conductive material (or substance) having a specific reflectivity. The conductive material (or substance) may include an opaque metal that is conducive to reflecting the light emitted from the light-emitting element LD in the image display direction of the display device. For example, the opaque metal may include metals such as silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), and their alloys. In an embodiment, each of the first electrode EL1 and the second electrode EL2 may include a transparent conductive material (or substance). The transparent conductive material (or substance) may include conductive oxides such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), and indium tin zinc oxide (ITZO), and conductive polymers such as PEDOT. In the case where the first electrode EL1 and the second electrode EL2 include a transparent conductive material, a separate conductive layer formed of an opaque metal for reflecting the light emitted from the light-emitting element LD in the image display direction of the display device may be added. However, the materials of the first electrode EL1 and the second electrode EL2 are not limited to the foregoing materials.

[0255] Although each of the first electrode EL1 and the second electrode EL2 may be provided and / or formed as a single-layer structure, the present disclosure is not limited thereto. In an embodiment, each of the first electrode EL1 and the second electrode EL2 may be provided and / or formed as a multi-layer structure formed by stacking at least two materials among metals, alloys, conductive oxides, and conductive polymers. Each of the first electrode EL1 and the second electrode EL2 may have a multi-layer structure including at least two layers to minimize distortion caused by signal delay when a signal (or voltage) is transmitted to opposite ends EP1 and EP2 of each of the light-emitting elements LD. In this case, each of the first electrode EL1 and the second electrode EL2 may have a multi-layer structure formed by stacking layers in the order of, for example, indium tin oxide (ITO) / silver (Ag) / indium tin oxide (ITO).

[0256] In the case where the first connection line CNL1 and the first electrode EL1 are integrally formed with each other, the first connection line CNL1 may include the same material as the first electrode EL1. In the case where the second connection line CNL2 and the second electrode EL2 are integrally formed with each other, the second connection line CNL2 may include the same material as the second electrode EL2.

[0257] As described above, since each of the first electrode EL1 and the second electrode EL2 has a surface profile corresponding to the shape of the first bank pattern BNK1 provided thereunder, the light emitted from each of the light-emitting elements LD can be reflected by each of the first electrode EL1 and the second electrode EL2 and travel more effectively in the image display direction of the display device. Therefore, the efficiency of the light emitted from each of the light-emitting elements LD can be further enhanced.

[0258] The first bank pattern BNK1, the first electrode EL1, and the second electrode EL2 can all be used as reflection components configured to guide the light emitted from the light-emitting elements LD in a desired direction, thereby enhancing the optical efficiency of the display device.

[0259] Any one of the first electrode EL1 and the second electrode EL2 can be an anode electrode, and the other electrode can be a cathode electrode. In an embodiment of the present disclosure, the first electrode EL1 can be an anode electrode, and the second electrode EL2 can be a cathode electrode.

[0260] Although in the foregoing embodiment, the first electrode EL1 has been described as including two electrodes branched from the first connection line CNL1 in the second direction DR2, for example, the 1-1 electrode EL1_1 and the 1-2 electrode EL1_2, the present disclosure is not limited thereto. In an embodiment, the first electrode EL1 can include at least one electrode branched from the first connection line CNL1 in the second direction DR2.

[0261] The first contact electrode CNE1 can be provided and / or formed on the first electrode EL1 to reliably electrically connect and / or physically connect one end of each of the opposite ends EP1 and EP2 of the first electrode EL1 to the light-emitting elements LD.

[0262] The first contact electrode CNE1 can cover the first electrode EL1 and be stacked with the first electrode EL1. The first contact electrode CNE1 can be directly provided on an area of the first electrode EL1 exposed from the first insulating layer INS1 and can be connected to the first electrode EL1. In an embodiment, in the case where a cover layer (not shown) is provided on the first electrode EL1 exposed from the first insulating layer INS1, the first contact electrode CNE1 can be provided on the cover layer and electrically connected to the first electrode EL1 through the cover layer. Here, the cover layer can protect the first electrode EL1 from defects that may occur during the process of manufacturing the display device and enhance the adhesion between the first electrode EL1 and the pixel circuit layer PCL provided thereunder. The cover layer can be formed of a transparent conductive material such as indium zinc oxide (IZO) to minimize the loss of light emitted from each of the light-emitting elements LD and reflected by the first electrode EL1 in the image display direction of the display device.

[0263] In addition, the first contact electrode CNE1 can be directly disposed on one end of each of the opposite ends EP1 and EP2 of the light-emitting element LD, and is stacked with the one end. The first contact electrode CNE1 can include a 1-1 contact electrode CNE1_1 disposed and / or formed on the 1-1 electrode EL1_1 and a 1-2 contact electrode CNE1_2 disposed and / or formed on the 1-2 electrode EL1_2.

[0264] The second contact electrode CNE2 can be disposed and / or formed on the second electrode EL2 to reliably electrically connect and / or physically connect the second electrode EL2 to the remaining end of each of the opposite ends EP1 and EP2 of the light-emitting element LD. The second contact electrode CNE2 can cover the second electrode EL2 and is stacked with the second electrode EL2. In addition, the second contact electrode CNE2 can cover the remaining end of each of the opposite ends EP1 and EP2 of the light-emitting element LD and is stacked with the remaining end.

[0265] The first contact electrode CNE1 and the second contact electrode CNE2 can be formed of various transparent conductive materials such that the light emitted from each of the light-emitting elements LD and reflected by the first electrode EL1 and the second electrode EL2 travels without loss in the image display direction of the display device. For example, the first contact electrode CNE1 and the second contact electrode CNE2 can include at least one of various transparent conductive materials including indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), and indium tin zinc oxide (ITZO), and can be substantially transparent or semi-transparent to meet a specific transmittance. However, the materials of the first contact electrode CNE1 and the second contact electrode CNE2 are not limited to the foregoing embodiments. In an embodiment, the first contact electrode CNE1 and the second contact electrode CNE2 can be formed of various opaque conductive materials.

[0266] The second contact electrode CNE2 can be disposed between the 1-1 contact electrode CNE1_1 and the 1-2 contact electrode CNE1_2. The 1-1 contact electrode CNE1_1 and the second contact electrode CNE2 can be spaced apart from each other by a specific distance. The second contact electrode CNE2 and the 1-2 contact electrode CNE1_2 can be spaced apart from each other by a specific distance. In the emission area EMA of each of the pixels PXL, the distance between the 1-1 contact electrode CNE1_1 and the second contact electrode CNE2 and the distance between the second contact electrode CNE2 and the 1-2 contact electrode CNE1_2 can be the same as each other. However, the present disclosure is not limited thereto. In an embodiment, the distance between the 1-1 contact electrode CNE1_1 and the second contact electrode CNE2 and the distance between the second contact electrode CNE2 and the 1-2 contact electrode CNE1_2 can be different from each other.

[0267] The first contact electrode CNE1 and the second contact electrode CNE2 can be disposed on the same layer and formed by the same process. However, the present disclosure is not limited thereto. In an embodiment, the first contact electrode CNE1 and the second contact electrode CNE2 can be disposed on different layers and formed by different processes. In the case where the first contact electrode CNE1 and the second contact electrode CNE2 are disposed on different layers and formed by different processes, as Figure 14 shown, the auxiliary insulating layer AUINS can be disposed between the first contact electrode CNE1 and the second contact electrode CNE2. The auxiliary insulating layer AUINS can be disposed on the 1-1 contact electrode CNE1_1 and cover the 1-1 contact electrode CNE1_1. Here, the auxiliary insulating layer AUINS can be an inorganic insulating layer including an inorganic material or an organic insulating layer including an organic material.

[0268] The encapsulation layer ENC can be disposed and / or formed on the first contact electrode CNE1 and the second contact electrode CNE2. The encapsulation layer ENC can be an inorganic insulating layer including an inorganic material or an organic insulating layer including an organic material. For example, the encapsulation layer ENC can have a structure formed by alternately stacking at least one inorganic insulating layer and at least one organic insulating layer. The encapsulation layer ENC can cover the entire display element layer DPL and prevent water or moisture from being sucked into the display element layer DPL including the light-emitting element LD from the outside.

[0269] Each of the light-emitting elements LD can include a super-small light-emitting element made of a material having an inorganic crystal structure and having a small size (for example, in the range of nanometers to micrometers). For example, each of the light-emitting elements LD can be a super-small light-emitting element formed by an etching scheme or a super-small light-emitting element formed by a growth scheme.

[0270] Although at least two to several dozen light-emitting elements LD can be aligned and / or disposed in the pixel region PXA of each of the pixels PXL, the number of the light-emitting elements LD is not limited thereto. In an embodiment, the number of the light-emitting elements LD aligned and / or disposed in the pixel region PXA can be changed in various ways.

[0271] The light-emitting element LD can be disposed between two electrodes adjacent to each other in the first direction DR1. The light-emitting element LD can include a first light-emitting element LD1 disposed between the 1-1 electrode EL1_1 and the second electrode EL2, and a second light-emitting element LD2 disposed between the second electrode EL2 and the 1-2 electrode EL1_2. In the following embodiments, the term "light-emitting element LD" will be used to arbitrarily designate one of the first light-emitting element LD1 and the second light-emitting element LD2, or to commonly designate the first light-emitting element LD1 and the second light-emitting element LD2.

[0272] Each of the light-emitting elements LD can be aligned between two electrodes such that the longitudinal direction L is parallel to the first direction DR1. The light-emitting element LD can be diffused in a solution and supplied into the pixel region PXA of each pixel PXL.

[0273] In an embodiment of the present disclosure, the light-emitting element LD can be supplied to the pixel region PXA of each pixel PXL by an inkjet printing scheme, a slot coating scheme, or various other schemes. For example, the light-emitting element LD can be mixed with a volatile solvent and then supplied to the pixel region PXA by an inkjet printing scheme or a slot coating scheme. Here, when the first electrode EL1 and the second electrode EL2 disposed in the pixel region PXA are respectively supplied with corresponding alignment signals, an electric field can be formed between two adjacent electrodes. Accordingly, the light-emitting element LD can be aligned between the 1-1 electrode EL1_1 and the second electrode EL2 and between the second electrode EL2 and the 1-2 electrode EL1_2.

[0274] After aligning the light-emitting element LD, the solvent can be removed by volatilization or other methods. As a result, the light-emitting element LD can be finally aligned and / or disposed in the pixel region PXA of each pixel PXL.

[0275] The light-emitting element LD can be disposed and / or formed on the first insulating layer INS1.

[0276] The first insulating layer INS1 can be disposed and / or formed in the pixel region PXA of each pixel PXL under each of the light-emitting elements LD aligned between two electrodes. The first insulating layer INS1 can be filled into the space between each of the light-emitting elements LD and the passivation layer PSV to stably support the light-emitting element LD and prevent the light-emitting element LD from separating from the passivation layer PSV.

[0277] The first insulating layer INS1 may include an inorganic insulating layer containing an inorganic material or an organic insulating layer containing an organic material. Although in the embodiments of the present disclosure, the first insulating layer INS1 may include an inorganic insulating layer that is conducive to protecting the light-emitting element LD from the pixel circuit layer PCL of each pixel PXL, the present disclosure is not limited thereto. In an embodiment, the first insulating layer INS1 may include an organic insulating layer that is conducive to planarizing the support surface of the light-emitting element LD.

[0278] The first insulating layer INS1 may expose one region of each of the first electrode EL1 and the second electrode EL2, and cover other regions except the one region. Here, the first contact electrode CNE1 may be disposed and / or formed on the exposed region of the first electrode EL1, and the second contact electrode CNE2 may be disposed and / or formed on the exposed region of the second electrode EL2.

[0279] The second insulating layer INS2 may be disposed and / or formed on the light-emitting element LD. The second insulating layer INS2 may be disposed and / or formed on each of the light-emitting elements LD to cover a part of the upper surface of each of the light-emitting elements LD, and expose opposite ends EP1 and EP2 of each of the light-emitting elements LD to the outside. The second insulating layer INS2 may be formed as an independent insulating pattern in the pixel region PXA of each pixel PXL, but the present disclosure is not limited thereto.

[0280] The second insulating layer INS2 may have a single-layer structure or a multi-layer structure, and include an inorganic insulating layer containing at least one inorganic material or an organic insulating layer containing at least one organic material. The second insulating layer INS2 may also reliably fix each of the light-emitting elements LD aligned in the pixel region PXA of each pixel PXL. The second insulating layer INS2 may include an inorganic insulating layer that is conducive to protecting the active layer 12 of each of the light-emitting elements LD from the influence of external oxygen, moisture, etc. However, the present disclosure is not limited thereto. According to the design conditions of the display device to which the light-emitting element LD is to be applied, etc., the second insulating layer INS2 may include an organic insulating layer containing an organic material.

[0281] In an embodiment of the present disclosure, after the alignment of the light-emitting element LD in each pixel region PXA of the pixel PXL is completed, a second insulating layer INS2 is formed on the light-emitting element LD so that the light-emitting element LD can be prevented from being separated from the alignment position. In the case where there is a gap (or space) between the first insulating layer INS1 and the light-emitting element LD before forming the second insulating layer INS2, the gap can be filled with the second insulating layer INS2 during the process of forming the second insulating layer INS2. In this case, the second insulating layer INS2 includes an organic insulating layer that is conducive to filling the gap between the first insulating layer INS1 and the light-emitting element LD with the second insulating layer INS2.

[0282] The second insulating layer INS2 may include a 2a insulating layer INS2a filled into the gap between the first insulating layer INS1 and the light-emitting element LD, and a 2b insulating layer INS2b located on the second light-emitting element LD2. The 2b insulating layer INS2b may include a first surface BF (or lower surface) in contact with each of the light-emitting elements LD and a second surface UF (or upper surface) opposite to the first surface BF (or lower surface). In an embodiment of the present disclosure, the first contact electrode CNE1 and the second contact electrode CNE2 may be spaced apart from each other by a specific distance on the second surface UF (or upper surface) of the 2b insulating layer INS2b.

[0283] The 2b insulating layer INS2b may have a trapezoidal cross-section in which its width decreases from the first surface BF (or lower surface) in contact with each of the light-emitting elements LD toward the second surface UF (or upper surface), but the present disclosure is not limited thereto. In an embodiment, as Figure 10 shown, the 2b insulating layer INS2b may have a rectangular cross-section in which the first surface BF (or lower surface) and the second surface UF (or upper surface) have the same width in the first direction DR1.

[0284] The second insulating layer INS2 may be formed on each of the light-emitting elements LD so that the active layer 12 of each of the light-emitting elements LD can be prevented from contacting an external conductive material. The second insulating layer INS2 may cover only a part of the surface of each of the light-emitting elements LD so that opposite ends EP1 and EP2 of each of the light-emitting elements LD can be exposed to the outside.

[0285] Each of the light-emitting elements LD may include a first semiconductor layer 11, an active layer 12, a second semiconductor layer 13, a third semiconductor layer 15, a fourth semiconductor layer 18, and an insulating film 14. For example, as Figures 9 to 11As shown, a first light-emitting element LD1 aligned between the first electrode EL1_1 and the second electrode EL2 may include a light-emitting stack pattern 10 and an insulating film 14 surrounding the outer peripheral surface of the light-emitting stack pattern 10. In the light-emitting stack pattern 10, a first semiconductor layer 11, an active layer 12, a second semiconductor layer 13, a third semiconductor layer 15, and a fourth semiconductor layer 18 are sequentially stacked in the listed order in the longitudinal direction (refer to Figure 1 and Figure 2 “L”) of a first light-emitting element LD1.

[0286] Each of the light-emitting elements LD may be disposed on a first insulating layer INS1 between two adjacent electrodes. For example, each of the first light-emitting elements LD1 may be disposed on the first insulating layer INS1 between the first electrode EL1_1 and the second electrode EL2. Each of the second light-emitting elements LD2 may be disposed on the first insulating layer INS1 between the second electrode EL2 and the first electrode EL1_2.

[0287] The third semiconductor layer 15 included in the light-emitting stack pattern 10 of each of the light-emitting elements LD may include a 3-1 semiconductor layer 16 disposed on the second semiconductor layer 13 and a 3-2 semiconductor layer 17 disposed between the 3-1 semiconductor layer 16 and the fourth semiconductor layer 18.

[0288] Based on a surface 15c (hereinafter referred to as “contact surface”) on which the 3-1 semiconductor layer 16 and the 3-2 semiconductor layer 17 are in contact with each other, both the second semiconductor layer 13 and the 3-1 semiconductor layer 16 disposed under the contact surface 15c may include p-type semiconductor layers doped with p-type dopants, and both the 3-2 semiconductor layer 17 and the fourth semiconductor layer 18 disposed above the contact surface 15c may include n-type semiconductor layers doped with n-type dopants. In an embodiment of the present disclosure, the third semiconductor layer 15 may be a tunnel junction layer including the 3-1 semiconductor layer 16 and the 3-2 semiconductor layer 17 including semiconductor layers of different types.

[0289] In a cross-sectional view, the contact surface 15c may be provided between the midpoint B of the width W of one surface BF (or the lower surface, the first surface) of the second insulating layer INS2b in the first direction DR1 and a point corresponding to one end (one of the two opposite corners where the opposite sides of the second insulating layer INS2b in the longitudinal direction L of each of the light-emitting elements LD contact the one surface BF (or the lower surface) therebetween) in the longitudinal direction L of each of the light-emitting elements LD. For example, in a cross-sectional view, the contact surface 15c may be provided at the first point C corresponding to +40% in the longitudinal direction L of each of the light-emitting elements LD starting from the midpoint B of the width W of one surface BF (or the lower surface) of the second insulating layer INS2b in the first direction DR1. Although in the foregoing embodiment, the contact surface 15c of each light-emitting element LD is provided between the midpoint B of the width W of one surface BF (or the lower surface) of the second insulating layer INS2b in the first direction DR1 and a point corresponding to one end in the longitudinal direction L of the corresponding light-emitting element LD, the present disclosure is not limited thereto. In an embodiment, the contact surface 15c of each of the light-emitting elements LD may be provided at any point in the longitudinal direction L within the range where the corresponding light-emitting element LD overlaps with the second insulating layer INS2b.

[0290] Here, different types of semiconductor layers based on the contact surface 15c may have different thicknesses. Specifically, in the longitudinal direction L of each of the light-emitting elements LD, the thickness d1, which is the sum of the thicknesses of the second semiconductor layer 13 and the 3-1 semiconductor layer 16 provided under the contact surface 15c, may be different from the thickness d2, which is the sum of the thicknesses of the 3-2 semiconductor layer 17 and the fourth semiconductor layer 18 provided above the contact surface 15c. For example, the thickness d2, which is the sum of the thicknesses of the 3-2 semiconductor layer 17 and the fourth semiconductor layer 18, may be thicker (or larger) than the thickness d1, which is the sum of the thicknesses of the second semiconductor layer 13 and the 3-1 semiconductor layer 16.

[0291] As described above, when the contact surface 15c is provided at the first point C in the longitudinal direction L of each of the light-emitting elements LD and the thickness d2 of the n-type semiconductor layer provided above the contact surface 15c is greater than the thickness d1 of the p-type semiconductor layer provided under the contact surface 15c, the active layer 12 of each of the light-emitting elements LD may be provided in the middle (or center) portion of the corresponding light-emitting element LD or adjacent to the middle (or center) portion of the corresponding light-emitting element LD.

[0292] The active layer 12 of each of the light-emitting elements LD may include a first surface 12a and a second surface 12b. The first surface 12a may be in contact with the first semiconductor layer 11 of the corresponding light-emitting element LD. The second surface 12b may be in contact with the second semiconductor layer 13 of the corresponding light-emitting element LD. In an embodiment, in a cross-sectional view, the first surface 12a of the active layer 12 of each of the light-emitting elements LD may be disposed between the midpoint B of the width W of one surface BF (or the lower surface) of the 2b insulating layer INS2b in a first direction DR1 and a point corresponding to the remaining end of one surface BF (or the lower surface) of the 2b insulating layer INS2b in the longitudinal direction L of the corresponding light-emitting element LD (the other of the opposite two corners where the opposite sides of the 2b insulating layer INS2b in the longitudinal direction L of the corresponding light-emitting element LD and one surface BF (or the lower surface) are in contact with each other). For example, in a cross-sectional view, the first surface 12a of the active layer 12 of each of the light-emitting elements LD may be disposed between the midpoint B of the width W of one surface BF (or the lower surface) of the 2b insulating layer INS2b in a first direction DR1 and a second point E corresponding to -40% in the longitudinal direction L of the corresponding light-emitting element LD starting from the midpoint B. In this case, the active layer 12 of each of the light-emitting elements LD may be disposed in the middle (or center) portion of the corresponding light-emitting element LD in the longitudinal direction L of the corresponding light-emitting element LD, or may be disposed adjacent to the middle (or center) portion of the corresponding light-emitting element LD. Although in the foregoing embodiment, the first surface 12a of the active layer 12 of each of the light-emitting elements LD is disposed between the midpoint B of the width W of one surface BF (or the lower surface) of the 2b insulating layer INS2b in a first direction DR1 and a point corresponding to the remaining end of one surface BF (or the lower surface) of the 2b insulating layer INS2b in the longitudinal direction L of the corresponding light-emitting element LD, the present disclosure is not limited thereto. In an embodiment, the first surface 12a of the active layer 12 of each of the light-emitting elements LD may be disposed at any point in the longitudinal direction L within the range where the corresponding light-emitting element LD overlaps with the 2b insulating layer INS2b.

[0293] When forming the second insulating layer INS2, as Figure 11As shown, a part of the insulating film 14 of each of the light-emitting elements LD can be separated such that not only the lower surface 11a (or outer surface) of the first semiconductor layer 11 and the upper surface 18b (or outer surface) of the fourth semiconductor layer 18 can be exposed to the outside, but also a part of the outer peripheral surface of the light-emitting stack pattern 10 can be exposed to the outside. For example, when forming the second insulating layer INS2, a part of the insulating film 14 of each of the light-emitting elements LD can be separated such that a region 11c of the first semiconductor layer 11 of the corresponding light-emitting element LD and a region 18c of the fourth semiconductor layer 18 of the corresponding light-emitting element LD can be exposed to the outside. Here, a region 11c of the first semiconductor layer 11 can be a part of the side surface (or outer peripheral surface) of the first semiconductor layer 11. A region 18c of the fourth semiconductor layer 18 can be a part of the side surface (or outer peripheral surface) of the fourth semiconductor layer 18. In this case, in each of the light-emitting elements LD, the exposed surface area of each of the first semiconductor layer 11 and the fourth semiconductor layer 18 can be increased. When the exposed surface area of the first semiconductor layer 11 is increased, the effective contact surface area between the first semiconductor layer 11 and the second contact electrode CNE2 can be further increased. In addition, when the exposed surface area of the fourth semiconductor layer 18 is increased, the effective contact surface area between the fourth semiconductor layer 18 and the first contact electrode CNE1 can be further increased.

[0294] The increase in the effective contact surface area of each of the light-emitting elements LD can minimize the contact defects of the corresponding light-emitting element LD and reduce the contact resistance of each of the first semiconductor layer 11 and the fourth semiconductor layer 18. Therefore, the characteristics of each of the light-emitting elements LD are enhanced, such that the output efficiency of the light emitted from each of the light-emitting elements LD can be further enhanced.

[0295] As described above, when the active layer 12 is disposed in the middle (or center) portion of each of the light-emitting elements LD in the longitudinal direction L of the corresponding light-emitting element LD or is disposed adjacent to the middle (or center) portion of the corresponding light-emitting element LD, the light emitted from the active layer 12 can travel uniformly (or evenly) toward the opposite ends EP1 and EP2 of the corresponding light-emitting element LD, rather than being biased to one side. Therefore, the intensity of the light emitted from the opposite ends EP1 and EP2 of each of the light-emitting elements LD can be uniform, such that the optical efficiency of each of the light-emitting elements LD can be enhanced.

[0296] When the active layer 12 of each of the light-emitting elements LD is set to be biased to one of the opposite ends EP1 and EP2 instead of being disposed in the middle (or center) portion of the corresponding light-emitting element LD, a part of the insulating film 14 may be separated when the second insulating layer INS2 is formed, such that the active layer 12 of the corresponding light-emitting element LD may be exposed. In this case, the first contact electrode CNE1 and the second contact electrode CNE2 formed by subsequent processes may come into contact with the exposed active layer 12, thereby causing an electrical short circuit. As a result, each of the light-emitting elements LD may not be driven by a forward bias.

[0297] In view of this, in an embodiment of the present disclosure, the active layer 12 of each of the light-emitting elements LD may be disposed in the middle (or center) portion of the corresponding light-emitting element LD in the longitudinal direction L of the corresponding light-emitting element LD, or may be disposed adjacent to the middle (or center) portion of the corresponding light-emitting element LD, such that defects that may occur due to the separation of the insulating film 14 during the manufacturing process can be prevented.

[0298] In addition, in an embodiment of the present disclosure, in the longitudinal direction L of each of the light-emitting elements LD, the first semiconductor layer 11 may be disposed at one of the opposite ends EP1 and EP2 of the corresponding light-emitting element LD, and the fourth semiconductor layer 18 may be disposed at the remaining end of the opposite ends EP1 and EP2 of the light-emitting element LD. In other words, n-type semiconductor layers may be respectively disposed at the opposite ends EP1 and EP2 of each of the light-emitting elements LD in the longitudinal direction L of the corresponding light-emitting element LD, such that the electrical characteristics of the corresponding light-emitting element LD can be enhanced.

[0299] Although various embodiments have been described above, those skilled in the art will understand that various modifications, additions, and substitutions are possible without departing from the scope of the present disclosure.

[0300] Therefore, the embodiments disclosed in this specification are for illustrative purposes only and do not limit the technical scope of the present disclosure. The scope of the present disclosure must be defined by the appended claims.

Claims

1. A display device, the display device comprising: a substrate including a display area including a plurality of pixel areas and a non-display area surrounding at least one side of the display area; and pixels disposed in each of the plurality of pixel areas, wherein each of the pixels includes a first electrode and a second electrode spaced apart from each other on the substrate, a plurality of light-emitting elements electrically connected to each of the first electrode and the second electrode, and an insulating pattern disposed on one surface of each of the plurality of light-emitting elements; each of the plurality of light-emitting elements includes: a first semiconductor layer, an active layer, a second semiconductor layer, a third semiconductor layer, and a fourth semiconductor layer sequentially stacked in one direction; the third semiconductor layer is a tunnel junction layer; the third semiconductor layer includes a 3-1 semiconductor layer directly disposed on the second semiconductor layer and a 3-2 semiconductor layer disposed between the 3-1 semiconductor layer and the fourth semiconductor layer, and the sum of the thicknesses of the fourth semiconductor layer and the 3-2 semiconductor layer is different from the sum of the thicknesses of the second semiconductor layer and the 3-1 semiconductor layer; in a plan view, the insulating pattern overlaps each of the plurality of light-emitting elements between the first electrode and the second electrode; the active layer of each of the plurality of light-emitting elements includes a first surface in contact with the first semiconductor layer and a second surface opposite to the first surface and in contact with the second semiconductor layer; the contact surface between the 3-1 semiconductor layer and the 3-2 semiconductor layer is disposed between a point corresponding to half of the entire width of one surface of the insulating pattern in contact with each of the plurality of light-emitting elements in the one direction and a point corresponding to one end of the one surface, and the first surface of the active layer is disposed between the point corresponding to half of the entire width of the one surface of the insulating pattern and a point corresponding to the other end of the one surface.

2. The display device according to claim 1, wherein: the first semiconductor layer, the fourth semiconductor layer, and the 3-2 semiconductor layer include n-type semiconductor layers doped with an n-type dopant, and the second semiconductor layer and the 3-1 semiconductor layer include p-type semiconductor layers doped with a p-type dopant.

3. The display device according to claim 2, wherein, The sum of the thicknesses of the 3-2 semiconductor layer and the fourth semiconductor layer sequentially stacked in the one direction is greater than the sum of the thicknesses of the second semiconductor layer and the 3-1 semiconductor layer sequentially stacked in the one direction.

4. The display device according to claim 3, wherein the 3-1 semiconductor layer is doped with a p-type dopant having a concentration higher than the concentration of the p-type dopant in the second semiconductor layer, and the 3-2 semiconductor layer is doped with an n-type dopant having a concentration higher than the concentration of the n-type dopant in the first semiconductor layer and the fourth semiconductor layer.

5. The display device according to claim 3, wherein, The distance from the contact surface to the outer surface of the fourth semiconductor layer in the one direction is less than the distance from the contact surface to the outer surface of the first semiconductor layer.

6. The display device according to claim 5, wherein, Based on points corresponding to half of the entire length of each of the plurality of light-emitting elements in the one direction, the contact surface is provided closer to the outer surface of the fourth semiconductor layer than to the outer surface of the first semiconductor layer.

7. The display device according to claim 5, wherein, The pixel further includes: Bank patterns provided between the substrate and the first electrode and between the substrate and the second electrode; A first contact electrode connecting each of the plurality of light-emitting elements to the first electrode; and A second contact electrode connecting each of the plurality of light-emitting elements to the second electrode.

8. The display device according to claim 7, wherein, each of the plurality of light-emitting elements includes: an insulating layer surrounding each of the outer peripheral surfaces of the first semiconductor layer, the active layer, the second semiconductor layer, the third semiconductor layer, and the fourth semiconductor layer sequentially stacked in the one direction, the outer surface of the first semiconductor layer is not covered by the insulating layer, and a part of the outer peripheral surface of the first semiconductor layer is not covered by the insulating layer, and the outer surface of the fourth semiconductor layer is not covered by the insulating layer, and a part of the outer peripheral surface of the fourth semiconductor is not covered by the insulating layer.

9. The display device according to claim 8, wherein, the first contact electrode is in direct contact with the part and the outer surface of the outer peripheral surface of the first semiconductor layer, and the second contact electrode is in direct contact with the part and the outer surface of the outer peripheral surface of the fourth semiconductor layer.

10. A display device, the display device includes: a substrate, on which a plurality of pixels are provided, wherein, each of the plurality of pixels includes: a plurality of light-emitting elements provided on the substrate; a first electrode and a second electrode, the first electrode being electrically connected to one end of each of the plurality of light-emitting elements, the second electrode being electrically connected to the remaining end of each of the plurality of light-emitting elements, the first electrode and the second electrode being spaced apart from each other; and an insulating pattern provided on one surface of each of the plurality of light-emitting elements, each of the plurality of light-emitting elements includes: a first semiconductor layer, an active layer, a second semiconductor layer, a third semiconductor layer, and a fourth semiconductor layer stacked in one direction, the third semiconductor layer is a tunnel junction layer and includes a 3-1 semiconductor layer directly provided on the second semiconductor layer and a 3-2 semiconductor layer provided between the 3-1 semiconductor layer and the fourth semiconductor layer, the same type of semiconductor layers are provided at opposite ends of each of the plurality of light-emitting elements, and the distance from the contact surface between the 3-1 semiconductor layer and the 3-2 semiconductor layer to the outer surface of the fourth semiconductor layer in the one direction is less than the distance from the contact surface to the outer surface of the first semiconductor layer, in a plan view, the insulating pattern overlaps each of the plurality of light-emitting elements between the first electrode and the second electrode, The active layer of each of the plurality of light-emitting elements includes a first surface in contact with the first semiconductor layer and a second surface opposite to the first surface and in contact with the second semiconductor layer. The contact surface between the 3-1 semiconductor layer and the 3-2 semiconductor layer is provided between a point corresponding to half of the entire width of the one surface of the insulating pattern in contact with each of the plurality of light-emitting elements in the one direction and a point corresponding to one end of the one surface, and The first surface of the active layer is provided between the point corresponding to half of the entire width of the one surface of the insulating pattern and a point corresponding to the other end of the one surface.

11. The display device according to claim 10, wherein, The first semiconductor layer is provided at one of the opposite ends of each of the plurality of light-emitting elements, and the fourth semiconductor layer is provided at the remaining end of the opposite ends of each of the plurality of light-emitting elements, The first semiconductor layer and the fourth semiconductor layer include n-type semiconductor layers doped with an n-type dopant.

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