Multiplexing control device with relay chip and relay chip thereof

Abstract

A relay chip includes a plurality of front-stage receiving pin groups, a plurality of front-stage transmitting pin groups, a plurality of back-stage transmitting pin groups, a plurality of back-stage receiving pin groups, and a plurality of selectors. The front-stage transmitting pin groups and the front-stage receiving pin groups are arranged in an alternating manner, and the back-stage receiving pin groups and the back-stage transmitting pin groups are arranged in an alternating manner. The number of the back-stage transmitting pin groups is an integer multiple of the number of the front-stage receiving pin groups, and the number of the back-stage receiving pin groups is the integer multiple of the number of the front-stage transmitting pin groups. Each selector is connected to the integer multiple of one of the front-stage receiving pin groups and the back-stage transmitting pin groups, or connected to the integer multiple of one of the front-stage transmitting pin groups and the back-stage receiving pin groups. The present application also relates to a multiplexing control device having the relay chip.

Description

Technical Field

[0001] This invention relates to a multiplexing control device, and more particularly to a multiplexing control device with a relay chip and the relay chip thereof. Background Technology

[0002] In the field of communications, signal strength gradually decreases with transmission. Therefore, a repeater is placed between the start and end points of signal transmission to amplify the input signal and extend the transmission distance. Repeaters are typically implemented using repeater chips. Common repeater chips can receive signals from the transmit pin (Tx) of a front-end device (such as a processor) and send them to a back-end device (such as PCIe), or receive signals from a back-end device and send them to the receive pin (Rx) of a front-end device. In recent years, the pace of PCIe version advancement has been much faster than before the release of version 4.0, and the transmission rate has increased accordingly. Common repeater chips no longer offer a significant advantage in transmission speed, and if placed between front-end and back-end devices for signal communication, they can generate excessive noise. Therefore, repeater chip manufacturers must also develop repeater chips with faster transmission rates.

[0003] In motherboards with repeater chips, the pins of processors, such as those manufactured by Intel, are arranged in an alternating Tx and Rx configuration. To connect to common repeater chips, the motherboard's wiring layout involves multiple Tx and Rx lines partially overlapping in the processor-to-repeater chip section. These lines are then grouped together according to the repeater chip's pin configuration before being connected to the repeater chip. However, this structure introduces uncertainty and difficulty into the wiring design, potentially requiring multiple layer changes (e.g., between upper and lower circuit board layers). Furthermore, transmission lines with the same signal direction but less than a certain distance apart are prone to causing greater far-end crosstalk (FEXT), subjecting each transmission line to more severe noise interference and ultimately affecting transmission quality. Summary of the Invention

[0004] In view of the above, the present invention provides a relay chip that meets the above requirements, comprising: a plurality of front-end receive pin groups for receiving a set of front-end signals from a front-end device; a plurality of front-end transmit pin groups for transmitting a set of back-end signals to the front-end device, wherein the front-end transmit pin groups and the front-end receive pin groups are arranged alternately; a plurality of back-end transmit pin groups, wherein the number of back-end transmit pin groups is an integer multiple of the number of front-end receive pin groups, and a portion of the back-end transmit pin groups is used to transmit the set of front-end signals to one of the plurality of back-end devices; and a plurality of back-end receive pin groups, wherein the number of back-end receive pin groups is an integer multiple of the number of front-end transmit pin groups. The number of transmit pin groups is an integer multiple of the number of transmit pin groups, and a portion of the subsequent receive pin groups is used to receive the subsequent signals from one of the subsequent devices, wherein the subsequent receive pin groups and the subsequent transmit pin groups are arranged alternately; and a plurality of selectors, each selector being connected to an integer multiple of one of the preceding receive pin groups and the subsequent transmit pin groups, or connected to an integer multiple of one of the preceding transmit pin groups and the subsequent receive pin groups, wherein each of the preceding receive pin groups, the preceding transmit pin groups, the subsequent receive pin groups, and the subsequent transmit pin groups corresponds to any one of the selectors.

[0005] The present invention further provides a multiplexing control device with a relay chip, comprising: a processor having a plurality of processing transmit pin groups and a plurality of processing receive pin groups, the processing transmit pin groups and the processing receive pin groups being arranged alternately; a first connection terminal having a plurality of first-level transmit pin groups and a plurality of first-level receive pin groups, the first-level transmit pin groups and the first-level receive pin groups being arranged alternately; a second connection terminal having a plurality of second-level transmit pin groups and a plurality of second-level receive pin groups, the second-level transmit pin groups and the second-level receive pin groups being arranged alternately; and a relay chip, wherein the... The front-end device is the processor, and the back-end device includes the first connection terminal and the second connection terminal. The processor transmits the set of front-end signals to the front-end receiving pin group through the processing transmit pin group, and receives the set of back-end signals from the front-end transmit pin group through the processing receive pin group. The relay chip transmits the set of front-end signals to the first-stage receiving pin group or the second-stage receiving pin group through a portion of the back-end transmit pin group, and receives the set of back-end signals from the first-stage transmitting pin group or the second-stage transmitting pin group through a portion of the back-end receiving pin group.

[0006] In summary, the relay chip of the present invention has alternating pin groups, which significantly reduces the far-end crosstalk amplitude caused by adjacent transmission lines of the same type (same transmission direction) when the relay chip is installed in the multiplexing control device of the present invention, thereby simplifying the wiring design complexity or the number of layers. Furthermore, since a single relay chip of the present invention has both a front-end transmit / receive pin group and a back-end transmit / receive pin group, only one relay chip of the present invention can be installed in a multiplexing control device with a relay chip, or multiple chips can be installed as needed, further enhancing the flexibility of wiring configuration.

[0007] The foregoing description of the contents of this disclosure and the following description of the embodiments are intended to demonstrate and explain the spirit and principles of the present invention, and to provide a further explanation of the claims of the present invention. Attached Figure Description

[0008] Figure 1 This is a schematic diagram of a relay chip with an implementation architecture according to the present invention during the research and development process.

[0009] Figure 2 To provide an implementation architecture with the present invention during the research and development process. Figure 1 A schematic diagram of a multiplexing control device with two relay chips.

[0010] Figure 3 This is a schematic diagram of a relay chip according to an embodiment of the present invention.

[0011] Figure 4 According to an embodiment of the present invention, having Figure 3 A schematic diagram of a multiplexing control device for a relay chip.

[0012] Figure 5 This is a wiring diagram of a multiplexing control device with a relay chip according to an embodiment of the present invention.

[0013] Figure 6 This is another wiring diagram of a multiplexing control device with a relay chip according to an embodiment of the present invention.

[0014] Figure 7 This is a schematic diagram comparing the remote crosstalk generated by a multiplexing control device using an interleaved relay chip according to an embodiment of the present invention with that generated by a multiplexing control device using a non-interleaved relay chip according to the prior art.

[0015] The reference numerals in the attached figures are explained as follows:

[0016] 11 Transmitter Relay Chip

[0017] 12 receiver relay chips

[0018] 13 relay chips

[0019] 131 First Relay Chip

[0020] 132 Second Relay Chip

[0021] 2 processors

[0022] 3 First connection end

[0023] 4 Second connection end

[0024] TX transmission line

[0025] RX receiver line

[0026] Pt11 First Transmit Pin Group

[0027] Pr11 First Receive Pin Group

[0028] Pt12 Second Transmit Pin Group

[0029] Pr12 Second Receive Pin Group

[0030] PTF13 preamplifier transmit pin group

[0031] Prf13 preamplifier receiver pin group

[0032] Ptr13 Post-Stage Transmit Pin Group

[0033] Prr13 Post-Stage Receive Pin Group

[0034] PTF131 First Preamp Transmit Pin Group

[0035] Prf131 First Pre-amplifier Receive Pin Group

[0036] Ptr131 First Post-Stage Transmit Pin Group

[0037] Prr131 First Rear Stage Receive Pin Group

[0038] PTF132 Second Preamp Transmit Pin Group

[0039] PRF132 Second Pre-amplifier Receive Pin Group

[0040] Ptr132 Second Post-Stage Transmit Pin Group

[0041] Prr132 Second Rear Stage Receive Pin Group

[0042] Pt2 Processing Transmit Pin Group

[0043] Pr2 processes the receive pin group

[0044] Pt3 primary transmit pin group

[0045] Pr3 primary receiver pin group

[0046] Pt4 Secondary Transmit Pin Group

[0047] Pr4 Secondary Receive Pin Group Detailed Implementation

[0048] The following detailed description of the features and advantages of the present invention in the embodiments is sufficient to enable anyone skilled in the art to understand the technical content of the present invention and implement it accordingly. Based on the disclosure, claims, and drawings in this specification, anyone skilled in the art can easily understand the related objectives and advantages of the present invention. The following embodiments are further detailed in illustrating the points of view of the present invention, but are not intended to limit the scope of the present invention in any way.

[0049] Please refer to Figure 1 This is a schematic diagram of a relay chip implementation architecture according to the present invention during the research and development process. The relay chip is typically arranged in a wiring structure connecting the processor and the external connection standard (PCIe), amplifying the input signal to extend the signal transmission distance. The relay chip can be, for example... Figure 1 It contains one of two relay chips, namely the left transmitting relay chip 11 or the right receiving relay chip 12. Figure 1 The black transmit line (TX) and gray receive line (RX) in the diagram are schematic representations of surrounding components connected to the relay chip. Transmission or reception is defined from the perspective of the upstream device (e.g., a processor) to which the relay chips 11 and 12 are connected. For example, the transmit line represents transmission from the upstream device and reception from the relay chip, while the receive line represents transmission from the relay chip and reception from the upstream device. The following description paragraphs and diagrams define the TX transmit line and RX receive line based on this principle.

[0050] One end of the transmitting relay chip 11 (e.g., the left end in the figure) may have multiple first receiving pin groups Pr11 for receiving multiple signals, such as those sent by a processor, and the other end (e.g., the right end in the figure) may have multiple first transmitting pin groups Pt11 for transmitting the signals. The number of first transmitting pin groups Pt11 may be an integer multiple of 1 greater than the number of first receiving pin groups Pr11. Figure 1In the illustrated transmit relay chip 11, the number of first transmit pin groups Pt11 is, for example, twice the number of first receive pin groups Pr11, and the first receive pin groups Pr11 and the first transmit pin groups Pt11 correspond to each other in a 1-to-2 manner. The transmit relay chip 11 further has multiple selectors (not shown) configured as multiple demultiplexers (DEMUX), each corresponding to one first receive pin group Pr11 and two first transmit pin groups Pt11. After receiving a signal from the first receive pin group Pr11, each demultiplexer selects one of the two first transmit pin groups Pt11 and transmits the signal to it at each preset unit time. It should be noted that the present invention does not actually limit the position of the first transmit pin groups Pt11 and the first receive pin groups Pr11; in practice, they can each be arranged at either end of the transmit relay chip 11 according to the wiring design.

[0051] One end of the receiving relay chip 12 (e.g., the right end in the figure) may have multiple second receive pin groups Pr12 for receiving signals, such as those transmitted via PCIe, and the other end (e.g., the left end in the figure) may have multiple second transmit pin groups Pt12 for transmitting the signals. The number of second receive pin groups Pr12 may be an integer multiple of 1 greater than the number of second transmit pin groups Pt12. Figure 1 In the illustrated receiver relay chip 12, the number of second receive pin groups Pr12 is twice that of second transmit pin groups Pt12, and the second receive pin groups Pr12 and the second transmit pin groups Pt12 correspond to each other in a 2-to-1 manner. The receiver relay chip 12 further includes multiple selectors (not shown) composed of multiple multiplexers (MUX), each corresponding to two second receive pin groups Pr12 and one second transmit pin group Pt12. Each multiplexer, after receiving two corresponding signals from the second receive pin groups Pr12, selects one signal and transmits it through the second transmit pin group Pt12 at the other end (e.g., the left end in the figure). It should be noted that the present invention does not actually limit the position of the second transmit pin groups Pt12 and the second receive pin groups Pr12; in practice, they can be arranged at either end of the receiver relay chip 12 according to the wiring design.

[0052] Furthermore, it should be noted that the term "pin group" rather than simply "pin" is used in the preceding paragraph and the following specification because, in practice, both the TX and RX lines in this related field transmit or receive differential signals. This means that each line requires two single-ended signal lines to transmit / receive single-frequency signals with the same voltage amplitude and one positive and one negative phase, respectively. One end of each of these two signal lines is connected to a pin. Therefore, for the practical repeater chips 11, 12, and the components described below, a complete implementation of the TX / RX terminals requires two pins each. Thus, a pin group can have two pins.

[0053] Please refer to more information. Figure 2 This is what has Figure 1 A schematic diagram of a multiplexing control device for two relay chips. Note that, for ease of description, the diagrams in this manual only show a single black / gray line representing a signal line connecting a set of pins at each end; however, in practice, this is not the only variation. Figure 2 The multiplexing control device includes: a transmitting relay chip 11, a receiving relay chip 12, a processor 2, a first connection terminal 3, and a second connection terminal 4. The processor 2 has multiple processing transmitting pin groups Pt2 and multiple processing receiving pin groups Pr2, which are arranged alternately. Here, signals transmitted from an upstream device (e.g., processor 2) to a downstream device (e.g., the first and second connection terminals 3 and 4) are defined as pre-stage signals, and signals transmitted from a downstream device to an upstream device are defined as post-stage signals. The processor 2 transmits all pre-stage signals to the first receiving pin group Pr11 via the processing transmitting pin group Pt2, and receives multiple post-stage signals from the second transmitting pin group Pt2 via the processing receiving pin group Pr2.

[0054] In one embodiment of the present invention, the first connection terminal 3 and the second connection terminal 4 can be PCIe. Figure 2 In an existing multiplexing control device, for example, a portion of the first transmitting pin group Pt11 can transmit the preceding stage signal to the first connection terminal 3, and another portion can transmit the preceding stage signal to the second connection terminal 4. Furthermore, a portion of the second receiving pin group Pr2 can receive the following stage signal from the first connection terminal 3, and another portion can receive the following stage signal from the second connection terminal 4. However, considering... Figure 2 In this structure, when the processor 2 wants to transmit and receive signals to downstream devices such as the first connection terminal 3 and the second connection terminal 4, at least one transmitting relay chip 11, which is only responsible for receiving and transmitting signals from the previous stage, and at least one receiving relay chip 12, which is only responsible for receiving and transmitting signals from the downstream stage, must be installed in the middle. Furthermore, to avoid large far-end crosstalk (FEXT) caused by similar signal transmission lines being too close together, the circuits are usually layered when implementing this structure on the printed circuit board, which may cause some difficulties in wiring design.

[0055] Therefore, this invention proposes an interleave-type relay chip. Please refer to [reference needed]. Figure 3 This is a schematic diagram of a relay chip 13 according to an embodiment of the present invention. Figure 3The relay chip 13 may include multiple front-end receive pin groups Prf13 and multiple front-end transmit pin groups Ptf13 disposed at one end (e.g., the left end in the figure), with the front-end transmit pin groups Ptf13 and the front-end receive pin groups Prf13 arranged alternately. The front-end receive pin groups Prf13 can be used to receive a set of front-end signals from a front-end device (e.g., a processor), while the front-end transmit pin groups Ptf13 can be used to transmit a set of back-end signals to the front-end device. The relay chip 13 may also include multiple back-end transmit pin groups Ptr13 and multiple back-end receive pin groups Prr13 disposed at the other end (e.g., the right end in the figure), with the back-end receive pin groups Prr13 and the back-end transmit pin groups Ptr13 arranged alternately. The number of subsequent stage transmit pin groups Ptr13 is an integer multiple of the number of preceding stage receive pin groups Prf13, and the number of subsequent stage receive pin groups Prr13 is an integer multiple of the number of preceding stage transmit pin groups Ptf13. Figure 3 In this configuration, the integer can be 2, and the front-end receive pin group Prf13 and the rear-end transmit pin group Ptr13 correspond to each other in a 1-to-2 manner, while the front-end transmit pin group Ptf13 and the rear-end receive pin group Prr13 also correspond to each other in a 1-to-2 manner. The relay chip 13 also includes multiple selectors (e.g., Figure 3 The two dashed lines in relay chip 13, Figure 3 (Only two sets are shown here, although in practice more selectors may be included.) Each selector may have multiple demultiplexers (shown in black) and multiple multiplexers (shown in gray), and the multiplexers and demultiplexers are arranged alternately. Specifically, the aforementioned selector can be connected to an integer multiple (e.g., two) of one of the pre-stage receive pin groups Prf13 and the subsequent stage transmit pin group Ptr13, and this selector may be, for example, a demultiplexer; alternatively, the aforementioned selector can also be connected to an integer multiple (e.g., two) of one of the pre-stage transmit pin groups Ptf13 and the subsequent stage receive pin group Prr13, and this selector may be, for example, a multiplexer. Furthermore, each of the pre-stage receive pin group Prf13, the pre-stage transmit pin group Ptf13, the subsequent stage receive pin group Prr13, and the subsequent stage transmit pin group Ptr13 corresponds to any one of the selectors. In other words, each pin group will only correspond to one selector; a single pin group will not correspond to multiple selectors simultaneously. Figure 3As can be seen from the structure of the relay chip 13, at least one relay chip with this alternating transmit / receive structure is required to enable signal transmission between the processor and downstream devices. Furthermore, since signal transmission lines of the same type (e.g., TX lines) are separated by different types of signal transmission lines (e.g., RX lines), far-end crosstalk is significantly reduced. It should be noted that the invention does not actually limit the position of each pin group; in practice, they can be placed at either end of the relay chip 13 according to the wiring design.

[0056] In addition, as Figure 1 The term "pin group" as defined in the previous paragraph and throughout the specification refers to the fact that each of the TX or RX lines requires two single-ended signal lines to transmit / receive single-frequency signals of the same voltage amplitude with different phases. Therefore, the defined "pin group" can practically have two pins. However, this is not intended to limit the invention. The invention does not limit the number of pins in the pin group. Any relay chip with a structure in which the transmit pin group and receive pin group are arranged alternately (and / or with a structure in which the demultiplexer and multiplexer are arranged alternately) can be considered to have the features of the invention and conform to the spirit of the invention.

[0057] Please refer to more information. Figure 4 This is what has Figure 3 A schematic diagram of a multiplexing control device with a relay chip 13 structure. It can be noted that a single relay chip 13 can complete the signal transmission between the processor and downstream devices; however, for ease of use, this is not shown here. Figure 2 Structural comparison, in Figure 4 The multiplexing control device includes a first relay chip 131 and a second relay chip 132 with a relay chip 13 structure. The first relay chip 131 and the second relay chip 132 may have the same structure, and the component names therein may be appropriately prefixed with "first" or "second".

[0058] Figure 4 The multiplexing control device includes a processor 2, a first relay chip 131, a second relay chip 132, a first connection terminal 3, and a second connection terminal 4. The structures of the processor 2, the first connection terminal 3, and the second connection terminal 4 can all be... Figure 2 The same applies, so I won't elaborate further. (And) Figure 2The structural difference lies in the fact that, since both relay chips 131 and 132 can transmit / receive both pre-stage and post-stage signals, the signal transmission sequence can be roughly as follows: the processor 2 can send the pre-stage signal to the first pre-stage receiving pin group Prf131 of the first relay chip 131 and the second pre-stage transmitting pin group Prf132 of the second relay chip 132 via the processing transmitting pin group Pt2. Then, the pre-stage signal can be selectively sent from the first post-stage transmitting pin group Ptr131 of the first relay chip 131 or the second post-stage transmitting pin group Ptr132 of the second relay chip 132 to the first pre-stage receiving pin group Pr3 of the first connection terminal 3 or the second pre-stage receiving pin group Pr4 of the second connection terminal 4 via the first post-stage transmitting pin group Ptr131 of the first relay chip 131 or the second post-stage transmitting pin group Ptr132 of the second relay chip 132. In addition, the two connection terminals 3 and 4 can send the subsequent signal to the first subsequent receiving pin group Prr131 of the first relay chip 131 and the second subsequent receiving pin group Prr132 of the second relay chip 132 through the first primary transmitting pin group Pt3 and the second secondary transmitting pin group Pt4, respectively. Then the subsequent signal can be sent to the processing receiving pin group Pr2 of the processor 2 through the first primary transmitting pin group Ptf131 of the first relay chip 131 and the second primary transmitting pin group Ptf132 of the second relay chip 132.

[0059] Therefore, the alternating arrangement structure of the multiplexing control device with relay chips in one embodiment of the present invention eliminates the need for layering in practical wiring design to centrally arrange similar signal lines between the processor 2 and the relay chip, or significantly reduces the difficulty of layering. Furthermore, the wiring between the relay chip and the connection terminals 3 and 4 is also relatively simple. If layering of the wiring between the relay chip and the connection terminals is desired to further reduce far-end crosstalk, the design difficulty is also simpler than in existing technologies.

[0060] Please refer to Figure 5 and Figure 6 This is a two-wiring diagram of a multiplexing control device with a relay chip according to an embodiment of the present invention. The approximate arrangement of the wiring diagram for implementing the present invention is illustrated here by way of example. Figure 5 This is the top layer of the wiring structure, and Figure 6 This is the bottom layer of the wiring structure. For ease of description and to emphasize the features to be highlighted in this invention, only the wiring structure of the processor 2 and the two relay chips 131 and 132 is shown here. This layering is due to the wiring design and may not be necessary in practice. Figure 5 The concentric circles in the diagram are drawn to represent screw holes and are not the focus of this invention. Figure 5On processor 2, a set of processing transmit pins (shown as black blocks) consists of two pins, each connected to a thin black line; these two thin black lines can be considered as a transmit line (TX). Similarly, a set of processing receive pins (shown as gray blocks) also consists of two pins, each connected to a thin gray line; these two thin gray lines can be considered as a receive line (RX). Figure 5 The wiring structure directly shows that the processor 2's processing transmit pin group and processing receive pin group are arranged alternately, and the extended TX line and RX line are also arranged alternately.

[0061] Figure 6 This illustrates the connection of the TX and RX lines to two repeater chips 131 and 132. The TX line, consisting of two thin black lines, and the RX line, consisting of two thin gray lines, are respectively connected to two pins (shown as black blocks) in the front-end receive pin group and two pins (shown as gray blocks) in the front-end transmit pin group of the two repeater chips 131 and 132, and the front-end receive pin group and the front-end transmit pin group of each repeater chip are arranged alternately.

[0062] also, Figure 5 , Figure 6 This illustration depicts a scenario with two relay chips 131 and 132. In practice, depending on the wiring design, there may be as few as one, as many as four, six, etc., relay chips. This invention does not limit the number of relay chips or the number of pin groups that the relay chips have.

[0063] Please refer to Figure 7 This is a comparative schematic diagram showing the far-end crosstalk (FEXT) generated by a multiplexing control device implementing an interleaved repeater chip according to an embodiment of the present invention and a multiplexing control device implementing a non-interleaved repeater chip according to the prior art. Here, the repeater chip of the prior art is defined as "non-interleaved," and the repeater chip of the present invention is defined as "interleaved." This figure shows the amplitude (in decibels (dB)) of the far-end crosstalk (FEXT) induced by the signal line at different signal frequencies (in GHz) by the applicant through experiments, recording the FEXT amplitude measured in signals from 0 Hz to 60 GHz using both existing non-interleaved repeater chips and interleaved repeater chip multiplexing control devices according to an embodiment of the present invention. As can be seen from the figure, from 0 Hz to 60 GHz, the amplitude of FEXT measured in signal verification using the interleaved repeater chip multiplexing structure device according to an embodiment of the present invention is smaller than the amplitude of FEXT measured in signal verification using the non-interleaved repeater chip multiplexing structure device according to the prior art.

[0064] In summary, the relay chip of the present invention has alternating pin groups, which significantly reduces the far-end crosstalk amplitude caused by adjacent transmission lines of the same type (same transmission direction) when the relay chip is installed in the multiplexing control device of the present invention, thereby simplifying the wiring design complexity or the number of layers. Furthermore, since a single relay chip of the present invention has both a front-end transmit / receive pin group and a back-end transmit / receive pin group, only one relay chip of the present invention can be installed in a multiplexing control device with a relay chip, or multiple chips can be installed as needed, further enhancing the flexibility of wiring configuration.

[0065] While the present invention has been disclosed above with reference to the foregoing embodiments, it is not intended to limit the invention. Any modifications and refinements made without departing from the spirit and scope of the invention are within the scope of patent protection of the present invention. For a description of the scope of protection defined in the present invention, please refer to the appended claims.

Claims

1. A relay chip, comprising: Multiple front-end receive pin groups are used to receive a set of front-end signals from a front-end device; Multiple front-end transmit pin groups are used to transmit a set of back-end signals to the front-end device, and the front-end transmit pin groups and the front-end receive pin groups are arranged alternately. Multiple downstream transmit pin groups, the number of which is an integer multiple of the number of upstream receive pin groups, and a portion of the downstream transmit pin groups is used to transmit the upstream signal to one of the multiple downstream devices; Multiple downstream receive pin groups, the number of which is an integer multiple of the number of upstream transmit pin groups, and a portion of each downstream receive pin group is used to receive downstream signals from one of the downstream devices, wherein the downstream receive pin groups and the downstream transmit pin groups are arranged alternately; and Multiple selectors, each selector being an integer multiple of the number of pins connected to one of the pre-stage receive pin groups and the subsequent transmit pin groups, or an integer multiple of the number of pins connected to one of the pre-stage transmit pin groups and the subsequent receive pin groups. Each of the pre-stage receive pin group, the pre-stage transmit pin group, the post-stage receive pin group, and the post-stage transmit pin group corresponds to any one of the selectors.

2. The relay chip as described in claim 1, wherein, The selector includes multiple multiplexers and multiple demultiplexers, and the multiplexers and demultiplexers are arranged alternately.

3. The relay chip as described in claim 1, wherein, Each of the aforementioned pre-stage transmit pin group, each of the aforementioned pre-stage receive pin group, each of the aforementioned post-stage transmit pin group, and each of the aforementioned post-stage receive pin group each has two pins.

4. A multiplexing control device with a relay chip, comprising: A processor has multiple processing transmit pin groups and multiple processing receive pin groups, wherein the processing transmit pin groups and the processing receive pin groups are arranged alternately. A first connection terminal has multiple first-stage transmitting pin groups and multiple first-stage receiving pin groups, wherein the first-stage transmitting pin groups and the first-stage receiving pin groups are arranged alternately; A second connection terminal has multiple secondary-stage transmitting pin groups and multiple secondary-stage receiving pin groups, wherein the secondary-stage transmitting pin groups and the secondary-stage receiving pin groups are arranged alternately; and A relay chip as described in claim 1, wherein the front-end device is the processor, and the back-end device includes the first connection terminal and the second connection terminal. The processor transmits the group of pre-stage signals to the pre-stage receiving pin group via the processing transmit pin group, and receives the group of post-stage signals from the pre-stage transmit pin group via the processing receive pin group. The relay chip transmits the group of pre-stage signals to the first-stage receiving pin group or the second-stage receiving pin group through a portion of the post-stage transmitting pin group, and receives the group of post-stage signals from the first-stage transmitting pin group or the second-stage transmitting pin group through a portion of the post-stage receiving pin group.

5. The multiplexing control device with a relay chip as described in claim 4, wherein, Each of the following pin groups—the processing transmit pin group, the processing receive pin group, the pre-stage transmit pin group, the pre-stage receive pin group, the post-stage transmit pin group, the post-stage receive pin group, the first-stage transmit pin group, the first-stage receive pin group, the second-stage transmit pin group, and the second-stage receive pin group—has two pins.

6. The multiplexing control device with a relay chip as described in claim 4, wherein, The processing transmit pin group is defined as a first processing transmit pin group, and the processing receive pin group is defined as a first processing receive pin group. The relay chip is defined as a first relay chip, the front-end receive pin group is defined as a first front-end receive pin group, the front-end transmit pin group is defined as a first front-end transmit pin group, the rear-end transmit pin group is defined as a first rear-end transmit pin group, and the rear-end receive pin group is defined as a first rear-end receive pin group. The multiplexing control device with a relay chip further includes a second relay chip, having the structure of the relay chip as described in claim 1, and the second relay chip having, corresponding to the first relay chip, a plurality of second front-end receive pin groups, a plurality of second front-end transmit pin groups, a plurality of second back-end transmit pin groups, and a plurality of second back-end receive pin groups. The processor further includes multiple second processing transmit pin groups and multiple second processing receive pin groups, which are arranged alternately. The processor transmits another set of pre-stage signals to the second pre-stage receiving pin group via the second processing transmit pin group, and receives another set of post-stage signals from the second pre-stage transmit pin group via the second processing receive pin group. The second relay chip transmits another set of pre-stage signals to the first stage receiving pin group or the second stage receiving pin group through a portion of the second stage transmitting pin group, and receives the other set of pre-stage signals from the first stage transmitting pin group or the second stage transmitting pin group through a portion of the second stage receiving pin group.

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