Pixel circuit and display panel

Abstract

The present application discloses a pixel circuit and a display panel. The pixel circuit includes a driving transistor, a first light-emitting control transistor and a clamping unit. The control end of the clamping unit is connected to the gate of the driving transistor. When the gate potential of the driving transistor changes, the clamping unit can reduce the resistance between the first node and the second node, so that the gate potential of the driving transistor and the source potential or the drain potential of the driving transistor change in the same direction, thereby maintaining the potential difference between the gate-drain or the gate-source of the driving transistor, improving the stability of the light-emitting current in the pixel circuit, and reducing or eliminating the phenomenon of excessive brightness changes within a frame.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a pixel circuit and a display panel. Background Art

[0002] With the continuous innovation and improvement of display technology, pixel circuit solutions have become more diversified, and customers' demands for display quality have become higher and higher. Flicker is an important indicator in the evaluation. The main reason for Flicker is the change in brightness. Among them, excessive brightness change within a frame is an important cause of Flicker. Summary of the invention

[0003] The present application provides a pixel circuit and a display panel to alleviate the technical problem of excessive brightness variation within a frame.

[0004] In a first aspect, the present application provides a pixel circuit, which includes a driving transistor, a first light-emitting control transistor and a clamping unit, wherein one of the source / drain of the first light-emitting control transistor is connected to a positive power line, the other of the source / drain of the first light-emitting control transistor is connected to one of the source / drain of the driving transistor, and the gate of the first light-emitting control transistor is connected to a first light-emitting control line; a control end of the clamping unit is connected to the gate of the driving transistor, one end of the clamping unit is connected to a first node, and the other end of the clamping unit is connected to a second node, for reducing the resistance between the first node and the second node according to the gate potential of the driving transistor.

[0005] In some embodiments, the first node is a connection point between the positive power line and one of the source / drain of the driving transistor; the second node is another connection point between the positive power line and one of the source / drain of the driving transistor.

[0006] In some of the embodiments, the first node is a connection point between the other of the source / drain of the first light-emitting control transistor and one of the source / drain of the driving transistor; the second node is another connection point between the other of the source / drain of the first light-emitting control transistor and one of the source / drain of the driving transistor, or the second node is a connection point between the positive power line and one of the source / drain of the first light-emitting control transistor.

[0007] In some of the embodiments, the clamping unit includes a clamping transistor, a gate of the clamping transistor is connected to the gate of the driving transistor, one of the source / drain of the clamping transistor is connected to the first node, and the other of the source / drain of the clamping transistor is connected to the second node; the channel type of the clamping transistor is different from the communication type of the driving transistor.

[0008] In some embodiments, the clamp transistor is one of an N-channel thin film transistor and a P-channel thin film transistor, and the driving transistor is the other of the N-channel thin film transistor and the P-channel thin film transistor.

[0009] In some embodiments, the pixel circuit also includes a second light-emitting control transistor and a parallel unit, one of the source / drain of the second light-emitting control transistor is connected to the other of the source / drain of the driving transistor, the gate of the second light-emitting control transistor is connected to a second light-emitting control line, and the second light-emitting control line is the same as or different from the first light-emitting control line; the parallel unit is connected in parallel with the second light-emitting control transistor.

[0010] In some of the embodiments, one end of the parallel unit is connected to one of the source / drain of the second light-emitting control transistor, the other end of the parallel unit is connected to the other of the source / drain of the second light-emitting control transistor, and the control end of the parallel unit is connected to the second light-emitting control line.

[0011] In some of the embodiments, the parallel unit includes a parallel transistor, one of the source / drain of the parallel transistor is connected to one of the source / drain of the second light emission control transistor, the other of the source / drain of the parallel transistor is connected to the other of the source / drain of the second light emission control transistor, and the gate of the parallel transistor is connected to the gate of the second light emission control transistor.

[0012] In some implementations, the operation process of the pixel circuit in one frame includes an initialization phase, a writing phase and a light emitting phase which are performed successively, and the clamping unit operates in the writing phase and / or the light emitting phase.

[0013] In a second aspect, the present application provides a display panel, which includes a plurality of pixel circuits according to at least one of the above-mentioned embodiments, wherein the plurality of pixels are distributed in an array.

[0014] The pixel circuit and display panel provided in the present application are connected to the gate of the driving transistor through the control end of the clamping unit. When the gate potential of the driving transistor changes, the clamping unit can reduce the resistance between the first node and the second node, so that the gate potential of the driving transistor and the source potential or the drain potential of the driving transistor change in the same direction, thereby maintaining the potential difference between the gate-drain or gate-source of the driving transistor, improving the stability of the light-emitting current in the pixel circuit, and reducing or eliminating the phenomenon of excessive brightness changes within a frame. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The technical solution and other beneficial effects of the present application will be made apparent by describing in detail the specific implementation methods of the present application in conjunction with the accompanying drawings.

[0016] Figure 1 A schematic diagram of brightness change of a pixel circuit in the related art.

[0017] Figure 2 It is a structural schematic diagram of a pixel circuit in the related art.

[0018] Figure 3 A schematic diagram of the structure of a pixel circuit provided in an embodiment of the present application.

[0019] Figure 4 for Figure 3 Timing diagram of the pixel circuit shown.

[0020] Figure 5 A schematic diagram for comparing brightness changes provided in an embodiment of the present application. DETAILED DESCRIPTION

[0021] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0022] Figure 1 Schematic diagram of brightness change of pixel circuit in related art, such as Figure 1 As shown, the ordinate represents the brightness percentage and the abscissa represents time. Curve S10 shows the brightness change within a frame; curve S20 shows the average brightness change, that is, the desired ideal brightness change, that is, keeping the brightness constant within a frame or between consecutive frames. It can be seen that the brightness change within a frame or between frames can easily lead to different degrees of flicker. The brightness within a frame is gradually attenuated.

[0023] For details on how the brightness within a frame is attenuated, please refer to Figure 2 As shown, the gate potential of the driving transistor T1, i.e., the Q point potential, rises due to film leakage, the difference between the Q point potential VQ and the A point potential VA becomes larger, the conduction angle of the driving transistor T1 becomes smaller, the light emitting current flowing through the driving transistor T1 decreases, and the brightness of the light emitting device D1 decreases.

[0024] In view of the technical problem of excessive brightness variation within a frame mentioned above, this embodiment provides a pixel circuit, see Figures 2 to 5 ,like Figure 3As shown, the pixel circuit includes a driving transistor T1, a first light-emitting control transistor T5 and a clamping unit 10, one of the source / drain of the first light-emitting control transistor T5 is connected to the positive power line, the other of the source / drain of the first light-emitting control transistor T5 is connected to one of the source / drain of the driving transistor T1, and the gate of the first light-emitting control transistor T5 is connected to the first light-emitting control line; the control end of the clamping unit 10 is connected to the gate of the driving transistor T1, one end of the clamping unit 10 is connected to the first node, and the other end of the clamping unit 10 is connected to the second node, for reducing the resistance between the first node and the second node according to the gate potential of the driving transistor T1.

[0025] It can be understood that the pixel circuit provided in this embodiment is connected to the gate of the driving transistor T1 through the control end of the clamping unit 10. When the gate potential of the driving transistor T1 changes, the clamping unit 10 can reduce the resistance between the first node and the second node, so that the gate potential of the driving transistor T1 and the source potential or the drain potential of the driving transistor T1 change in the same direction, thereby maintaining the potential difference between the gate-drain or gate-source of the driving transistor T1, improving the stability of the light-emitting current in the pixel circuit, and reducing or eliminating the phenomenon of excessive brightness changes within a frame.

[0026] In one embodiment, the first node is a connection point between the positive power line and one of the source / drain of the driving transistor T1 ; the second node is another connection point between the positive power line and one of the source / drain of the driving transistor T1 .

[0027] It should be noted that the first node and the second node can be any two non-overlapping connection points on the connection path between the positive power line and one of the source / drain of the driving transistor T1. The clamping unit 10 can be connected in parallel with the path between the first node and the second node when it is turned on, thereby reducing the equivalent resistance between the first node and the second node, reducing the voltage drop loss from the positive power line to point A, and increasing the potential at point A.

[0028] In one embodiment, the first node is a connection point between the other of the source / drain of the first light-emitting control transistor T5 and one of the source / drain of the driving transistor T1; the second node is another connection point between the other of the source / drain of the first light-emitting control transistor T5 and one of the source / drain of the driving transistor T1, or the second node is a connection point between the positive power line and one of the source / drain of the first light-emitting control transistor T5.

[0029] It should be noted that, as the distance between the first node and the second node increases, the equivalent resistance between the first node and the second node decreases more, so that the voltage drop loss from the positive power line to point A decreases more, and the potential of point A increases faster. In particular, when the second node is a connection point between the positive power line and one of the source / drain of the first light-emitting control transistor T5, at this time, the first light-emitting control transistor T5 is also connected in parallel with the clamping unit 10, and the equivalent resistance between the source and the drain of the first light-emitting control transistor T5 can also be reduced.

[0030] In one embodiment, the clamping unit 10 includes a clamping transistor T8, a gate of the clamping transistor T8 is connected to the gate of the driving transistor T1, one of the source / drain of the clamping transistor T8 is connected to the first node, and the other of the source / drain of the clamping transistor T8 is connected to the second node; the channel type of the clamping transistor T8 is different from the channel type of the driving transistor T1.

[0031] It should be noted that this embodiment further limits the specific structure of the clamping unit 10, and implements the function of the clamping unit 10 with only a single transistor, which is beneficial to reducing the number of devices required for the pixel circuit and reducing the design complexity of the pixel circuit.

[0032] In one embodiment, the clamp transistor T8 is one of an N-channel thin film transistor and a P-channel thin film transistor, and the driving transistor T1 is the other of the N-channel thin film transistor and the P-channel thin film transistor.

[0033] It should be noted that, in the present embodiment, when the clamping transistor T8 is an N-channel thin film transistor, the driving transistor T1 is a P-channel thin film transistor. At this time, when the potential at point Q rises due to film leakage, the conduction angle of the clamping transistor T8 increases accordingly, and the equivalent resistance of the branch where the clamping transistor T8 is located, namely Ry, also decreases accordingly. The equivalent resistance of the line between the first node and the second node is Rx, and the equivalent resistance between the first node and the second node, namely RBA, is equal to Rx*Ry / (Rx+Ry). It can be seen that RBA also decreases accordingly, and the potential at point A is increased by pulling up the potential of the positive power signal VDD transmitted in the positive power line, and the potential difference VQA between point Q and point A is reduced. Then, the change in the potential at point Q reduces the influence of the light-emitting current flowing through the driving transistor T1, thereby also reducing the influence of the light-emitting current on the brightness of the light-emitting device D1, thereby reducing the brightness change amplitude of the light-emitting device D1 within the frame.

[0034] When the clamping transistor T8 is a P-channel thin film transistor and the driving transistor T1 is an N-channel thin film transistor, at this time, when the potential at point Q decreases due to film leakage, the conduction angle of the clamping transistor T8 increases accordingly, and RBA also decreases accordingly. The potential at point A is increased by pulling up the potential of the positive power signal VDD transmitted in the positive power line, and the potential difference VAQ between point A and point Q increases. The light-emitting current flowing through the driving transistor T1 also increases accordingly, thereby increasing the light-emitting brightness of the light-emitting device D1, thereby improving the trend of gradual brightness attenuation within the frame.

[0035] In one embodiment, the pixel circuit further includes a second light emitting control transistor T6 and a parallel unit 20, one of the source / drain of the second light emitting control transistor T6 is connected to the other of the source / drain of the driving transistor T1, the gate of the second light emitting control transistor T6 is connected to a second light emitting control line, and the second light emitting control line is the same as or different from the first light emitting control line; the parallel unit 20 is connected in parallel with the second light emitting control transistor T6.

[0036] It should be noted that the parallel connection of the parallel unit 20 and the second light-emitting control transistor T6 can reduce the equivalent resistance between point A and point C, thereby allowing the potential of the anode of the light-emitting device D1, i.e., point C, to rise faster. The light-emitting device D1 can emit light earlier in the light-emitting stage, thereby improving the start-up voltage during low grayscale display, thereby increasing the light-emitting time or display time within the frame.

[0037] In this embodiment, when the first light-emitting control line is the same as the second light-emitting control line, the gate of the first light-emitting control transistor T5 and the gate of the second light-emitting control transistor T6 can share the same light-emitting control line, which can save the number of signal transmission lines required for the pixel circuit. When the first light-emitting control line is different from the second light-emitting control line, the first light-emitting control transistor T5 and the second light-emitting control transistor T6 can be controlled separately, which improves the flexibility of the pixel circuit.

[0038] In one embodiment, one end of the parallel unit 20 is connected to one of the source / drain of the second light-emitting control transistor T6, the other end of the parallel unit 20 is connected to the other of the source / drain of the second light-emitting control transistor T6, and the control end of the parallel unit 20 is connected to the second light-emitting control line.

[0039] It should be noted that the parallel unit 20 and the second light-emitting control transistor T6 can be turned on or off synchronously. The control end of the parallel unit 20 and the gate of the second light-emitting control transistor T6 can share the same second light-emitting control line, which can save the number of signal transmission lines required by the pixel circuit.

[0040] In one embodiment, the parallel unit 20 includes a parallel transistor T9, one of the source / drain of the parallel transistor T9 is connected to one of the source / drain of the second light-emitting control transistor T6, the other of the source / drain of the parallel transistor T9 is connected to the other of the source / drain of the second light-emitting control transistor T6, and the gate of the parallel transistor T9 is connected to the gate of the second light-emitting control transistor T6.

[0041] It should be noted that, in this embodiment, the channel type of the parallel transistor T9 is the same as the channel type of the second light emitting control transistor T6. When the gates of the two transistors share the same light emitting control line, the two transistors can be turned on or off synchronously.

[0042] In one embodiment, the gate of the first light-emitting control transistor T5, the gate of the second light-emitting control transistor T6 and the gate of the parallel transistor T9 share the same light-emitting control line, for example, the first light-emitting control line or the second light-emitting control line, so that the number of signal transmission lines required for the pixel circuit can be minimized.

[0043] In one embodiment, the pixel circuit further includes a light emitting device D1, an anode of the light emitting device D1 is connected to the other of the source / drain of the second light emitting control transistor T6 and the other of the source / drain of the parallel transistor T9, and a cathode of the light emitting device D1 is connected to a negative power line.

[0044] It should be noted that the light emitting device D1 may be an organic light emitting diode, a micro light emitting diode, a mini light emitting diode or a quantum dot light emitting diode.

[0045] In one embodiment, the pixel circuit further includes a storage capacitor C1 , one end of the storage capacitor C1 is connected to the gate of the driving transistor T1 , and the other end of the storage capacitor C1 is connected to the positive power line.

[0046] In one of the embodiments, the pixel circuit further includes a write transistor T2 and a transfer transistor T3, one of the sources / drains of the write transistor T2 is connected to one of the sources / drains of the drive transistor T1, the other of the sources / drains of the write transistor T2 is connected to the data line, and the gate of the write transistor T2 is connected to the first scan line; one of the sources / drains of the transfer transistor T3 is connected to the other of the sources / drains of the drive transistor T1, the other of the sources / drains of the transfer transistor T3 is connected to the gate of the drive transistor T1, and the gate of the transfer transistor T3 is connected to the second scan line.

[0047] It should be noted that, in this embodiment, the data signal Data transmitted in the data line can be written into the gate of the driving transistor T1 or the storage capacitor C1 via the writing transistor T2 , the driving transistor T1 and the transmission transistor T3 in sequence.

[0048] In one embodiment, the pixel circuit further includes a first initialization transistor T7, one of the source / drain of the first initialization transistor T7 is connected to the anode of the light-emitting device D1, the other of the source / drain of the first initialization transistor T7 is connected to the first initialization line, and the gate of the first initialization transistor T7 is connected to the third scan line.

[0049] It should be noted that, in this embodiment, the anode potential of the light emitting device D1 can be initialized by the first initialization transistor T7.

[0050] In one embodiment, the pixel circuit further includes a second initialization transistor T4, one of the source / drain of the second initialization transistor T4 is connected to the gate of the driving transistor T1, the other of the source / drain of the second initialization transistor T4 is connected to the second initialization line, and the gate of the second initialization transistor T4 is connected to the fourth scan line.

[0051] It should be noted that, in this embodiment, the gate potential of the driving transistor T1 can be initialized by the second initialization transistor T4 .

[0052] Among them, the transmission transistor T3, the second initialization transistor T4, and the clamping transistor T8 can be N-channel thin film transistors, specifically oxide thin film transistors, such as indium gallium zinc oxide thin film transistors. The first light-emitting control transistor T5, the second light-emitting control transistor T6, the first initialization transistor T7, the write transistor T2, the drive transistor T1, and the parallel transistor T9 can be P-channel thin film transistors, specifically polysilicon thin film transistors, such as low-temperature polysilicon thin film transistors.

[0053] Wherein, the data line is used to transmit the data signal Data. The first scan line is used to transmit the nth level scan signal PS [n] with a negative pulse. The second scan line is used to transmit the nth level scan signal NS [n] with a positive pulse. The third scan line is used to transmit the n-1th level scan signal PS [n-1] with a negative pulse. The fourth scan line is used to transmit the n-1th level scan signal NS [n-1] with a positive pulse. The positive power line is used to transmit the positive power signal VDD. The negative power line is used to transmit the negative power signal VSS. The first initialization line is used to transmit the first initialization signal VI1. The second initialization line is used to transmit the second initialization signal VI2. The first light-emitting control line and / or the second light-emitting control line are used to transmit the light-emitting control signal EM.

[0054] Figure 4 for Figure 3 The timing diagram of the pixel circuit shown in FIG. 1 is a timing diagram of the pixel circuit, wherein Fn, Fn+1, and Fn+2 represent the nth frame time, the n+1th frame time, and the n+2th frame time, respectively. In the nth frame time, the operation process of the pixel circuit may include: Figure 4 The following are the working stages shown:

[0055] Initialization stage F10: the n-1th level scan signal PS [n-1] and the nth level scan signal NS [n] are at a low potential, the n-1th level scan signal NS [n-1], the nth level scan signal PS [n], and the light-emitting control signal EM are at a high potential, the first initialization transistor T7 and the second initialization transistor T4 are in the on state, so as to respectively initialize the anode potential of the light-emitting device D1 and the gate potential of the driving transistor T1.

[0056] Writing stage F20: the n-1th level scanning signal PS [n-1], the nth level scanning signal NS [n], and the light-emitting control signal EM are at a low potential, the n-1th level scanning signal NS [n-1] and the nth level scanning signal PS [n] are at a low potential, the writing transistor T2, the transmission transistor T3, and the driving transistor T1 are in the on state, and the data signal Data is written to the storage capacitor C1 through the writing transistor T2, the driving transistor T1, and the transmission transistor T3 in sequence.

[0057] Light-emitting stage F30: the n-1th level scan signal PS [n-1] and the nth level scan signal PS [n] are at a high potential, the n-1th level scan signal NS [n-1], the nth level scan signal NS [n], and the light-emitting control signal EM are at a low potential, the first light-emitting control transistor T5, the second light-emitting control transistor T6, and the driving transistor T1 are in the on state, and the light-emitting current flows through the light-emitting device D1 through the first light-emitting control transistor T5, the driving transistor T1, and the second light-emitting control transistor T6 in sequence, and the light-emitting device D1 starts to emit light.

[0058] The clamping unit 10 works in the writing stage and / or the light emitting stage, and the parallel unit 20 works in the light emitting stage.

[0059] Figure 5 A schematic diagram of brightness change comparison provided in an embodiment of the present application, wherein the ordinate represents brightness, the abscissa represents time, F is the time of one frame, and curve S30 is Figure 2 The brightness variation trend of the pixel circuit shown in FIG. 4 within a frame, curve S40 is Figure 3 The brightness variation trend of the light emitting device D1 in the pixel circuit shown in FIG. 1 during the lighting process, curve S50 is Figure 3 The brightness change trend of the pixel circuit shown in one frame.

[0060] From the above Figure 5 It can be seen that the brightness variation amplitude shown by curve S50 is much smaller than the brightness variation amplitude shown by curve S30, indicating that after the improvement of the present application, the brightness variation amplitude within the frame is significantly improved. At the same time, after the action of the parallel unit 20, the curve S40 becomes steeper, indicating that the light-emitting device D1 can emit light at a faster speed at the beginning of a frame. Correspondingly, the anode potential of the light-emitting device D1 can reach the start-up voltage faster at a low gray scale, which can enable the light-emitting device D1 to enter the light-emitting state earlier in a frame, which increases the light-emitting time or display time of a frame.

[0061] In one embodiment, the present embodiment provides a display panel, which includes a plurality of pixel circuits according to at least one of the above embodiments, and the plurality of pixels are distributed in an array.

[0062] It can be understood that the display panel provided in this embodiment is connected to the gate of the driving transistor T1 through the control end of the clamping unit 10. When the gate potential of the driving transistor T1 changes, the clamping unit 10 can reduce the resistance between the first node and the second node, so that the gate potential of the driving transistor T1 and the source potential or the drain potential of the driving transistor T1 change in the same direction, thereby maintaining the potential difference between the gate-drain or gate-source of the driving transistor T1, improving the stability of the light-emitting current in the pixel circuit, and reducing or eliminating the phenomenon of excessive brightness changes within a frame.

[0063] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0064] The pixel circuit and display panel provided in the embodiments of the present application are introduced in detail above. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present application. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some of the technical features therein with equivalents. These modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A pixel circuit, characterized in that: include: Driver transistor; a first light emission control transistor, wherein a first electrode of the first light emission control transistor is connected to a positive power supply line, a second electrode of the first light emission control transistor is connected to a first electrode of the driving transistor, and a gate of the first light emission control transistor is connected to a first light emission control line; a clamping unit, wherein a control end of the clamping unit is connected to the gate of the driving transistor, one end of the clamping unit is connected to a first node, and the other end of the clamping unit is connected to a second node, and is used to reduce the resistance between the first node and the second node according to the gate potential of the driving transistor; a second light emission control transistor, wherein a first electrode of the second light emission control transistor is connected to a second electrode of the driving transistor, and a gate of the second light emission control transistor is connected to a second light emission control line; and A parallel unit, the parallel unit being connected in parallel with the second light emitting control transistor; The first node is a connection point between the positive power line and the first electrode of the driving transistor; the second node is another connection point between the positive power line and the first electrode of the driving transistor.

2. The pixel circuit according to claim 1, characterized in that: The first node is a connection point between the second pole of the first light-emitting control transistor and the first pole of the driving transistor; the second node is another connection point between the second pole of the first light-emitting control transistor and the first pole of the driving transistor, or the second node is a connection point between the positive power line and the first pole of the first light-emitting control transistor.

3. The pixel circuit according to claim 1, characterized in that: The clamping unit includes a clamping transistor, a gate of the clamping transistor is connected to the gate of the driving transistor, a first electrode of the clamping transistor is connected to the first node, and a second electrode of the clamping transistor is connected to the second node; a channel type of the clamping transistor is different from a channel type of the driving transistor.

4. The pixel circuit according to claim 3, characterized in that: The clamp transistor is one of an N-channel thin film transistor and a P-channel thin film transistor, and the drive transistor is the other of the N-channel thin film transistor and the P-channel thin film transistor.

5. The pixel circuit according to claim 1, characterized in that: The second light emitting control line is the same as or different from the first light emitting control line.

6. The pixel circuit according to claim 5, characterized in that: One end of the parallel unit is connected to the first electrode of the second light emitting control transistor, the other end of the parallel unit is connected to the second electrode of the second light emitting control transistor, and the control end of the parallel unit is connected to the second light emitting control line.

7. The pixel circuit according to claim 6, characterized in that: The parallel unit includes a parallel transistor, a first electrode of the parallel transistor is connected to the first electrode of the second light emitting control transistor, a second electrode of the parallel transistor is connected to the second electrode of the second light emitting control transistor, and a gate of the parallel transistor is connected to the gate of the second light emitting control transistor.

8. The pixel circuit according to any one of claims 1 to 7, characterized in that: The working process of the pixel circuit in one frame includes an initialization phase, a writing phase and a light-emitting phase which are performed successively, and the clamping unit works in the writing phase and / or the light-emitting phase.

9. A display panel, characterized in that: It comprises a plurality of pixel circuits as claimed in any one of claims 1 to 8, wherein the plurality of pixel circuits are distributed in an array.

Images