Gate drive circuit and display panel

Abstract

The present application provides a gate driving circuit and a display panel; the gate driving circuit sets a reset module in a gate driving unit, connects the output end of the reset module to a first point, and resets the potential of the first point after the output module outputs a low potential, so that the output module will not continue to output a low potential due to the excessively high potential of the first point, thereby causing the transistor in the pixel driving circuit to be turned on, thereby avoiding the pixel from being lit when it is turned off and increasing the threshold voltage surplus.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a gate driving circuit and a display panel. Background Art

[0002] In order to reduce the number of external chips, existing display panels use GOA (Gate Driver On Array, array substrate row drive technology) circuits instead of external chips. Since there are size differences between the transistors of the gate drive circuit and the pixel drive circuit, and since the gate drive circuit needs to ensure normal output at any time, it is necessary to set a certain threshold voltage surplus for the transistors in the gate drive circuit to cover the influence of process and test conditions, so that the gate drive circuit can still work normally within a certain deviation range. However, during the operation of the gate drive circuit, the potential of the connection point of the gate of the output transistor cannot be maintained at a low potential after completing the low potential output, resulting in a small threshold voltage surplus of the gate drive circuit, which may cause the transistor in the pixel drive circuit to turn on, the pixel to be lit, and the influence of the delay on the scan line to become larger.

[0003] Therefore, the existing gate driving circuit has a technical problem that the potential of the transistor connection point cannot be maintained at a low potential after completing the low potential output, resulting in the pixel being lit when it is turned off. Summary of the invention

[0004] The embodiments of the present application provide a gate drive circuit and a display panel to alleviate the technical problem in existing gate drive circuits that the potential of a transistor connection point cannot be maintained at a low potential after completing the low potential output, resulting in the pixel being lit when it is turned off.

[0005] An embodiment of the present application provides a gate driving circuit, the gate driving circuit comprising a plurality of cascaded gate driving units, the gate driving unit comprising:

[0006] A first control module, connected to the first point, and used to control the potential of the first point;

[0007] A second control module, connected to the second point, and used to control the potential of the second point according to the frame start signal;

[0008] a linkage module, connected to the first point and the second point, and configured to link the first point and the second point;

[0009] an output module connected to the first point and the second point, wherein an output end of the output module is electrically connected to a scan line and is used to output a scan signal to the scan line;

[0010] The gate driving unit further includes a reset module, an output end of which is connected to the first point, and is used to reset the potential of the first point after the output module outputs a low potential.

[0011] In some embodiments, the reset module includes a reset transistor, a first signal terminal and a second signal terminal, the gate of the reset transistor is connected to the first signal terminal, the first electrode of the reset transistor is connected to the second signal terminal, the second electrode of the reset transistor is connected to the first point, the first signal terminal is used to input a signal to turn on the reset transistor after the output module outputs a low potential, and the second signal terminal is used to input a reset signal after the output module outputs a low potential.

[0012] In some embodiments, the gate drive unit also includes a first clock signal terminal and a low potential signal terminal, the first control module includes a first control transistor and a second control transistor, the gate of the first control transistor is connected to the first clock signal terminal, the first electrode of the first control transistor is connected to the low potential signal terminal, and the second electrode of the first control transistor is connected to the first point; the gate of the second control transistor is connected to the second point, the first electrode of the second control transistor is connected to the first clock signal terminal, and the second electrode of the second control transistor is connected to the first point.

[0013] In some embodiments, the gate drive unit also includes a frame start signal terminal, the second control module includes a third control transistor, the gate of the third control transistor is connected to the first clock signal terminal, the first electrode of the third control transistor is connected to the frame start signal terminal, and the second electrode of the third control transistor is connected to the second point.

[0014] In some embodiments, the gate drive unit also includes a high potential signal terminal and a second clock signal terminal, the linkage module includes a first linkage transistor and a second linkage transistor, the gate of the first linkage transistor is connected to the second clock signal terminal, the first electrode of the first linkage transistor is connected to the second electrode of the second linkage transistor, the second electrode of the first linkage transistor is connected to the second point, the gate of the second linkage transistor is connected to the first point, and the first electrode of the second linkage transistor is connected to the high potential signal terminal.

[0015] In some embodiments, the output module includes a first output transistor, a second output transistor and a signal output terminal, the gate of the first output transistor is connected to the second point, the first electrode of the first output transistor is connected to the second clock signal terminal, the second electrode of the first output transistor is connected to the signal output terminal, the gate of the second output transistor is connected to the first point, the first electrode of the second output transistor is connected to the high potential signal terminal, and the second electrode of the second output transistor is connected to the signal output terminal.

[0016] In some embodiments, the gate drive unit also includes a protection transistor, a first capacitor and a second capacitor, the gate of the protection transistor is connected to the low potential signal terminal, the first electrode of the protection transistor is connected to the third point, the second electrode of the protection transistor is connected to the second point, one end of the first capacitor is connected to the second point, the other end of the first capacitor is connected to the signal output terminal, one end of the second capacitor is connected to the first point, and the other end of the second capacitor is connected to the high potential signal terminal.

[0017] In some embodiments, the first signal terminal is the second point or the first signal terminal is the signal output terminal, and the reset transistor is turned on when the gate is at a high potential.

[0018] In some embodiments, the second signal terminal is the low potential signal terminal or the second signal terminal is the first clock signal terminal.

[0019] At the same time, an embodiment of the present application provides a display panel, which includes the gate driving circuit as described in any of the above embodiments.

[0020] Beneficial effects: The present application provides a gate drive circuit and a display panel; the gate drive circuit includes a plurality of cascaded gate drive units, the gate drive unit includes a first control module, a second control module, a linkage module and an output module, the first control module is connected to the first point, and is used to control the potential of the first point, the second control module is connected to the second point, and is used to control the potential of the second point according to the frame start signal, the linkage module is connected to the first point and the second point, and is used to link the first point and the second point, the output module is connected to the first point and the second point, and the output end of the output module is electrically connected to the scan line, and is used to output a scan signal to the scan line, wherein the gate drive circuit also includes a reset module, and the output end of the reset module is connected to the first point, and is used to reset the potential of the first point after the output module outputs a low potential. The present application sets a reset module in the gate drive unit, connects the output end of the reset module to the first point, and resets the potential of the first point after the output module outputs a low potential, so that the output module will not still output a low potential due to the excessive potential of the first point, thereby causing the transistor in the pixel drive circuit to turn on, avoiding the pixel from being lit when it is turned off, and increasing the threshold voltage surplus. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The technical solution and other beneficial effects of the present application will be made apparent by describing in detail the specific implementation methods of the present application in conjunction with the accompanying drawings.

[0022] Figure 1 A circuit diagram of a gate drive circuit provided in an embodiment of the present application.

[0023] Figure 2 A timing diagram of a gate drive circuit provided in an embodiment of the present application. DETAILED DESCRIPTION

[0024] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0025] In the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application. In addition, the terms "first" and "second" are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined.

[0026] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, an electrical connection, or mutual communication; it can be a direct connection, or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0027] In the present application, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may include that the first and second features are in direct contact, or may include that the first and second features are not in direct contact but are in contact through another feature between them. Moreover, a first feature being "above", "above" and "above" a second feature includes that the first feature is directly above and obliquely above the second feature, or simply indicates that the first feature is higher in level than the second feature. A first feature being "below", "below" and "below" a second feature includes that the first feature is directly below and obliquely below the second feature, or simply indicates that the first feature is lower in level than the second feature.

[0028] The disclosure below provides many different embodiments or examples to realize the different structures of the present application. In order to simplify the disclosure of the present application, the parts and settings of specific examples are described below. Of course, they are only examples, and the purpose is not to limit the present application. In addition, the present application can repeat reference numbers and / or reference letters in different examples, and this repetition is for the purpose of simplification and clarity, which itself does not indicate the relationship between the various embodiments and / or settings discussed. In addition, the various specific processes and material examples provided by the present application, but those of ordinary skill in the art can appreciate the application of other processes and / or the use of other materials.

[0029] In order to solve the technical problem that the potential of the transistor connection point in the existing gate driving circuit cannot be maintained at a low potential after the low potential is output, resulting in the pixel being lit when it is turned off, the embodiments of the present application provide a gate driving circuit and a display panel to alleviate the above technical problem.

[0030] like Figure 1 As shown, an embodiment of the present application provides a gate driving circuit, the gate driving circuit includes a plurality of cascaded gate driving units 10, and the gate driving unit 10 includes:

[0031] A first control module 11, connected to a first point P, and configured to control the potential of the first point P;

[0032] A second control module 12, connected to the second point Q, for controlling the potential of the second point Q according to a frame start signal;

[0033] A linkage module 13, connected to the first point P and the second point Q, and configured to link the first point P and the second point Q;

[0034] An output module 14, connected to the first point P and the second point Q, wherein an output end of the output module 14 is electrically connected to a scan line, and is used to output a scan signal to the scan line;

[0035] The gate driving unit 10 further includes a reset module 15 , the output end of which is connected to the first point P, and is used to reset the potential of the first point P after the output module 14 outputs a low potential.

[0036] An embodiment of the present application provides a gate driving circuit, which sets a reset module in a gate driving unit, connects the output end of the reset module to a first point, and resets the potential of the first point after the output module outputs a low potential, so that the output module will not continue to output a low potential due to the excessively high potential of the first point, thereby causing the transistor in the pixel driving circuit to be turned on, thereby avoiding the pixel from being lit when it is turned off and increasing the threshold voltage surplus.

[0037] It should be noted that Figure 1 The scan line is not shown in the figure, and the signal output terminal OUT of the output module 14 is electrically connected to the scan line. The electrical connection means that the signal output terminal is electrically connected to the scan line, and the electrical connection can be achieved through a physical connection. Specifically, the signal output terminal can be a part of the scan line, or it can be set separately and connected to the scan line through routing.

[0038] The potential of the first point after the output module outputs a low potential cannot drop to a low potential, resulting in a small threshold voltage surplus of the gate drive circuit. More threshold voltage surplus needs to be designed, or the transistor in the pixel drive circuit may be turned on and the pixel may be lit. In one embodiment, Figure 1 As shown, the reset module 15 includes a reset transistor T9, a first signal terminal ( Figure 1 The first point in the middle) and the second signal end ( Figure 1 The gate of the reset transistor T9 is connected to the first signal terminal, the first electrode of the reset transistor T9 is connected to the second signal terminal, the second electrode of the reset transistor T9 is connected to the first point P, the first signal terminal is used to input a signal to turn on the reset transistor T9 after the output module 14 outputs a low potential, and the second signal terminal is used to input a reset signal after the output module 14 outputs a low potential. By setting the reset transistor, the reset transistor is connected to the first point, and through signal control, after the output module outputs a low potential, the reset transistor is turned on to output a reset signal to the first point, so that the first point can be kept at a low potential, so that the threshold voltage surplus of the gate drive circuit is large, and there is no need to design more threshold voltage surpluses, and the transistor in the pixel drive circuit is prevented from being turned on, the pixel is illuminated, and the influence of the delay on the scan line is prevented from becoming larger.

[0039] In one embodiment, if Figure 1As shown, the gate driving unit 10 further includes a first clock signal terminal XCK and a low potential signal terminal VGL, the first control module 11 includes a first control transistor T1 and a second control transistor T3, the gate of the first control transistor T1 is connected to the first clock signal terminal XCK, the first electrode of the first control transistor T1 is connected to the low potential signal terminal VGL, and the second electrode of the first control transistor T1 is connected to the first point P; the gate of the second control transistor T3 is connected to the second point Q, the first electrode of the second control transistor T3 is connected to the first clock signal terminal XCK, and the second electrode of the second control transistor T3 is connected to the first point P. By setting the first control transistor and the second control transistor, the first clock signal terminal and the second point respectively control the opening and closing of the first control transistor and the second control transistor, thereby controlling the potential of the first point, and then controlling the potential output by the output module, so that the output module can output normally.

[0040] In one embodiment, if Figure 1 As shown, the gate driving unit 10 further includes a frame start signal terminal STV, the second control module 12 includes a third control transistor T2, the gate of the third control transistor T2 is connected to the first clock signal terminal XCK, the first electrode of the third control transistor T2 is connected to the frame start signal terminal STV, and the second electrode of the third control transistor T2 is connected to the second point Q. By setting the third control transistor so that the gate of the third control transistor is connected to the first clock signal terminal, the opening and closing of the third control transistor can be controlled by the first clock signal terminal, and the transistor of the output module is controlled to be turned on or off by the first control transistor, the second control transistor and the third control transistor, and the signal is output according to the input signal of the output module to control the transistor in the pixel driving circuit. By connecting the first electrode of the third control transistor to the frame start signal terminal and the second electrode to the second point, the potential of the second point can be controlled by the timing change of the frame start signal terminal, thereby controlling the transistor of the output module to be turned on or off.

[0041] In one embodiment, if Figure 1As shown, the gate driving unit 10 also includes a high potential signal terminal VGH and a second clock signal terminal CK, and the linkage module 13 includes a first linkage transistor T4 and a second linkage transistor T5, the gate of the first linkage transistor T4 is connected to the second clock signal terminal CK, the first electrode of the first linkage transistor T4 is connected to the second electrode of the second linkage transistor T5, the second electrode of the first linkage transistor T4 is connected to the second point Q, the gate of the second linkage transistor T5 is connected to the first point P, and the first electrode of the second linkage transistor T5 is connected to the high potential signal terminal VGH. By connecting the gate of the second linkage transistor to the first point, the second linkage transistor is turned on and off by controlling the potential of the first point, so that when the first point is at a low potential, the second linkage transistor can be controlled to turn on by the first point, and the gate of the first linkage transistor is connected to the second clock signal terminal, and the first linkage transistor can be controlled to turn on by the second clock signal terminal, and the first electrode of the second linkage transistor is connected to the high potential signal terminal, so that when the first point is at a low potential, the second point is at a high potential, so as to realize the linkage between the first point and the second point, and avoid signal interference in the control module.

[0042] In one embodiment, if Figure 1 As shown, the output module 14 includes a first output transistor T6, a second output transistor T7 and a signal output terminal OUT, the gate of the first output transistor T6 is connected to the second point Q, the first electrode of the first output transistor T6 is connected to the second clock signal terminal CK, the second electrode of the first output transistor T6 is connected to the signal output terminal OUT, the gate of the second output transistor T7 is connected to the first point P, the first electrode of the second output transistor T7 is connected to the high potential signal terminal VGH, and the second electrode of the second output transistor T7 is connected to the signal output terminal OUT. By setting the first output transistor and the second output transistor, the gate of the first output transistor is connected to the first point, and the gate of the second output transistor is connected to the second point, the first output transistor and the second output transistor can be turned on and off by the potential of the first point and the second point, the first electrode of the first output transistor is connected to the high potential signal terminal, and the second electrode is connected to the signal output terminal, the first electrode of the second output transistor is connected to the second clock signal terminal, and the second electrode is connected to the signal output terminal, so that the first output transistor can output a high potential, and the second output transistor can output a low potential, so that the output module can be controlled to output different signals to control the transistors connected to the scan line.

[0043] In one embodiment, if Figure 1As shown, the gate drive unit 10 also includes a protection transistor T8, a first capacitor C1 and a second capacitor C2, the gate of the protection transistor T8 is connected to the low potential signal terminal VGL, the first electrode of the protection transistor T8 is connected to the third point N, the second electrode of the protection transistor T8 is connected to the second point Q, one end of the first capacitor C1 is connected to the second point Q, the other end of the first capacitor C1 is connected to the signal output terminal OUT, one end of the second capacitor C2 is connected to the first point P, and the other end of the second capacitor C2 is connected to the high potential signal terminal VGH. By setting the protection transistor, the protection transistor can avoid the potential of the second point affecting the potential of the third point. By setting the first capacitor, when the first output transistor needs to be turned on, the gate potential of the first output transistor can be guaranteed to be low, so that the first output transistor is turned on normally. By setting the second capacitor, when the second output transistor needs to be turned on, the second capacitor can maintain the gate potential of the second output transistor, so that the second output transistor is turned on normally.

[0044] In order to solve the problem that adding a signal terminal to the gate drive circuit will occupy space and increase the complexity of the circuit, in one embodiment, Figure 1 As shown, the first signal terminal is the second point Q or the first signal terminal is the signal output terminal, and the reset transistor T9 is turned on when the gate is at a high potential. By making the first signal terminal the second point, and the reset transistor turned on when the gate is at a high potential, when the first point needs to be kept at a low potential, the reset transistor is turned on by the high potential of the second point, and a low potential is input to the first point, so that the first point is kept at a low potential, and there is no need to increase the signal terminal, thereby reducing the occupied space and circuit complexity. By making the first signal terminal the signal output terminal, when the first point needs to be kept at a low potential, the high potential output by the signal output terminal can turn on the reset transistor, so that the reset transistor outputs a low potential to the first point, so that the first point is kept at a low potential, and there is no need to increase the signal terminal, thereby reducing the occupied space and circuit complexity.

[0045] In order to solve the problem that adding a signal terminal to the gate drive circuit will occupy space and increase the complexity of the circuit, in one embodiment, Figure 1 As shown, the second signal terminal is the low potential signal terminal VGL or the second signal terminal is the first clock signal terminal. By making the second signal terminal a low potential signal terminal or the second signal terminal a first clock signal terminal, the second signal terminal can input a low potential to the first point when the first point needs to maintain a low potential, thereby ensuring that the first point maintains a low potential, and there is no need to increase the signal terminal, thereby reducing the occupied space and circuit complexity.

[0046] In one embodiment, the first control transistor, the second control transistor, the third control transistor, the first linkage transistor, the second linkage transistor, the first output transistor, the second output transistor and the protection transistor are all P-type transistors, and the reset transistor is an N-type transistor.

[0047] In one embodiment, the reset transistor is an indium gallium zinc oxide thin film transistor. The reset transistor can be formed by utilizing the indium gallium zinc oxide thin film transistor in the display area, without increasing the film layer structure, thereby reducing the thickness of the display panel.

[0048] Specifically, Figure 1 The gate drive unit shown, Figure 2 The working process of the gate driving unit is described by taking the timing diagram of each signal terminal and each point in the gate driving unit as an example. Figure 1 , Figure 2 As shown, in the first stage T1, the first clock signal terminal XCK inputs a low potential, the second clock signal terminal CK inputs a high potential, and the frame start signal terminal STV inputs a high potential. At this time, the first control transistor T1 and the third control transistor T2 are turned on, the second point Q and the third point N input a high potential through the third control transistor, the second control transistor T3 and the first output transistor T6 are turned off, the first point P inputs a low potential through the first control transistor T1, the second output transistor T7 is turned on, and the signal output terminal OUT outputs a high potential. For the P-type transistor in the pixel driving circuit, it will be closed at this time.

[0049] In the second stage T2, the first clock signal terminal XCK inputs a high potential, the second clock signal terminal CK inputs a low potential, and the frame start signal terminal STV inputs a high potential. At this time, the first control transistor T1 and the third control transistor T2 are turned off, the first linkage transistor T4 and the second linkage transistor T5 are turned on, the second point Q inputs a high potential, the second control transistor T3 and the first output transistor T6 are turned off, there is no write signal at the first point, and the low potential is maintained through the second capacitor C2, and the signal output terminal OUT outputs a high potential.

[0050] In the third stage T3, the first clock signal terminal XCK inputs a low potential, the second clock signal terminal CK inputs a high potential, the frame start signal terminal STV inputs a low potential, the first control transistor T1 and the third control transistor T2 are turned on, and the second point Q inputs a low potential through the third control transistor T2, but due to the action of the first capacitor C1, the potential of the second point Q is not fully written, the second control transistor T3 and the first output transistor T6 are turned on, the first point P is written with a low potential, and the signal output terminal OUT outputs a high potential.

[0051] In the fourth stage T4, the first clock signal terminal XCK inputs a high potential, the second clock signal terminal CK inputs a low potential, the frame start signal terminal STV inputs a low potential, the first control transistor T1 and the third control transistor T2 are turned off, the second clock signal terminal CK jumps from a high potential to a low potential, and the second point Q is coupled by the bootstrap effect of the first capacitor C1 and pulled down to a lower potential, ensuring that the first output transistor T6 is turned on and the signal output terminal OUT outputs a low potential. At the same time, the second control transistor T3 is turned on, so that the potential of the first point P is a high potential, and the second output transistor T7 is turned off, ensuring that the signal output terminal OUT continuously outputs a low potential.

[0052] After the signal output terminal OUT outputs a low potential, the first point P needs to be kept at a low potential. At this time, as shown in the first stage, the second point Q is at a high potential, so that the reset transistor T9 is turned on, and the low potential signal terminal VGL continues to input a low potential to the first point P, so that the first point P can be kept at a low potential, and the signal output terminal OUT outputs a high potential, so that the output module will not still output a low potential due to the excessively high potential of the first point, thereby causing the transistor in the pixel driving circuit to be turned on, thereby avoiding the pixel from being lit when it is turned off, and increasing the threshold voltage surplus.

[0053] At the same time, an embodiment of the present application provides a display panel, which includes the gate driving circuit described in any of the above embodiments.

[0054] According to the above embodiments, it can be seen that:

[0055] The embodiment of the present application provides a gate drive circuit and a display panel; the gate drive circuit includes a plurality of cascaded gate drive units, the gate drive unit includes a first control module, a second control module, a linkage module and an output module, the first control module is connected to the first point, and is used to control the potential of the first point, the second control module is connected to the second point, and is used to control the potential of the second point according to the frame start signal, the linkage module is connected to the first point and the second point, and is used to link the first point and the second point, the output module is connected to the first point and the second point, and the output end of the output module is electrically connected to the scan line, and is used to output a scan signal to the scan line, wherein the gate drive circuit also includes a reset module, and the output end of the reset module is connected to the first point, and is used to reset the potential of the first point after the output module outputs a low potential. The present application sets a reset module in the gate drive unit, connects the output end of the reset module to the first point, and resets the potential of the first point after the output module outputs a low potential, so that the output module will not still output a low potential due to the excessive potential of the first point, thereby causing the transistor in the pixel drive circuit to turn on, avoiding the pixel from being lit when it is turned off, and increasing the threshold voltage surplus.

[0056] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0057] The above is a detailed introduction to a gate drive circuit and a display panel provided in the embodiments of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present application. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some of the technical features therein with equivalents. These modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A gate drive circuit, characterized in that: The invention comprises a plurality of gate driving units connected in cascade, wherein the gate driving unit comprises: A first control module, connected to the first point, and used to control the potential of the first point; A second control module, connected to the second point, and used to control the potential of the second point according to the frame start signal; a linkage module, connected to the first point and the second point, and configured to link the first point and the second point; an output module connected to the first point and the second point, wherein an output end of the output module is electrically connected to a scan line and is used to output a scan signal to the scan line; Wherein, the gate driving unit further comprises a reset module, the output end of the reset module is connected to the first point, and is used to reset the potential of the first point after the output module outputs a low potential; The reset module comprises a reset transistor, a first signal terminal and a second signal terminal, the gate of the reset transistor is connected to the first signal terminal, the first electrode of the reset transistor is connected to the second signal terminal, the second electrode of the reset transistor is connected to the first point, the first signal terminal is used to input a signal to turn on the reset transistor after the output module outputs a low potential, and the second signal terminal is used to input a reset signal after the output module outputs a low potential; The gate drive circuit also includes a second clock signal terminal and a high potential signal terminal, the output module includes a first output transistor, a second output transistor and a signal output terminal, the gate of the first output transistor is connected to the second point, the first electrode of the first output transistor is connected to the second clock signal terminal, the second electrode of the first output transistor is connected to the signal output terminal, the gate of the second output transistor is connected to the first point, the first electrode of the second output transistor is connected to the high potential signal terminal, and the second electrode of the second output transistor is connected to the signal output terminal.

2. The gate driving circuit according to claim 1, wherein: The gate driving unit further includes a first clock signal terminal and a low potential signal terminal, the first control module includes a first control transistor and a second control transistor, the gate of the first control transistor is connected to the first clock signal terminal, the first electrode of the first control transistor is connected to the low potential signal terminal, and the second electrode of the first control transistor is connected to the first point; A gate of the second control transistor is connected to the second point, a first electrode of the second control transistor is connected to the first clock signal terminal, and a second electrode of the second control transistor is connected to the first point.

3. The gate driving circuit according to claim 2, characterized in that: The gate driving unit also includes a frame start signal terminal, the second control module includes a third control transistor, the gate of the third control transistor is connected to the first clock signal terminal, the first electrode of the third control transistor is connected to the frame start signal terminal, and the second electrode of the third control transistor is connected to the second point.

4. The gate driving circuit according to claim 3, characterized in that: The linkage module includes a first linkage transistor and a second linkage transistor, the gate of the first linkage transistor is connected to the second clock signal end, the first electrode of the first linkage transistor is connected to the second electrode of the second linkage transistor, the second electrode of the first linkage transistor is connected to the second point, the gate of the second linkage transistor is connected to the first point, and the first electrode of the second linkage transistor is connected to the high potential signal end.

5. The gate driving circuit according to claim 4, characterized in that: The gate driving unit also includes a protection transistor, a first capacitor and a second capacitor, the gate of the protection transistor is connected to the low potential signal terminal, the first electrode of the protection transistor is connected to the third point, the second electrode of the protection transistor is connected to the second point, one end of the first capacitor is connected to the second point, the other end of the first capacitor is connected to the signal output terminal, one end of the second capacitor is connected to the first point, and the other end of the second capacitor is connected to the high potential signal terminal.

6. The gate driving circuit according to claim 5, characterized in that: The first signal terminal is the second point or the first signal terminal is the signal output terminal, and the reset transistor is turned on when the gate is at a high potential.

7. The gate driving circuit according to claim 6, characterized in that: The second signal terminal is the low potential signal terminal or the second signal terminal is the first clock signal terminal.

8. A display panel, characterized in that: The invention comprises a gate driving circuit as claimed in any one of claims 1 to 7.

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