Memory device programming techniques using fewer latches

Abstract

This application relates to memory device programming techniques using fewer latches. A command to program data to a memory device is received. A target charge level for a set of memory cells in the memory device for a first programming step is determined based on the data. A first set of indicators is provided to the memory device. The first set of indicators indicates the target charge level for the first programming step. A target charge level for the set of memory cells for a second programming step is determined based on the data. A second set of indicators is provided to the memory device. The second set of indicators indicates the target charge level for the second programming step.

Description

Technical Field

[0001] Embodiments of this disclosure generally relate to memory subsystems, and more specifically, to programming data into a memory device using indicators of memory cell charge levels. Background Technology

[0002] The memory subsystem may include one or more memory devices for storing data. Memory components may be, for example, non-volatile memory devices and volatile memory devices. Generally, a host system can utilize the memory subsystem to store data at memory devices and retrieve data from memory devices. Summary of the Invention

[0003] According to one aspect of this application, a system is provided. The system includes: a memory device; and a processing means coupled to the memory device, the processing means being configured to perform operations including: receiving a command to program data into the memory device; determining, based on the data, a target charge level for a first programming step using a set of memory cells in the memory device; sending a first set of indicators to the memory device, indicating the target charge level for the first programming step using the set of memory cells; determining, based on the data, a target charge level for a second programming step using the set of memory cells in the memory device; and sending a second set of indicators to the memory device, indicating the target charge level for the second programming step using the set of memory cells in the memory device.

[0004] According to another aspect of this application, a method is provided. The method includes: receiving, via a processing device, a command to program data into a memory device; determining, via the processing device, a target charge level for a first programming step using a set of memory cells in the memory device, based on the data; sending to the memory device a first set of indicators indicating the target charge level for the first programming step using the set of memory cells; detecting completion of the first programming step at the memory device; and, in response to detecting completion of the first programming step at the memory device, determining, via the processing device, a target charge level for a second programming step using the set of memory cells in the memory device, based on the data; and sending to the memory device a second set of indicators indicating the target charge level for the second programming step using the set of memory cells in the memory device.

[0005] According to another aspect of this application, a memory device is provided. The memory device includes: a set of memory cells; and a processing means coupled to the set of memory cells, the processing means being configured to perform operations including: receiving from a memory subsystem controller a first set of indicators indicating a target charge level for a first programming step of the set of memory cells; performing the first programming step according to the target charge level indicated by the first set of indicators; receiving from the memory subsystem controller a second set of indicators indicating a target charge level for a second programming step of the set of memory cells in the memory device; and performing the second programming step according to the target charge level indicated by the second set of indicators. Attached Figure Description

[0006] This disclosure will be more fully understood from the detailed description provided below and the accompanying drawings of various embodiments thereof.

[0007] Figure 1 This is a block diagram illustrating an instance computing environment including a memory subsystem according to some embodiments of the present disclosure.

[0008] Figures 2A-2D This is an interaction diagram illustrating instances of interactions between components of a memory subsystem when data is programmed into a memory device using an indicator of the charge level of a memory cell, according to some embodiments of the present disclosure.

[0009] Figure 3 This is a conceptual diagram illustrating the mapping between programming data, charge levels, and charge level indicators according to some embodiments of this disclosure.

[0010] Figure 4-6 This is a flowchart illustrating an example method for programming data into a memory device by transmitting an indicator of a target charge level to the memory device, according to some embodiments of the present disclosure.

[0011] Figure 7 and 8 This is a flowchart illustrating an example method for programming data into a memory device based on an indicator of a target charge level received from a memory subsystem controller, consistent with some embodiments.

[0012] Figure 9 This is a block diagram of an example computer system in which embodiments of the present disclosure can be operated. Detailed Implementation

[0013] This disclosure relates to various aspects of programming memory devices within a memory subsystem. The memory subsystem may be a storage device, a memory module, or a mixture of both. The following is in conjunction with… Figure 1Describe examples of storage devices and memory modules. Generally, a host system may utilize a memory subsystem that contains one or more components (e.g., memory devices) for storing data. The host system can provide data to be stored in the memory subsystem and can request data to be retrieved from the memory subsystem.

[0014] Data operations can be performed by the memory subsystem. Data operations can be host-initiated. For example, the host system can initiate data operations on the memory subsystem (e.g., write, read, erase, etc.). The host system can send access requests (e.g., write commands, read commands) to the memory subsystem to store data in and read data from the memory devices of the memory subsystem.

[0015] Memory devices can be non-volatile memory devices. One example of a non-volatile memory device is a NAND flash memory device. Other examples of non-volatile memory devices are described below. Figure 1 Description. Some memory devices, such as NAND memory devices, contain an array of memory cells (e.g., flash cells) for storing data. Each cell contains a transistor, and within each cell, data is stored as a threshold voltage of the transistor. More precisely, the threshold voltage range of the transistor can be divided into multiple regions, where each region corresponds to a charge level decoded into a data value. Memory cells in these devices can be grouped into pages, and a page can refer to a logic cell of the memory device used to store data. For example, memory cells in a NAND memory device are horizontally connected to word lines at their control gates to form pages. In some types of memory devices (e.g., NAND), pages can be grouped to form blocks (also referred to herein as "memory blocks").

[0016] One type of memory cell, such as a single-level cell (SLC), stores one bit per cell. Other types of memory cells, such as multi-level cell (MLC), three-level cell (TLC), four-level cell (QLC), and five-level cell (PLC), store multiple bits per cell. A memory device may comprise one or more arrays of SLC, MLC, TLC, QLC, or any combination thereof. In some cases, a memory device may comprise an SLC portion and any one or more of an MLC, TLC, QLC, or PLC portion of memory cells.

[0017] Peripheral circuitry is used to read and write data from memory cells. For example, complementary metal-oxide-semiconductor (CMOS) circuitry or "array-controlled CMOS" circuitry can be used to read and write data from memory cells. Furthermore, the peripheral circuitry includes one or more page buffers, typically implemented by one or more latch circuits (also simply called "latches"). Page buffers act as intermediate storage components, temporarily storing data read from memory cells so that it can be passed outside the memory device via the memory subsystem controller.

[0018] Typically, the number of page buffers included in the peripheral circuitry depends on the number of memory cell levels. That is, the number of page buffers used for reading from and writing to memory cells is usually based on the number of bits that can be stored in the memory cell. For example, as mentioned above, a QLC can store four bits per cell and therefore typically uses four page buffers to read and write data to QLC pages. On the other hand, a TLC can store only three bits per cell and therefore uses three page buffers to read and write data to TLC pages. However, each page buffer increases the on-chip area occupied by the peripheral circuitry, which also increases the manufacturing cost of the memory device. Therefore, although a QLC can store one more bit per cell than a TLC, a QLC typically utilizes more on-chip area to support the additional page buffers. Generally, the more bits that can be stored in a cell, the larger the on-chip area consumed by that portion of the cell, because the additional bits require more buffers.

[0019] Various aspects of this disclosure relate to a memory subsystem for programming data into a memory device comprising multiple levels of cells (e.g., MLC, TLC, QLC, and PLC) using fewer page buffers than the conventional methods discussed above. Specifically, the memory subsystem employs a programming technique that allows data to be programmed into pages of the memory device using fewer page buffers than the number of bits a cell can store. For example, the memory subsystem can program data into a QLC page using fewer than four buffers per cell. Instead of providing programming data to be written to the memory device, the memory subsystem provides the memory device with a set of charge level indicators that indicate the target charge level of the memory cell at each programming step.

[0020] The memory subsystem programs data into one or more pages in the memory device through multiple programming steps. For each programming step, the programming component of the memory subsystem controller determines the target memory cell charge level for that programming step and sends a charge level indicator to the memory device. Upon receiving the indicator, the memory device performs the programming step by moving the charge level of the memory cell to the target charge level corresponding to the indicator provided by the programming component. The programming component waits for the programming step to complete successfully before determining the charge level for subsequent programming steps and sending corresponding indicators to the memory device for use in subsequent programming steps. This process continues until the memory cell reaches the charge level corresponding to the data intended to be stored in each cell.

[0021] As mentioned above, the data programming technique employed in the memory subsystem described herein offers the advantage of programming data to memory cells using fewer latches (page buffers), thus reducing the on-chip area consumed by the circuitry used to read and write data to the memory cells of the memory device. In this way, the data programming technique allows TLC dies to support QLC programming without the need for additional latches. Furthermore, this programming technique provides a better performance / cost ratio than conventional methods for hybrid SLC, TLC, and QLC implementations. This approach also reduces the cost of QLC and TLC dies.

[0022] Figure 1 An example computing system 100 including a memory subsystem 110 is illustrated according to some embodiments of the present disclosure. The memory subsystem 110 may include media, such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination of such devices.

[0023] The memory subsystem 110 may be a storage device, a memory module, or a mixture of a storage device and a memory module. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash memory (UFS) drives, secure digital cards (SD cards), and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0024] The computing system 100 may be a computing device, such as a desktop computer, laptop computer, web server, mobile device, vehicle (e.g., airplane, drone, train, car or other means of transport), device with Internet of Things (IoT) capabilities, embedded computer (e.g., embedded computer contained in a vehicle, industrial equipment or networked business device), or such computing device containing memory and processing devices.

[0025] The computing system 100 may include multiple host systems coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to different types of memory subsystems 110. Figure 1 An example host system 120 is shown coupled to a memory subsystem 110. As used herein, “coupled to” or “coupled with” generally refers to a connection between components, which can be an indirect or direct communication connection (e.g., without an intermediate component), whether wired or wireless, and includes electrical, optical, magnetic, and other connections.

[0026] Host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a Peripheral Component Interconnect (PCIe) controller, a Serial Advanced Technology Attachment (SATA) controller). Host system 120 uses memory subsystem 110, for example, to write data to and read data from memory subsystem 110.

[0027] Host system 120 can be coupled to memory subsystem 110 via a physical host interface. Examples of host interfaces include, but are not limited to, SATA interfaces, PCIe interfaces, USB interfaces, Fibre Channel, Serial Attached SCSI (SAS), Small Computer System Interface (SCSI), Double Data Rate (DDR) memory bus, DIMM interfaces (e.g., DIMM socket interfaces supporting Double Data Rate (DDR), Open NAND Flash Interface (ONFI), Double Data Rate (DDR), Low Power Double Data Rate (LPDDR), or any other interface. The host interface can be used to transfer data between host system 120 and memory subsystem 110. Host system 120 may further utilize an NVM Fast (NVMe) interface to access components (e.g., memory device 130) when memory subsystem 110 is coupled to host system 120 via a PCIe interface. The host interface provides an interface for passing control, address, data, and other signals between memory subsystem 110 and host system 120. As an example, Figure 1The memory subsystem 110 is shown. Generally, the host system 120 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0028] Memory devices 130 and 140 may comprise any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory device 140) may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0029] Some examples of non-volatile memory devices (e.g., memory device 130) include NAND-type flash memory and in-situ write memory, such as three-dimensional (3D) crosspoint memory devices, which are crosspoint arrays of non-volatile memory cells. Non-volatile memory crosspoint arrays can perform bit storage based on variations in bulk resistance in conjunction with stackable cross-grid data access arrays. Furthermore, compared to many flash-based memories, crosspoint non-volatile memories can perform in-situ write operations, where non-volatile memory cells can be programmed even after they have been previously erased. NAND-type flash memory includes, for example, two-dimensional NAND (2D NAND) and 3D NAND.

[0030] Each of the memory devices 130 may include one or more arrays of memory cells. One type of memory cell, such as a single-level cell (SLC), may store one bit per cell. Other types of memory cells, such as multi-level cell (MLC), three-level cell (TLC), four-level cell (QLC), and five-level cell (PLC), may store multiple bits per cell. In some embodiments, each of the memory devices 130 may include one or more arrays of memory cells, such as SLC, MLC, TLC, QLC, or any combination thereof. In some embodiments, a particular memory device may include an SLC portion, as well as an MLC portion, a TLC portion, a QLC portion, or a PLC portion of memory cells. The memory cells of the memory device 130 may be grouped into pages, and a page may refer to a logical cell of the memory device used to store data. For example, memory cells in a NAND memory device are horizontally connected to word lines at their control gates to form pages. In some types of memory (e.g., NAND), pages may be grouped to form blocks. In addition, word lines within a memory device can be organized into multiple word line groups, each of which contains one or more word lines, but each word line group contains fewer word lines than a block contains.

[0031] Although non-volatile memory components such as NAND flash memory (e.g., 2D NAND, 3D NAND) and 3D cross-point non-volatile memory cell arrays are described, memory device 130 can be based on any other type of non-volatile memory, such as read-only memory (ROM), phase-change memory (PCM), select memory, other chalcogenide-based memories, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), NOR flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0032] The memory subsystem controller 115 (or, for simplicity, controller 115) can communicate with the memory device 130 to perform operations, such as reading data, writing data, erasing data, and other such operations at the memory device 130. The memory subsystem controller 115 may include hardware such as one or more integrated circuits and / or discrete components, buffer memories, or combinations thereof. The hardware may include a digital circuit system with dedicated (i.e., hard-decoded) logic to perform the operations described herein. The memory subsystem controller 115 may be a microcontroller, a dedicated logic circuit system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or another suitable processor.

[0033] The memory subsystem controller 115 may include a processor 117 (processing device) configured to execute instructions stored in local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes embedded memory configured to store instructions for performing various processes, operations, logic flows, and routines for controlling the operation of the memory subsystem 110, including handling communication between the memory subsystem 110 and the host system 120.

[0034] In some embodiments, local memory 119 may include memory registers storing memory pointers, retrieved data, etc. Local memory 119 may also include ROM for storing microcode. Although Figure 1 The instance memory subsystem 110 is shown to include a memory subsystem controller 115, but in another embodiment of this disclosure, the memory subsystem 110 may not include a memory subsystem controller 115 and may instead rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0035] Generally, the memory subsystem controller 115 can receive commands or operations from the host system 120 and can translate these commands or operations into instructions or appropriate commands to achieve the desired access to memory devices 130 and / or 140. The memory subsystem controller 115 may be responsible for other operations, such as wear leveling, garbage collection, error detection and ECC, encryption, caching, and address translation between logical addresses (e.g., logical block addresses, namespaces) and physical addresses (e.g., physical block addresses) associated with memory device 130. The memory subsystem controller 115 may further include a host interface circuitry for communicating with the host system 120 via a physical host interface. The host interface circuitry can translate commands received from the host system 120 into instructions for accessing memory devices 130 and / or 140, and translate responses associated with memory devices 130 and / or 140 into information for the host system 120.

[0036] In some embodiments, the memory device 130 includes a local media controller 135 that operates in conjunction with the memory subsystem controller 115 to perform operations on one or more memory cells of the memory device 130.

[0037] The memory subsystem 110 also includes a programming component 113 responsible for programming data to memory devices 130 and 140 based on commands from the host system 120. The programming component 113 programs data to a set of memory cells (e.g., one or more pages of a word line) within the memory device using multiple programming steps. The number of programming steps depends on the number of page buffers contained within the memory cell being programmed. Instead of providing programming data to be written to memory devices 130 or 140, the programming component 113 provides a set of charge level indicators in each programming step, indicating the target charge level of the memory cell. More specifically, for each programming step, the programming component 113 determines the target charge level for each memory cell in the set of memory cells for the programming step, and sends the charge level indicator (also referred to herein as a "charge level indicator") to the memory device. The memory device receiving the charge level indicator performs the programming step by moving the charge level of the memory cell to the indicated target charge level. Programming component 113 waits for the programming step to complete successfully before determining the charge level for subsequent programming steps and sending a corresponding indicator to memory device 130 or 140 for use in subsequent programming steps. This process continues until each memory cell in the set of memory cells reaches the charge level corresponding to the data that the cell intends to store based on a predefined mapping of data values ​​to charge levels.

[0038] In some embodiments, the memory subsystem controller 115 includes at least a portion of the programming component 113. For example, the memory subsystem controller 115 may include a processor 117 (processing means) configured to execute instructions stored in local memory 119 to perform the operations described herein. In some embodiments, at least a portion of the programming component 113 is part of the host system 120, an application program, or an operating system.

[0039] Figures 2A-2D This is an interaction diagram illustrating instances of interactions between components of a memory subsystem when data is programmed into a memory device using indicators of memory cell charge levels, according to some embodiments of this disclosure. Figures 2A-2D In the example shown, memory device 130 is a NAND memory device comprising multiple memory blocks. As shown, NAND block 200 comprises an array (2D or 3D) of pages (rows) and strings (columns). Each NAND cell contains a transistor, and within each cell, data is stored as the threshold voltage of the transistor. For example, SLC NAND may store one bit per cell. Other types of memory cells, such as MLC, TLC, QLC, and PLC, may store multiple bits per cell. Strings are connected within NAND block 200 to allow storage and retrieval of data from selected cells. NAND cells in the same column are connected in series to form a bit line (BL). All cells in a bit line are connected at one end to a common ground and at the other end to a common sense amplifier to read the threshold voltage of one of the cells when decoding data. NAND cells are horizontally connected to word lines (WL) at their control gates to form pages. In MLC, TLC, QLC, and PLC NAND, a page is a group of connected cells sharing the same word line and is the smallest programmable unit.

[0040] As mentioned above, each NAND cell operates at the threshold voltage (V) of the transistor. th Data is stored in the form of a 3-bit value. The threshold voltage range of a memory cell is divided into multiple zones based on the number of bits stored in the cell, and each zone corresponds to a value that can be represented by the cell. More precisely, each zone corresponds to a charge level, and each charge level is decoded into a multi-bit value. For example, a TLC NAND flash cell can be in one of eight charge levels—ER (erased), L0, L1, L2, L3, L4, L5, or L6. Each charge level is decoded into a 3-bit value stored in the flash cell (e.g., 111, 110, 100, 000, 010, 011, 001, and 101).

[0041] During each programming step, data is programmed into a block of memory device 130 using a programming sequence comprising multiple passes, wherein programming pulses are applied to cells within the block. Within the multiple passes, the programming pulses configure the threshold voltage of the cells in each page according to a target charge level based on a value intended to be represented by the cell. As the programming sequence progresses, the voltage level of the programming pulses increases until the threshold voltage of the cell reaches the target charge level.

[0042] Figures 2A-2D Figure 250 also shows the charge level of an instance page during the process of programming data into block 200 of memory device 130. (See reference) Figure 2A The instance page is initially an erased page (represented as "ER" in Figure 250). A command to program data into memory device 130 is received by memory subsystem controller 115, and programming data 202 specified by the command is provided to programming component 113. At 204, programming component 113 determines a target charge level for a set of memory cells within block 200 of memory device 130 for the first programming step. This set of memory cells is the memory cells to which programming data 202 will be programmed and corresponds to one or more pages in block 200. Programming component 113 determines the target charge level for each memory cell for the first programming step based on a predefined mapping 206 from charge level to programming data value. The predefined mapping 206 specifies the charge level (e.g., ER, L1, L2, L3, L4, L5, L6, or L7) for each programming data value (e.g., 111, 110, 100, 000, 010, 011, 001, and 101).

[0043] refer to Figure 2B At point 208, programming component 113 sends a first set of charge level indicators 210 to memory device 130. The first set of charge level indicators 210 indicates the target charge level of the set of memory cells for the first programming step. Each indicator may contain one or more binary values, and the number of binary values ​​in each indicator is based on the number of page buffers per page in memory device 130. In this example, the memory block contains QLCs, and only one page buffer (e.g., containing one or more latches) is used per page. Processing device may write the first set of indicators to the page buffers in the memory device. Each indicator in the first set of charge level indicators 210 indicates whether the target charge level of the cell is at least at a first level (L0). That is, each indicator contains a binary value where '1' indicates that the target charge level of the corresponding cell is greater than or equal to L0.

[0044] In response to receiving the first set of charge level indicators 210, the memory device 130 performs a first programming step in part by moving the set of memory cells to the target charge level indicated by the first set of charge level indicators 210. The first programming step may include multiple programming passes, as described above. As shown in FIG250, after the first programming step is successfully completed, the cells within the instance page indicated to have a target charge level of at least L0 are programmed.

[0045] refer to Figure 2C Based on the detection of completion of the first programming step at 212, at 214, programming component 113 determines the target charge level for the second programming step using the set of memory cells. Programming component 113 determines the target charge level for the second programming step based on programming data 202 and predefined mapping 206.

[0046] refer to Figure 2D At 216, programming component 113 sends a second set of charge level indicators 218 to memory device 130. The second set of charge level indicators 218 indicates the target charge level of the set of memory cells for the second programming step. The processing device may write the second set of indicators into a page buffer in the memory device. In this example, each indicator in the second set of charge level indicators 210 indicates whether the target charge level of the cell is at least at the second level (L1). That is, each indicator contains a binary value where '1' indicates that the target charge level of the corresponding cell is greater than or equal to L1.

[0047] In response to receiving the second set of charge level indicators 218, the memory device 130 performs a second programming step in part by moving the set of memory cells to the target charge level indicated by the second set of charge level indicators 218. Like the first programming step and any subsequent programming steps, the second programming step may include multiple programming passes, as described above. As shown in FIG250, upon successful completion of the second programming step, cells within the instance page indicated to have a target charge level of at least L1 are programmed, while cells indicated not to be at least L1 are maintained at their previous levels (ER or L0).

[0048] In this example of a TLC block with only a single latch per TLC, a total of eight programming steps are performed, and the process described above is repeated until the memory device 130 completes these eight programming steps based on eight sets of charge level indicators provided by the programming component 113. It should be understood that the techniques described herein for programming data into a memory device are not limited to any number of programming steps. That is, in other embodiments, such as those in which the memory device 130 includes an MLC, TLC, or PLC, or a different number of latches per unit, fewer or additional programming steps may be used.

[0049] As another example, Figure 3 This diagram illustrates a mapping between charge levels and charge level indicators for programming to a QLC page using three page buffers, according to some example embodiments. As shown, data is programmed to the QLC using 16 charge levels. Given the three page buffers and 16 charge levels, this example uses three programming steps to program the data.

[0050] In the first programming step, "111" is provided for memory cells with a target charge level equal to or greater than 7. The indicator for memory cells with a target charge level less than 6 is based on the corresponding binary value of the charge level.

[0051] In the second programming step, a "000" is provided for memory cells with a target charge level less than 5 to indicate that the memory cells should be maintained at their current charge level. That is, "000" indicates that the current charge level of the corresponding cell is the target charge level for the cell used in the second and other programming steps. For the second programming step, "111" indicates that the corresponding cell has a target charge level equal to or greater than 14.

[0052] In the third programming step, memory cells with a target charge level less than 13 are provided with "000" to indicate that the memory cells should be maintained at their current charge level. For the third programming step, only a single bit is used to indicate whether the target charge level is 14 or 15.

[0053] Figure 4-6 This is a flowchart illustrating an example method 400 for programming data into a memory device by transmitting an indicator of a target charge level to the memory device, according to some embodiments of the present disclosure. Method 400 may be executed by processing logic, which may include hardware (e.g., processing device, circuit system, dedicated logic, programmable logic, microcode, device hardware, integrated circuit, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, method 400 is performed by… Figure 1The programming component 113 executes. Although the processes are shown in a specific order or sequence, the order of the processes can be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as merely examples, and the illustrated processes can be executed in different orders, and some processes can be executed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are utilized in every embodiment. Other process flows are possible.

[0054] At operation 405, the processing device receives a command to program data into a memory device (e.g., memory device 130). This command may be received from a host system (e.g., host system 120).

[0055] The processing device determines, based on the data, the target charge level for a set of memory cells in the memory device for the first programming step (at operation 410). That is, the processing device determines the target charge level for each memory cell in the set of memory cells for the first programming step. For example, the processing device may determine that the target charge level for a first memory cell or subset of memory cells is a first charge level, and the target charge level for a second memory cell or subset of second memory cells is at least a second charge level. The processing device may determine the charge level based on a predefined mapping between charge levels and programming data. The set of memory cells may correspond to one or more pages of word lines in the memory device.

[0056] At operation 415, the processing device sends a first set of indicators to the memory device, indicating the target charge level of the set of memory cells for the first programming step. Each indicator may contain one or more binary values. The number of binary values ​​in each indicator is based on the number of page buffers per page in the memory device. The processing device may write the first set of indicators to one or more page buffers in the memory device. In response to receiving the first set of indicators, the memory device performs the first programming step in part by moving the set of memory cells to the target charge level indicated by the first set of indicators.

[0057] In response to the detection that the first programming step is complete (operation 420), at operation 425, the processing device determines the charge level of the group of memory cells in the second programming step based on the data. At operation 430, the processing device sends a second set of indicators to the memory device. The second set of indicators indicates the target charge level of the group of memory cells in the second programming step. In response to receiving the second set of indicators, the memory device performs the second programming step in part by moving one or more memory cells in the group of memory cells to the target charge level indicated by the second set of indicators.

[0058] Consistent with some embodiments, the programming of data to the memory device is complete upon successful completion of the second programming step. However, it should be understood that method 400 is not limited to two programming steps, and in other embodiments, additional programming steps may be used to program data to the memory device. Therefore, as Figure 5 As shown, in some embodiments, method 400 may include operations 435 and 440 for the Nth programming step, and one or more intermediate operations designed to provide indicators for one or more intermediate programming steps.

[0059] At operation 435, the processing device determines the target charge level of the group of memory cells in the Nth programming step. At operation 440, the processing device sends the Nth set of indicators to the memory device. The Nth set of indicators indicates the target charge level of the group of memory cells in the Nth programming step.

[0060] like Figure 6 As shown, in some embodiments, method 400 may further include operations 605, 610, 615, and 620. Consistent with these embodiments, operations 605 and 610 may be performed as part of operation 410, in which the processing device determines the target charge level of the set of memory cells for the first programming step. At operation 605, the processing device accesses a predefined mapping between data values ​​and memory cell charge levels. That is, for each data value that a memory cell can store, which is related to the number of bits that the cell can store, the predefined mapping specifies the corresponding charge level of the cell. For each memory cell in the set of memory cells, at operation 610, the processing device identifies the target charge level for the first programming step based on the value to be stored by the cell according to the predefined mapping.

[0061] Consistent with these embodiments, operations 615 and 620 can be performed as part of operation 425, in which the processing device determines the target charge level for the second programming step using the set of memory cells. At operation 615, the processing device accesses a predefined mapping between data values ​​and memory cell charge levels. For each memory cell in the set of memory cells, at operation 620, the processing device identifies the target charge level for the second programming step based on the value to be stored in the cell according to the predefined mapping.

[0062] Figure 7 and 8This is a flowchart illustrating an example method 700, consistent with some embodiments, for programming data into a memory device based on an indicator of a target charge level received from a memory subsystem controller (e.g., memory subsystem controller 115). Method 700 can be executed by processing logic, which may include hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, device hardware, integrated circuit, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, method 700 is performed by… Figure 1 The local media controller 135 executes the process. Although the processes are shown in a specific order or sequence, the order of the processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as merely examples, and the illustrated processes may be executed in different orders, and some processes may be executed in parallel. Furthermore, in various embodiments, one or more processes may be omitted. Therefore, not all processes are utilized in every embodiment. Other process flows are possible.

[0063] At operation 705, the processing device receives a first set of indicators from the memory subsystem controller, which indicates the target charge level of a set of memory cells for the first programming step. The first set of indicators may be provided by the memory subsystem controller in response to a command received from the host system to program data into the memory device. The memory subsystem controller writes the first set of indicators to one or more page buffers connected to the set of memory cells.

[0064] In response to receiving the first set of indicators, at operation 710, the processing device performs a first programming step according to the first set of indicators. That is, the processing device moves the group of memory cells to the target charge level indicated by the first set of indicators. The processing device uses a programming sequence comprising multiple passes to move the group of memory cells to the target charge level, wherein programming pulses are applied to cells in a block. Within the multiple passes, the programming pulses change the threshold voltage of the cells in each page according to the target charge level. As the programming sequence progresses, the voltage level of the programming pulses increases until the threshold voltage of the cells reaches the target charge level indicated by the first set of indicators.

[0065] At operation 715, the processing device receives a second set of indicators from the memory subsystem controller, which indicates the target charge level of the group of memory cells for the second programming step. In response to receiving the second set of indicators, at operation 720, the processing device performs the second programming step according to the second set of indicators. That is, the processing device moves one or more cells in the group of memory cells to the target charge level indicated by the second set of indicators. In some cases, based on the first programming step, one or more cells may be at the target charge level. In these cases, during the second programming step, the processing device maintains the one or more cells at the current charge level while moving one or more cells to a higher target charge level indicated by the second set of indicators associated with the second programming step.

[0066] Consistent with some embodiments, the programming of data to the memory device is complete upon successful completion of the second programming step. However, it should be understood that method 700 is not limited to two programming steps, and in other embodiments, additional programming steps may be used to program data to the memory device. Therefore, as Figure 8 As shown, in some embodiments, method 700 may include operations 725 and 730 for the Nth programming step, and one or more intermediate operations designed to provide indicators for one or more intermediate programming steps.

[0067] At operation 725, the processing device receives the Nth set of indicators from the memory subsystem controller, which indicates the target charge level for the Nth programming step for the group of memory cells. In response to receiving the Nth set of indicators, at operation 730, the processing device performs the Nth programming step according to the Nth set of indicators. Similar to the second programming step, one or more cells may be at the corresponding target charge level indicated by the Nth set of indicators, and in these cases, the processing device maintains the one or more cells at their current charge level while moving one or more cells to a higher target charge level indicated by the Nth set of indicators.

[0068] The embodiments described in the subject matter may include one or more features, individually or in combination, as illustrated below by way of examples.

[0069] Example 1 is a system comprising: a memory device; and a processing means coupled to the memory device, the processing means being configured to perform operations including: receiving a command to program data into the memory device; determining, based on the data, a target charge level for a first programming step using a set of memory cells in the memory device; sending a first set of indicators to the memory device indicating the target charge level for the first programming step using the set of memory cells; determining, based on the data, a target charge level for a second programming step using the set of memory cells in the memory device; and sending a second set of indicators to the memory device indicating the target charge level for the second programming step using the set of memory cells in the memory device.

[0070] Example 2 includes the system according to Example 1, wherein determining the target charge level of the set of memory cells includes identifying the target charge level of the set of memory cells based on a predefined mapping between data values ​​and charge levels.

[0071] Example 3 includes the system according to any one or more of Examples 1 or 2, wherein the operation further includes: detecting the completion of the first programming step at the memory device, and sending the second set of indicators in response to detecting the completion of the first programming step at the memory device.

[0072] Example 4 includes a system according to any one or more of Examples 1-3, wherein the operation further includes: determining, based on the data, a target charge level for the set of memory cells in the third programming step; and sending a third set of indicators to the memory device, which indicates the target charge level for the set of memory cells in the third programming step.

[0073] Example 5 includes a system according to any one or more of Examples 1-4, wherein: an indicator in the first set of indicators indicates whether the target charge level of the first memory cell is at least at a first charge level; and an indicator in the second set of indicators indicates whether the target charge level of the second memory cell is at least at a second charge level.

[0074] Example 6 includes a system according to any one or more of Examples 1-5, wherein: each of the first and second sets of indicators includes one or more binary values, the number of binary values ​​in each indicator being based on the number of page buffers for each page in the memory device.

[0075] Example 7 includes a system according to any one or more of Examples 1-6, wherein: sending the first set of indicators includes writing the first set of indicators to one or more page buffers of the memory device; and sending the second set of indicators includes writing the second set of indicators to one or more page buffers of the memory device.

[0076] Example 8 is a method comprising: receiving, via a processing device, a command to program data into a memory device; determining, via the processing device, a target charge level for a first programming step using a set of memory cells in the memory device, based on the data; sending to the memory device a first set of indicators indicating the target charge level for the first programming step using the set of memory cells; detecting completion of the first programming step at the memory device; and, in response to detecting completion of the first programming step at the memory device, determining, via the processing device, a target charge level for a second programming step using the set of memory cells in the memory device, based on the data; and sending to the memory device a second set of indicators indicating the target charge level for the second programming step using the set of memory cells in the memory device.

[0077] Example 9 includes the method according to Example 8, wherein determining the target charge level of the set of memory cells includes identifying the target charge level of the set of memory cells based on a predefined mapping between data values ​​and charge levels.

[0078] Example 10 includes the method according to any one or more of Examples 8 or 9, further comprising: determining, based on the data, a target charge level for the set of memory cells in the third programming step; and sending a third set of indicators to the memory device, indicating the target charge level for the set of memory cells in the third programming step.

[0079] Example 11 includes the method according to any one or more of Examples 8-10, wherein: an indicator in the first set of indicators indicates whether the target charge level of the first memory cell is at least at a first charge level; and an indicator in the second set of indicators indicates whether the target charge level of the second memory cell is at least at a second charge level.

[0080] Example 12 includes the method according to any one or more of Examples 8-11, wherein: each of the first and second sets of indicators includes one or more binary values, the number of binary values ​​in each indicator being based on the number of page buffers for each page in the memory device.

[0081] Example 13 includes the method according to any one or more of Examples 8-12, wherein: sending the first set of indicators includes writing the first set of indicators to one or more page buffers of the memory device; and sending the second set of indicators includes writing the second set of indicators to one or more page buffers of the memory device.

[0082] Example 14 is a memory device comprising: a set of memory cells; and a processing means coupled to the set of memory cells, the processing means being configured to perform operations including: receiving from a memory subsystem controller a first set of indicators indicating a target charge level of the set of memory cells for a first programming step; performing the first programming step according to the target charge level indicated by the first set of indicators; receiving from the memory subsystem controller a second set of indicators indicating a target charge level of the set of memory cells in the memory device for a second programming step; and performing the second programming step according to the target charge level indicated by the second set of indicators.

[0083] Example 15 includes a memory device according to Example 14, wherein: performing the first programming step includes moving the charge level of the set of memory cells to the target charge level indicated by the first set of indicators; and performing the second programming step includes moving the charge level of the set of memory cells to the target charge level indicated by the second set of indicators.

[0084] Example 16 includes a memory device according to any one or more of Examples 14 or 15, wherein the target charge level for the first and second programming steps is based on a predefined mapping between data values ​​and charge levels.

[0085] Example 17 includes a memory device according to any one or more of Examples 14-16, wherein the first and second sets of indicators are determined based on data contained in a command received by the memory subsystem controller to write the data to the memory device.

[0086] Example 18 includes a memory device according to any one or more of Examples 14-17, wherein: an indicator in the first set of indicators indicates whether a target charge level of a first memory cell is at least at a first charge level; and an indicator in the second set of indicators indicates whether a target charge level of a second memory cell is at least at a second charge level.

[0087] Example 19 includes a memory device according to any one or more of Examples 14-18, wherein: a third set of indicators is received from a memory subsystem controller, indicating a target charge level for a third programming step in the set of memory cells in the memory device; and the third programming step is performed according to the target charge level indicated by the third set of indicators.

[0088] Example 20 includes a memory device according to any one or more of Examples 14-19, further comprising: one or more page buffers for receiving the first and second sets of indicators, wherein each of the first and second sets of indicators includes one or more binary values, wherein the number of binary values ​​in each indicator is based on the number of page buffers for each page in the memory device.

[0089] Figure 9 An example machine in the form of a computer system 900 is shown, within which a set of instructions can be executed to cause the machine to perform any one or more of the methods discussed herein. In some embodiments, the computer system 900 may correspond to a host system (e.g., Figure 1 The host system 120 includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 The memory subsystem 110), or may be used to perform controller operations (e.g., to execute an operating system, thereby executing commands corresponding to...). Figure 1 (Operation of programming component 113). In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a local area network (LAN), intranet, extranet, and / or the Internet. The machine may operate as a qualified server or client machine in a client-server network environment, as a peer-to-peer (or distributed) network environment, or as a server or client machine in a cloud computing infrastructure or environment.

[0090] The machine may be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), cellular phone, network appliance, server, network router, switch, or bridge, or any machine capable of executing (sequentially or otherwise) a set of instructions specifying actions to be taken by the machine. Furthermore, although a single machine is shown, the term "machine" should also be considered to include any collection of machines that individually or collectively execute a set (or more) of instructions to perform any or more of the methods discussed herein.

[0091] The example computer system 900 includes a processing device 902, a main memory 904 (e.g., ROM, flash memory, DRAM, such as SDRAM or RDRAM), a static memory 906 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 918, which communicate with each other via a bus 930.

[0092] Processing device 902 represents one or more general-purpose processing devices, such as microprocessors, central processing units, etc. More specifically, processing device 902 may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processor implementing other instruction sets, or a combination of instruction sets. Processing device 902 may also be one or more special-purpose processing devices, such as ASICs, FPGAs, digital signal processors (DSPs), network processors, etc. Processing device 902 is configured to execute instructions 926 for performing the operations and steps discussed herein. Computer system 900 may further include a network interface device 908 communicating via network 920.

[0093] Data storage system 918 may include machine-readable storage medium 924 (also referred to as computer-readable medium) on which one or more sets of instructions 926 or software embodying any one or more of the methods or functions described herein are stored. Instructions 926 may also reside wholly or at least partially in main memory 904 and / or processing device 902 during execution by computer system 900, main memory 904, and processing device 902, which also constitute machine-readable storage media. Machine-readable storage medium 924, data storage system 918, and / or main memory 904 may correspond to... Figure 1 The memory subsystem 110.

[0094] In one embodiment, instruction 926 includes implementing a security component (e.g., Figure 1 The programming component 113) contains functional instructions. Although the machine-readable storage medium 924 is shown as a single medium in the exemplary embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding a set of instructions executable by a machine and causing the machine to perform any one or more of the methods of this disclosure. The term "machine-readable storage medium" should therefore be considered to include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0095] Some of the previously described sections have presented algorithms and symbolic representations of operations on data bits within computer memory. These algorithmic descriptions and representations are the most efficient way for those skilled in the art of data processing to communicate their work to others skilled in the art. Here and generally, an algorithm is conceived as a self-consistent sequence of operations that produces a desired result. These operations are those that require physical manipulation of physical quantities. Typically, but not necessarily, these quantities take the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. It has been found convenient, primarily for common reasons, to refer to these signals as bits, values, elements, symbols, characters, items, numbers, etc.

[0096] However, it should be remembered that all these and similar terms are associated with appropriate physical quantities and are merely convenient labels for application to those quantities. This disclosure may refer to the actions and processes of a computer system or similar electronic computing device that manipulate and transform data represented as physical (electronic) quantities in the registers and memories of a computer system into other data similarly represented as physical quantities in the computer system's memory or registers or other such information storage systems.

[0097] This disclosure also relates to apparatus for performing the operations described herein. Such apparatus may be constructed for the desired purpose, or may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in a computer. Such computer programs may be stored in computer-readable storage media, such as, but not limited to, any type of disk, including floppy disks, optical disks, CD-ROMs and magneto-optical disks, ROMs, RAMs, EPROMs, EEPROMs, magnetic cards or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

[0098] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general-purpose systems can be used with the programs taught herein, or it may prove convenient to construct more specialized devices to perform the methods described herein. Structures for various such systems will be presented in the following description. Furthermore, this disclosure is described without reference to any particular programming language. It should be understood that the teachings of this disclosure as described herein can be implemented using a variety of programming languages.

[0099] This disclosure may be provided as a computer program product or software, which may include machine-readable media on which instructions are stored for programming a computer system (or other electronic device) to perform processes according to this disclosure. Machine-readable media includes any means for storing information in a machine-readable (e.g., computer-readable) form. In some embodiments, machine-readable (e.g., computer-readable) media includes machine-readable storage media such as ROM, RAM, disk storage media, optical storage media, flash memory components, etc.

[0100] In the foregoing description, embodiments of this disclosure have been described with reference to specific example embodiments thereof. It will be apparent that various modifications can be made to the embodiments of this disclosure without departing from the broader scope set forth in the appended claims. Therefore, the description and drawings should be viewed in an illustrative rather than restrictive sense.

Claims

1. A memory system comprising: Memory devices; as well as A processing device coupled to the memory device, the processing device being configured to perform operations including the following: Receive a command to program data into the memory device; Based on the data, a set of memory cells in the memory device is determined to be of a target charge level for the first programming step; Sending a first set of indicators to the memory device, which indicates the target charge level of the set of memory cells for the first programming step, the sending of the first set of indicators includes writing the first set of indicators to one or more page buffers of the memory device; Based on the data, the target charge level of the set of memory cells in the memory device for the second programming step is determined; as well as Sending a second set of indicators to the memory device, which indicates the target charge level of the set of memory cells in the memory device for the second programming step, the sending of the second set of indicators includes writing the second set of indicators to the one or more page buffers of the memory device.

2. The memory system of claim 1, wherein determining the target charge level of the set of memory cells includes identifying the target charge level of the set of memory cells based on a predefined mapping between data values ​​and charge levels.

3. The memory system of claim 1, wherein the operation further comprises: The completion of the first programming step is detected at the memory device, and The second set of indicators is sent in response to the detection of the completion of the first programming step at the memory device.

4. The memory system of claim 1, wherein the operation further comprises: Based on the data, the target charge level of the set of memory cells for the third programming step is determined; as well as A third set of indicators is sent to the memory device, indicating the target charge level of the set of memory cells for the third programming step.

5. The memory system according to claim 1, wherein: The indicator in the first set of indicators indicates whether the target charge level of the first memory cell is at least at the first charge level; and The indicator in the second set of indicators indicates whether the target charge level of the second memory cell is at least at the second charge level.

6. The memory system according to claim 1, wherein: Each of the first and second sets of indicators includes one or more binary values, and the number of binary values ​​in each indicator is based on the number of page buffers for each page in the memory device.

7. A method for a memory system, the method comprising: The processing device receives a command to program data into a memory device; Based on the data, the processing device determines the target charge level of a set of memory cells in the memory device for the first programming step. Sending a first set of indicators to the memory device, which indicates the target charge level of the set of memory cells for the first programming step, the sending of the first set of indicators includes writing the first set of indicators to one or more page buffers of the memory device; The completion of the first programming step is detected at the memory device. In response to the detection of completion of the first programming step at the memory device, the processing device determines, based on the data, the target charge level of the set of memory cells in the memory device for the second programming step; as well as Sending a second set of indicators to the memory device, which indicates the target charge level of the set of memory cells in the memory device for the second programming step, the sending of the second set of indicators includes writing the second set of indicators to the one or more page buffers of the memory device.

8. The method of claim 7, wherein determining the target charge level of the set of memory cells includes identifying the target charge level of the set of memory cells based on a predefined mapping between data values ​​and charge levels.

9. The method of claim 7, further comprising: Based on the data, the target charge level of the set of memory cells for the third programming step is determined; as well as A third set of indicators is sent to the memory device, indicating the target charge level of the set of memory cells for the third programming step.

10. The method according to claim 7, wherein: The indicator in the first set of indicators indicates whether the target charge level of the first memory cell is at least at the first charge level; and The indicator in the second set of indicators indicates whether the target charge level of the second memory cell is at least at the second charge level.

11. The method according to claim 7, wherein: Each of the first and second sets of indicators includes one or more binary values, and the number of binary values ​​in each indicator is based on the number of page buffers for each page in the memory device.

12. A memory device comprising: A set of memory units; as well as A processing means coupled to the set of memory cells, the processing means being configured to perform operations including the following: The memory subsystem controller receives a first set of indicators for writing to one or more page buffers of the memory device, the first set of indicators indicating the target charge level of the set of memory cells for a first programming step; The first programming step is performed based on the target charge level indicated by the first set of indicators; Receives a second set of indicators from the memory subsystem controller for writing to one or more page buffers in the memory device, the second set of indicators indicating the target charge level of the set of memory cells in the memory device for a second programming step; as well as The second programming step is performed based on the target charge level indicated by the second set of indicators.

13. The memory device according to claim 12, wherein: Performing the first programming step includes moving the charge level of the set of memory cells to the target charge level indicated by the first set of indicators; and Performing the second programming step includes moving the charge level of the set of memory cells to the target charge level indicated by the second set of indicators.

14. The memory device of claim 12, wherein the target charge level for the first and second programming steps is based on a predefined mapping between data values ​​and charge levels.

15. The memory device of claim 12, wherein the first and second sets of indicators are determined based on data contained in a command received by the memory subsystem controller, the command writing the data into the memory device.

16. The memory device according to claim 12, wherein: The indicator in the first set of indicators indicates whether the target charge level of the first memory cell is at least at the first charge level; and The indicator in the second set of indicators indicates whether the target charge level of the second memory cell is at least at the second charge level.

17. The memory device according to claim 12, wherein: Receives a third set of indicators from the memory subsystem controller, which indicates the target charge level of the set of memory cells in the memory device for the third programming step; as well as The third programming step is performed based on the target charge level indicated by the third set of indicators.

18. The memory device of claim 12, further comprising: One or more page buffers for receiving the first and second sets of indicators, wherein each indicator in the first and second sets of indicators includes one or more binary values, wherein the number of binary values ​​in each indicator is based on the number of page buffers for each page in the memory device.

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