Semiconductor structure and method of forming a semiconductor structure

Abstract

The application provides a semiconductor structure and a forming method of the semiconductor structure. The semiconductor structure comprises a substrate and a conductive channel structure. The conductive channel structure comprises a first conductive channel layer, a second conductive channel layer and a conductive buffer layer. The first conductive channel layer comprises a first conductive channel and first and second doped regions located at two ends of the first conductive channel. The second conductive channel layer comprises a second conductive channel and third and fourth doped regions located at two ends of the second conductive channel. The conductive buffer layer is used for reducing the electrical interference between the first and third doped regions. The semiconductor structure further comprises a first wire layer, a second wire layer and a gate structure. The first wire layer is located on the substrate, extends in a first direction and is in contact with the second doped region. The second wire layer extends in a second direction and is in contact with the first and third doped regions. The gate structure surrounds the first and second conductive channels. The application provides a CFET structure with vertically arranged conductive channels, which avoids occupying a large area in the horizontal direction of the conductive channels.

Description

Technical Field

[0001] This application relates to the field of semiconductor structures, and in particular to a semiconductor structure and a method for forming a semiconductor structure. Background Technology

[0002] The process and performance of integrated circuit chips are closely related to the structure of transistor devices. Below 5nm technology nodes, the drawbacks of MOS field-effect transistors based on PN junction theory become increasingly apparent: the channel length is constantly shrinking, and the distance between the source and drain is getting closer and closer. To prevent source-drain punch-through, the industry commonly employs ultra-steep source-drain concentration gradient doping processes, which severely limit the thermal budget of the device process. Furthermore, due to the statistical distribution of dopant atoms and their natural tendency to diffuse at certain temperatures, fabricating ultra-steep PN junctions at the nanoscale becomes extremely difficult, resulting in severe short-channel effects. This leads to a decrease in transistor threshold voltage, a deterioration in gate control capability, an increase in leakage current, and an increase in power consumption; in severe cases, the device may even be unable to turn off.

[0003] One or more pairs of nFET and pFET cylindrical nanowires or nanosheets (nanoribbons) are vertically stacked in a cross-gravity configuration to form a complementary fully enclosed gate cylindrical nanowire or nanosheet field-effect transistor (CFET) device structure. In the CFET structure, the nFET and pFET share a single gate electrode as the signal input and a single drain electrode as the signal output. The source electrodes are grounded and powered, respectively. The device size can be flexibly adjusted to meet different chip performance requirements. While maintaining the electrical integrity of the vertically stacked nanowire or nanosheet fully enclosed gate field-effect transistor, this design significantly saves chip area, enhances device drive current, and improves chip integration density.

[0004] CFETs enhance device drive current while significantly saving chip area and increasing chip device integration. However, because pFETs and nFETs share a single source or drain connection and their fabrication processes are complex, variable, and difficult to control, current nFETs or pFETs are all horizontally placed GAA transistors. The horizontally positioned conductive channels occupy a large area in the horizontal direction, which limits the development of CFETs. Summary of the Invention

[0005] This application provides a semiconductor structure and a method for forming the semiconductor structure, and provides a CFET structure with a vertically arranged conductive channel to avoid occupying a large area in the horizontal direction of the conductive channel.

[0006] To address the aforementioned technical problems, embodiments of this application provide a semiconductor structure, including: a substrate, and a conductive channel structure located on the substrate. The conductive channel structure includes a first conductive channel layer, a conductive buffer layer, and a second conductive channel layer stacked sequentially. The first conductive channel layer includes a first conductive channel and a first doped region and a second doped region located at both ends of the first conductive channel, wherein the first doped region is close to the second conductive channel layer. The second conductive channel layer includes a second conductive channel and a third doped region and a fourth doped region located at both ends of the second conductive channel, wherein the third doped region is close to the first conductive channel layer. The conductive buffer layer is used to reduce electrical interference between the first doped region and the third doped region. A first conductive layer is located on the substrate, extends in a first direction, and contacts the second doped region in the first direction. A second conductive layer extends in a second direction and contacts the first doped region and the third doped region in the second direction. A gate structure is disposed around the first conductive channel and the second conductive channel.

[0007] Compared with related technologies, the vertically arranged first and second conductive channel layers, i.e., two vertically arranged conductive channels, with the gate structure surrounding the first and second conductive channels in the horizontal direction, avoid the conductive channels occupying a large area in the horizontal direction.

[0008] In addition, the conductive channel structures are discretely disposed on the substrate; the first conductor layer is in contact with the second doped region of all conductive channel structures disposed in the first direction; the second conductor layer is in contact with the first doped region and the third doped region of all conductive channel structures disposed in the second direction; the gate structure also fills the gap between the plane where the first conductor layer is located and the plane where the second conductor layer is located.

[0009] In addition, the substrate includes a structural region and a connecting region, with the connecting region located around the structural region; a peripheral insulation structure is provided on the substrate of the connecting region, and the first conductor layer and the second conductor layer extend into the peripheral insulation structure of the connecting region; it also includes: a first conductive plug and a second conductive plug; the first conductive plug penetrates the peripheral insulation structure and contacts the first conductor layer; the second conductive plug penetrates a portion of the peripheral insulation structure and contacts the second conductor layer.

[0010] Furthermore, the included angle between the first and second extension directions is greater than 0°. By extending the first and second conductive layers in different directions, electrical connections between the first and second conductive layers can be achieved in the peripheral insulation structures on different sides, further reducing the area occupied by the semiconductor structure.

[0011] In addition, the semiconductor structure also includes: a third conductive plug in contact with the fourth doped region; and a fourth conductive plug in contact with the top of the gate structure.

[0012] Furthermore, the height of the contact surface between the conductive buffer layer and the first doped region is lower than the height of the center thickness position of the second conductive layer, but higher than the height of the bottom surface of the second conductive layer; the height of the contact surface between the conductive buffer layer and the first doped region is higher than the height of the center thickness position of the second conductive layer, but lower than the height of the top surface of the second conductive layer. By limiting the thickness of the second conductive layer, the stability of the electrical connection between the second conductive layer and the first and third doped regions is ensured.

[0013] In addition, the thickness of the conductive buffer layer is less than 1 / 3 of the thickness of the second conductive layer. By limiting the thickness of the conductive buffer layer, the stability of the electrical connection between the second conductive layer and the first and third doped regions is further ensured.

[0014] In addition, the substrate includes a substrate and an isolation layer, a first conductive layer is located inside the substrate, an isolation layer is located on the top surface of the substrate, and a first conductive channel layer penetrates the isolation layer and part of the substrate so that the second doped region is in contact with the first conductive layer.

[0015] Additionally, the substrate includes a substrate and an isolation layer, with the isolation layer located on the top surface of the substrate and the first conductive layer located on the top surface of the isolation layer.

[0016] In addition, the semiconductor structure also includes a first insulating layer surrounding the first conductive layer. By covering the first insulating layer, the first conductive layer is isolated, thus preventing electrical crosstalk from occurring in the first conductive layer.

[0017] In addition, the semiconductor structure also includes a second insulating layer surrounding the second conductive layer. By covering the first insulating layer, the first conductive layer is isolated, thus preventing electrical crosstalk from occurring in the first conductive layer.

[0018] In addition, the semiconductor structure also includes a protective layer, nested on top of all the discrete conductive channel structures and in contact with the fourth doped region. The protective layer has through-holes in a direction perpendicular to the substrate surface, and the gate structure fills these through-holes. This nested protective layer covers part of the gate structure surface, preventing electrical crosstalk issues.

[0019] In addition, the top surface of the protective layer is flush with the top surface of the second conductive channel layer.

[0020] In addition, one of the first conductive channel layer and the second conductive channel layer is an N-type conductive channel, and the other is a P-type conductive channel.

[0021] This application embodiment also provides a method for forming a semiconductor structure, comprising: providing a substrate including a structural region and an interconnect region, the substrate including a substrate, a first conductive layer and an isolation layer, the first conductive layer extending in a first direction; forming a first sacrificial layer on the substrate of the structural region, and forming a peripheral insulating structure on the substrate of the interconnect region; patterning the first sacrificial layer to form a first channel penetrating the first sacrificial layer; forming a second conductive layer filling the first channel and partially located on the first sacrificial layer, the second conductive layer extending into the peripheral insulating structure of the interconnect region, and the second conductive layer extending in a second direction; sequentially forming a second sacrificial layer and a protective layer on the substrate of the structural region; patterning the second sacrificial layer to form a second channel penetrating the second sacrificial layer, the projections of the first channel and the second channel on the substrate coinciding; forming a second conductive channel layer filling the second channel; patterning a portion of the protective layer until the second sacrificial layer is exposed, removing the second sacrificial layer and the first sacrificial layer; and forming a gate structure filling a gap.

[0022] Additionally, providing a substrate including a structural region and an interconnect region includes: providing a substrate including a structural region and an interconnect region, forming an isolation layer on the substrate of the structural region, and forming a first conductive layer on the isolation layer. Alternatively, providing a substrate including a structural region and an interconnect region includes: providing a substrate including a structural region and an interconnect region, doping the substrate of the structural region to form a first conductive layer, and forming an isolation layer on the substrate of the structural region.

[0023] This application also provides a method for forming a semiconductor structure, comprising: providing a substrate including a structural region and an interconnect region, the substrate including a substrate, a first conductive layer and an isolation layer, the first conductive layer extending in a first direction; forming a first sacrificial layer on the substrate of the structural region, and forming a peripheral insulating structure on the substrate of the interconnect region; forming a second conductive layer on the first sacrificial layer, the second conductive layer extending into the peripheral insulating structure of the interconnect region, and the second conductive layer extending in a second direction; sequentially forming a second sacrificial layer and a protective layer on the substrate of the structural region; patterning the protective layer, the second sacrificial layer and the first sacrificial layer to form an opening, and filling the opening to form a conductive channel structure; patterning a portion of the protective layer until the second sacrificial layer is exposed, and removing the second sacrificial layer and the first sacrificial layer; and forming a gate structure with a gap filled.

[0024] Additionally, a substrate including a structural region and an interconnect region is provided, comprising: providing a substrate including a structural region and an interconnect region, forming an isolation layer on the substrate of the structural region, and forming a first conductive layer on the isolation layer.

[0025] Additionally, a substrate including a structural region and an interconnect region is provided, comprising: providing a substrate including a structural region and an interconnect region, doping the substrate of the structural region to form a first conductive layer, and forming an isolation layer on the substrate of the structural region.

[0026] Compared to related technologies, by forming a vertically arranged first conductive channel layer and a second conductive channel layer, that is, forming two vertically arranged conductive channels, and the gate structure surrounds the first conductive channel and the second conductive channel in the horizontal direction, the conductive channels are avoided from occupying a large area in the horizontal direction. Attached Figure Description

[0027] Figure 1 This is a cross-sectional schematic diagram of a semiconductor structure provided in an embodiment of the present invention;

[0028] Figure 2 A schematic cross-sectional view of a semiconductor structure along the AA1 direction provided in an embodiment of the present invention;

[0029] Figure 3 A schematic cross-sectional view of a semiconductor structure along the BB1 ​​direction provided in an embodiment of the present invention;

[0030] Figure 4 A schematic cross-sectional view of a semiconductor structure along the CC1 direction provided in an embodiment of the present invention;

[0031] Figure 5 This is a schematic cross-sectional view of a semiconductor structure along another AA1 direction provided in an embodiment of the present invention;

[0032] Figure 6 This is a schematic cross-sectional view of a semiconductor structure along another BB1 direction provided in an embodiment of the present invention;

[0033] Figure 7 This is a schematic cross-sectional view of a semiconductor structure along another CC1 direction provided in an embodiment of the present invention;

[0034] Figure 8 , Figure 11 , Figure 13 , Figure 15 , Figure 17 , Figure 19 , Figure 21 and Figure 27 A top view schematic diagram of each step in a method for forming a semiconductor structure according to another embodiment of the present invention;

[0035] Figure 9 , Figure 12 , Figure 14 , Figure 16 , Figure 18 , Figure 20 , Figure 22 , Figure 23 and Figure 28 A schematic cross-sectional view of each step in a method for forming a semiconductor structure according to another embodiment of the present invention;

[0036] Figure 10 , Figure 24 , Figure 25 and Figure 26 A method for forming a semiconductor structure according to another embodiment of the present invention is shown in the cross-sectional structure diagram corresponding to the formation of a first conductive layer in a substrate;

[0037] Figures 29-34 This is a schematic cross-sectional view of each step in the method for forming a semiconductor structure according to another embodiment of the present invention. Detailed Implementation

[0038] CFETs enhance device drive current while significantly saving chip area and increasing chip device integration. However, because pFETs and nFETs share a single source or drain connection and their fabrication processes are complex, variable, and difficult to control, current nFETs or pFETs are all horizontally placed GAA transistors. The horizontally positioned conductive channels occupy a large area in the horizontal direction, which limits the development of CFETs.

[0039] To address the aforementioned problems, one embodiment of this application provides a semiconductor structure, including: a substrate, and a conductive channel structure located on the substrate. The conductive channel structure includes a first conductive channel layer, a conductive buffer layer, and a second conductive channel layer stacked sequentially. The first conductive channel layer includes a first conductive channel and a first doped region and a second doped region located at both ends of the first conductive channel, wherein the first doped region is close to the second conductive channel layer. The second conductive channel layer includes a second conductive channel and a third doped region and a fourth doped region located at both ends of the second conductive channel, wherein the third doped region is close to the first conductive channel layer. The conductive buffer layer is used to reduce electrical interference between the first doped region and the third doped region. A first conductive layer is located on the substrate, extends in a first direction, and contacts the second doped region in the first direction. A second conductive layer extends in a second direction and contacts the first doped region and the third doped region in the second direction. A gate structure is disposed around the first conductive channel and the second conductive channel.

[0040] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the various embodiments of this application will be described in detail below with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details are presented in the various embodiments of this application to facilitate a better understanding of the application. However, the technical solutions claimed in this application can be implemented even without these technical details and various variations and modifications based on the following embodiments. The division of the various embodiments below is for ease of description and should not constitute any limitation on the specific implementation of this application. The various embodiments can be combined with and referenced by each other without contradiction.

[0041] Figure 1This is a cross-sectional schematic diagram of the semiconductor structure provided in this embodiment. Figure 2 This is a schematic cross-sectional view of the semiconductor structure along the AA1 direction provided in this embodiment. Figure 3 This is a schematic cross-sectional view of the semiconductor structure along the BB1 ​​direction provided in this embodiment. Figure 4 This is a schematic cross-sectional view of the semiconductor structure along the CC1 direction provided in this embodiment. Figure 5 This is a schematic cross-sectional view of the semiconductor structure along another AA1 direction provided in this embodiment. Figure 6 This is a schematic cross-sectional view of the semiconductor structure along another BB1 direction provided in this embodiment. Figure 7 This is a cross-sectional view of the semiconductor structure provided in this embodiment along the CC1 direction. The semiconductor structure provided in this embodiment will be further described in detail below with reference to the accompanying drawings.

[0042] refer to Figures 1 to 7 Semiconductor structures, including:

[0043] A substrate (unidentified) and a conductive channel structure 500 located on the substrate (unidentified), the conductive channel structure 500 including a first conductive channel layer 501, a conductive buffer layer 502 and a second conductive channel layer 503 stacked sequentially.

[0044] It should be noted that the conductive channel structure 500 located on the substrate can be one or more, with multiple conductive channel structures 500 discretely disposed on the substrate (unmarked); Reference Figure 1 This embodiment uses four conductive channel structures 500 located on a substrate as an example for specific illustration, and does not constitute a limitation on this embodiment. In other embodiments, the conductive channel structure can be one, three, five, etc.; in specific applications, the number of conductive channel structures 500 can be specifically set according to requirements. In addition, in this embodiment, the four conductive channel structures 500 are arranged in a square arrangement.

[0045] Specifically, one of the first conductive channel layer 501 and the second conductive channel layer 503 is an N-type conductive channel, and the other is a P-type conductive channel. In this embodiment, the first conductive channel layer 501 is an N-type conductive channel and the second conductive channel layer 503 is a P-type conductive channel as an example for detailed description, which does not constitute a limitation on this embodiment; in other embodiments, the first conductive channel layer can be a P-type conductive channel and the second conductive channel layer can be an N-type conductive channel as an example for detailed description.

[0046] The first conductive channel layer 501 includes a first conductive channel (unidentified) and a first doped region (unidentified) and a second doped region (unidentified) located at both ends of the first conductive channel (unidentified), wherein the first doped region (unidentified) is close to the second conductive channel layer 503.

[0047] Specifically, the first conductive channel layer 501 is formed by in-situ doping or by deposition followed by doping. The material of the first conductive channel layer 501 is an N-type semiconductor material formed by doping group VA elements into single-crystal silicon. The doping concentration at both ends of the first conductive channel layer 501 is greater than the doping concentration in the middle, thereby forming a first doped region (unidentified) and a second doped region (unidentified). In this embodiment, a detailed description is provided with the second doped region (unidentified) close to the substrate (unidentified) and the first doped region (unidentified) close to the second conductive channel layer 503, which does not constitute a limitation on this embodiment; in other embodiments, the first doped region may be close to the substrate and the second doped region close to the second conductive channel layer.

[0048] The second conductive channel layer 503 includes a second conductive channel (unidentified) and a third doped region (unidentified) and a fourth doped region (unidentified) located at both ends of the second conductive channel (unidentified), wherein the third doped region (unidentified) is close to the first conductive channel layer 501.

[0049] Specifically, the second conductive channel layer 503 is formed by in-situ doping or by deposition followed by doping. The material of the second conductive channel layer 503 is a P-type semiconductor material formed by doping group IIIA elements into single-crystal silicon. The doping concentration at both ends of the second conductive channel layer 503 is greater than the doping concentration in the middle, thereby forming a third doped region (unidentified) and a fourth doped region (unidentified). In this embodiment, the fourth doped region (unidentified) is located away from the substrate (unidentified), and the third doped region (unidentified) is located close to the first conductive channel layer 501, as an example for detailed description. This does not constitute a limitation on this embodiment; in other embodiments, the third doped region may be located away from the substrate, and the fourth doped region may be located close to the first conductive channel layer.

[0050] A conductive buffer layer 502 is located between the first conductive channel layer 501 and the second conductive channel layer 503 to reduce electrical interference between the first doped region (unidentified) and the third doped region (unidentified). In one example, the conductive buffer layer 502 is made of polycrystalline silicon. The conductive buffer layer 502 prevents electrical interference between the first doped region (unidentified) and the third doped region (unidentified) by reducing the dielectric constant between them.

[0051] Continue to refer to Figures 1 to 7 A first conductive layer is located on a substrate (unidentified), extends in a first direction, and is in contact with a second doped region (unidentified) in the first direction. In this embodiment, the material of the first conductive layer is a semiconductor conductive material or a metallic conductive material such as tungsten.

[0052] In this embodiment, the arrangement is described with the first direction being the BB1 ​​direction, which does not constitute a limitation on this embodiment. In other embodiments, the extension direction of the first conductor layer can be determined according to specific needs.

[0053] In addition, the first conductive layer is simultaneously in contact with the second doped regions (unidentified) of all conductive channel structures 500 disposed in the first direction. Specifically, the first conductive layer is simultaneously in contact with the second doped regions (unidentified) of the two conductive channel structures 500 disposed in the first direction, for deriving electrical signals from the second doped regions (unidentified) of the two conductive channel structures 500.

[0054] Specifically, this embodiment provides two implementation methods for the first conductor layer, as follows:

[0055] In one example, refer to Figures 2-4 The substrate (not identified) includes a substrate 101 and an isolation layer 102, with the isolation layer 102 located on the top surface of the substrate 101 and the first conductive layer 201 located on the top surface of the isolation layer 102. In this embodiment, a first barrier layer 211 is also included, located in the plane of the first conductive layer 201, and is formed of an insulating material to improve the stability of the semiconductor structure.

[0056] In another example, refer to Figures 5-7 The substrate (unidentified) includes a substrate 101 and an isolation layer 102. A first conductive layer (unidentified) is located inside the substrate. The isolation layer 102 is located on the top surface of the substrate 101. A first conductive channel layer 501 penetrates the isolation layer 102 and a portion of the substrate 101 to make the second doped region (unidentified) contact the first conductive layer (unidentified).

[0057] In the two examples above, the material of substrate 101 includes silicon, silicon carbide, or gallium arsenide, etc. In this embodiment, substrate 101 is formed of silicon material. The use of silicon material as substrate 101 in this embodiment is to facilitate the understanding of the subsequent formation method by those skilled in the art and does not constitute a limitation. In actual application, the appropriate material of substrate 101 can be selected according to the requirements. In addition, the material of isolation layer 102 is silicon nitride.

[0058] Continue to refer to Figures 1 to 7 The second conductive layer 202 is nested on the conductive channel structure 500 and is in contact with the first doped region (unidentified) and the third doped region (unidentified) in the second direction. In this embodiment, the material of the second conductive layer 202 is a semiconductor conductive material or a metallic conductive material such as tungsten.

[0059] In this embodiment, a second barrier layer 212 is also included, located in the plane of the second conductive layer 202, and is formed of an insulating material to improve the stability of the semiconductor structure.

[0060] Specifically, in this embodiment, the included angle between the extension of the first direction and the second direction is greater than 0 degrees, that is, the first direction and the second direction do not coincide, and there is an angle between the first direction and the second direction, so that the electrical connection of the first conductor layer 201 and the second conductor layer 202 can be realized at different positions.

[0061] In this embodiment, the arrangement is described with the second direction being the CC1 direction, that is, the first direction and the second direction are perpendicular. This does not constitute a limitation on this embodiment. In other embodiments, the extension direction of the second conductor layer 202 can be determined according to specific needs. When there is an angle between the first conductor layer 201 and the second conductor layer 202, it should fall within the protection scope of this application.

[0062] Specifically, the second conductive layer 202 is in contact with the first doped region (unidentified) and the third doped region (unidentified) of all conductive channel structures 500 disposed in the second direction. Specifically, the second conductive layer 202 is simultaneously in contact with the first doped region (unidentified) and the third doped region (unidentified) of the two conductive channel structures 500 disposed in the second direction, for deriving electrical signals from the first doped region (unidentified) and the third doped region (unidentified) of the two conductive channel structures 500.

[0063] Furthermore, in a direction perpendicular to the surface of the substrate (unidentified), the second barrier layer 212 has a sub-connecting hole penetrating the second barrier layer 212 (see reference). Figure 2 or Figure 5 ).

[0064] In this embodiment, the height of the contact surface between the conductive buffer layer 502 and the first doped region (unidentified) is lower than the height of the center thickness position of the second conductive layer 202, but higher than the height of the bottom surface of the second conductive layer 202; the height of the contact surface between the conductive buffer layer 502 and the third doped region (unidentified) is higher than the height of the center thickness position of the second conductive layer 202, but lower than the height of the top surface of the second conductive layer 202. By limiting the thickness of the second conductive layer 202, a large contact area is achieved between the second conductive layer 202 and the first and third doped regions (unidentified), thereby ensuring the stability of the electrical connection between the second conductive layer 202 and the first and third doped regions (unidentified).

[0065] Furthermore, the thickness of the conductive buffer layer 502 is less than 1 / 3 of the thickness of the second conductive layer 202. By limiting the thickness of the conductive buffer layer 502, a larger contact area is created between the second conductive layer 202 and the first doped region (unidentified) and the third doped region (unidentified), thereby ensuring the stability of the electrical connection between the second conductive layer 202 and the first doped region (unidentified) and the third doped region (unidentified).

[0066] Continue to refer to Figures 1 to 7 The gate structure 700 is arranged around the first conductive channel (unidentified) and the second conductive channel (unidentified).

[0067] Specifically, the gate structure 700 includes a gate oxide layer 702 and a metal gate layer 701, with the gate oxide layer covering the first conductive channel, the second conductive channel, and the first conductive layer 201 (see reference). Figures 2-4 ) or isolation layer 102 (reference) Figures 5-7 The second conductive layer 202 exposes the surface; the metal gate layer 701 is used to fill the gaps between the gate oxide layers 702, thereby forming the gate structure 700.

[0068] In one example, to prevent electrical crosstalk between the first conductive layer 201 and the second conductive layer 202 and the gate structure 700, the semiconductor structure further includes: a first insulating layer (not shown) surrounding the first conductive layer 201; and a second insulating layer (not shown) surrounding the second conductive layer 202.

[0069] In another example, to protect the top surface of the gate structure 700, the semiconductor structure further includes a protective layer 104, nested on top of all discrete conductive channel structures 500, in contact with a fourth doped region (unidentified), and having a through-hole (reference) in a direction perpendicular to the substrate (unidentified) surface. Figure 2 and Figure 5 The gate structure 700 is also filled with vias.

[0070] In other embodiments, if no first barrier layer fills the plane of the first conductor layer and no second barrier layer fills the plane of the second conductor layer, the gate structure also fills the gap between the plane of the first conductor layer and the plane of the second conductor layer.

[0071] Specifically, the top surface of the protective layer 104 is flush with the top surface of the second conductive channel layer 503 to facilitate the subsequent extraction and encapsulation of electrical signals from the semiconductor structure.

[0072] Continue to refer to Figures 1 to 7 The substrate (unidentified) of the semiconductor structure includes a structural region and an interconnect region, with the interconnect region located around the structural region. An external insulating structure 103 is provided on the substrate (unidentified) of the interconnect region. The first conductive layer 201 and the second conductive layer 202 extend into the external insulating structure 103 of the interconnect region on one side, so as to allow subsequent electrical connection of the first conductive layer 201 and the second conductive layer 202 through the interconnect region.

[0073] Specifically, in this embodiment, the first conductive plug 801 is electrically connected to the first conductive layer 201, the second conductive plug 802 is electrically connected to the second conductive layer 202, the third conductive plug 803 is electrically connected to the fourth doped region (unmarked), and the fourth conductive plug 804 is electrically connected to the gate structure 700, as detailed below:

[0074] If the first conductive layer 201 and the substrate 101 are disposed separately, refer to Figure 2 and Figure 3 The first conductive plug 801 penetrates the outer insulating structure 103 and is electrically connected to the first conductive layer 201. Furthermore, the first conductive plug 801 also penetrates a portion of the first conductive layer 201 to increase the contact area between the first conductive plug 801 and the first conductive layer 201, thereby reducing the contact resistance between the first conductive plug 801 and the first conductive layer 201.

[0075] If the first conductive layer is disposed in the substrate 101, refer to Figure 4 and Figure 5 The first conductive plug 801 penetrates the peripheral insulating structure 103 and the isolation layer 102, and is electrically connected to the first conductive layer in the substrate 101. Furthermore, the first conductive plug 801 also penetrates a portion of the substrate 101 and the first conductive layer to increase the contact area between the first conductive plug 801 and the first conductive layer, thereby reducing the contact resistance between the first conductive plug 801 and the first conductive layer.

[0076] The second conductive plug 802 penetrates a portion of the outer insulating structure 103 and comes into contact with the second wire 202. Furthermore, the second conductive plug 802 also penetrates a portion of the second wire 202 to increase the contact area between the second conductive plug 802 and the second wire 202, thereby reducing the contact resistance between the second conductive plug 802 and the second wire 202.

[0077] The third conductive plug 803 is in contact with the fourth doped region (unidentified). Furthermore, the third conductive plug 803 also extends through a portion of the fourth doped region (unidentified) to increase the contact area between the third conductive plug 803 and the fourth doped region (unidentified), thereby reducing the contact resistance between the third conductive plug 803 and the fourth doped region (unidentified).

[0078] The fourth conductive plug 804 is in contact with the top of the gate structure 700. Furthermore, the fourth conductive plug 804 also penetrates a portion of the gate structure 700 to increase the contact area between the fourth conductive plug 804 and the gate structure 700, thereby reducing the contact resistance between the fourth conductive plug 804 and the gate structure 700.

[0079] Compared to related technologies, the vertically arranged first and second conductive channel layers, i.e., two vertically arranged conductive channels, with the gate structure surrounding the first and second conductive channels in the horizontal direction, avoid the conductive channels occupying a large area in the horizontal direction.

[0080] Another embodiment of this application relates to a method for forming a semiconductor structure, comprising: providing a substrate including a structural region and an interconnect region, the substrate including a substrate, a first conductive layer and an isolation layer, the first conductive layer extending in a first direction; forming a first sacrificial layer on the substrate of the structural region, and forming a peripheral insulating structure on the substrate of the interconnect region; forming a second conductive layer on the first sacrificial layer, the second conductive layer extending into the peripheral insulating structure of the interconnect region, and the second conductive layer extending in a second direction; sequentially forming a second sacrificial layer and a protective layer on the substrate of the structural region; patterning the protective layer, the second sacrificial layer and the first sacrificial layer to form an opening, and filling the opening to form a conductive channel structure; patterning a portion of the protective layer until the second sacrificial layer is exposed, removing the second sacrificial layer and the first sacrificial layer; and forming a gate structure with a gap filled.

[0081] Figure 8 , Figure 11 , Figure 13 , Figure 15 , Figure 17 , Figure 19 , Figure 21 and Figure 27 This is a top view schematic diagram of each step in the semiconductor structure formation method provided in this embodiment. Figure 9 , Figure 12 , Figure 14 , Figure 16 , Figure 18 , Figure 20 , Figure 22 , Figure 23 and Figure 28 This is a schematic cross-sectional view of each step in the semiconductor structure formation method provided in this embodiment. Figure 10 , Figure 24 , Figure 25 and Figure 26 The semiconductor structure formation method provided in this embodiment is based on a cross-sectional structural diagram corresponding to the formation of the first conductive layer in the substrate. The semiconductor structure formation method provided in this embodiment will be described in detail below with reference to the accompanying drawings. The parts that are the same as or corresponding to those in the above embodiment will not be described in detail below.

[0082] refer to Figures 8-10 A substrate (unidentified) is provided, comprising a structural region and an interconnect region. The substrate (unidentified) includes a substrate 101, a first conductive layer 201, and an isolation layer 102, wherein the first conductive layer 201 extends in a first direction.

[0083] In one example, refer to Figure 9 The substrate (not identified) includes a structural region and an interconnect region, comprising: providing a substrate 101 including a structural region and an interconnect region, forming an isolation layer 102 on the substrate 101 of the structural region, and forming a first conductive layer 201 on the isolation layer 102.

[0084] It should be noted that, in this embodiment, a first barrier layer 211 is formed on the plane of the first conductive layer 201. The first barrier layer 211 is formed of an insulating material to improve the stability of the semiconductor structure.

[0085] In another example, refer to Figure 10 The substrate (not shown) includes a structural region and an interconnect region, comprising: providing a substrate 101 including the structural region and the interconnect region, doping the substrate 101 of the structural region to form a first conductive layer (not shown), and forming an isolation layer 102 on the substrate 101 of the structural region.

[0086] In this embodiment, the substrate 101 is made of materials such as silicon, silicon carbide, or gallium arsenide. In this embodiment, the substrate 101 is formed of silicon material. The use of silicon material as the substrate 101 in this embodiment is to facilitate the understanding of the subsequent formation method by those skilled in the art and does not constitute a limitation. In actual application, a suitable material for the substrate 101 can be selected according to the requirements. In addition, the material of the isolation layer 102 is silicon nitride. The first conductive layer 201 is formed of semiconductor conductive material or metal conductive material, such as doped silicon or tungsten.

[0087] refer to Figure 11 and Figure 12 A first sacrificial layer 301 is formed on the substrate (unidentified) of the structural region, and a peripheral insulation structure 103 (see reference) is formed on the substrate (unidentified) of the interconnecting region. Figure 13 A second conductor layer 202 is formed on the first sacrificial layer 301, wherein the second conductor layer 202 extends in the second direction.

[0088] It should be noted that, in this embodiment, a second barrier layer 212 is also formed on the plane where the second conductive layer 202 is located. The second barrier layer 212 is formed of an insulating material to improve the stability of the semiconductor structure.

[0089] It should be noted that in this embodiment, the first conductor layer 201 and the second conductor layer 202 are arranged vertically, which does not constitute a limitation on this embodiment. In other embodiments, it is only ensured that there is an included angle between the first conductor layer 201 and the second conductor layer 202, which are all within the protection scope of this application.

[0090] In this embodiment, the first sacrificial layer 301 is formed by spin coating. Selective coating offers a fast deposition rate, allowing for the deposition of a relatively thick first sacrificial layer 301 in a shorter time. Furthermore, the first sacrificial layer 301 is formed using a carbon- or oxygen-containing semiconductor material, and can be subsequently removed by ashing or dry etching without affecting other structures. Additionally, the second conductive layer 202 is formed from a semiconductor conductive material or a metallic conductive material, such as doped silicon or tungsten.

[0091] Combination Figure 13 and Figure 14 The second conductive layer 202 extends into the peripheral insulation structure 103 of the interconnection area. Specifically, the first conductive layer 201 also extends into the peripheral insulation structure 103 of the interconnection area.

[0092] Preferably, the first conductive layer 201 extends into the peripheral insulation structure 103 on the first side of the interconnect region, and the second conductive layer 202 extends into the peripheral insulation structure 103 on the second side of the interconnect region. The first and second sides of the interconnect region are located on different sides of the structural region. The first conductive layer 201 and the second conductive layer 202 extend in different directions, thereby enabling the electrical signals of the first conductive layer 201 and the second conductive layer 202 to be derived from the interconnect regions on different sides of the structural region, further reducing the horizontal area of ​​the semiconductor structure.

[0093] refer to Figure 15 and Figure 16 A protective layer 104 of a second sacrificial layer 302 is sequentially formed on the substrate (unidentified) of the structural region.

[0094] In this embodiment, the second sacrificial layer 302 is formed by spin coating. Selective coating offers a fast deposition rate, allowing for the deposition of a thicker second sacrificial layer 302 in a shorter time. Furthermore, the second sacrificial layer 302 is formed using a carbon- or oxygen-containing semiconductor material, and the first sacrificial layer can be removed subsequently by ashing or dry etching without affecting other structures. Additionally, the protective layer 104 is made of silicon nitride.

[0095] refer to Figure 17 Similar to 18, a patterned protective layer 104, a second sacrificial layer 302, a second conductive layer 202, and a first sacrificial layer 301 form an opening 401. Further, in this embodiment, a portion of the first conductive layer 201 is patterned to increase the surface area of ​​the first conductive layer 201 exposed by the opening 401.

[0096] The patterning method includes, but is not limited to: forming a mask layer on the protective layer 104, and then performing a process to pattern the aforementioned semiconductor structure based on the formed mask layer. Furthermore, the patterned opening 401 can be one or multiple, with multiple openings discretely disposed on the substrate (not shown); see reference. Figure 15 This embodiment uses the example of four graphically formed openings 401 for specific illustration, and does not constitute a limitation on this embodiment. In other embodiments, the graphically formed openings can be one, three, five, etc.; in specific applications, the number of graphically formed openings 401 can be specifically set according to requirements. In addition, in this embodiment, the four openings are arranged in a square arrangement.

[0097] refer to Figure 19 and Figure 20 This forms a conductive channel structure 500 that fills the opening 401.

[0098] Specifically, the conductive channel structure 500 includes a first conductive channel layer 501, a conductive buffer layer 502, and a second conductive channel layer 503 stacked sequentially.

[0099] The first conductive channel layer 501 includes a first conductive channel (unidentified) and a first doped region (unidentified) and a second doped region (unidentified) located at both ends of the first conductive channel (unidentified), wherein the first doped region (unidentified) is close to the second conductive channel layer 503.

[0100] Specifically, the first conductive channel layer 501 is formed by in-situ doping or by deposition followed by doping. The material of the first conductive channel layer 501 is an N-type semiconductor material formed by doping group VA elements into single-crystal silicon. The doping concentration at both ends of the first conductive channel layer 501 is greater than the doping concentration in the middle, thereby forming a first doped region (unidentified) and a second doped region (unidentified). In this embodiment, a detailed description is provided with the second doped region (unidentified) close to the substrate (unidentified) and the first doped region (unidentified) close to the second conductive channel layer 503, which does not constitute a limitation on this embodiment; in other embodiments, the first doped region may be close to the substrate and the second doped region close to the second conductive channel layer.

[0101] The second conductive channel layer 503 includes a second conductive channel (unidentified) and a third doped region (unidentified) and a fourth doped region (unidentified) located at both ends of the second conductive channel (unidentified), wherein the third doped region (unidentified) is close to the first conductive channel layer 501.

[0102] Specifically, the second conductive channel layer 503 is formed by in-situ doping or by deposition followed by doping. The material of the second conductive channel layer 503 is a P-type semiconductor material formed by doping group IIIA elements into single-crystal silicon. The doping concentration at both ends of the second conductive channel layer 503 is greater than the doping concentration in the middle, thereby forming a third doped region (unidentified) and a fourth doped region (unidentified). In this embodiment, the fourth doped region (unidentified) is located away from the substrate (unidentified), and the third doped region (unidentified) is located close to the first conductive channel layer 501, as an example for detailed description. This does not constitute a limitation on this embodiment; in other embodiments, the third doped region may be located away from the substrate, and the fourth doped region may be located close to the first conductive channel layer.

[0103] It should be noted that one of the first conductive channel layer 501 and the second conductive channel layer 503 is an N-type conductive channel, and the other is a P-type conductive channel. In this embodiment, the first conductive channel layer 501 is an N-type conductive channel and the second conductive channel layer 503 is a P-type conductive channel for detailed description, which does not constitute a limitation on this embodiment; in other embodiments, the first conductive channel layer can be a P-type conductive channel and the second conductive channel layer can be an N-type conductive channel for detailed description.

[0104] A conductive buffer layer 502 is located between the first conductive channel layer 501 and the second conductive channel layer 503 to reduce electrical interference between the first doped region (unidentified) and the third doped region (unidentified). In one example, the conductive buffer layer 502 is made of polycrystalline silicon. The conductive buffer layer 502 prevents electrical interference between the first doped region (unidentified) and the third doped region (unidentified) by reducing the dielectric constant between them.

[0105] refer to Figures 21-23 The graphical portion of the protective layer 104 is extended until the second sacrificial layer 302 is no longer exposed, forming a connecting hole 602, and the second sacrificial layer is removed based on the connecting hole 602; the graphical portion of the second blocking layer 212 is extended until the first sacrificial layer 301 is exposed, forming a sub-connecting hole 601, and the first sacrificial layer 301 is removed based on the sub-connecting hole 601.

[0106] The patterning method includes, but is not limited to: forming a mask layer on the protective layer 104, and then implementing the process of patterning the above-mentioned semiconductor structure based on the formed mask layer.

[0107] In this embodiment, wet etching is used to remove the first sacrificial layer 301 and the second sacrificial layer 302. Those skilled in the art will understand that wet etching is used to etch a specific semiconductor material without affecting other semiconductor structures. In other embodiments, ashing can be used to remove the first and second sacrificial layers. The ashing process has a faster removal rate for the first and second sacrificial layers and does not affect other semiconductor structures.

[0108] In other embodiments, if there is no first barrier layer 211 filling the plane of the first conductor layer 201, and no second barrier layer 212 filling the plane of the second conductor layer 202, refer to Figures 24-26 The graphical part of the protective layer 104 is processed until the second sacrificial layer 302 is exposed, and then the second sacrificial layer 302 and the first sacrificial layer 301 are removed.

[0109] refer to Figure 27 and Figure 28 A gate structure 700 is formed to fill the gaps.

[0110] Specifically, the gate structure 700 includes a gate oxide layer 702 and a metal gate layer 701, with the gate oxide layer covering the first conductive channel, the second conductive channel, and the first conductive layer 201 (see reference). Figures 2-4 ) or isolation layer 102 (reference) Figures 5-7 The second conductive layer 202 exposes the surface; the metal gate layer 701 is used to fill the gaps between the gate oxide layers 702, thereby forming the gate structure 700.

[0111] In one example, to prevent electrical crosstalk between the first conductive layer 201 and the second conductive layer 202 and the gate structure 700, the formation of the above semiconductor structure further includes: forming a first insulating layer (not shown) between the first conductive layer 201 and the gate structure 700; and forming a second insulating layer (not shown) between the second conductive layer 202 and the gate structure 700.

[0112] refer to Figures 1 to 7 (using the substrate as a reference for the first conductor layer) Figures 5-7 This forms a first conductive plug 801 electrically connected to the first conductive layer 201, a second conductive plug 802 electrically connected to the second conductive layer 202, a third conductive plug 803 electrically connected to the fourth doped region (unidentified), and a fourth conductive plug 804 electrically connected to the gate structure 700. Specifically:

[0113] If the first conductive layer 201 and the substrate 101 are disposed separately, refer to Figure 2 and Figure 3The first conductive plug 801 penetrates the outer insulating structure 103 and is electrically connected to the first conductive layer 201. Furthermore, the first conductive plug 801 also penetrates a portion of the first conductive layer 201 to increase the contact area between the first conductive plug 801 and the first conductive layer 201, thereby reducing the contact resistance between the first conductive plug 801 and the first conductive layer 201.

[0114] If the first conductive layer is disposed in the substrate 101, refer to Figure 4 and Figure 5 The first conductive plug 801 penetrates the peripheral insulating structure 103 and the isolation layer 102, and is electrically connected to the first conductive layer in the substrate 101. Furthermore, the first conductive plug 801 also penetrates a portion of the substrate 101 and the first conductive layer to increase the contact area between the first conductive plug 801 and the first conductive layer, thereby reducing the contact resistance between the first conductive plug 801 and the first conductive layer.

[0115] The second conductive plug 802 penetrates a portion of the peripheral insulation structure 103 and contacts the second conductive layer 202. Furthermore, the second conductive plug 802 also penetrates a portion of the second conductive layer 202 to increase the contact area between the second conductive plug 802 and the second conductive layer 202, thereby reducing the contact resistance between the second conductive plug 802 and the second conductive layer 202.

[0116] The third conductive plug 803 is in contact with the fourth doped region (unidentified). Furthermore, the third conductive plug 803 also extends through a portion of the fourth doped region (unidentified) to increase the contact area between the third conductive plug 803 and the fourth doped region (unidentified), thereby reducing the contact resistance between the third conductive plug 803 and the fourth doped region (unidentified).

[0117] The fourth conductive plug 804 is in contact with the top of the gate structure 700. Furthermore, the fourth conductive plug 804 also penetrates a portion of the gate structure 700 to increase the contact area between the fourth conductive plug 804 and the gate structure 700, thereby reducing the contact resistance between the fourth conductive plug 804 and the gate structure 700.

[0118] Compared to related technologies, by forming a vertically arranged first conductive channel layer and a second conductive channel layer, that is, forming two vertically arranged conductive channels, and the gate structure surrounds the first conductive channel and the second conductive channel in the horizontal direction, the conductive channels are avoided from occupying a large area in the horizontal direction.

[0119] The various steps described above are only for clarity. In practice, they can be combined into one step or some steps can be broken down into multiple steps. As long as they include the same logical relationship, they are all within the scope of protection of this patent. Adding insignificant modifications or introducing insignificant designs to the process, but without changing the core design of the process, are also within the scope of protection of this patent.

[0120] Since the above embodiments correspond to this embodiment, this embodiment can be implemented in conjunction with the above embodiments. The relevant technical details mentioned in the above embodiments remain valid in this embodiment, and the technical effects achievable in the above embodiments can also be achieved in this embodiment. To reduce repetition, they will not be repeated here. Correspondingly, the relevant technical details mentioned in this embodiment can also be applied to the above embodiments.

[0121] Another embodiment of this application relates to a method for forming a semiconductor structure, comprising: providing a substrate including a structural region and an interconnect region, the substrate including a substrate, a first conductive layer and an isolation layer, the first conductive layer extending in a first direction; forming a first sacrificial layer on the substrate of the structural region, and forming a peripheral insulating structure on the substrate of the interconnect region; patterning the first sacrificial layer to form a first channel penetrating the first sacrificial layer; forming a second conductive layer filling the first channel and partially located on the first sacrificial layer, the second conductive layer extending into the peripheral insulating structure of the interconnect region, and the second conductive layer extending in a second direction; sequentially forming a second sacrificial layer and a protective layer on the substrate of the structural region; patterning the second sacrificial layer to form a second channel penetrating the second sacrificial layer, the projections of the first channel and the second channel on the substrate coinciding; forming a second conductive channel layer filling the second channel; patterning a portion of the protective layer until the second sacrificial layer is exposed, removing the second sacrificial layer and the first sacrificial layer; and forming a gate structure filling a gap. Compared to the previous embodiment, this embodiment forms the conductive channel structure in different steps. Compared to a conductive channel structure formed in one step, the required depth-to-width ratio of the trench to be filled is smaller, thereby ensuring that the formed conductive channel structure has good compactness.

[0122] Figures 29-34 The accompanying drawings are cross-sectional structural diagrams corresponding to each step in the semiconductor structure formation method provided in this embodiment. The semiconductor structure formation method provided in this embodiment will be described in detail below with reference to the accompanying drawings. The parts that are the same as or corresponding to those in the above embodiment will not be described in detail below.

[0123] refer to Figure 8 and Figure 29 A substrate (unidentified) is provided, comprising a structural region and an interconnect region. The substrate (unidentified) includes a substrate 101, a first conductive layer 201, and an isolation layer 102.

[0124] refer to Figure 30A first sacrificial layer 301 is formed on the substrate (unidentified) of the structural region.

[0125] refer to Figure 31 An outer insulating structure 103 is formed on the base (unmarked) of the connecting area, a first sacrificial layer 301 is patterned, and a first channel 402 is formed through the first sacrificial layer.

[0126] The patterning method includes, but is not limited to: forming a mask layer on the first sacrificial layer 301, and then performing a process to pattern the aforementioned semiconductor structure based on the formed mask layer. Furthermore, the patterned first channel 402 can be one or multiple, with multiple openings discretely disposed on a substrate (not shown); see reference. Figure 31 This embodiment uses the graphically formed four first channels 402 as an example for specific explanation, and does not constitute a limitation on this embodiment. In other embodiments, the graphically formed openings can be 1, 3, 5, etc.; in specific applications, the number of graphically formed first channels 402 can be specifically set according to requirements. In addition, in this embodiment, the four openings are arranged in a square arrangement.

[0127] refer to Figure 32 A second conductive layer 202 is formed on the first sacrificial layer 301, filling the first channel 402 and covering it. The second conductive layer 202 extends into the peripheral insulation structure 103 of the interconnection area, wherein the second conductive layer 202 filling the first channel 402 serves as the first conductive channel layer 501.

[0128] The first conductive channel layer 501 includes a first conductive channel (unidentified) and a first doped region (unidentified) and a second doped region (unidentified) located at both ends of the first conductive channel (unidentified), wherein the first doped region (unidentified) is close to the second conductive channel layer 503.

[0129] Specifically, the first conductive channel layer 501 is formed by in-situ doping or by deposition followed by doping. The material of the first conductive channel layer 501 is an N-type semiconductor material formed by doping group VA elements into single-crystal silicon. The doping concentration at both ends of the first conductive channel layer 501 is greater than the doping concentration in the middle, thereby forming a first doped region (unidentified) and a second doped region (unidentified). In this embodiment, a detailed description is provided with the second doped region (unidentified) close to the substrate (unidentified) and the first doped region (unidentified) close to the second conductive channel layer 503, which does not constitute a limitation on this embodiment; in other embodiments, the first doped region may be close to the substrate and the second doped region close to the second conductive channel layer.

[0130] refer to Figure 33A second sacrificial layer 302 and a protective layer 104 are sequentially formed on the substrate (unidentified) of the structural region; the second sacrificial layer 302 is patterned to form a second channel 403 that penetrates the second sacrificial layer 302, and the projections of the first channel 402 and the second channel 403 on the substrate coincide.

[0131] The patterning method includes, but is not limited to: forming a mask layer on the second sacrificial layer 302, and then performing a process to pattern the aforementioned semiconductor structure based on the formed mask layer. Furthermore, the patterned second channel 403 can be one or multiple, with multiple openings discretely disposed on a substrate (not shown); see reference. Figure 33 This embodiment uses the example of four graphically formed second channels 403 for specific illustration, and does not constitute a limitation on this embodiment. In other embodiments, the graphically formed openings can be 1, 3, 5, etc.; in specific applications, the number of graphically formed first channels 402 can be specifically set according to requirements. In addition, in this embodiment, the projections of the first channel 402 and the second channel 403 on the substrate coincide; in other embodiments, the first channel and the second channel can be arbitrarily set.

[0132] refer to Figure 34 This forms a conductive buffer layer 502 and a second conductive channel layer 503 that fill the second channel.

[0133] The second conductive channel layer 503 includes a second conductive channel (unidentified) and a third doped region (unidentified) and a fourth doped region (unidentified) located at both ends of the second conductive channel (unidentified), wherein the third doped region (unidentified) is close to the first conductive channel layer 501.

[0134] Specifically, the second conductive channel layer 503 is formed by in-situ doping or by deposition followed by doping. The material of the second conductive channel layer 503 is a P-type semiconductor material formed by doping group IIIA elements into single-crystal silicon. The doping concentration at both ends of the second conductive channel layer 503 is greater than the doping concentration in the middle, thereby forming a third doped region (unidentified) and a fourth doped region (unidentified). In this embodiment, the fourth doped region (unidentified) is located away from the substrate (unidentified), and the third doped region (unidentified) is located close to the first conductive channel layer 501, as an example for detailed description. This does not constitute a limitation on this embodiment; in other embodiments, the third doped region may be located away from the substrate, and the fourth doped region may be located close to the first conductive channel layer.

[0135] It should be noted that one of the first conductive channel layer 501 and the second conductive channel layer 503 is an N-type conductive channel, and the other is a P-type conductive channel. In this embodiment, the first conductive channel layer 501 is an N-type conductive channel and the second conductive channel layer 503 is a P-type conductive channel for detailed description, which does not constitute a limitation on this embodiment; in other embodiments, the first conductive channel layer can be a P-type conductive channel and the second conductive channel layer can be an N-type conductive channel for detailed description.

[0136] A conductive buffer layer 502 is located between the first conductive channel layer 501 and the second conductive channel layer 503 to reduce electrical interference between the first doped region (unidentified) and the third doped region (unidentified). In one example, the conductive buffer layer 502 is made of polycrystalline silicon. The conductive buffer layer 502 prevents electrical interference between the first doped region (unidentified) and the third doped region (unidentified) by reducing the dielectric constant between them.

[0137] refer to Figures 21-23 The graphical portion of the protective layer 104 is extended until the second sacrificial layer 302 is no longer exposed, forming a connecting hole 602, and the second sacrificial layer is removed based on the connecting hole 602; the graphical portion of the second blocking layer 212 is extended until the first sacrificial layer 301 is exposed, forming a sub-connecting hole 601, and the first sacrificial layer 301 is removed based on the sub-connecting hole 601.

[0138] The patterning method includes, but is not limited to: forming a mask layer on the protective layer 104, and then implementing the process of patterning the above-mentioned semiconductor structure based on the formed mask layer.

[0139] In this embodiment, wet etching is used to remove the first sacrificial layer 301 and the second sacrificial layer 302. Those skilled in the art will understand that wet etching is used to etch a specific semiconductor material without affecting other semiconductor structures. In other embodiments, ashing can be used to remove the first and second sacrificial layers. The ashing process has a faster removal rate for the first and second sacrificial layers and does not affect other semiconductor structures.

[0140] In other embodiments, if there is no first barrier layer 211 filling the plane of the first conductor layer 201, and no second barrier layer 212 filling the plane of the second conductor layer 202, refer to Figures 24-26 The graphical part of the protective layer 104 is processed until the second sacrificial layer 302 is exposed, and then the second sacrificial layer 302 and the first sacrificial layer 301 are removed.

[0141] refer to Figure 27 and Figure 28 A gate structure 700 is formed to fill the gaps.

[0142] Specifically, the gate structure 700 includes a gate oxide layer 702 and a metal gate layer 701, with the gate oxide layer covering the first conductive channel, the second conductive channel, and the first conductive layer 201 (see reference). Figures 2-4 ) or isolation layer 102 (reference) Figures 5-7 The second conductive layer 202 exposes the surface; the metal gate layer 701 is used to fill the gaps between the gate oxide layers 702, thereby forming the gate structure 700.

[0143] In one example, to prevent electrical crosstalk between the first conductive layer 201 and the second conductive layer 202 and the gate structure 700, the formation of the above semiconductor structure further includes: forming a first insulating layer (not shown) between the first conductive layer 201 and the gate structure 700; and forming a second insulating layer (not shown) between the second conductive layer 202 and the gate structure 700.

[0144] refer to Figures 1 to 7 (using the substrate as a reference for the first conductor layer) Figures 5-7 This forms a first conductive plug 801 electrically connected to the first conductive layer 201, a second conductive plug 802 electrically connected to the second conductive layer 202, a third conductive plug 803 electrically connected to the fourth doped region (unidentified), and a fourth conductive plug 804 electrically connected to the gate structure 700. Specifically:

[0145] If the first conductive layer 201 and the substrate 101 are disposed separately, refer to Figure 2 and Figure 3 The first conductive plug 801 penetrates the outer insulating structure 103 and is electrically connected to the first conductive layer 201. Furthermore, the first conductive plug 801 also penetrates a portion of the first conductive layer 201 to increase the contact area between the first conductive plug 801 and the first conductive layer 201, thereby reducing the contact resistance between the first conductive plug 801 and the first conductive layer 201.

[0146] If the first conductive layer is disposed in the substrate 101, refer to Figure 4 and Figure 5 The first conductive plug 801 penetrates the peripheral insulating structure 103 and the isolation layer 102, and is electrically connected to the first conductive layer in the substrate 101. Furthermore, the first conductive plug 801 also penetrates a portion of the substrate 101 and the first conductive layer to increase the contact area between the first conductive plug 801 and the first conductive layer, thereby reducing the contact resistance between the first conductive plug 801 and the first conductive layer.

[0147] The second conductive plug 802 penetrates a portion of the peripheral insulation structure 103 and contacts the second conductive layer 202. Furthermore, the second conductive plug 802 also penetrates a portion of the second conductive layer 202 to increase the contact area between the second conductive plug 802 and the second conductive layer 202, thereby reducing the contact resistance between the second conductive plug 802 and the second conductive layer 202.

[0148] The third conductive plug 803 is in contact with the fourth doped region (unidentified). Furthermore, the third conductive plug 803 also extends through a portion of the fourth doped region (unidentified) to increase the contact area between the third conductive plug 803 and the fourth doped region (unidentified), thereby reducing the contact resistance between the third conductive plug 803 and the fourth doped region (unidentified).

[0149] The fourth conductive plug 804 is in contact with the top of the gate structure 700. Furthermore, the fourth conductive plug 804 also penetrates a portion of the gate structure 700 to increase the contact area between the fourth conductive plug 804 and the gate structure 700, thereby reducing the contact resistance between the fourth conductive plug 804 and the gate structure 700.

[0150] Compared to related technologies, by forming a vertically arranged first conductive channel layer and a second conductive channel layer, that is, forming two vertically arranged conductive channels, and the gate structure surrounds the first conductive channel and the second conductive channel in the horizontal direction, the conductive channels are avoided from occupying a large area in the horizontal direction.

[0151] The various steps described above are only for clarity. In practice, they can be combined into one step or some steps can be broken down into multiple steps. As long as they include the same logical relationship, they are all within the scope of protection of this patent. Adding insignificant modifications or introducing insignificant designs to the process, but without changing the core design of the process, are also within the scope of protection of this patent.

[0152] Since the above embodiments correspond to this embodiment, this embodiment can be implemented in conjunction with the above embodiments. The relevant technical details mentioned in the above embodiments remain valid in this embodiment, and the technical effects achievable in the above embodiments can also be achieved in this embodiment. To reduce repetition, they will not be repeated here. Correspondingly, the relevant technical details mentioned in this embodiment can also be applied to the above embodiments.

[0153] Those skilled in the art will understand that the above embodiments are specific embodiments for implementing this application, and in practical applications, various changes can be made to them in form and detail without departing from the spirit and scope of this application.

Claims

1. A semiconductor structure, characterized in that, include: A substrate, and a conductive channel structure located on the substrate, the conductive channel structure comprising a first conductive channel layer, a conductive buffer layer and a second conductive channel layer stacked sequentially; The first conductive channel layer includes a first conductive channel and a first doped region and a second doped region located at both ends of the first conductive channel, wherein the first doped region is close to the second conductive channel layer; The second conductive channel layer includes a second conductive channel and a third doped region and a fourth doped region located at both ends of the second conductive channel, wherein the third doped region is close to the first conductive channel layer; The conductive buffer layer is used to reduce electrical interference between the first doped region and the third doped region; A first conductive layer is located on the substrate, extends in a first direction, and is in contact with the second doped region in the first direction; The second conductive layer extends in the second direction and is in contact with the first doped region and the third doped region in the second direction; A gate structure is disposed around the first conductive channel and the second conductive channel; A fourth conductive plug, the fourth conductive plug being electrically connected to the gate structure surrounding the first conductive channel and the second conductive channel.

2. The semiconductor structure according to claim 1, characterized in that, The conductive channel structure is discretely disposed on the substrate; The first conductive layer is in contact with the second doped region of all the conductive channel structures disposed in the first direction; The second conductive layer is in contact with the first doped region and the third doped region of all the conductive channel structures provided in the second direction; The gate structure also fills the gaps in the plane where the first conductor layer is located and the plane where the second conductor layer is located.

3. The semiconductor structure according to claim 1 or 2, characterized in that, The substrate includes a structural region and a connecting region, wherein the connecting region is disposed around the structural region; An outer insulation structure is provided on the base of the connection area, and the first conductor layer and the second conductor layer extend into the outer insulation structure of the connection area; It also includes: a first conductive plug and a second conductive plug; The first conductive plug penetrates the outer insulating structure and contacts the first conductor layer; The second conductive plug penetrates the outer insulating structure and contacts the second conductive layer.

4. The semiconductor structure according to claim 3, characterized in that, The angle between the extensions of the first direction and the second direction is greater than 0°.

5. The semiconductor structure according to claim 3, characterized in that, Also includes: The third conductive plug is in contact with the fourth doped region; The fourth conductive plug is in contact with the top of the gate structure.

6. The semiconductor structure according to claim 1, characterized in that, include: The height of the contact surface between the conductive buffer layer and the first doped region is lower than the height of the center thickness of the second conductive layer, but higher than the height of the bottom surface of the second conductive layer. The height of the contact surface between the conductive buffer layer and the first doped region is higher than the height of the center thickness of the second conductive layer, but lower than the height of the top surface of the second conductive layer.

7. The semiconductor structure according to claim 6, characterized in that, The thickness of the conductive buffer layer is less than 1 / 3 of the thickness of the second conductor layer.

8. The semiconductor structure according to claim 1, characterized in that, The substrate includes a substrate and an isolation layer, the first conductive layer is located within the substrate, the isolation layer is located on the top surface of the substrate, and the first conductive channel layer penetrates the isolation layer and a portion of the substrate to make the second doped region contact the first conductive layer.

9. The semiconductor structure according to claim 1, characterized in that, The substrate includes a substrate and an isolation layer, the isolation layer being located on the top surface of the substrate, and the first conductive layer being located on the top surface of the isolation layer.

10. The semiconductor structure according to claim 9, characterized in that, Also includes: A first insulating layer is disposed surrounding the first conductor layer.

11. The semiconductor structure according to claim 1, characterized in that, Also includes: A second insulating layer is disposed surrounding the second conductor layer.

12. The semiconductor structure according to claim 1, characterized in that, Also includes: A protective layer, nested on top of all the discrete conductive channel structures and in contact with the fourth doped region, has a through-hole in a direction perpendicular to the substrate surface, and the gate structure also fills the through-hole.

13. The semiconductor structure according to claim 12, characterized in that, The top surface of the protective layer is flush with the top surface of the second conductive channel layer.

14. The semiconductor structure according to claim 1, characterized in that, One of the first conductive channel layer and the second conductive channel layer is an N-type conductive channel, and the other is a P-type conductive channel.

15. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided that includes a structural region and an interconnect region, the substrate including a substrate, a first conductive layer and an isolation layer, the first conductive layer extending in a first direction; A first sacrificial layer is formed on the substrate of the structural region, and a peripheral insulating structure is formed on the substrate of the interconnection region; The first sacrificial layer is graphically represented to form a first channel penetrating the first sacrificial layer; A second conductive layer is formed to fill the first channel and is partially located on the first sacrificial layer. The second conductive layer extends into the peripheral insulation structure of the interconnect region and extends in a second direction. A second sacrificial layer and a protective layer are sequentially formed on the substrate of the structural region; The second sacrificial layer is graphically represented to form a channel penetrating the second sacrificial layer and a second channel, wherein the projections of the first channel and the second channel on the substrate coincide. A second conductive channel layer is formed to fill the second channel; The graphical portion describes the protective layer until the second sacrificial layer is exposed, then the second sacrificial layer and the first sacrificial layer are removed; A gate structure is formed to fill the voids.

16. The method for forming a semiconductor structure according to claim 15, characterized in that, Providing a substrate including a structural region and an interconnect region includes: providing a substrate including a structural region and an interconnect region, forming an isolation layer on the substrate including the structural region, and forming a first conductive layer on the isolation layer.

17. The method for forming a semiconductor structure according to claim 15, characterized in that, Providing a substrate including a structural region and an interconnect region includes: providing a substrate including a structural region and an interconnect region, doping the substrate in the structural region to form the first conductive layer, and forming the isolation layer on the substrate in the structural region.

18. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided that includes a structural region and an interconnect region, the substrate including a substrate, a first conductive layer and an isolation layer, the first conductive layer extending in a first direction; A first sacrificial layer is formed on the substrate of the structural region, and a peripheral insulating structure is formed on the substrate of the interconnection region; A second conductive layer is formed on the first sacrificial layer, the second conductive layer extending into the peripheral insulation structure of the interconnection area, and the second conductive layer extending in a second direction; A second sacrificial layer and a protective layer are sequentially formed on the substrate of the structural region; The protective layer, the second sacrificial layer, and the first sacrificial layer are graphically represented to form an opening, and the opening is filled to form a conductive channel structure; The graphical portion describes the protective layer until the second sacrificial layer is exposed, then the second sacrificial layer and the first sacrificial layer are removed; A gate structure is formed to fill the voids.

19. The method for forming a semiconductor structure according to claim 18, characterized in that, Providing a substrate including a structural region and an interconnect region includes: providing a substrate including a structural region and an interconnect region, forming an isolation layer on the substrate including the structural region, and forming a first conductive layer on the isolation layer.

20. The method for forming a semiconductor structure according to claim 18, characterized in that, Providing a substrate including a structural region and an interconnect region includes: providing a substrate including a structural region and an interconnect region, doping the substrate in the structural region to form the first conductive layer, and forming the isolation layer on the substrate in the structural region.

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