Memory processing method and device, memory management system, electronic equipment and chip

Abstract

The invention relates to a memory processing method and device, a memory management system, electronic equipment and a chip, and belongs to the technical field of memory management. The method comprises the following steps: in response to a memory processing request, performing memory allocation and memory recovery processing corresponding to the memory processing request by adopting a target memory; wherein the target memory is a memory allocated to target hardware of the electronic equipment by a processor of the electronic equipment; in response to the fact that the first number of idle memories in the target memories is smaller than a first set threshold value, requesting the processor to distribute the idle memories to the target hardware to increase the first number; and in response to the first number being greater than a second set threshold, releasing the idle memory to the processor to reduce the first number. Therefore, the processor can distribute the target memory to the target hardware, the target hardware can respond to the memory processing request, the target memory is adopted for memory distribution and recovery processing, the load of the processor can be remarkably reduced, and the memory processing efficiency is remarkably improved.

Description

Technical Field

[0001] This disclosure relates to the field of memory management technology, and in particular to a memory processing method, apparatus, memory management system, electronic device, chip, and storage medium. Background Technology

[0002] Currently, most memory processing operations (such as memory allocation and deallocation) in electronic devices are performed by processors, such as CPUs (Central Processing Units). Since these operations occur frequently during operation and usually involve complex processing logic, the processor load increases significantly, which in turn affects the overall performance of electronic devices, especially in application scenarios with high concurrency, large data volume, or high real-time requirements. Summary of the Invention

[0003] This disclosure provides a memory processing method, apparatus, memory management system, electronic device, chip, and storage medium to at least solve the problem of high processor load in related technologies. The technical solution of this disclosure is as follows: According to a first aspect of the present disclosure, a memory processing method is provided, comprising: responding to a memory processing request, using target memory to perform memory allocation and memory reclamation processing corresponding to the memory processing request; wherein the target memory is memory allocated by a processor of an electronic device to target hardware of the electronic device; responding to a first amount of free memory in the target memory being less than a first preset threshold, requesting the processor to allocate free memory to the target hardware to increase the first amount; responding to a first amount being greater than a second preset threshold, releasing free memory to the processor to decrease the first amount; wherein the first preset threshold is less than the second preset threshold.

[0004] According to a second aspect of the present disclosure, a memory processing apparatus is provided, comprising: a first processing module configured to, in response to a memory processing request, perform memory allocation and memory reclamation processing corresponding to the memory processing request using target memory; wherein the target memory is memory allocated by a processor of an electronic device to target hardware of the electronic device; a second processing module configured to, in response to a first amount of free memory in the target memory being less than a first preset threshold, request the processor to allocate free memory to the target hardware to increase the first amount; and a third processing module configured to, in response to the first amount being greater than a second preset threshold, release free memory to the processor to decrease the first amount; wherein the first preset threshold is less than the second preset threshold.

[0005] According to a third aspect of the present disclosure, a memory management system is provided, comprising: a processor, target hardware, and target memory; wherein the processor is configured to allocate the target memory to the target hardware; and the target hardware is configured to execute the steps of the memory processing method described in the first aspect of the present disclosure.

[0006] According to a fourth aspect of the present disclosure, an electronic device is provided, including the memory management system described in the third aspect of the present disclosure.

[0007] According to a fifth aspect of the present disclosure, a computer-readable storage medium is provided that stores computer program instructions thereon, which, when executed by a processor, implement the steps of the memory processing method described in the first aspect of the present disclosure.

[0008] According to a sixth aspect of the present disclosure, a chip is provided, the chip including an interface circuit and a processing circuit coupled to each other, the interface circuit being used to input or output signals, and the processing circuit being configured to implement the steps of the memory processing method described in the first aspect of the present disclosure.

[0009] According to a seventh aspect of the present disclosure, a computer program product is provided, including a computer program that, when executed by a processor, implements the steps of the memory processing method described in the first aspect of the present disclosure.

[0010] The technical solution provided by the embodiments of this disclosure brings at least the following beneficial effects: In response to a memory processing request, target memory is used to perform memory allocation and memory reclamation processing corresponding to the memory processing request; wherein, the target memory is the memory allocated by the processor of the electronic device to the target hardware of the electronic device; in response to a first quantity of free memory in the target memory being less than a first preset threshold, the processor is requested to allocate free memory to the target hardware to increase the first quantity; in response to a first quantity being greater than a second preset threshold, free memory is released to the processor to decrease the first quantity. Therefore, this disclosure proposes a memory processing mechanism in which the processor can allocate target memory to the target hardware, and the target hardware can respond to memory processing requests and use the target memory for memory allocation and reclamation processing. This can significantly reduce the processor load and significantly improve memory processing efficiency, helping to improve the overall performance of the electronic device, optimize the user experience, and support unified management of heterogeneous memory.

[0011] In addition, when the initial amount of free memory in the target memory is small, the processor can be requested to allocate free memory to the target hardware to increase the initial amount. That is, when the amount of free memory in the target memory is small, the target hardware can dynamically request the processor to supplement the free memory.

[0012] In addition, when the initial amount of free memory in the target memory is large, the free memory can be released to the processor to reduce the initial amount. That is, when there is a lot of free memory in the target memory, the target hardware can dynamically release free memory to the processor to avoid the target hardware occupying too much free memory.

[0013] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0014] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure, and are not intended to unduly limit this disclosure.

[0015] Figure 1 This is a flowchart illustrating a memory processing method according to an exemplary embodiment.

[0016] Figure 2 This is a flowchart illustrating a memory processing method according to another exemplary embodiment.

[0017] Figure 3 This is a flowchart illustrating a memory processing method according to another exemplary embodiment.

[0018] Figure 4 This is a flowchart illustrating a memory processing method according to another exemplary embodiment.

[0019] Figure 5 This is a flowchart illustrating a memory processing method according to another exemplary embodiment.

[0020] Figure 6 This is a flowchart illustrating a memory processing method according to another exemplary embodiment.

[0021] Figure 7 This is a flowchart illustrating a memory processing method according to another exemplary embodiment.

[0022] Figure 8 This is an interactive schematic diagram illustrating a memory processing method according to an exemplary embodiment.

[0023] Figure 9 This is a schematic diagram of the structure of a hardware device UBM for memory management according to an exemplary embodiment.

[0024] Figure 10 This is a schematic diagram illustrating a memory allocation process according to an exemplary embodiment.

[0025] Figure 11This is a schematic diagram illustrating a memory reclamation process according to an exemplary embodiment.

[0026] Figure 12 This is a schematic diagram illustrating a method for attaching memory requests according to an exemplary embodiment.

[0027] Figure 13 This is a schematic diagram illustrating a method for attaching a memory request according to another exemplary embodiment.

[0028] Figure 14 This is a schematic diagram illustrating a method for attaching a memory request according to another exemplary embodiment.

[0029] Figure 15 This is a schematic diagram illustrating a memory swapping method according to an exemplary embodiment.

[0030] Figure 16 This is a schematic diagram illustrating a memory borrowing process according to an exemplary embodiment.

[0031] Figure 17 This is a schematic diagram illustrating a segmentation information table according to an exemplary embodiment.

[0032] Figure 18 This is a schematic diagram illustrating a memory reclamation process according to another exemplary embodiment.

[0033] Figure 19 This is a schematic diagram illustrating a memory reclamation method according to an exemplary embodiment.

[0034] Figure 20 This is a schematic diagram illustrating a memory reclamation process according to another exemplary embodiment.

[0035] Figure 21 This is a schematic diagram of the structure of a memory processing device according to an exemplary embodiment.

[0036] Figure 22 This is a schematic diagram illustrating the structure of a memory management system according to an exemplary embodiment.

[0037] Figure 23 This is a schematic diagram of the structure of an electronic device according to an exemplary embodiment.

[0038] Figure 24 This is a schematic diagram of the structure of a chip according to an exemplary embodiment. Detailed Implementation

[0039] To enable those skilled in the art to better understand the technical solutions of this disclosure, the technical solutions in the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings.

[0040] It should be noted that the terms "first," "second," etc., used in this disclosure and the accompanying drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this disclosure described herein can be implemented in orders other than those illustrated or described herein. The implementations described in the following exemplary embodiments do not represent all implementations consistent with this disclosure.

[0041] The memory processing method, apparatus, memory management system, electronic device, chip, and storage medium of the present disclosure are described below with reference to the accompanying drawings.

[0042] Figure 1 This is a flowchart illustrating a memory processing method according to an exemplary embodiment, such as... Figure 1 As shown, the memory processing method of this disclosure includes the following steps.

[0043] S101, in response to a memory processing request, performs memory allocation and memory reclamation processing corresponding to the memory processing request using the target memory; wherein, the target memory is the memory allocated by the processor of the electronic device to the target hardware of the electronic device.

[0044] It should be noted that the execution entity of the memory processing method in this embodiment is the target hardware, such as UBM (Unified Buffer Manager), intelligent memory controller, memory allocation accelerator, etc. The memory processing method in this embodiment can be executed by the memory processing device in this embodiment, which can be configured in any target hardware to execute the memory processing method in this embodiment.

[0045] Currently, most memory processing operations (such as memory allocation and deallocation) in electronic devices are performed by processors, such as CPUs (Central Processing Units). Since these operations occur frequently during operation and usually involve complex processing logic, the processor load increases significantly, which in turn affects the overall performance of electronic devices, especially in application scenarios with high concurrency, large data volume, or high real-time requirements.

[0046] In addition, most memory processing operations in electronic devices are performed by system software running on the processor, which results in low memory processing efficiency.

[0047] To address the aforementioned issues, this disclosure proposes a memory processing mechanism in which the processor can allocate target memory to the target hardware, and the target hardware can respond to memory processing requests and use the target memory for memory allocation and reclamation. This can significantly reduce the processor load, help improve the overall performance of electronic devices, optimize the user experience, and support unified management of heterogeneous memory.

[0048] In addition, this disclosure implements hardware-level memory processing through the target hardware, which is different from the memory processing implemented through system software in most related technologies. It can replace software to perform high-frequency memory processing operations with hardware. The hardware has low latency and high throughput characteristics, which can significantly improve memory processing efficiency, such as accelerating memory allocation and recycling, thereby improving the overall performance of electronic devices and optimizing the user experience.

[0049] In this disclosure, the target hardware has management rights over the target memory. The target memory is not limited in many ways; it may include SRAM (Static Random Access Memory) or DRAM (Dynamic Random Access Memory). DRAM includes DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory), which can be abbreviated as DDR.

[0050] It should be noted that the memory allocation and reclamation processes corresponding to the memory processing requests can be implemented using any memory allocation and reclamation method in the relevant technologies, and no further restrictions are imposed here.

[0051] Optionally, the target memory is used to perform memory allocation and memory reclamation processes corresponding to the memory processing requests, including determining the memory allocation requirements of the target functional module based on the memory processing requests, and allocating free memory in the target memory to the target functional module based on the memory allocation requirements.

[0052] It should be noted that any functional module includes memory-using hardware and memory-using applications. There are no strict limitations on memory-using hardware, such as GPU (Graphics Processing Unit), hardware accelerators, input / output controllers and peripherals, etc. Memory-using applications include user-mode applications, drivers, firmware, etc.

[0053] Optionally, based on memory allocation requirements, free memory in the target memory is allocated to the target functional module. This includes dividing the free memory in the target memory into multiple sub-memory blocks based on memory allocation requirements, and allocating at least one sub-memory block to the target functional module. Therefore, by taking memory allocation requirements into account, dividing larger amounts of free memory into blocks and allocating at least one sub-memory block to the target functional module, the direct allocation of larger amounts of free memory to the target functional module can be avoided, thus helping to improve memory resource utilization.

[0054] Optionally, the target memory is used for memory allocation and reclamation corresponding to the memory processing requests. This includes determining the memory reclamation requirements of the target functional modules based on the memory processing requests, and reclaiming the memory in the target memory that has been used by the target functional modules after the memory reclamation requests have been completed. For example, the memory in the target memory that has been used by the target functional modules after the memory is completed is marked as free memory, or the usage status of the memory in the target memory that has been used by the target functional modules after the memory is completed is marked as free.

[0055] S102, in response to the first number of free memory in the target memory being less than a first set threshold, a request is made to the processor to allocate free memory to the target hardware to increase the first number.

[0056] In this disclosure, when the first amount of free memory in the target memory is small, the processor can be requested to allocate free memory to the target hardware to increase the first amount. That is, when the free memory in the target memory is small, the target hardware can dynamically request the processor to supplement the free memory.

[0057] Optionally, requesting the processor to allocate free memory to the target hardware includes sending a third instruction to the processor, wherein the third instruction is used to instruct the processor to allocate free memory to the target hardware.

[0058] Optionally, the third indication information is also used to indicate a second amount of free memory to be allocated to the target hardware.

[0059] It should be noted that there are no strict limitations on the second quantity; for example, it can be a preset quantity or it can be determined in real time by the target hardware or processor.

[0060] Optionally, requesting the processor to allocate free memory to the target hardware includes determining a first difference between a first quantity and a first preset threshold, determining a second quantity of free memory to be allocated to the target hardware based on the first difference, and requesting the processor to allocate the second quantity of free memory to the target hardware. Thus, taking into account the first difference between the first quantity and the first preset threshold, the second quantity of free memory to be supplemented and allocated to the target hardware can be determined, and the processor can be requested to allocate the second quantity of free memory to the target hardware.

[0061] Optionally, the second quantity is positively correlated with the absolute value of the first difference, for example, the second quantity is the product of the absolute value of the first difference and a set coefficient.

[0062] S103, in response to the first quantity being greater than the second set threshold, free memory is released to the processor to reduce the first quantity.

[0063] It should be noted that the first set threshold is lower than the second set threshold. No further restrictions are imposed on either the first or second set threshold.

[0064] In this disclosure, when the first amount of free memory in the target memory is large, the free memory can be released to the processor to reduce the first amount. That is, when there is a lot of free memory in the target memory, the target hardware can dynamically release free memory to the processor to avoid the target hardware occupying too much free memory.

[0065] Optionally, freeing up free memory for the processor may include requesting the processor to reclaim free memory from the target hardware.

[0066] Optionally, requesting the processor to reclaim free memory from the target hardware includes sending a fourth instruction message to the processor, wherein the fourth instruction message is used to instruct the reclaiming of free memory from the target hardware.

[0067] Optionally, the fourth indication information is also used to indicate a third amount of free memory to be released to the processor.

[0068] It should be noted that there are no strict restrictions on the third quantity; for example, it can be a preset quantity or it can be determined in real time by the target hardware or processor.

[0069] Optionally, releasing free memory to the processor includes determining a second difference between a first quantity and a second preset threshold, determining a third quantity of free memory to be released to the processor based on the second difference, and releasing the third quantity of free memory to the processor. Thus, the third quantity of free memory to be released from the target hardware can be determined by taking into account the second difference between the first quantity and the second preset threshold, and the third quantity of free memory can be released to the processor.

[0070] Optionally, the third quantity is positively correlated with the absolute value of the second difference, for example, the third quantity is the product of the absolute value of the second difference and a set coefficient.

[0071] It should be noted that this disclosure does not limit the execution sequence of steps S101-S103. For example, steps S101 and S102 can be implemented as independent embodiments, and steps S101 and S103 can be implemented as independent embodiments.

[0072] The memory processing method provided in the embodiments of this disclosure, in response to a memory processing request, uses target memory to perform memory allocation and memory reclamation processing corresponding to the memory processing request. The target memory is memory allocated by the processor of an electronic device to the target hardware of the electronic device. In response to a first quantity of free memory in the target memory being less than a first preset threshold, the processor is requested to allocate free memory to the target hardware to increase the first quantity. In response to a first quantity being greater than a second preset threshold, the free memory is released to the processor to decrease the first quantity. Therefore, this disclosure proposes a memory processing mechanism whereby the processor can allocate target memory to the target hardware, and the target hardware can respond to memory processing requests and use the target memory for memory allocation and reclamation. This significantly reduces the processor load and significantly improves memory processing efficiency, contributing to improved overall performance of the electronic device, optimized user experience, and support for unified management of heterogeneous memory.

[0073] In addition, when the initial amount of free memory in the target memory is small, the processor can be requested to allocate free memory to the target hardware to increase the initial amount. That is, when the amount of free memory in the target memory is small, the target hardware can dynamically request the processor to supplement the free memory.

[0074] In addition, when the initial amount of free memory in the target memory is large, the free memory can be released to the processor to reduce the initial amount. That is, when there is a lot of free memory in the target memory, the target hardware can dynamically release free memory to the processor to avoid the target hardware occupying too much free memory.

[0075] Figure 2 This is a flowchart illustrating a memory processing method according to another exemplary embodiment, such as... Figure 2 As shown, the memory processing method of this disclosure includes the following steps.

[0076] S201, in response to a memory processing request, performs memory allocation and memory reclamation processing corresponding to the memory processing request using the target memory; wherein, the target memory is the memory allocated by the processor of the electronic device to the target hardware of the electronic device.

[0077] S202, in response to the first number of free memory in the target memory being less than a first set threshold, a request is made to the processor to allocate free memory to the target hardware to increase the first number.

[0078] The details of steps S201-S202 can be found in the above embodiments and will not be repeated here.

[0079] S203, receive first indication information sent by the processor; wherein, the first indication information is used to indicate that the first memory of the electronic device in an idle state has been successfully allocated to the target hardware.

[0080] S204, in response to the first instruction information, determines that the first memory belongs to the target memory.

[0081] In this embodiment, after requesting the processor to allocate free memory to the target hardware, the method further includes receiving first indication information sent by the processor and, in response to the first indication information, determining that the first memory reallocated by the processor belongs to the target memory, so as to realize the dynamic replenishment of the target memory.

[0082] Optionally, the first indication information is triggered when the processor writes the memory address of the first memory to the target storage space of the electronic device; the target storage space is used to store the memory address of the target memory. Thus, the first indication information is triggered by the event of the processor writing the memory address of the first memory to the target storage space. This triggering mechanism is based on hardware-level operations and has high reliability. Therefore, the first indication information can reliably reflect that the first memory has been successfully allocated to the target hardware, thereby improving the reliability of the processor allocating memory to the target hardware.

[0083] It should be noted that the target storage space is used to store the memory address of the memory allocated to the target hardware (i.e., the target memory), and is used by the target hardware to retrieve the memory address in order to perform memory allocation processing on the corresponding memory. It is also used by the target hardware to store the memory address in order to perform memory reclamation operation on the corresponding memory.

[0084] When the processor writes the memory address of the first memory into the target storage space of the electronic device, it indicates that the processor has allocated the first memory to the target hardware. The target storage space is not subject to many restrictions; for example, it may include memory, registers, etc.

[0085] For example, taking the target hardware as UBM and the processor as CPU, UBM responds when the first amount of free memory in the target memory is less than a first set threshold and requests the CPU to allocate free memory to UBM.

[0086] The UBM receives a first indication message sent by the CPU. This first indication message indicates that the idle raw memory blocks 1 to 3 of the electronic device have been successfully allocated to the UBM. The first indication message is triggered when the CPU writes the memory addresses of raw memory blocks 1 to 3 to the target storage space. It should be noted that in this embodiment, the first memory includes raw memory blocks 1 to 3.

[0087] In response to the first instruction, UBM determines that original memory blocks 1 to 3 belong to the target memory.

[0088] As another possible implementation, after requesting the processor to allocate free memory to the target hardware, the system further includes receiving a fifth indication message sent by the processor. This fifth indication message indicates that the free memory allocation to the target hardware was unsuccessful, and in response to the fifth indication message, the target memory is maintained. It is understood that in cases such as insufficient free memory in the electronic device, the processor may refuse to supplement the target hardware with free memory and inform the target hardware that free memory allocation has failed. The target hardware may then maintain the target memory in response to the fifth indication message.

[0089] It should be noted that this disclosure does not impose any restrictions on the execution sequence of steps S201-S204. Figure 2 The example only demonstrates the execution of steps S201-S204 in sequence.

[0090] The memory processing method provided in the embodiments of this disclosure receives first indication information sent by a processor; wherein the first indication information is used to indicate that a first memory in an idle state of an electronic device has been successfully allocated to target hardware, and in response to the first indication information, it is determined that the first memory belongs to the target memory. Therefore, after requesting the processor to allocate idle memory to the target hardware, the method further includes receiving the first indication information sent by the processor, and in response to the first indication information, determining that the first memory reallocated by the processor belongs to the target memory, so as to realize dynamic replenishment of the target memory.

[0091] Figure 3 This is a flowchart illustrating a memory processing method according to another exemplary embodiment, such as... Figure 3 As shown, the memory processing method of this disclosure includes the following steps.

[0092] S301, in response to a memory processing request, performs memory allocation and memory reclamation processing corresponding to the memory processing request using the target memory; wherein, the target memory is the memory allocated by the processor of the electronic device to the target hardware of the electronic device.

[0093] The details of step S301 can be found in the above embodiments and will not be repeated here.

[0094] S302, in response to the first quantity being greater than a second preset threshold, retrieve the memory address of the second memory that is in an idle state from the target storage space of the electronic device; wherein, the target storage space is used to store the memory address of the target memory.

[0095] S303 sends the memory address of the second memory to the processor in order to release the second memory to the processor.

[0096] In this embodiment, the target hardware retrieves the memory address of the second memory that is in an idle state from the target storage space and sends the memory address of the second memory to the processor, indicating that the target hardware has removed the memory address of the second memory from the target storage space, and informs the processor of the removed memory address in order to release the second memory to the processor.

[0097] For example, taking the target hardware as UBM and the processor as CPU, in response to the first quantity exceeding the second preset threshold, the UBM retrieves the memory addresses of the original memory blocks 4 to 5 that are in an idle state from the target storage space and sends the memory addresses of the original memory blocks 4 to 5 to the CPU to release the original memory blocks 4 to 5 to the CPU. It should be noted that in this embodiment, the second memory includes the original memory blocks 4 to 5.

[0098] S304, receive the second indication information sent by the processor; wherein, the second indication information is used to indicate that the second memory has been successfully released to the processor, and the second indication information is triggered when the processor receives the memory address of the second memory.

[0099] S305, in response to the second instruction information, determines that the second memory does not belong to the target memory.

[0100] In this embodiment, after sending the memory address of the second memory to the processor, the method further includes receiving the second indication information sent by the processor, and in response to the second indication information, determining that the second memory that has been successfully released to the CPU does not belong to the target memory, so as to realize the dynamic release of the target memory.

[0101] The second indication is triggered when the processor receives the memory address of the second memory. Therefore, the second indication is triggered by the event of the processor receiving the memory address of the second memory. This triggering mechanism is based on hardware-level operations and has high reliability. Thus, the second indication can reliably reflect that the second memory has been successfully released to the processor, thereby improving the reliability of the target hardware releasing memory to the processor.

[0102] When the processor receives the memory address of the second memory, it indicates that the target hardware has released the second memory to the processor.

[0103] For example, taking the target hardware as UBM and the processor as CPU, in response to the first quantity exceeding the second preset threshold, the UBM retrieves the memory addresses of the original memory blocks 4 to 5 that are in an idle state from the target storage space and sends the memory addresses of the original memory blocks 4 to 5 to the CPU to release the original memory blocks 4 to 5 to the CPU. It should be noted that in this embodiment, the second memory includes the original memory blocks 4 to 5.

[0104] The UBM receives a second instruction message sent by the CPU, which indicates that the original memory blocks 4 to 5 have been successfully released to the CPU. The second instruction message is triggered when the CPU receives the memory addresses of the original memory blocks 4 to 5.

[0105] In response to the second instruction, UBM determines that original memory blocks 4 to 5 do not belong to the target memory.

[0106] It should be noted that this disclosure does not impose any restrictions on the execution sequence of steps S301-S305. Figure 3 The example only demonstrates the sequential execution of steps S301-S305. For instance, steps S301-S303 can be implemented as a standalone embodiment.

[0107] The memory processing method provided in the embodiments of this disclosure retrieves the memory address of a second memory that is in a free state from the target storage space of an electronic device; wherein the target storage space is used to store the memory address of the target memory, and the memory address of the second memory is sent to the processor to release the second memory to the processor. Thus, the memory address of the second memory can be removed from the target storage space, and the removed memory address is informed to the processor to release the second memory to the processor.

[0108] As another possible implementation, freeing up free memory for the processor includes requesting the processor to reclaim free memory from the target hardware.

[0109] After requesting the processor to reclaim free memory from the target hardware, the process also includes receiving a sixth instruction message sent by the processor. The sixth instruction message is used to indicate that the second memory has been successfully released to the processor. The sixth instruction message is triggered when the processor retrieves the memory address of the second memory from the target storage space.

[0110] In response to the sixth instruction, it is determined that the second memory does not belong to the target memory.

[0111] In this embodiment, after requesting the processor to reclaim free memory from the target hardware, the system further includes receiving a sixth instruction message sent by the processor and, in response to the sixth instruction message, determining that the second memory that has been successfully released to the CPU does not belong to the target memory, so as to realize the dynamic release of the target memory.

[0112] The sixth indication is triggered when the processor fetches the memory address of the second memory from the target memory space. Therefore, the sixth indication is triggered by the event of the processor fetching the memory address of the second memory from the target memory space. This triggering mechanism is based on hardware-level operations and has high reliability. Thus, the sixth indication can reliably reflect that the second memory has been successfully released to the processor, thereby improving the reliability of the target hardware releasing memory to the processor.

[0113] When the processor retrieves the memory address of the second memory from the target memory space, it indicates that the processor has reclaimed the second memory from the target hardware.

[0114] For example, taking the target hardware as UBM and the processor as CPU, UBM responds when the first quantity exceeds the second set threshold and requests the CPU to reclaim free memory from UBM.

[0115] The UBM receives a sixth instruction message sent by the CPU, which indicates that the original memory blocks 4 to 5 have been successfully released to the CPU. This sixth instruction message is triggered when the CPU retrieves the memory addresses of the original memory blocks 4 to 5 from the target storage space. It should be noted that in this embodiment, the second memory includes the original memory blocks 4 to 5.

[0116] In response to the sixth instruction message, UBM determines that original memory blocks 4 to 5 do not belong to the target memory.

[0117] Figure 4 This is a flowchart illustrating a memory processing method according to another exemplary embodiment, such as... Figure 4 As shown, the memory processing method of this disclosure includes the following steps.

[0118] S401, based on the memory processing request, determine the memory allocation requirements of the target functional module to determine the target request queue; wherein, the target request queue is used to store the memory addresses of the memory allocated to the target functional module.

[0119] It should be noted that the target allocation queue refers to the allocation queue corresponding to a memory processing request, and there is at least one target allocation queue for each memory processing request.

[0120] For example, the target request queue is determined based on at least one of the following: the amount of memory required by the target functional module and the physical medium from which the memory required by the target functional module originates.

[0121] S402, based on memory allocation requirements, determines the first memory address of free memory from the memory addresses of the target storage space from the electronic device, and uses it as the memory address of the memory allocated to the target functional module; wherein, the target storage space is used to store the memory address of the target memory.

[0122] Optionally, based on memory allocation requirements, a first memory address of free memory is determined from memory addresses in the target storage space of the electronic device. This includes determining the first memory address from the target storage space based on memory allocation requirements, or determining the first memory address from the local storage space of the target hardware based on memory allocation requirements; wherein the memory address in the local storage space is determined based on the memory address retrieved from the target storage space. Therefore, determining the first memory address from the target storage space can take memory allocation requirements into account. Alternatively, determining the first memory address from the local storage space of the target hardware can reduce the transmission latency required to access the target storage space, thus helping to improve memory allocation efficiency.

[0123] Optionally, the method further includes retrieving the memory address from the target storage space and writing the retrieved memory address to the local storage space. This allows the memory address to be retrieved from the target storage space and written to the local storage space in advance, avoiding the transmission latency caused by real-time access to the target storage space during memory allocation.

[0124] It should be noted that there are no restrictions on the specific method of determining the first memory address from the target storage space or the local storage space. For example, taking the target storage space as an example, the first memory address can be retrieved from the target storage space based on memory allocation requirements, or the memory address can be retrieved from the target storage space and then segmented based on memory allocation requirements to obtain the first memory address.

[0125] S403, write the first memory address into the target allocation queue; wherein, the target allocation queue is used by the target functional module to retrieve the memory address in order to perform read and write operations on the corresponding memory.

[0126] For example, taking the target hardware as UBM and the target functional modules as game applications, UBM determines the memory allocation requirements of the game applications based on the memory processing request 1 sent by the game applications, and thus determines the target request queue 1; wherein, the target request queue 1 is used to store the memory addresses of the memory allocated to the game applications.

[0127] Based on the memory allocation requirements of game applications, the first memory address A of the free memory is determined from the memory addresses of the target storage space of the electronic device, and is used as the memory address to allocate memory to the game applications.

[0128] Write the first memory address A into the target allocation queue 1; where the target allocation queue 1 is used by game applications to retrieve memory addresses in order to perform read and write operations on the corresponding memory.

[0129] For example, taking the target hardware as UBM and the target functional module as a hardware accelerator, UBM determines the memory allocation requirements of the hardware accelerator based on the memory processing request 2 sent by the hardware accelerator, and thus determines the target request queue 2; wherein, the target request queue 2 is used to store the memory address of the memory allocated to the hardware accelerator.

[0130] Based on the memory allocation requirements of the hardware accelerator, the first memory address B of the free memory is determined from the memory addresses of the target storage space of the electronic device, and used as the memory address for the memory allocated to the hardware accelerator.

[0131] Write the first memory address B into the target request queue 2; where the target request queue 2 is used by the hardware accelerator to retrieve the memory address in order to perform read and write operations on the corresponding memory.

[0132] It should be noted that this disclosure does not impose any restrictions on the execution sequence of steps S401-S403. Figure 4 The example only demonstrates the execution of steps S401-S403 in sequence.

[0133] The memory processing method provided in this disclosure determines the memory allocation requirements of a target functional module based on a memory processing request, thereby determining a target request queue. The target request queue stores the memory addresses of memory allocated to the target functional module. Based on the memory allocation requirements, a first memory address of free memory is determined from the memory addresses of the target storage space of the electronic device, and this first memory address is used as the memory address of the memory allocated to the target functional module. The target storage space stores the memory addresses of the target memory, and the first memory address is written into the target request queue. The target request queue is used by the target functional module to retrieve the memory address for read / write operations on the corresponding memory. Therefore, considering the memory allocation requirements, the target request queue and the first memory address are determined separately, and the first memory address is written into the target request queue to allocate the corresponding memory to the target functional module.

[0134] Based on any of the above embodiments, the target storage space includes multiple candidate address pools, each of which is used to store the memory address of a single type of raw memory block.

[0135] Different types of raw memory blocks differ in at least one of the following: the amount of memory they contain and the physical medium from which they originate.

[0136] For example, the target storage space includes candidate address pools 1 to 10. Candidate address pool i is used to store the memory address of the original memory block of type i, where i is a positive integer not greater than 10.

[0137] Taking the first to fifth types of raw memory blocks as examples, the first type of raw memory block contains 128B (Bytes) of memory, and the physical medium from which it originates is DDR.

[0138] The second type of raw memory block contains 256 bytes of memory, and the physical medium from which it originates is DDR.

[0139] The third type of raw memory block contains 512 bytes of memory, and the physical medium from which it originates is DDR.

[0140] The fourth type of raw memory block contains 1kB (kilobytes) of memory and originates from DDR physical media.

[0141] The fifth type of raw memory block contains 16kB of memory and originates from DDR physical media.

[0142] Figure 5 This is a flowchart illustrating a memory processing method according to another exemplary embodiment, such as... Figure 5 As shown, the memory processing method of this disclosure includes the following steps.

[0143] S501, based on the memory processing request, determine the memory allocation requirements of the target functional module to determine the target request queue; wherein, the target request queue is used to store the memory addresses of the memory allocated to the target functional module.

[0144] The details of step S501 can be found in the above embodiments and will not be repeated here.

[0145] S502, determine the association between the candidate application queue and the candidate address pool; wherein, the candidate application queue is used to store the memory address of the memory allocated to the candidate functional module, and there is an association between at least one candidate address pool and multiple candidate application queues.

[0146] S503 determines the target address pool from multiple candidate address pools based on the association relationship.

[0147] S504 determines the first memory address from the memory addresses derived from the target address pool based on memory allocation requirements.

[0148] It should be noted that multiple candidate application queues include the target application queue.

[0149] In this embodiment, there is an association between the candidate application queue and the candidate address pool. This association can be flexibly configured according to the actual application scenario, which improves the flexibility and scalability of memory allocation.

[0150] Furthermore, there is an association between at least one candidate address pool and multiple candidate application queues, meaning that multiple candidate application queues can share a single candidate address pool. Based on this sharing mechanism, different candidate application queues can achieve efficient memory reuse by circulating through the same candidate address pool. Compared to related technologies where each application queue maintains an independent address pool, resulting in low memory resource utilization, this solution helps improve memory resource utilization and eliminates the need to maintain an independent address pool for each application queue.

[0151] Optionally, based on the association relationship, a target address pool is determined from multiple candidate address pools. This includes determining the candidate address pool corresponding to the target request queue as the first address pool based on the association relationship, and determining whether the target request queue has the authority to acquire memory addresses in the first address pool based on an arbitration strategy. If the target request queue only has the authority to acquire one first address pool, the corresponding first address pool is used as the target address pool. If the target request queue has the authority to acquire multiple first address pools, the target address pool is determined from multiple first address pools. Therefore, considering the association relationship, the candidate address pool corresponding to the target request queue is determined as the first address pool. Considering the arbitration strategy, it is determined whether the target request queue has the authority to acquire memory addresses in the first address pool. If the target request queue only has the authority to acquire one first address pool, the corresponding first address pool is used as the target address pool. If the target request queue has the authority to acquire multiple first address pools, the target address pool is determined from multiple first address pools.

[0152] It should be noted that there are no strict restrictions on arbitration strategies, such as RR (Round Robin), WRR (Weighted Round Robin), and dynamic priority arbitration.

[0153] For example, candidate application queue 0 is associated with candidate address pools 0 and 1, candidate application queue 1 is associated with candidate address pools 0 and 2, candidate application queue 2 is associated with candidate address pools 1 and 3, and candidate application queue 3 is associated with candidate address pools 1 and 3.

[0154] The target application queue includes candidate application queues 0, 2, and 3.

[0155] Based on the association, candidate address pools 0 and 1 corresponding to candidate application queue 0 are determined as the first address pool corresponding to candidate application queue 0. Based on the arbitration strategy, it is determined whether candidate application queue 0 has the right to obtain memory addresses in candidate address pools 0 and 1.

[0156] Based on the association, candidate address pools 1 and 3 corresponding to candidate application queue 2 are determined as the first address pool corresponding to candidate application queue 2. Based on the arbitration strategy, it is determined whether candidate application queue 2 has the right to obtain memory addresses in candidate address pools 1 and 3.

[0157] Based on the association, candidate address pools 1 and 3 corresponding to candidate application queue 3 are determined as the first address pool corresponding to candidate application queue 3. Based on the arbitration strategy, it is determined whether candidate application queue 3 has the right to obtain memory addresses in candidate address pools 1 and 3.

[0158] Taking the RR (Round-Robin) arbitration strategy as an example, the permission to acquire memory addresses in candidate address pool 0 is round-robin to candidate request queue 0, the permission to acquire memory addresses in candidate address pool 1 is round-robin to candidate request queue 2, and the permission to acquire memory addresses in candidate address pool 3 is round-robin to candidate request queue 2.

[0159] It can be determined that candidate request queue 0 has the authority to obtain memory addresses from candidate address pool 0. Candidate address pool 0 is used as the target address pool. Based on memory allocation requirements, a first memory address is determined from the memory addresses originating from candidate address pool 0 and written to candidate request queue 0. Candidate request queue 0 is used by game applications to retrieve memory addresses for read / write operations on the corresponding memory.

[0160] It can be determined that candidate request queue 2 has the authority to obtain memory addresses from candidate address pools 1 and 3. The target address pool is then determined from candidate address pools 1 and 3, for example, candidate address pool 1 is used as the target address pool. Based on memory allocation requirements, a first memory address is determined from the memory addresses originating from candidate address pool 1, and this first memory address is written into candidate request queue 2. Candidate request queue 2 is used by the hardware accelerator to retrieve memory addresses for read and write operations on the corresponding memory.

[0161] If it can be determined that candidate application queue 3 does not have the permission to obtain memory addresses in any candidate address pool, then no write operation will be performed on candidate application queue 3 during this polling cycle.

[0162] Optionally, the target address pool is determined from multiple candidate address pools based on the association relationship. This includes determining the candidate address pool corresponding to the target application queue as the first address pool based on the association relationship. If the number of first address pools is one, the corresponding first address pool is used as the target address pool. If the number of first address pools is multiple, the target address pool is determined from multiple first address pools.

[0163] S505, write the first memory address into the target allocation queue; wherein, the target allocation queue is used by the target functional module to retrieve the memory address in order to perform read and write operations on the corresponding memory.

[0164] The details of step S505 can be found in the above embodiments and will not be repeated here.

[0165] It should be noted that this disclosure does not impose any restrictions on the execution sequence of steps S501-S505. Figure 5 The example only demonstrates the sequential execution of steps S501-S505.

[0166] The memory processing method provided in this disclosure determines the association between a candidate application queue and a candidate address pool. The candidate application queue stores the memory addresses of memory allocated to candidate functional modules. At least one candidate address pool is associated with multiple candidate application queues. Based on this association, a target address pool is determined from the multiple candidate address pools. Based on memory allocation requirements, a first memory address is determined from the memory addresses originating from the target address pool. Therefore, an association exists between the candidate application queue and the candidate address pool. This association can be flexibly configured according to actual application scenarios, improving the flexibility and scalability of memory allocation.

[0167] Furthermore, there is an association between at least one candidate address pool and multiple candidate application queues, meaning that multiple candidate application queues can share a single candidate address pool. Based on this sharing mechanism, different candidate application queues can achieve efficient memory reuse by circulating through the same candidate address pool. Compared to related technologies where each application queue maintains an independent address pool, resulting in low memory resource utilization, this solution helps improve memory resource utilization and eliminates the need to maintain an independent address pool for each application queue.

[0168] Figure 6 This is a flowchart illustrating a memory processing method according to another exemplary embodiment, such as... Figure 6 As shown, the memory processing method of this disclosure includes the following steps.

[0169] S601, based on the memory processing request, determines the memory allocation requirements of the target functional module, and determines the target request queue; wherein, the target request queue is used to store the memory addresses of the memory allocated to the target functional module.

[0170] The details of step S601 can be found in the above embodiments and will not be repeated here.

[0171] S602, determine the target address pool from multiple candidate address pools.

[0172] S603 determines the first memory address from the memory addresses derived from the target address pool based on memory allocation requirements.

[0173] Optionally, a target address pool is determined from multiple candidate address pools, including the candidate address pool with the largest number of free memory addresses among the multiple candidate address pools, which is then used as the target address pool.

[0174] Optionally, the target address pool is determined from multiple candidate address pools, including determining the target address pool based on the association between the candidate application queue and the candidate address pool. It should be noted that the details of determining the target address pool based on the association between the candidate application queue and the candidate address pool can be found in the above embodiments and will not be repeated here.

[0175] S604, in response to the fact that the target address pool does not meet the memory allocation requirements, determines an auxiliary address pool from the candidate address pools outside the target address pool.

[0176] S605, based on memory allocation requirements, continues to determine the first memory address from the memory addresses derived from the auxiliary address pool.

[0177] In this embodiment, if the target address pool does not meet the memory allocation requirements, an auxiliary address pool can be determined from the candidate address pools other than the target address pool. Taking into account the memory allocation requirements, the first memory address can be determined from the memory address from the auxiliary address pool. That is, in cases where the memory resources of the target address pool are exhausted, the first memory address can be determined from the memory address from the auxiliary address pool to meet the memory allocation requirements, which helps to improve the utilization rate of memory resources.

[0178] Optionally, an auxiliary address pool is determined from candidate address pools other than the target address pool, including using the corresponding candidate address pool as an auxiliary address pool in response to any candidate address pool other than the target address pool satisfying a set condition.

[0179] The conditions set include at least one of the following: The candidate address pool meets the memory allocation requirements; The memory addresses from the candidate address pool do not exist in the candidate request queue to be written; the candidate request queue is used to store the memory addresses of the memory allocated to the candidate functional modules.

[0180] Therefore, the candidate address pool can be used as an auxiliary address pool when the candidate address pool meets the memory allocation requirements and / or when there is no candidate request queue to be written for the memory address from the candidate address pool.

[0181] Optionally, in response to any candidate address pool other than the target address pool satisfying the set condition, the corresponding candidate address pool is designated as an auxiliary address pool. This includes determining the hierarchical relationship between multiple candidate address pools, determining the next-level candidate address pool of the target address pool based on the hierarchical relationship, and designating it as the currently traversed candidate address pool. In response to the currently traversed candidate address pool satisfying the set condition, the currently traversed candidate address pool is designated as an auxiliary address pool. In response to the currently traversed candidate address pool not satisfying the set condition, determining the next-level candidate address pool of the currently traversed candidate address pool based on the hierarchical relationship, designating it as a second address pool, updating the currently traversed candidate address pool to the second address pool, and re-determining whether the currently traversed candidate address pool satisfies the third set condition. Thus, starting from the next-level candidate address pool of the target address pool, the candidate address pools can be traversed layer by layer downwards, and it can be determined whether the currently traversed candidate address pool satisfies the set condition, until a candidate address pool that satisfies the set condition is traversed and designated as an auxiliary address pool.

[0182] Optionally, an auxiliary address pool is determined from candidate address pools other than the target address pool, including determining the candidate address pool with the largest number of free memory addresses from candidate address pools other than the target address pool as the auxiliary address pool.

[0183] S606, write the first memory address into the target allocation queue; wherein, the target allocation queue is used by the target functional module to retrieve the memory address in order to perform read and write operations on the corresponding memory.

[0184] The details of step S606 can be found in the above embodiments and will not be repeated here.

[0185] It should be noted that this disclosure does not impose any restrictions on the execution sequence of steps S601-S606. Figure 6 The example only demonstrates the execution of steps S601-S606 in sequence.

[0186] The memory processing method provided in the embodiments of this disclosure determines a target address pool from multiple candidate address pools, determines a first memory address from memory addresses derived from the target address pool based on memory allocation requirements, and, in response to the target address pool not meeting memory allocation requirements, determines an auxiliary address pool from candidate address pools other than the target address pool. Based on memory allocation requirements, the first memory address is then determined from memory addresses derived from the auxiliary address pool. Therefore, if the target address pool does not meet memory allocation requirements, an auxiliary address pool can be determined from candidate address pools other than the target address pool, and considering memory allocation requirements, the first memory address can be determined from memory addresses derived from the auxiliary address pool. That is, even when the memory resources of the target address pool are exhausted, the first memory address can be determined from memory addresses derived from the auxiliary address pool to meet memory allocation requirements, thus helping to improve memory resource utilization.

[0187] Figure 7 This is a flowchart illustrating a memory processing method according to another exemplary embodiment, such as... Figure 7 As shown, the memory processing method of this disclosure includes the following steps.

[0188] S701, based on the memory processing request, determines the memory reclamation requirements of the target functional module, and determines the target reclamation queue; wherein, the target reclamation queue is used to store the memory addresses of the memory that the target functional module has finished using.

[0189] It should be noted that the target reclamation queue refers to the allocation queue corresponding to a memory processing request, and there is at least one target reclamation queue for each memory processing request. For example, there is a one-to-one correspondence between the target reclamation queue and the target allocation queue.

[0190] For example, the target recycling queue is determined based on at least one of the following: the number of memory addresses from which the target functional module has finished using the memory, and the physical medium from which the target functional module's finished memory originated.

[0191] S702 retrieves a memory address from the target reclamation queue and uses it as the second memory address to be reclaimed.

[0192] S703 writes the second memory address to the local storage space of the target hardware; or, in response to the completion of use of the original memory block to which the second memory address belongs, writes the memory address of the original memory block to which the second memory address belongs to the candidate address pool associated with the original memory block.

[0193] In this embodiment, the second memory address can be written into the local storage space of the target hardware, which can reduce the transmission latency required to access the target storage space, help improve memory reclamation efficiency, and also help determine the memory address to be allocated directly from the local storage space during the memory allocation stage, which can reduce the transmission latency required to access the target storage space and help improve memory allocation efficiency.

[0194] Alternatively, when the original memory block to which the second memory address belongs is no longer in use, the memory address of the original memory block to which the second memory address belongs is written into the candidate address pool associated with the original memory block, so that the memory address of the original memory block that has been used can be recycled to the candidate address pool associated with the corresponding original memory block.

[0195] Optionally, before writing the second memory address to the local storage space of the target hardware, the method further includes determining that a memory allocation request has been received from at least one candidate functional module. Therefore, writing the second memory address to the local storage space of the target hardware upon receiving a memory allocation request from at least one candidate functional module helps to directly determine the memory address to be allocated from the local storage space during the memory allocation phase, reducing the transmission latency required to access the target storage space and improving memory allocation efficiency.

[0196] Optionally, the method further includes determining that the corresponding original memory block has been used up in response to the second memory address being the memory address of any original memory block.

[0197] The second memory address is obtained by partitioning the memory address of any original memory block. Based on the partitioning information of the memory address of the corresponding original memory block and the number of second memory addresses belonging to the corresponding original memory block, it is determined whether the corresponding original memory block has been used up.

[0198] Therefore, when the second memory address is the memory address of any original memory block, it can be determined that the corresponding original memory block has been used up.

[0199] Alternatively, if the second memory address is obtained by partitioning the memory address of any original memory block, it can be determined whether the original memory block has been used up based on the partitioning information of the memory address of the original memory block and the number of second memory addresses belonging to the original memory block.

[0200] It should be noted that there are no excessive restrictions on the segmentation information, such as including segmentation counts.

[0201] It should be noted that this disclosure does not impose any restrictions on the execution sequence of steps S701-S703. Figure 7 The example only demonstrates the execution of steps S701-S703 in sequence.

[0202] The memory processing method provided in the embodiments of this disclosure determines the memory reclamation needs of a target functional module based on a memory processing request, thereby determining a target reclamation queue. The target reclamation queue stores the memory addresses of memory that has been used up by the target functional module. A memory address is retrieved from the target reclamation queue as a second memory address to be reclaimed, and this second memory address is written to the local storage space of the target hardware. Alternatively, in response to the completion of use of the original memory block to which the second memory address belongs, the memory address of the original memory block to which the second memory address belongs is written to a candidate address pool associated with the original memory block. Therefore, writing the second memory address to the local storage space of the target hardware reduces the transmission latency required to access the target storage space, thus improving memory reclamation efficiency. It also helps to directly determine the memory address to be allocated from the local storage space during the memory allocation phase, further reducing the transmission latency required to access the target storage space and improving memory allocation efficiency.

[0203] Alternatively, when the original memory block to which the second memory address belongs is no longer in use, the memory address of the original memory block to which the second memory address belongs is written into the candidate address pool associated with the original memory block, so that the memory address of the original memory block that has been used can be recycled to the candidate address pool associated with the corresponding original memory block.

[0204] For ease of understanding, an exemplary embodiment is provided: This disclosure proposes a hardware device UBM (Unified Buffer Manager) for memory management, and the entire memory management process, including allocation and deallocation, may include the following steps.

[0205] like Figure 8 As shown, in step S1, when the memory managed by UBM is less than the low threshold, it will request additional memory from the CPU, and the CPU will allocate memory to UBM according to the preset threshold.

[0206] Step S2 involves the UBM allocating a corresponding amount of memory to the user based on the user's request. It should be noted that in this embodiment, the user refers to the target functional module, also called the user module. For example... Figure 9 As shown, there are N user modules, namely user module 1 to N.

[0207] Step S3 involves the user sending the used free memory to UBM for recycling.

[0208] Step S4 involves the UBM releasing the excess memory to the CPU when the amount of memory managed by the UBM exceeds a high threshold. During initialization, a certain amount of memory is allocated to the UBM in step S1. During normal operation, the UBM responds to user requests to reclaim memory, eliminating the need for frequent CPU responses. Only during sudden high traffic spikes, when the memory flow between the UBM and users is insufficient, does the UBM dynamically request additional memory via step S1. Once the traffic stabilizes, the excess memory is released to the CPU via step S4, reducing memory usage.

[0209] like Figure 9 As shown, UBM mainly contains the following processing units: (1) Memory Pool Management Unit. Internally, it contains N pool management component modules, designated as Pool Management Module 1-N. Each pool management module corresponds to a type of memory pool, handling memory address access. Each pool management module includes an independent read / write pointer register, supporting dynamic memory allocation and deallocation based on low / high thresholds. A memory pool is a series of contiguous address spaces located on the bus, and each memory pool can store memory addresses of different granularities or types. A memory pool is also called an address pool. For example, ... Figure 9 As shown, the memory pool includes raw memory blocks of types such as 128B, 256B, 512B, 1KB, and 16KB.

[0210] (2) Segmentation Control Unit. Internally, it contains N segmentation modules, designated as Segmentation Module 1-N, each corresponding to one of the N pool management modules. These modules handle the segmentation, use, and reclamation of raw memory blocks. In the requesting direction, the module obtains the original address of the memory pool from the pool management module, segments the original address into corresponding sizes according to the user's requested memory size, and records the segmentation information in a table. In the reclamation direction, the segmentation module determines whether the original memory address should be reclaimed; reclamation is only complete when all segmented addresses have been reclaimed.

[0211] (3) Segmentation Entries Unit. This unit includes a segmentation information table for storing address segmentation counts, and an entry arbitration module for arbitrating when multiple segmentation modules access the information table simultaneously, enabling shared storage of segmentation information among multiple segmentation modules. The arbitration method for accessing entries can be either Round Robin (RR) arbitration or Weighted Round Robin (WRR) arbitration.

[0212] (4) User Management Unit. Internally, it contains N application queue management modules (Application Queue Management Modules 1-N), each corresponding to one of the user's N application queues (i.e., application queues 1-N). These modules fill memory addresses into the application queues, with the memory addresses originating from the user's attached memory pool. It also contains N recycling queue management modules (Recycling Queue Management Modules 1-N), each corresponding to one of the user's N recycling queues (i.e., recycling queues 1-N). These modules retrieve the user's recycling addresses from the recycling queues and return them to the corresponding memory pools. Each application queue management module maintains a write pointer register for the application queue. After writing a memory address to the application queue, it refreshes the write pointer and pushes it to the user side, as well as receiving the read pointer from the user side. The actual depth of the application queue is calculated based on the read and write pointers. Similarly, each recycling queue management module maintains a read pointer register for the recycling queue. After retrieving a memory address from the recycling queue, it refreshes the read pointer and pushes it to the user side, as well as receiving the write pointer from the user side. The actual depth of the recycling queue is calculated based on the read and write pointers. The request and reclamation queues can be located locally in the user module or in a series of consecutive address spaces on the bus. Each user can correspond to one or more request queues and corresponding reclamation queues according to their memory needs.

[0213] (5) Switching Network. This network facilitates data exchange from N inputs to N outputs. Switching network A operates in the allocation direction, transferring memory addresses from multiple partitioning modules to multiple allocation queues. Switching network B operates in the reclamation direction, transferring memory addresses from multiple reclamation queues to multiple partitioning and reclamation modules. Switching network C also operates in the reclamation direction, transferring addresses reclaimed by the partitioning and reclamation modules to the corresponding pool management modules. The switching network can employ a batcher-banyan structure, a typical switching network structure, which will not be elaborated upon here.

[0214] (6) Scheduling and Arbitration Module. Each switching network has a corresponding scheduling and arbitration module used to resolve conflicts arising from multiple entry points competing for the same exit point. Memory management based on UBM mainly involves memory allocation and deallocation.

[0215] Among them, such as Figure 10 As shown, the memory allocation process includes the following steps.

[0216] S01: The memory pool management module obtains the address from the memory pool and refreshes the read pointer; S02: The segmentation module obtains memory address blocks from the memory pool management module; S03: The memory allocation queue management module receives a user's memory request and allocates memory according to the bitmap binding relationship. The user request is generated by the threshold setting of the corresponding allocation queue. If the number of memory addresses actually written to the allocation queue reaches the threshold, the user request is invalid. If the user's memory allocation reduces the number of memory addresses in the allocation queue to less than the threshold, the user request is valid. S04: The scheduling arbitration module generates an arbitration result, completes the matching between the application queue and the splitting module, and provides the corresponding application channel number for which authorization has been obtained, as well as the memory size information required by the application channel, to the splitting module; S05: The segmentation module segments the current original memory block according to the arbitration information and the memory size required by the application channel, generates address information, and includes the destination application channel number, and inputs it to the switching network; S06: The segmented address information is output to the corresponding application channel management module through the switching network; S07: The application channel management module writes the split address into the application queue, maintains the write pointer information, and pushes it to the user module; S08: The user obtains the split address from the application queue, maintains the read pointer information, and pushes it to the application queue management module after refreshing.

[0217] Among them, such as Figure 11 As shown, the memory reclamation process includes the following steps.

[0218] S01: The user module writes the used split addresses into the recycling queue, maintains the write pointer, and pushes it to the recycling queue management module; S02: The recycling queue management module retrieves the address from the recycling queue, maintains the read pointer, and pushes it to the user module; S03: The recycling queue management module initiates arbitration with the partitioning module to which the partitioned address belongs. Since it is a many-to-one arbitration, RR (Round Robin) or WRR (Weighted Round Robin) can be used. S04: The authorized recycling queue management module sends the memory address to the switching network B, along with the destination splitting module information; S05: Switching network B returns the memory address to the corresponding destination splitting module; S06: The partitioning module determines whether the original memory block corresponding to the partitioned address can be reclaimed by querying the partitioning information unit. When multiple modules access the memory simultaneously, arbitration is required to query the entry.

[0219] S07: Determine the memory addresses to be fully reclaimed, initiate an arbitration request, and return to the corresponding memory pool management module; S08: After authorization is obtained, the memory address is sent to the switching network C, carrying with it the corresponding destination memory pool management module information; S09: The switching network C returns the memory address block to the corresponding destination memory pool management module; S10: The memory pool management module writes memory address blocks into the memory pool and maintains write pointers.

[0220] Based on the aforementioned UBM structure, this disclosure provides a method for flexible binding and attaching of memory requests, allowing any request queue to be bound to any memory pool for address requests. A bitmap is set for each request queue, where each bit corresponds to whether it is bound to the memory pool with that number for address requests, i.e., attached to the pool management module corresponding to that memory pool. This bitmap serves as the input information for the request direction scheduling arbitration module A. By arbitrating the binding information set of all request queues, the input / output allocation relationship of the switching network is obtained. This allocation relationship completes the transfer of a memory address from the splitting module to the corresponding request queue. An optional scheduling arbitration algorithm is RRM (Round RobinMatching). The RRM algorithm maintains a set of arbitration authorization information for each bit in the request queue and memory pool, such as... Figure 12-14 As shown, the process is illustrated using 4 users and 4 memory pools. From top to bottom, these are the request queues 0-3 and the memory pools 0-3.

[0221] like Figure 12 This corresponds to the first step of the RRM request, where the request queue initiates a request to the memory pool. Currently, there are 3 request queues initiating valid requests according to a bitmap. Each request queue corresponds to a set of bitmap information, where each bit indicates whether the request queue can request the current memory pool. Bit 0 corresponds to memory pool 0, bit 3 corresponds to memory pool 3, and a bit value of 1 indicates that the queue can request the current memory pool, while a bit value of 0 indicates that the queue cannot request the current memory pool. Based on Figure 12 The connection relationships are defined in the memory pool, and each memory pool receives a corresponding request. In this embodiment, request queue 0 sends requests to memory pools 0 and 1, request queue 2 sends requests to memory pools 1 and 3, and request queue 3 sends requests to memory pools 1 and 3.

[0222] like Figure 12 The current grant in memory pool 1 (referred to as g1) is in application queue 2, and the current grant in memory pool 3 (referred to as g3) is in application queue 2.

[0223] like Figure 13 This corresponds to the authorization in step two. The current grant for memory pool 0 is in request queue 0. Since the current grants for memory pool 1 and memory pool 3 are both in request queue 2, then... Figure 13The authorization relationship. The memory pool currently polled by application queue 2 (referred to as a2) is memory pool 1.

[0224] like Figure 14 This corresponds to the confirmation in step three. Based on the memory pool authorization information maintained by application queue 2, the current grant for memory pool authorization is memory pool 1. Therefore, the final RRM matching result for this round is obtained: application queue 0 requests memory pool 0, and application queue 2 requests memory pool 1. Switching network A performs data exchange based on this result; that is, memory pool 0 provides memory to application queue 0, and memory pool 1 provides memory to application queue 2. Switching networks B and C, as well as the corresponding scheduling and arbitration modules, can all complete the data exchange of the pathway in this way. Optionally, the binding configuration can also be placed on the memory pool side as a request mask for authorization arbitration, with each bit corresponding to whether the application queue can participate in arbitration. Furthermore, the scheduling matching algorithm is not limited to RRM; others such as iSLIP and PIM can also use the bitmap of the binding relationship as mask input information to participate in result matching.

[0225] Flexible application binding allows different users to simultaneously bind to the same memory pool and share the same type of memory blocks. Since the memory requests and reclamation by different users are relatively staggered throughout the business process, a shared memory pool can reduce the overall memory usage compared to allocating a separate memory pool for each request queue.

[0226] This embodiment also provides a method for memory sharing and utilization, such as... Figure 15 The diagram shows a memory sharing mechanism. Since the pool management module maintains read and write pointers for the corresponding memory pool, when the remaining amount in the memory pool is less than the lower threshold, it will send a memory sharing request to the next level to meet the needs of the users attached to the current pool management module, thereby realizing memory pool sharing across modules and improving the overall memory utilization.

[0227] In this process, the borrowing request is passed down level by level, such as... Figure 16 The diagram shown illustrates the process of handling a loan request. (In conjunction with the aforementioned...) Figure 13 If the memory pool corresponding to pool management module 1 is exhausted (low threshold is 0), it initiates a borrowing request to pool management module 2. Pool management module 2 decides whether to respond to the previous level's borrowing request based on the depth of its current memory pool and the currently attached user requests. If the current level does not meet the borrowing conditions, pool management module 2 continues to borrow from the next lower level in response to pool management module 1's request, that is, pool management module 2 initiates a borrowing request to pool management module 3. Pool management module 3 then decides whether to respond to the previous level's borrowing request based on the depth of its current memory pool and the currently attached user requests.

[0228] For example, if pool management module 3 decides to respond to the previous borrowing, it sends the borrowed memory address to pool management module 2, and pool management module 2 forwards the borrowed memory address to pool management module 1.

[0229] like Figure 16 As shown, upon receiving a memory pool borrowing request from a previous level, it checks if the current memory pool depth exceeds a threshold. If the depth exceeds the threshold, it checks if there are any user requests in the current memory pool. If there are no user requests, it decides to borrow memory from the previous level. It should be noted that this step of borrowing memory from the previous level refers to borrowing memory from the current memory pool. Conversely, if there are user requests in the current memory pool, it initiates a borrowing request to the next lower level.

[0230] Conversely, if the current memory pool depth is less than or equal to the threshold, a borrowing operation is initiated at the next lower level.

[0231] If the memory transfer to the next level is successful, then the memory will be transferred to the previous level. It should be noted that this step of transferring memory to the previous level refers to transferring the memory from the memory pool corresponding to the pool management module of the next level to the previous level.

[0232] If the attempt to borrow from the next level fails, the current memory pool depth is reassessed to see if it exceeds the threshold.

[0233] Because of memory sharing, the memory block addresses processed by the partitioning module do not correspond to the memory pools belonging to the pool management module. The original memory block addresses reclaimed by the partitioning module need to be returned to the corresponding memory pool. For example... Figure 17 This embodiment provides a partitioning information table format. For the application direction, after the original memory address is partitioned, the generated address partitioning information, the original memory address, and the memory pool number (which is the same as the pool management module number) are stored in the partitioning information table. For the reclamation direction, the partitioned memory is first returned to the corresponding partitioning module via the switching network B. The partitioning module queries the partitioning information table, calculates and determines that the reclamation is finally completed based on the address partitioning information, and obtains the original memory address and memory pool number. Then, it sends the original memory address to the corresponding pool management module via the switching network C, and finally returns it to the corresponding memory pool.

[0234] like Figure 18The diagram illustrates a method for address reclamation using stored partitioning information, representing the reclamation direction. Optionally, one implementation of the address partitioning information stored in the partitioning information table is a partitioning counter. Each time the original memory block to be partitioned in the request direction is partitioned, the partitioning counter for that memory block is incremented by 1. After partitioning is complete, this counter, along with the memory address and its associated memory pool number, is stored in the partitioning information table as address partitioning information. In the reclamation direction, after the partitioned address returns to the partitioning module, the partitioning information table is queried to retrieve the partitioning information to which the partitioned address belongs. The partitioning counter is decremented by 1. If the partitioning counter reaches zero, all partitioned addresses have been returned (i.e., the partitioning information indicates reclamation is complete), and the original memory address has been reclaimed; otherwise, the calculated partitioning counter is written back to the table, i.e., the calculated partitioning information is refreshed, and the partitioning information is written back to the partitioning information table.

[0235] like Figure 19 This is a schematic diagram of a fast recycling channel structure provided in an embodiment of this disclosure. The recycling direction returns to the original memory block of the pool management module, without needing to return to the memory pool. It directly loops back to the request direction within the pool management module for direct use, reducing cross-bus transmission latency and improving the overall system throughput efficiency. For a single pool management module, the fast recycling method is as follows: Figure 20 As shown.

[0236] like Figure 20 As shown, the original memory address in the recycling direction is returned to the memory pool management module. It then checks if there is a user request for a memory address in the request direction. If so, the memory address in the recycling direction is quickly returned to the request direction; that is, the memory address in the recycling direction from the memory pool management module is quickly returned to the request direction. If there is no user request for a memory address in the request direction, it is returned to the memory pool; that is, the memory address in the recycling direction from the memory pool management module is returned to the memory pool.

[0237] Figure 21 This is a schematic diagram of the structure of a memory processing device according to an exemplary embodiment.

[0238] Reference Figure 21 The memory processing device 2100 of this disclosure includes: a first processing module 2101, a second processing module 2102 and a third processing module 2103.

[0239] The first processing module 2101 is configured to, in response to a memory processing request, perform memory allocation and memory reclamation processing corresponding to the memory processing request using target memory; wherein, the target memory is the memory allocated by the processor of the electronic device to the target hardware of the electronic device; The second processing module 2102 is configured to, in response to a first quantity of free memory in the target memory being less than a first preset threshold, request the processor to allocate free memory to the target hardware to increase the first quantity; The third processing module 2103 is configured to release free memory to the processor in response to the first quantity being greater than a second preset threshold, so as to reduce the first quantity; Wherein, the first set threshold is less than the second set threshold.

[0240] In some possible implementations, after requesting the processor to allocate free memory to the target hardware, the second processing module 2102 is further configured to: receive first indication information sent by the processor; wherein the first indication information is used to indicate that the first memory of the electronic device in an idle state has been successfully allocated to the target hardware; and in response to the first indication information, determine that the first memory belongs to the target memory.

[0241] In some possible implementations, the first indication information is triggered when the processor writes the memory address of the first memory into the target storage space of the electronic device; the target storage space is used to store the memory address of the target memory.

[0242] In some possible implementations, the second processing module 2102 is further configured to: determine a first difference between the first quantity and the first set threshold; determine a second quantity of free memory to be allocated to the target hardware based on the first difference; and request the processor to allocate the second quantity of free memory to the target hardware.

[0243] In some possible implementations, the third processing module 2103 is further configured to: retrieve the memory address of a second memory that is in an idle state from the target storage space of the electronic device; wherein the target storage space is used to store the memory address of the target memory; and send the memory address of the second memory to the processor to release the second memory to the processor.

[0244] In some possible implementations, after sending the memory address of the second memory to the processor, the third processing module 2103 is further configured to: receive second indication information sent by the processor; wherein the second indication information is used to indicate that the second memory has been successfully released to the processor, and the second indication information is triggered when the processor receives the memory address of the second memory; in response to the second indication information, determine that the second memory does not belong to the target memory.

[0245] In some possible implementations, the third processing module 2103 is further configured to: determine a second difference between the first quantity and the second set threshold; determine a third quantity of free memory to be released to the processor based on the second difference; and release the third quantity of free memory to the processor.

[0246] In some possible implementations, the first processing module 2101 is further configured to: determine the memory allocation requirements of the target functional module based on the memory processing request, thereby determining a target request queue; wherein the target request queue is used to store the memory addresses of the memory allocated to the target functional module; based on the memory allocation requirements, determine a first memory address of free memory from the memory addresses of the target storage space originating from the electronic device, as the memory address of the memory allocated to the target functional module; wherein the target storage space is used to store the memory addresses of the target memory; and write the first memory address into the target request queue; wherein the target request queue is used by the target functional module to retrieve the memory address for read / write operations on the corresponding memory.

[0247] In some possible implementations, the first processing module 2101 is further configured to: determine the first memory address from the target storage space based on the memory allocation requirement; or, determine the first memory address from the local storage space of the target hardware based on the memory allocation requirement; wherein the memory address in the local storage space is determined based on the memory address retrieved from the target storage space.

[0248] In some possible implementations, the target storage space includes a plurality of candidate address pools, each of which is used to store the memory address of a raw memory block of a single type; The original memory blocks of different types differ in at least one of the following: the amount of memory they contain and the physical medium from which they originate.

[0249] In some possible implementations, the first processing module 2101 is further configured to: determine the association between the candidate application queue and the candidate address pool; wherein the candidate application queue is used to store the memory addresses of the memory allocated to the candidate functional modules, and there is an association between at least one of the candidate address pools and multiple candidate application queues; based on the association, determine the target address pool from the multiple candidate address pools; and based on the memory allocation requirement, determine the first memory address from the memory addresses derived from the target address pool.

[0250] In some possible implementations, the first processing module 2101 is further configured to: determine a candidate address pool corresponding to the target application queue as a first address pool based on the association relationship; determine whether the target application queue has the permission to obtain memory addresses in the first address pool based on an arbitration strategy; in response to the target application queue having only the permission to obtain one first address pool, use the corresponding first address pool as the target address pool; in response to the target application queue having the permission to obtain multiple first address pools, determine the target address pool from the multiple first address pools.

[0251] In some possible implementations, the first processing module 2101 is further configured to: determine a target address pool from a plurality of candidate address pools; determine a first memory address from memory addresses derived from the target address pool based on the memory allocation requirement; determine an auxiliary address pool from candidate address pools other than the target address pool in response to the target address pool not meeting the memory allocation requirement; determine a second memory address from memory addresses derived from the auxiliary address pool based on the memory allocation requirement; and use both the first memory address and the second memory address as the first memory address.

[0252] In some possible implementations, the first processing module 2101 is further configured to: in response to any candidate address pool other than the target address pool satisfying a set condition, use the corresponding candidate address pool as the auxiliary address pool; The setting conditions include at least one of the following: The candidate address pool satisfies the memory allocation requirements; The memory addresses from the candidate address pool do not have a candidate application queue to be written to; wherein, the candidate application queue is used to store the memory addresses of the memory allocated to the candidate functional modules.

[0253] In some possible implementations, the first processing module 2101 is further configured to: determine the hierarchical relationship between the plurality of candidate address pools; based on the hierarchical relationship, determine the next level candidate address pool of the target address pool as the currently traversed candidate address pool; in response to the currently traversed candidate address pool satisfying the set condition, designate the currently traversed candidate address pool as the auxiliary address pool; in response to the currently traversed candidate address pool not satisfying the set condition, based on the hierarchical relationship, determine the next level candidate address pool of the currently traversed candidate address pool as the second address pool; update the currently traversed candidate address pool to the second address pool, and re-determine that the currently traversed candidate address pool satisfies the third set condition.

[0254] In some possible implementations, the first processing module 2101 is further configured to: determine the memory reclamation requirements of the target functional module based on the memory processing request, and determine a target reclamation queue; wherein the target reclamation queue is used to store the memory addresses of the memory that the target functional module has finished using; retrieve the memory address from the target reclamation queue as a second memory address to be reclaimed; write the second memory address into the local storage space of the target hardware; or, in response to the original memory block to which the second memory address belongs being used up, write the memory address of the original memory block to which the second memory address belongs into the candidate address pool associated with the original memory block.

[0255] In some possible implementations, before writing the second memory address into the local storage space of the target hardware, the first processing module 2101 is further configured to: determine that a memory allocation request has been received from at least one candidate functional module.

[0256] In some possible implementations, the first processing module 2101 is further configured to: determine that the corresponding original memory block has been used up in response to the second memory address being the memory address of any of the original memory blocks; and determine whether the corresponding original memory block has been used up in response to the second memory address being obtained by segmentation processing based on the memory address of any of the original memory blocks, based on the segmentation information of the memory address of the corresponding original memory block and the number of second memory addresses belonging to the corresponding original memory block.

[0257] Regarding the apparatus in the above embodiments, the specific manner in which each module performs its operation has been described in detail in the embodiments related to the method, and will not be elaborated upon here.

[0258] The memory processing apparatus provided in the embodiments of this disclosure, in response to a memory processing request, uses target memory to perform memory allocation and memory reclamation processing corresponding to the memory processing request. The target memory is memory allocated by the processor of an electronic device to the target hardware of the electronic device. In response to a first quantity of free memory in the target memory being less than a first preset threshold, the processor is requested to allocate free memory to the target hardware to increase the first quantity. In response to a first quantity being greater than a second preset threshold, the free memory is released to the processor to decrease the first quantity. Therefore, this disclosure proposes a memory processing mechanism in which the processor can allocate target memory to the target hardware, and the target hardware can respond to memory processing requests and use the target memory for memory allocation and reclamation processing. This significantly reduces the processor load and significantly improves memory processing efficiency, contributing to improved overall performance of the electronic device, optimized user experience, and support for unified management of heterogeneous memory.

[0259] In addition, when the initial amount of free memory in the target memory is small, the processor can be requested to allocate free memory to the target hardware to increase the initial amount. That is, when the amount of free memory in the target memory is small, the target hardware can dynamically request the processor to supplement the free memory.

[0260] In addition, when the initial amount of free memory in the target memory is large, the free memory can be released to the processor to reduce the initial amount. That is, when there is a lot of free memory in the target memory, the target hardware can dynamically release free memory to the processor to avoid the target hardware occupying too much free memory.

[0261] To implement the above embodiments, this disclosure also proposes a memory management system, including a processor, target hardware, and target memory; wherein the processor is used to allocate the target memory to the target hardware; and the target hardware is used to execute the steps of the memory processing method provided in this disclosure.

[0262] In some possible implementations, the memory management system further includes a target storage space for storing the memory address of the target memory; the processor is also configured to perform read and write operations on the target storage space to update the memory address of the target memory.

[0263] In some possible implementations, the target hardware communicates with the processor via a system bus; The target hardware and the memory-using hardware communicate via a system bus; At least one of the processor and the target hardware accesses the target storage space via a system bus.

[0264] For ease of understanding, an exemplary embodiment is provided: like Figure 22 As shown, the memory management system includes the CPU, UBM, DDR, and SRAM. The target functional modules include hardware acceleration module 1, hardware acceleration module 2, software user 1, and software user 2.

[0265] These devices are interconnected via the system bus to process data. Different target functional modules have varying requirements for memory size and quantity, all of which are managed uniformly through the UBM. The UBM dynamically requests the corresponding memory from the CPU as needed, and completes memory allocation and deallocation operations with each target functional module according to the system-defined descriptor structure. The memory allocation and deallocation interfaces between the UBM and the target functional modules are all based on the system bus, and they exchange memory space read and write pointers through the system bus.

[0266] For details regarding the internal structure of a UBM, please refer to the above embodiments; they will not be repeated here.

[0267] To implement the above embodiments, this disclosure also proposes an electronic device including a memory management system provided in this disclosure.

[0268] In some possible implementations, the electronic device includes candidate functional modules for sending memory processing requests to the target hardware.

[0269] In some possible implementations, the candidate functional module includes at least one of the following: Memory usage applications; Memory uses hardware.

[0270] In some possible implementations, memory-using applications include applications running on the processor.

[0271] Figure 23 This is a schematic diagram illustrating the structure of an electronic device according to an exemplary embodiment. For example, the electronic device 2300 may be a vehicle, mobile phone, computer, digital broadcasting terminal, messaging device, game console, tablet device, medical device, fitness equipment, personal digital assistant, etc.

[0272] Reference Figure 23 The electronic device 2300 may include one or more of the following components: processing component 2302, memory 2304, power component 2306, multimedia component 2308, audio component 2310, input / output (I / O) interface 2312, sensor component 2314, and communication component 2316.

[0273] Processing component 2302 typically controls the overall operation of electronic device 2300, such as operations associated with display, telephone calls, data communication, camera operation, and recording operations. Processing component 2302 may include one or more processors 2320 to execute instructions to complete all or part of the steps of the memory processing method described above. Furthermore, processing component 2302 may include one or more modules to facilitate interaction between processing component 2302 and other components. For example, processing component 2302 may include a multimedia module to facilitate interaction between multimedia component 2308 and processing component 2302.

[0274] Memory 2304 is configured to store various types of data to support the operation of electronic device 2300. Examples of this data include instructions for any application or method operating on electronic device 2300, contact data, phonebook data, messages, pictures, videos, etc. Memory 2304 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as Static Random Access Memory (SRAM), Electrically Erasable Programmable Read-Only Memory (EEPROM), Erasable Programmable Read-Only Memory (EPROM), Programmable Read-Only Memory (PROM), Read-Only Memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk.

[0275] Power component 2306 provides power to various components of electronic device 2300. Power component 2306 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power to electronic device 2300.

[0276] Multimedia component 2308 includes a screen that provides an output interface between electronic device 2300 and the user. In some embodiments, the screen may include a Liquid Crystal Display (LCD) and a Touch Panel (TP). If the screen includes a Touch Panel, the screen may be implemented as a touchscreen to receive input signals from the user. The Touch Panel includes one or more touch sensors to sense touches, swipes, and gestures on the Touch Panel. The touch sensors may sense not only the boundaries of touch or swipe actions but also the duration and pressure associated with the touch or swipe operation. In some embodiments, multimedia component 2308 includes a front-facing camera and / or a rear-facing camera. When electronic device 2300 is in an operating mode, such as a shooting mode or a video mode, the front-facing camera and / or rear-facing camera may receive external multimedia data. Each front-facing camera and rear-facing camera may be a fixed optical lens system or have focal length and optical zoom capabilities.

[0277] Audio component 2310 is configured to output and / or input audio signals. For example, audio component 2310 includes a microphone (MIC) configured to receive external audio signals when electronic device 2300 is in an operating mode, such as call mode, recording mode, and voice recognition mode. The received audio signals may be further stored in memory 2304 or transmitted via communication component 2316. In some embodiments, audio component 2310 also includes a speaker for outputting audio signals.

[0278] I / O interface 2312 provides an interface between processing component 2302 and peripheral interface modules, such as keyboards, click wheels, buttons, etc. These buttons may include, but are not limited to, home buttons, volume buttons, power buttons, and lock buttons.

[0279] Sensor assembly 2314 includes one or more sensors for providing state assessment of various aspects of electronic device 2300. For example, sensor assembly 2314 may detect the on / off state of electronic device 2300, the relative positioning of components such as the display and keypad of electronic device 2300, changes in position of electronic device 2300 or a component of electronic device 2300, the presence or absence of user contact with electronic device 2300, orientation or acceleration / deceleration of electronic device 2300, and temperature changes of electronic device 2300. Sensor assembly 2314 may include a proximity sensor configured to detect the presence of nearby objects without any physical contact. Sensor assembly 2314 may also include an optical sensor, such as a complementary metal-oxide-semiconductor (CMOS) or charge-coupled device (CCD) image sensor, for use in imaging applications. In some embodiments, sensor assembly 2314 may also include an accelerometer, gyroscope, magnetometer, pressure sensor, or temperature sensor.

[0280] Communication component 2316 is configured to facilitate wired or wireless communication between electronic device 2300 and other devices. Electronic device 2300 can access wireless networks based on communication standards, such as WiFi, 4G, or 5G, or combinations thereof. In one exemplary embodiment, communication component 2316 receives broadcast signals or broadcast-related information from an external broadcast management system via a broadcast channel. In one exemplary embodiment, communication component 2316 also includes a Near Field Communication (NFC) module to facilitate short-range communication. For example, the NFC module may be implemented based on Radio Frequency Identification (RFID), Infrared Data Association (IrDA), Ultra-Wideband (UWB), Bluetooth, and other technologies.

[0281] In an exemplary embodiment, the electronic device 2300 may be implemented by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components to perform the steps of the memory processing method described above.

[0282] In an exemplary embodiment, a non-transitory computer-readable storage medium including instructions is also provided, such as a memory 2304 including instructions, which can be executed by a processor 2320 of an electronic device 2300 to complete the memory processing method described above. For example, the non-transitory computer-readable storage medium may be a read-only memory (ROM), a random access memory (RAM), a compact disc read-only memory (CD-ROM), magnetic tape, a floppy disk, and an optical data storage device, etc.

[0283] To implement the above embodiments, this disclosure also proposes a computer-readable storage medium storing computer program instructions thereon, which, when executed by a processor, implement the steps of the memory processing method provided in this disclosure.

[0284] Alternatively, the computer-readable storage medium may be ROM, random access memory (RAM), CD-ROM, magnetic tape, floppy disk, and optical data storage device, etc.

[0285] To implement the above embodiments, this disclosure also proposes a chip including an interface circuit and a processing circuit coupled to each other. The interface circuit is used to input or output signals, and the processing circuit is configured to implement the steps of the memory processing method provided in this disclosure.

[0286] Figure 24 This is a schematic diagram illustrating the structure of a chip according to an exemplary embodiment. See also... Figure 24 The diagram shown is a schematic representation of the structure of chip 2400, but it is not limited to this.

[0287] Chip 2400 includes processing circuitry 2401, which is configured to perform the steps of any of the memory processing methods described above.

[0288] In some embodiments, chip 2400 further includes one or more interface circuits 2402. Optionally, the interface circuit 2402 is connected to memory 2403, and the interface circuit 2402 can be used to receive signals from memory 2403 or other devices, and the interface circuit 2402 can be used to send signals to memory 2403 or other devices. For example, the interface circuit 2402 can read instructions stored in memory 2403 and send the instructions to processing circuit 2401.

[0289] In some embodiments, the interface circuit 2402 performs at least one of the communication steps such as sending and / or receiving in the above method, while the processing circuit 2401 performs other steps.

[0290] In some embodiments, the terms interface circuit, interface, transceiver pin, transceiver, etc., can be used interchangeably.

[0291] In some embodiments, chip 2400 further includes one or more memories 2403 for storing instructions. Optionally, all or part of the memories 2403 may be located outside of chip 2400.

[0292] To implement the above embodiments, this disclosure also proposes a computer program product, including a computer program, which, when executed by a processor, implements the steps of the memory processing method provided in this disclosure.

[0293] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only.

[0294] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope.

Claims

1. A memory processing method, characterized in that, include: In response to a memory processing request, memory allocation and reclamation corresponding to the memory processing request are performed using the target memory; wherein, the target memory is the memory allocated by the processor of the electronic device to the target hardware of the electronic device; In response to a first quantity of free memory in the target memory being less than a first preset threshold, the processor is requested to allocate free memory to the target hardware to increase the first quantity; In response to the first quantity being greater than a second preset threshold, free memory is released to the processor to reduce the first quantity; Wherein, the first set threshold is less than the second set threshold.

2. The method according to claim 1, characterized in that, After requesting the processor to allocate free memory to the target hardware, the process further includes: The processor sends a first indication message; wherein the first indication message is used to indicate that the first memory of the electronic device, which is in an idle state, has been successfully allocated to the target hardware. In response to the first indication information, it is determined that the first memory belongs to the target memory.

3. The method according to claim 2, characterized in that, The first indication information is triggered when the processor writes the memory address of the first memory into the target storage space of the electronic device; the target storage space is used to store the memory address of the target memory.

4. The method according to claim 1, characterized in that, The request to the processor to allocate free memory to the target hardware includes: Determine the first difference between the first quantity and the first set threshold; Based on the first difference, a second quantity of free memory to be allocated to the target hardware is determined; The processor is requested to allocate the second amount of free memory to the target hardware.

5. The method according to claim 1, characterized in that, The step of releasing free memory to the processor includes: Retrieve the memory address of the second memory that is in an idle state from the target storage space of the electronic device; wherein, the target storage space is used to store the memory address of the target memory; Send the memory address of the second memory to the processor to release the second memory to the processor.

6. The method according to claim 5, characterized in that, After sending the memory address of the second memory to the processor, the method further includes: The processor receives a second indication message; wherein the second indication message is used to indicate that the second memory has been successfully released to the processor, and the second indication message is triggered when the processor receives the memory address of the second memory; In response to the second indication information, it is determined that the second memory does not belong to the target memory.

7. The method according to claim 1, characterized in that, The step of releasing free memory to the processor includes: Determine a second difference between the first quantity and the second set threshold; Based on the second difference, a third amount of free memory to be released to the processor is determined; Release the third amount of free memory to the processor.

8. The method according to any one of claims 1-7, characterized in that, The process of using target memory to perform memory allocation and reclamation corresponding to the memory processing request includes: Based on the memory processing request, the memory allocation requirements of the target functional module are determined to identify the target request queue; wherein, the target request queue is used to store the memory addresses allocated to the target functional module. Based on the memory allocation requirements, a first memory address of free memory is determined from the memory addresses of the target storage space of the electronic device, and used as the memory address of the memory allocated to the target functional module; wherein, the target storage space is used to store the memory address of the target memory; The first memory address is written into the target request queue; wherein the target request queue is used by the target functional module to retrieve the memory address in order to perform read and write operations on the corresponding memory.

9. The method according to claim 8, characterized in that, The step of determining the first memory address of free memory from the memory addresses of the target storage space of the electronic device based on the memory allocation requirement includes: Based on the memory allocation requirements, the first memory address is determined from the target storage space; or... Based on the memory allocation requirements, the first memory address is determined from the local storage space of the target hardware; wherein the memory address in the local storage space is determined based on the memory address retrieved from the target storage space.

10. The method according to claim 8, characterized in that, The target storage space includes multiple candidate address pools, each of which is used to store the memory address of a single type of original memory block; The original memory blocks of different types differ in at least one of the following: the amount of memory they contain and the physical medium from which they originate.

11. The method according to claim 10, characterized in that, The step of determining the first memory address of free memory from the memory addresses of the target storage space of the electronic device based on the memory allocation requirement includes: Determine the association between the candidate application queue and the candidate address pool; wherein the candidate application queue is used to store the memory addresses allocated to the candidate functional modules, and there is an association between at least one candidate address pool and multiple candidate application queues; Based on the aforementioned association, a target address pool is determined from the multiple candidate address pools; Based on the memory allocation requirements, the first memory address is determined from the memory addresses derived from the target address pool.

12. The method according to claim 11, characterized in that, The step of determining the target address pool from multiple candidate address pools based on the association relationship includes: Based on the aforementioned association, a candidate address pool corresponding to the target application queue is determined as the first address pool; Based on the arbitration strategy, it is determined whether the target request queue has the permission to obtain memory addresses in the first address pool; Since the target application queue only has the right to obtain one first address pool, the corresponding first address pool is used as the target address pool; In response to the target application queue having the right to acquire multiple first address pools, the target address pool is determined from the multiple first address pools.

13. The method according to claim 10, characterized in that, The step of determining the first memory address to be allocated to the target functional module from the memory addresses of the target storage space of the electronic device based on the memory allocation requirements includes: Determine the target address pool from the plurality of candidate address pools; Based on the memory allocation requirements, the first memory address is determined from the memory addresses derived from the target address pool; In response to the fact that the target address pool does not meet the memory allocation requirement, an auxiliary address pool is determined from the candidate address pool other than the target address pool; Based on the memory allocation requirements, the first memory address is further determined from the memory addresses derived from the auxiliary address pool.

14. The method according to claim 13, characterized in that, The step of determining an auxiliary address pool from candidate address pools other than the target address pool includes: If any candidate address pool other than the target address pool meets the set conditions, the corresponding candidate address pool is used as the auxiliary address pool; The setting conditions include at least one of the following: The candidate address pool satisfies the memory allocation requirements; The memory addresses from the candidate address pool do not have a candidate application queue to be written to; wherein, the candidate application queue is used to store the memory addresses of the memory allocated to the candidate functional modules.

15. The method according to claim 14, characterized in that, The step of using a candidate address pool other than the target address pool as the auxiliary address pool in response to any of the candidate address pools satisfying a set condition includes: Determine the hierarchical relationship between the multiple candidate address pools; Based on the hierarchical relationship, the next level of candidate address pools of the target address pool is determined as the currently traversed candidate address pool; In response to the current candidate address pool satisfying the set condition, the current candidate address pool is used as the auxiliary address pool; In response to the fact that the currently traversed candidate address pool does not meet the set condition, based on the hierarchical relationship, the next level of candidate address pool is determined as the second address pool; The currently traversed candidate address pool is updated to the second address pool, and the currently traversed candidate address pool is re-determined to satisfy the third set condition.

16. The method according to claim 10, characterized in that, The process of using target memory to perform memory allocation and reclamation corresponding to the memory processing request includes: Based on the memory processing request, the memory reclamation requirements of the target functional module are determined, and a target reclamation queue is determined; wherein, the target reclamation queue is used to store the memory addresses of the memory that the target functional module has finished using; Retrieve the memory address from the target reclamation queue as the second memory address to be reclaimed; Write the second memory address to the local storage space of the target hardware; or, in response to the completion of use of the original memory block to which the second memory address belongs, write the memory address of the original memory block to which the second memory address belongs to the candidate address pool associated with the original memory block.

17. The method according to claim 16, characterized in that, Before writing the second memory address into the local storage space of the target hardware, the method further includes: It is determined that at least one memory allocation request has been received from a candidate functional module.

18. The method according to claim 16, characterized in that, The method further includes: In response to the second memory address being the memory address of any of the original memory blocks, it is determined that the corresponding original memory block has been used up; In response to the fact that the second memory address is obtained by partitioning the memory address of any of the original memory blocks, based on the partitioning information of the memory address of the corresponding original memory block and the number of second memory addresses belonging to the corresponding original memory block, it is determined whether the corresponding original memory block has been used up.

19. A memory processing device, characterized in that, include: The first processing module is configured to, in response to a memory processing request, perform memory allocation and memory reclamation processing corresponding to the memory processing request using target memory; wherein, the target memory is the memory allocated by the processor of the electronic device to the target hardware of the electronic device; The second processing module is configured to, in response to a first quantity of free memory in the target memory being less than a first preset threshold, request the processor to allocate free memory to the target hardware to increase the first quantity; The third processing module is configured to release free memory to the processor in response to the first quantity being greater than a second preset threshold, thereby reducing the first quantity; Wherein, the first set threshold is less than the second set threshold.

20. The apparatus according to claim 19, characterized in that, After the processor is requested to allocate free memory to the target hardware, the second processing module is further configured to: The processor sends a first indication message; wherein the first indication message is used to indicate that the first memory of the electronic device, which is in an idle state, has been successfully allocated to the target hardware. In response to the first indication information, it is determined that the first memory belongs to the target memory.

21. The apparatus according to claim 20, characterized in that, The first indication information is triggered when the processor writes the memory address of the first memory into the target storage space of the electronic device; the target storage space is used to store the memory address of the target memory.

22. A memory management system, characterized in that, include: Processor, target hardware, and target memory; The processor is configured to allocate the target memory to the target hardware. The target hardware is used to perform the steps of the method according to any one of claims 1-18.

23. The system according to claim 22, characterized in that, Also includes: The target storage space is used to store the memory address of the target memory. The processor is also used to perform read and write operations on the target storage space to update the memory address of the target memory.

24. The system according to claim 23, characterized in that, The target hardware communicates with the processor via a system bus; The target hardware and the memory-using hardware communicate via a system bus; At least one of the processor and the target hardware accesses the target storage space via a system bus.

25. An electronic device, characterized in that, The memory management system included in any one of claims 22-24.

26. A computer-readable storage medium having computer program instructions stored thereon, characterized in that, When executed by a processor, the program instructions implement the steps of the method described in any one of claims 1-18.

27. A chip, characterized in that, The chip includes an interface circuit and a processing circuit coupled to each other. The interface circuit is used to input or output signals, and the processing circuit is configured to implement the steps of the method according to any one of claims 1-18.

28. A computer program product, characterized in that, Includes a computer program, which, when executed by a processor, implements the steps of the method according to any one of claims 1-18.

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