A SiC trench mosfet device and a method of manufacturing the same

Abstract

The application discloses a SiC trench MOSFET device and a manufacturing method thereof. The application forms a second conductive type column region, reduces a gate oxide layer peak electric field, protects the gate oxide layer, uses a super-junction structure formed by the column region and an epitaxial layer, obviously reduces a drift region resistance of the device on the premise of ensuring that a breakdown characteristic of the device is not degraded, and thus effectively improves a forward conduction characteristic of the device.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor device technology, specifically relating to a SiC trench MOSFET device and its manufacturing method. Background Technology

[0002] The development of power electronic systems has placed higher demands on the performance of semiconductor devices, especially in areas such as high temperature, high frequency, radiation resistance, and high voltage. While traditional silicon-based devices have mature fabrication processes, the inherent properties of the material limit their application in extreme operating environments. SiC, a typical representative of third-generation wide-bandgap semiconductor materials, has become one of the most important semiconductor materials for fabricating high-power devices capable of withstanding extreme environments due to its stable physical and chemical properties, large bandgap, high thermal conductivity, high breakdown voltage, high electron saturation drift velocity, and strong radiation resistance.

[0003] Conventional planar gate SiC MOSFET devices exhibit a parasitic junction field-effect transistor structure, increasing the device's on-resistance. SiC trench MOSFET devices, by forming channels on the trench sidewalls, improve channel mobility and eliminate the JFET effect, significantly reducing on-resistance and allowing for smaller cell size and increased power density. However, a major problem with SiC trench MOSFET devices is that the gate oxide layer at the trench corners must withstand a large electric field, affecting device reliability. A traditional solution is to form a P-shield region at the bottom of the trench to protect the gate oxide layer, but this narrows the forward current path, increasing the device's on-resistance. Summary of the Invention

[0004] Technical problem solved: To address the above-mentioned technical problems, the present invention provides a SiC trench MOSFET device and its manufacturing method, which can effectively solve the problem that the gate oxide layer at the trench corner of the SiC trench MOSFET device is subjected to a large electric field strength, which reduces the reliability of the device.

[0005] Technical solution: A SiC trench MOSFET device, including

[0006] Drain electrode;

[0007] A substrate of the first conductivity type is located on the upper surface of the drain electrode;

[0008] The first conductivity type epitaxial layer is located on the upper surface of the first conductivity type substrate;

[0009] The second conductivity type well region is located on the upper surface of the first conductivity type epitaxial layer;

[0010] The first conductivity type source region is located on the upper surface of the preset region of the second conductivity type well region;

[0011] The second conductivity type heavily doped region is located on the upper surface of the remaining region of the second conductivity type well region;

[0012] The gate trench is located in the first conductivity type epitaxial layer, the second conductivity type well region, and the first conductivity type source region;

[0013] A gate dielectric layer is located on the surface of the gate trench;

[0014] The gate electrode is located inside the gate dielectric layer;

[0015] The source electrode is located on the upper surface of the source region portion of the first conductivity type and the upper surface of the heavily doped region of the second conductivity type.

[0016] The second conductivity type pillar region is located in the first conductivity type epitaxial layer below the second conductivity type well region and the gate trench;

[0017] An isolation dielectric layer is located on the upper surface of the remaining portion of the source region of the first conductivity type and on the upper surface of the gate dielectric layer.

[0018] Preferably, there is at least one gate trench.

[0019] Preferably, two or more gate trenches are arranged in a continuous or discontinuous manner.

[0020] Preferably, the depth-to-width ratio of the second conductive type column region is greater than 2:1.

[0021] A method for manufacturing a SiC trench MOSFET device includes the following steps:

[0022] S1. An epitaxial layer of the first conductivity type is formed on a first conductivity type substrate by epitaxial growth;

[0023] S2. Remove the epitaxial layer of the first conductivity type in the region where the second conductivity type pillar area is located by deep trench etching;

[0024] S3. Form a second type of conductive column region through epitaxial backfilling process or multiple injection-epitaxy process;

[0025] S4. Secondary epitaxy forms a well region epitaxial layer, and a second conductivity type well region, a second conductivity type heavily doped region, and a first conductivity type source region are formed through photolithography and ion implantation processes;

[0026] S5. A gate trench is formed by etching from the source region of the first conductivity type to the epitaxial layer of the first conductivity type;

[0027] S6. Remove the etching mask layer, passivate the gate trench, and perform high-temperature annealing;

[0028] S7. A gate dielectric layer is deposited inside the gate trench and then subjected to high-temperature annealing.

[0029] S8. A gate electrode material is grown inside the gate dielectric layer by chemical vapor deposition to form a gate electrode;

[0030] S9. An isolation dielectric layer is deposited on the upper surface of the source region of the first conductivity type and the upper surface of the gate dielectric layer to form a source window, through which a source ohmic contact is formed, and a drain ohmic contact is formed on the lower surface of the first conductivity type substrate. A source electrode is formed on the upper surface of the source ohmic contact layer, and a drain electrode is formed on the lower surface of the drain ohmic contact layer.

[0031] Preferably, in step S5, the depth of the gate trench is greater than the thickness of the epitaxial layer of the well region, and the second conductivity type pillar region below the gate trench is connected to the bottom of the gate trench.

[0032] Preferably, the difference between the width of the second conductivity type post region and the width of the gate trench does not exceed 1µm.

[0033] Beneficial effects: By forming a pillar region of the second conductivity type, this invention reduces the peak electric field of the gate oxide layer and protects the gate oxide layer. At the same time, by utilizing the superjunction structure formed by the pillar region and the epitaxial layer, it significantly reduces the drift region resistance of the device without degrading the breakdown characteristics, thereby effectively improving the forward conduction characteristics of the device. Attached Figure Description

[0034] Figure 1 This is a schematic diagram of the SiC trench MOSFET device in Example 1;

[0035] Figure 2 This is a schematic diagram of the SiC trench MOSFET device in Example 2;

[0036] Figure 3 This is a schematic diagram of the SiC trench MOSFET device in Example 3;

[0037] Figures 4-12 This is a schematic diagram of the fabrication process of the SiC trench MOSFET device in Example 1;

[0038] In the figure, the numbers represent: 1. Drain electrode; 2. Substrate of the first conductivity type; 3. Epitaxial layer of the first conductivity type; 4. Pillar region of the second conductivity type; 5. Gate dielectric layer; 6. Well region of the second conductivity type; 7. Gate electrode; 8. Heavy doped region of the second conductivity type; 9. Source region of the first conductivity type; 10. Source electrode; 11. Isolation dielectric layer; 12. Modulation region of the second conductivity type. Detailed Implementation

[0039] The present invention will now be described in detail with reference to the accompanying drawings and specific embodiments:

[0040] Example 1

[0041] like Figure 1 As shown, a SiC trench MOSFET device includes a drain electrode 1; a first conductivity type substrate 2 located on the upper surface of the drain electrode 1; and a first conductivity type epitaxial layer 3 located on the upper surface of the first conductivity type substrate 2, wherein the doping concentration of the first conductivity type epitaxial layer 3 is 1×10⁻⁶. 16 cm -3 ~2×10 17 cm -3 The second conductivity type well region 6 is located on the upper surface of the first conductivity type epitaxial layer 3; the first conductivity type source region 9 is located on the upper surface of a predetermined region of the second conductivity type well region 6; the second conductivity type heavily doped region 8 is located on the upper surface of the remaining regions of the second conductivity type well region 6; and a gate trench is located in the first conductivity type epitaxial layer 3, the second conductivity type well region 6, and the first conductivity type source region 9. There is at least one gate trench, and two or more gate trenches are arranged in a continuous or discontinuous manner. The depth of the gate trench is 0.7~1. The gate trench has a diameter of 5µm and a width of 0.8~1.4µm, and the depth of the gate trench is greater than the thickness of the epitaxial layer of the well region; a gate dielectric layer 5 is located on the surface of the gate trench; a gate electrode 7 is located inside the gate dielectric layer 5, and the gate electrode 7 is metal or doped polysilicon; a source electrode 10 is located on the upper surface of the first conductivity type source region 9 and the upper surface of the second conductivity type heavily doped region 8; a second conductivity type pillar region 4 is located in the first conductivity type epitaxial layer 3 below the second conductivity type well region 6 and the gate trench, and the doping concentration of the second conductivity type pillar region 4 is 1×10⁻⁶. 16 cm -3 ~5×10 17 cm -3 The depth-to-width ratio of the second conductive type pillar region 4 is greater than 2:1, the width of the second conductive type pillar region 4 is less than the width of the gate trench, and the difference between the two does not exceed 1 μm; the isolation dielectric layer 11 is located on the upper surface of the remaining part of the first conductive type source region 9 and the upper surface of the gate dielectric layer 5, and the isolation dielectric layer 11 is silicon dioxide, nitride or a composite of different nitrides.

[0042] A method for manufacturing a SiC trench MOSFET device includes the following steps:

[0043] S1. As Figures 4-5 As shown, an epitaxial layer 3 of the first conductivity type is formed on a first conductivity type substrate 2 by epitaxial growth;

[0044] S2. For example Figure 6As shown, an etching mask layer is grown on the surface of the first conductivity type epitaxial layer 3 by chemical vapor deposition, and then the etching mask layer is patterned by photolithography. The patterned etching mask layer is used to perform inductively coupled plasma etching on the first conductivity type epitaxial layer 3 to remove the first conductivity type epitaxial layer 3 in the area where the second conductivity type pillar region 4 is located.

[0045] S3. For example Figure 7 As shown, the etch mask layer is removed, and a second conductive type pillar region 4 is formed by epitaxial backfill process or multiple implantation-epitaxy process;

[0046] S4. For example Figures 8-9 As shown, a well region epitaxial layer is formed by secondary epitaxy, and a second conductivity type well region 6, a second conductivity type heavily doped region 8, and a first conductivity type source region 9 are formed by photolithography and ion implantation processes;

[0047] S5. For example Figure 10 As shown, a patterned etching mask layer is formed on the surface of the epitaxial layer of the well region, and inductively coupled plasma etching is performed from the source region 9 of the first conductivity type to the epitaxial layer 3 of the first conductivity type to form a gate trench.

[0048] S6. Remove the etching mask layer, passivate the gate trench, and perform high-temperature annealing;

[0049] S7. For example Figure 11 As shown, a silicon dioxide layer is formed on the surface of the trench through thermal oxidation and chemical vapor deposition processes, serving as the gate dielectric layer 5, and then subjected to high-temperature annealing.

[0050] S8. For example Figure 12 As shown, polysilicon is grown inside the gate dielectric layer 5 by chemical vapor deposition, polysilicon implantation is performed, and then polysilicon etching is performed to remove the polysilicon outside the trench area to form the gate electrode 7.

[0051] S9. For example Figure 1 As shown, an isolation dielectric layer 11 is deposited on the upper surface of the source region 9 of the first conductivity type and the upper surface of the gate dielectric layer 5 to form a source window. A source ohmic contact is formed through this source window. A drain ohmic contact is formed on the lower surface of the first conductivity type substrate 2. A source electrode 10 is formed on the upper surface of the source ohmic contact layer, and a drain electrode 1 is formed on the lower surface of the drain ohmic contact layer.

[0052] In step S5, the depth of the gate trench is greater than the thickness of the epitaxial layer of the well region, and the second conductivity type pillar region below the gate trench is connected to the bottom of the gate trench.

[0053] The difference between the width of the post region and the width of the gate trench in the second conductivity type mentioned above does not exceed 1µm.

[0054] Example 2

[0055] A SiC trench MOSFET device, such as Figure 2 As shown, it is basically the same as in Embodiment 1, except that a second conductivity type modulation region 12 is formed between the second conductivity type well region 6 and the second conductivity type pillar region 4 by ion implantation, so that the second conductivity type pillar region 4 can be short-circuited with the source and can help modulate the electric field of the gate oxide layer.

[0056] Example 3

[0057] A SiC trench MOSFET device, such as Figure 3 As shown, it is basically the same as in Example 1, except that the bottom thickness of the gate dielectric layer 5 is not less than 300 nm and the sidewall thickness is 40~60 nm. The bottom thickness is significantly greater than the sidewall thickness, and the thickened SiC trench MOSFET device can improve the capacitance characteristics of the device.

[0058] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A method for manufacturing a SiC trench MOSFET device, characterized in that, The SiC trench MOSFET device includes: Drain electrode (1); A first conductivity type substrate (2) is located on the upper surface of the drain electrode (1); The first conductivity type epitaxial layer (3) is located on the upper surface of the first conductivity type substrate (2), and the doping concentration of the first conductivity type epitaxial layer (3) is 1×10⁻⁶. 16 cm -3 ~2×10 17 cm -3 ; The second conductivity type well region (6) is located on the upper surface of the first conductivity type epitaxial layer (3); The first conductivity type source region (9) is located on the upper surface of the preset region of the second conductivity type well region (6); The second conductivity type heavily doped region (8) is located on the upper surface of the remaining region of the second conductivity type well region (6); The gate trench is located in the first conductivity type epitaxial layer (3), the second conductivity type well region (6), and the first conductivity type source region (9); The gate dielectric layer (5) is located on the surface of the gate trench; The gate electrode (7) is located inside the gate dielectric layer (5); The source electrode (10) is located on the upper surface of the first conductivity type source region (9) and the upper surface of the second conductivity type heavily doped region (8); The second conductivity type pillar region (4) is located in the first conductivity type epitaxial layer (3) below the second conductivity type well region (6) and the gate trench. The doping concentration of the second conductivity type pillar region (4) is 1×10⁻⁶. 16 cm -3 ~5×10 17 cm -3 A second conductivity type modulation region is formed between the second conductivity type well region (6) and the second conductivity type pillar region (4) through ion implantation; An isolation dielectric layer (11) is located on the upper surface of the remaining portion of the source region (9) of the first conductivity type and on the upper surface of the gate dielectric layer (5); The manufacturing method includes the following steps: S1. An epitaxial layer (3) of the first conductivity type is formed on a substrate (2) by epitaxial growth. S2. Remove the first conductivity type epitaxial layer (3) in the area where the second conductivity type pillar region (4) is located by deep trench etching; S3. A second conductive type column region is formed by epitaxial backfilling process or multiple injection-epitaxy process (4). S4. Secondary epitaxy forms a well region epitaxial layer, and a second conductivity type well region (6), a second conductivity type heavily doped region (8), and a first conductivity type source region (9) are formed by photolithography and ion implantation processes. S5. A gate trench is formed from the source region (9) of the first conductivity type to the epitaxial layer (3) of the first conductivity type by etching; S6. Remove the etching mask layer, passivate the gate trench, and perform high-temperature annealing; S7. A gate dielectric layer (5) is deposited inside the gate trench and subjected to high-temperature annealing. S8. A gate electrode material is grown inside the gate dielectric layer (5) by chemical vapor deposition to form a gate electrode (7). S9. An isolation dielectric layer (11) is deposited on the upper surface of the source region (9) of the first conductivity type and the upper surface of the gate dielectric layer (5) to form a source window, through which a source ohmic contact is formed, a drain ohmic contact is formed on the lower surface of the substrate (2) of the first conductivity type, a source electrode (10) is formed on the upper surface of the source ohmic contact layer, and a drain electrode (1) is formed on the lower surface of the drain ohmic contact layer.

2. The manufacturing method according to claim 1, characterized in that: There must be at least one gate trench.

3. The manufacturing method according to claim 2, characterized in that: Two or more gate trenches are arranged in a continuous or discontinuous manner.

4. The manufacturing method according to claim 1, characterized in that: The depth-to-width ratio of the second conductive type column region (4) is greater than 2:

1.

5. The manufacturing method according to claim 1, characterized in that: In step S5, the depth of the gate trench is greater than the thickness of the epitaxial layer of the well region, and the second conductivity type pillar region (4) below the gate trench is connected to the bottom of the gate trench.

6. The manufacturing method according to claim 5, characterized in that: The difference between the width of the second conductivity type column region (4) and the width of the gate trench does not exceed 1µm.

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