A trench MOSFET device and a method of fabricating the same

Abstract

The application provides a trench MOSFET device and a preparation method thereof, wherein the n-stage ladder source trench is located at the bottom of the gate trench, which is equivalent to that the gate trench and the n-stage ladder source trench are both in the same trench, so that the cell size can be reduced, and the high-doped fifth doped area injected at the bottom of the n-stage ladder source trench can be deeper, so as to better protect and optimize the electric field distribution at the bottom of the gate oxide layer; and a reverse-parallel Schottky diode is further arranged near the source, so that the MOSFET transistor diode pressure drop can be significantly reduced on the basis of not affecting the cell size, the integration of the chip is improved, the manufacturing cost of the MOSFET device integrated with the Schottky diode is reduced, the current density can be further improved through the improvement of the multiple structures, the specific on-resistance is reduced, and the integrated Schottky diode can obviously improve the Schottky contact area and further improve the reverse current flow capacity of the Schottky diode.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device technology, and more specifically, to a trench MOSFET device and its fabrication method. Background Technology

[0002] Silicon carbide (chemical formula SiC) materials have advantages in physical properties such as large bandgap, high breakdown electric field, fast electron mobility, and high thermal conductivity. These characteristics make silicon carbide materials very suitable for high temperature, high pressure, high frequency and radiation-resistant environments.

[0003] SiC power MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) are unipolar voltage-controlled devices, mainly used in power supplies and power processing systems to control power conversion. Compared with traditional Si-based power devices, SiC devices are easier to achieve high voltage, low loss and high power density, and therefore have gradually become the mainstream in the market.

[0004] One of the key factors currently limiting the cost reduction and further parameter improvement of MOSFET devices is how to reduce their on-resistance (on-resistance per unit chip area). To reduce on-resistance, trench MOSFETs have become a hot research and development topic. Compared to the low channel mobility of planar MOSFET cells in the (0001) plane, the channel of a trench MOSFET is located on a crystal plane perpendicular to the (0001) plane, typically in the (11-20) plane. The electron mobility near the channel on this crystal plane is significantly higher than that on the (0001) plane, and the size of the channel cell can be made smaller. Therefore, trench MOSFET devices have lower specific on-resistance and higher current density.

[0005] However, in trench MOSFET structures, electric field concentration is easily formed at the bottom of the gate trench. Since the gate oxide material is generally SiO2 with a dielectric constant of 3.9, while SiC has a dielectric constant of 9.7, the electric field in SiO2 at the gate oxide interface is 2.5 times that of SiC, and the critical electric field of SiC is 10 times that of Si. Therefore, when the device is subjected to high voltage, the gate oxide layer at the bottom of the gate trench of SiC device is prone to reliability problems. Thus, how to alleviate or avoid electric field concentration at the bottom of the gate trench is a current research hotspot.

[0006] To alleviate the electric field concentration at the bottom of the gate trench, P-type doped ions are typically injected into the bottom of the gate trench or into the bottom of the source trench in a dual-trench structure (i.e., the gate and source of a trench MOSFET are in two separate trenches). However, injecting P-type doped ions into the bottom of the gate trench can block the current path near the bottom of the gate trench. The dual-trench structure of the gate and source will significantly increase the cell size, increase the specific on-resistance, and decrease the current density. Furthermore, the bottom of the source trench is far from the bottom of the gate trench, making it difficult to significantly alleviate the electric field concentration at the bottom of the gate trench.

[0007] In addition, in practical applications, transistors often need to be connected in anti-parallel with a freewheeling diode, which increases both cost and size. If a Schottky diode is integrated inside the device cell, the chip integration density can be improved. However, currently, integrating diodes inside the device generally increases the cell size significantly, resulting in increased on-resistance and reduced current density.

[0008] Therefore, how to integrate Schottky diodes inside the device without affecting the cell size, and thus improve the chip integration, reduce diode voltage drop, and reduce device manufacturing cost without affecting the specific on-resistance and current density, is a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0009] In view of this, to solve the above problems, the present invention provides a trench MOSFET device and a method for fabricating the same, the technical solution of which is as follows:

[0010] A trench MOSFET device, the trench MOSFET device comprising:

[0011] Substrate;

[0012] In a first direction, a buffer layer, an epitaxial layer, and a current spreading layer are sequentially located on one side of the substrate; the current spreading layer has a gate trench on the side opposite to the substrate and an n-level stepped source trench located at the bottom of the gate trench, where n is a positive integer greater than or equal to 1; the first direction is perpendicular to the plane where the substrate is located and points from the substrate to the current spreading layer;

[0013] A first structural portion located within the gate trench, the first structural portion including a gate oxide layer, a gate, and an isolation dielectric layer; wherein the gate oxide layer covers the bottom and sidewalls of the gate trench, the gate is located on the gate oxide layer, and the isolation dielectric layer covers the surface of the gate facing away from the substrate, and covers the sidewall of the gate adjacent to the n-stage stepped source trench.

[0014] The sidewalls of the gate trench adjacent to the first structural portion have a first doped region, a second doped region, and a third doped region. The first doped region and the second doped region are located between the third doped region and the first structural portion, and the first doped region and the second doped region are arranged sequentially in the first direction.

[0015] The sidewalls of the gate trench adjacent to the n-level stepped source trench have a fourth doped region, and the bottom of the n-level stepped source trench has a fifth doped region.

[0016] An ohmic contact layer is provided at the bottom of the n-level stepped source trench, and a Schottky contact layer is provided on the sidewall of the first-level stepped source trench adjacent to the gate trench.

[0017] The source electrode is located within the n-level stepped source trench, and the drain electrode is located on the side of the substrate opposite to the buffer layer.

[0018] Preferably, in the above-described trench MOSFET device, the ohmic contact layer further extends onto the sidewall of the first-stage stepped source trench adjacent to the first structural portion of the n-stage stepped source trench.

[0019] Preferably, in the above-described trench MOSFET device, the Schottky contact layer further extends onto the sidewall of the first-stage stepped source trench adjacent to the first structural portion of the n-stage stepped source trench.

[0020] Preferably, in the above-mentioned trench MOSFET device, the n-stage stepped source trench is a two-stage stepped source trench;

[0021] The ohmic contact layer also extends to the sidewall of the second-level stepped source trench in the n-level stepped source trench.

[0022] Preferably, in the above-described trench MOSFET device, the n-stage stepped source trench is located in the middle region of the gate trench, and the first structural portion is located on one side of the n-stage stepped source trench.

[0023] The trench MOSFET device further includes:

[0024] A second structural portion is located within the gate trench, and the second structural portion is located on the other side of the n-stage stepped source trench. The first structural portion and the second structural portion have the same structure.

[0025] The sixth and seventh doped regions are located between the fourth doped region and the second structural portion, and the sixth and seventh doped regions are arranged sequentially in the first direction.

[0026] Preferably, in the above-mentioned trench MOSFET device, the first doped region is a low-doped region of the second doping type;

[0027] The second doped region is a highly doped region of the first doping type;

[0028] The third doping region is a highly doped region of the second doping type;

[0029] The fourth doping region is a highly doped region of the second doping type;

[0030] The fifth doping region is a highly doped region of the second doping type;

[0031] The sixth doping region is a low-doped region of the second doping type;

[0032] The seventh doping region is a highly doped region of the first doping type.

[0033] Preferably, in the above-described trench MOSFET device, the doping concentration of the first doped region is 1E16cm⁻¹. -3 -1E18cm -3 ;

[0034] The doping concentration of the second doped region is 1E18cm. -3 -5E20cm -3 ;

[0035] The doping concentration of the third doped region is 1E17cm⁻¹. -3 -8E20cm -3 ;

[0036] The doping concentration of the fourth doped region is 1E17cm⁻¹. -3 -8E20cm -3 ;

[0037] The doping concentration of the fifth doped region is 1E16cm⁻¹ -3 -5E20cm -3 ;

[0038] The doping concentration of the sixth doped region is 1E16cm⁻¹ -3 -1E18cm -3 ;

[0039] The doping concentration of the seventh doped region is 1E18cm⁻¹. -3 -5E20cm -3 .

[0040] Preferably, in the above-mentioned trench MOSFET device, the doping depth of the first doped region is 0.2um-1.5um;

[0041] The doping depth of the second doped region is 0.1µm-0.5µm;

[0042] The doping depth of the third doped region is 0.3µm-1.5µm;

[0043] The doping depth of the fourth doping region is 0.3-1.5 μm;

[0044] The doping depth of the fifth doping region is 0.2µm-1.5µm;

[0045] The doping depth of the sixth doping region is 0.2µm-1.5µm;

[0046] The doping depth of the seventh doping region is 0.1um-0.5um.

[0047] Preferably, in the above-mentioned trench MOSFET device, the first doping type is N-type doping and the second doping type is P-type doping.

[0048] A method for fabricating a trench MOSFET device, used to fabricate the trench MOSFET device described in any one of the above claims, the method comprising:

[0049] Provide a substrate;

[0050] In a first direction, a buffer layer, an epitaxial layer, and a current spreading layer are sequentially formed on one side of the substrate; the current spreading layer has a gate trench on the side opposite to the substrate and an n-level stepped source trench located at the bottom of the gate trench, where n is a positive integer greater than or equal to 1; the first direction is perpendicular to the plane where the substrate is located and points from the substrate to the current spreading layer;

[0051] A subsequent structure is fabricated, wherein the subsequent structure includes a first structural portion located within the gate trench, the first structural portion including a gate oxide layer, a gate, and an isolation dielectric layer; wherein the gate oxide layer covers the bottom and sidewalls of the gate trench, the gate is located on the gate oxide layer, the isolation dielectric layer covers the surface of the gate facing away from the substrate, and covers the sidewall of the gate adjacent to the n-stage stepped source trench; the sidewall of the gate trench adjacent to the first structural portion has a first doped region, a second doped region, and a third doped region, the first doped region and the second doped region are located between the third doped region and the first structural portion, and the first doped region and the second doped region are sequentially arranged in the first direction; the sidewall of the gate trench adjacent to the n-stage stepped source trench has a fourth doped region, and the bottom of the n-stage stepped source trench has a fifth doped region; an ohmic contact layer is disposed at the bottom of the n-stage stepped source trench, and a Schottky contact layer is disposed on the sidewall of the first-stage stepped source trench adjacent to the gate trench;

[0052] A source electrode is formed within the n-level stepped source trench, and a drain electrode is formed on the side of the substrate opposite to the buffer layer.

[0053] Compared with the prior art, the beneficial effects achieved by the present invention are as follows:

[0054] The trench MOSFET device provided by this invention features an n-stage stepped source trench located at the bottom of the gate trench, effectively placing both the gate trench and the n-stage stepped source trench within the same trench. This allows for a smaller cell size, reducing the specific on-resistance of the MOSFET device and increasing the current density per unit area. Furthermore, the n-stage stepped source trench allows for a deeper highly doped fifth doped region injected at the bottom of the trench, better protecting and optimizing the electric field distribution at the bottom of the gate oxide layer, thus improving gate oxide reliability. An isolation dielectric layer separates the gate and source. When the trench MOSFET device is forward-biased, the distance between the bottom of the gate trench and the bottom of the n-stage stepped source trench is... The highly doped third doped region injected into the sidewall is at a certain distance, and the n-stage stepped source trench is deeper. This highly doped third doped region does not affect the current path near the bottom of the trench. At the same time, under the influence of the current spreading layer, the current path from the vicinity of the channel to the bottom of the n-stage stepped source trench is unobstructed. When the device is reverse-biased, compared with the structure where the gate and source are in two trenches, the structure of this invention has the source and gate in the same trench, the lateral distance between the source and gate is closer, and the source is located in the n-stage stepped source trench, which allows the highly doped fifth doped region injected at the bottom of the n-stage stepped source trench to be deeper, which can effectively and significantly alleviate the electric field concentration at the bottom of the gate trench and better protect the gate oxide layer.

[0055] Furthermore, a Schottky diode is connected in antiparallel near the source, which significantly reduces the diode voltage drop of the MOSFET transistor without affecting the cell size, improves the chip integration, and reduces the manufacturing cost of MOSFET devices with integrated Schottky diodes. Further improvements through multiple structures can further increase the current density, significantly reduce the specific on-resistance, and, without affecting the cell size, integrate the Schottky diode to significantly improve the Schottky contact area, further enhancing the reverse freewheeling capability of the Schottky diode. Attached Figure Description

[0056] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0057] Figure 1 This is a schematic diagram of the structure of a trench MOSFET device provided in an embodiment of the present invention;

[0058] Figure 2 This is a schematic diagram of another trench MOSFET device provided in an embodiment of the present invention;

[0059] Figure 3 This is a schematic diagram of another trench MOSFET device provided in an embodiment of the present invention;

[0060] Figure 4 This is a schematic diagram of another trench MOSFET device provided in an embodiment of the present invention;

[0061] Figure 5 This is a schematic diagram of another trench MOSFET device provided in an embodiment of the present invention;

[0062] Figure 6 This is a schematic diagram of another trench MOSFET device provided in an embodiment of the present invention;

[0063] Figure 7 This is a schematic flowchart illustrating a method for fabricating a trench MOSFET device according to an embodiment of the present invention.

[0064] Figures 8-11 for Figure 7 A partial structural schematic diagram corresponding to the preparation method shown. Detailed Implementation

[0065] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0066] Based on the background art, this invention provides a novel trench MOSFET device. On the one hand, this novel trench MOSFET device can reduce the size of the trench cell while ensuring gate oxide reliability, thereby reducing the specific on-resistance of the MOSFET transistor and increasing the current density per unit area. On the other hand, a Schottky diode is connected in anti-parallel near the source of the cell structure, which can significantly reduce the diode voltage drop of the MOSFET transistor without affecting the cell size, thereby increasing the chip integration and reducing the manufacturing cost of the MOSFET device with integrated Schottky diode.

[0067] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0068] refer to Figure 1 , Figure 1 This is a schematic diagram of a trench MOSFET device provided in an embodiment of the present invention. The trench MOSFET device includes:

[0069] Substrate 11; in a first direction, a buffer layer 12, an epitaxial layer 13, and a current spreading layer 14 are sequentially located on one side of the substrate 11; the current spreading layer 14 has a gate trench on the side opposite to the substrate 11 and an n-level stepped source trench located at the bottom of the gate trench, where n is a positive integer greater than or equal to 1; the first direction is perpendicular to the plane where the substrate 11 is located and points from the substrate 11 to the current spreading layer 14.

[0070] A first structural portion located within the gate trench, the first structural portion including a gate oxide layer 15, a gate 16, and an isolation dielectric layer 17; wherein the gate oxide layer 15 covers the bottom and sidewalls of the gate trench, the gate 16 is located on the gate oxide layer 15, and the isolation dielectric layer 17 covers the surface of the gate 16 facing away from the substrate 11, and covers the sidewall of the gate 16 adjacent to the n-stage stepped source trench.

[0071] The sidewalls of the gate trench adjacent to the first structural portion have a first doped region 18, a second doped region 19 and a third doped region 20. The first doped region 18 and the second doped region 19 are located between the third doped region 20 and the first structural portion, and the first doped region 18 and the second doped region 19 are arranged sequentially in the first direction.

[0072] The sidewalls of the gate trench adjacent to the n-stage stepped source trench have a fourth doped region 21, and the bottom of the n-stage stepped source trench has a fifth doped region 22.

[0073] An ohmic contact layer 23 is provided at the bottom of the n-stage stepped source trench, and a Schottky contact layer 24 is provided on the sidewall of the first-stage stepped source trench adjacent to the gate trench.

[0074] The source 25 is located within the n-level stepped source trench, and the drain 26 is located on the side of the substrate 11 opposite to the buffer layer 12.

[0075] Specifically, in this embodiment of the invention, the drain 26 includes, but is not limited to, a drain made of a metal material, and the substrate 11 includes, but is not limited to, an N-type highly doped SiC substrate with a doping concentration of 1E18cm⁻¹. -3 -5E19cm -3 The thickness is 80um-400um; the buffer layer 12 includes, but is not limited to, a highly doped N-type SiC buffer layer with a doping concentration of 7E17cm⁻¹. -3 -3E18cm -3 The thickness is about 1 μm; the epitaxial layer 13 includes, but is not limited to, an N-type lightly doped SiC epitaxial layer with a doping concentration of 1E15cm⁻¹. -3 -8E16cm -3 The thickness ranges from 4µm to 100µm; the current spreading layer 14 is N-type doped with a doping concentration of 1E15cm. -3 -1E18cm -3 The depth is 0.3um-5um.

[0076] By processing the current spreading layer 14, a gate trench and an n-stage stepped source trench located at the bottom of the gate trench are formed. Since the n-stage stepped source trench is located at the bottom of the gate trench, it is equivalent to the gate trench and the n-stage stepped source trench being inside the same trench, which can reduce the cell size. Furthermore, a fifth doped region 22 is formed by injection at the bottom of the n-stage stepped source trench. This fifth doped region 22 is a highly doped P-type region, i.e., a well is formed. Then, an ohmic contact layer 23 and a Schottky contact layer 24 are formed in the well. After that, other structures required for subsequent formation are formed, such as the first doped region 18, the second doped region 19, the third doped region 20, the fourth doped region 21, the gate oxide layer 15, the gate 16, the isolation dielectric layer 17, and the source 25, etc.

[0077] The gate oxide layer 15 includes, but is not limited to, a gate oxide layer made of silicon dioxide; the gate electrode 16 includes, but is not limited to, a gate electrode made of metal or polycrystalline material; and the source electrode 25 includes, but is not limited to, a source electrode made of metal.

[0078] Optionally, in this embodiment of the invention, the first doped region 18 is a low-doped region of the second doping type; the doping concentration of the first doped region 18 is 1E16cm⁻¹. -3 -1E18cm -3 The doping depth of the first doped region 18 is 0.2um-1.5um.

[0079] The second doped region 19 is a highly doped region of the first doping type; the doping concentration of the second doped region 19 is 1E18cm⁻¹. -3 -5E20cm -3 The doping depth of the second doped region 19 is 0.1um-0.5um.

[0080] The third doped region 20 is a highly doped region of the second doping type; the doping concentration of the third doped region 20 is 1E17cm⁻¹. -3 -8E20cm -3 The doping depth of the third doped region 20 is 0.3um-1.5um.

[0081] The fourth doped region 212 is a highly doped region of the second doping type; the doping concentration of the fourth doped region 1 is 1E17cm. -3 -8E20cm -3 The doping depth of the fourth doped region 21 is 0.3-1.5 μm.

[0082] The fifth doped region 22 is a highly doped region of the second doping type. The doping concentration of the fifth doped region 22 is 1E16cm⁻¹. -3 -5E20cm-3 The doping depth of the fifth doping region 22 is 0.2um-1.5um.

[0083] Wherein, the first doping type is N-type doping, and the second doping type is P-type doping.

[0084] It should be noted that the third doped region 20 and the fourth doped region 21 can be a single doped region or two independent doped regions, and this is not limited in the embodiments of the present invention.

[0085] Optional, such as Figure 1 As shown, the ohmic contact layer 23 also extends onto the sidewall of the first-level stepped source trench adjacent to the first structural portion of the n-level stepped source trench.

[0086] As described above, in the trench MOSFET device provided by this embodiment, the n-stage stepped source trench is located at the bottom of the gate trench, which is equivalent to the gate trench and the n-stage stepped source trench being inside the same trench. This can reduce the cell size, and the setting of the n-stage stepped source trench can also make the highly doped fifth doped region 22 injected at the bottom of the n-stage stepped source trench deeper, so as to better protect and optimize the electric field distribution at the bottom of the gate oxide layer 15 of the gate trench. The gate 16 and the source 25 are isolated by an isolation dielectric layer 17. When the trench MOSFET device is forward-biased, the bottom of the gate trench is far from the bottom and sidewall of the n-stage stepped source trench, where the highly doped third doped region 20 is injected. With a certain distance between them, and the n-stage stepped source trench being deeper, this highly doped third doped region 20 will not affect the current path near the bottom of the trench. At the same time, under the influence of the current extension layer 14, the current path from the vicinity of the channel to the bottom of the n-stage stepped source trench is unobstructed. When the device is reverse-biased, compared to the structure where the gate and source are in two trenches, the structure of the present invention has the source 25 and the gate 16 in the same trench, the lateral distance between the source 25 and the gate 16 is closer, and the n-stage stepped source trench where the source 25 is located allows the highly doped fifth doped region 22 injected at the bottom of the n-stage stepped source trench to be deeper, which can effectively and significantly alleviate the electric field concentration at the bottom of the gate trench and better protect the gate oxide layer 15.

[0087] Furthermore, a Schottky diode is connected in antiparallel near the source 25. Without affecting the cell size, this can significantly reduce the diode voltage drop of the MOSFET transistor, improve the chip integration, reduce the manufacturing cost of MOSFET devices with integrated Schottky diodes, increase current density, reduce specific on-resistance, and significantly improve the Schottky contact area, thereby further enhancing the reverse freewheeling capability of the Schottky diode.

[0088] Optionally, in another embodiment of the invention, reference is made to... Figure 2 , Figure 2 This is a schematic diagram of another trench MOSFET device provided in an embodiment of the present invention.

[0089] The Schottky contact layer 24 also extends onto the sidewall of the first-stage stepped source trench adjacent to the first structural portion of the n-stage stepped source trench.

[0090] Specifically, in the embodiments of the present invention, based on Figure 1 The structure of the trench MOSFET device shown replaces the ohmic contact layer 23 on the sidewall of the first-stage stepped source trench adjacent to the first structural portion with a Schottky contact layer 24.

[0091] In other words, Figure 2 In the structure of the trench MOSFET device shown, the two sidewalls of the first step source trench of the n-stage stepped source trench are Schottky contacts. The bottom of the n-stage stepped source trench is injected with highly doped ions of the second doping type to form a fifth doped region 22, where an ohmic contact is formed with the source 25 through an ohmic contact layer 23.

[0092] As can be seen from the above description... Figure 2 The trench MOSFET device shown is compared to Figure 1 The trench MOSFET device shown increases the Schottky contact area, which can effectively improve the freewheeling capability of the reverse diode.

[0093] Optionally, in another embodiment of the invention, reference is made to... Figure 3 , Figure 3 This is a schematic diagram of another trench MOSFET device provided in an embodiment of the present invention.

[0094] The ohmic contact layer 23 also extends onto the sidewall of the first-level stepped source trench adjacent to the first structural portion of the n-level stepped source trench.

[0095] The n-level stepped source trench is a two-level stepped source trench.

[0096] The ohmic contact layer 23 also extends to the sidewall of the second-level stepped source trench of the n-level stepped source trench.

[0097] Specifically, in the embodiments of the present invention, based on Figure 1 The structure of the trench MOSFET device shown can be made into a two-stage, three-stage, four-stage, five-stage or other multi-stage stepped source trench with an n-stage stepped source trench. In this embodiment of the invention, a two-stage stepped source trench with an n-stage stepped source trench is used as an example for illustration.

[0098] In other words, the n-stage stepped source trench configuration allows for deeper implantation of the second doped type high-concentration doped ions at the bottom of the n-stage stepped source trench, i.e., deeper implantation of the fifth doped region 22 of the second doped type, in order to better protect and optimize the electric field distribution at the bottom of the gate oxide layer 15 of the gate trench, thereby protecting the gate oxide layer 15. Furthermore, by tilting the implantation method, an ohmic contact can be formed on one sidewall and the bottom of the trench, and a Schottky contact can be formed on the other sidewall of the source trench.

[0099] Optionally, in another embodiment of the invention, reference is made to... Figure 4 , Figure 4 This is a schematic diagram of another trench MOSFET device provided in an embodiment of the present invention.

[0100] The Schottky contact layer 24 also extends onto the sidewall of the first-stage stepped source trench adjacent to the first structural portion of the n-stage stepped source trench.

[0101] The n-level stepped source trench is a two-level stepped source trench.

[0102] The ohmic contact layer 23 also extends to the sidewall of the second-level stepped source trench of the n-level stepped source trench.

[0103] Specifically, in the embodiments of the present invention Figure 4 In the structure of the trench MOSFET device shown, the two sidewalls of the first step source trench of the n-stage stepped source trench are Schottky contacts. The bottom of the n-stage stepped source trench is injected with highly doped ions of the second doping type to form a fifth doped region 22, where an ohmic contact is formed with the source 25 through an ohmic contact layer 23.

[0104] In other words, Figure 4 The trench MOSFET device shown is compared to Figure 1 The trench MOSFET device shown increases the Schottky contact area, which can effectively improve the freewheeling capability of the reverse diode.

[0105] And based on Figure 1 The structure of the trench MOSFET device shown can be made into a two-stage, three-stage, four-stage, five-stage or other multi-stage stepped source trench with an n-stage stepped source trench. In this embodiment of the invention, a two-stage stepped source trench with an n-stage stepped source trench is used as an example for illustration.

[0106] In other words, the setting of the n-level stepped source trench can also allow the high concentration of doped ions of the second doping type at the bottom of the n-level stepped source trench to be implanted deeper, that is, the high doped fifth doped region 22 of the second doping type is implanted deeper, so as to better protect and optimize the electric field distribution at the bottom of the gate oxide layer 15 of the gate trench, thereby protecting the gate oxide layer 15. The bottom of the n-level stepped source trench forms an ohmic contact with the source 25 through the ohmic contact layer 23.

[0107] Optionally, in another embodiment of the invention, reference is made to... Figure 5 , Figure 5 This is a schematic diagram of another trench MOSFET device provided in an embodiment of the present invention.

[0108] The ohmic contact layer 23 also extends onto the sidewall of the first-level stepped source trench adjacent to the first structural portion of the n-level stepped source trench.

[0109] The n-level stepped source trench is a two-level stepped source trench.

[0110] The ohmic contact layer 23 also extends to the sidewall of the second-level stepped source trench of the n-level stepped source trench.

[0111] The n-stage stepped source trench is located in the middle region of the gate trench, and the first structural portion is located on one side of the n-stage stepped source trench.

[0112] The trench MOSFET device further includes:

[0113] The second structural portion is located within the gate trench, and the second structural portion is located on the other side of the n-stage stepped source trench. The first structural portion and the second structural portion have the same structure.

[0114] The sixth doped region 27 and the seventh doped region 28 are located between the fourth doped region 21 and the second structural portion, and the sixth doped region 27 and the seventh doped region 28 are arranged sequentially in the first direction.

[0115] Specifically, in the embodiments of the present invention, based on Figure 3 The trench MOSFET device shown has a second structural portion added. The second structural portion has the same structure as the first structural portion, that is to say... Figure 5 The trench MOSFET device shown is a symmetrical structure. The second structural part and the first structural part can be an integral structure or two independent structures. This is not limited in the embodiments of the present invention.

[0116] Similarly, the third doped region 20 and the fourth doped region 21 can be a single doped region or two independent doped regions, which is not limited in this embodiment of the invention; the sixth doped region 27 and the first doped region 18 can be a single doped region or two independent doped regions, which is not limited in this embodiment of the invention; the seventh doped region 28 and the second doped region 19 can be a single doped region or two independent doped regions, which is not limited in this embodiment of the invention.

[0117] Figure 5 The trench MOSFET device shown is a symmetrical structure, and the n-stage stepped source trench configuration allows for deeper implantation of the second-stage highly doped ions at the bottom of the trench, specifically a deeper fifth doped region 22 of the second-stage highly doped type. This better protects and optimizes the electric field distribution at the bottom of the gate oxide layer 15, thus protecting the gate oxide layer 15 and improving the reliability of the device's gate oxide layer. Furthermore, by tilting the implantation method, highly doped ions can be implanted into one sidewall and the bottom of the n-stage stepped source trench to form an ohmic contact, while the other sidewall forms a Schottky contact. In this structure, the gates of the two first-stage stepped trenches share the same multi-stage stepped source trench, effectively increasing the vertical channel path, improving the current density of the trench MOSFET device, and reducing the specific on-resistance. This MOSFET device cell integrates a Schottky diode, effectively improving the reverse freewheeling capability.

[0118] Optionally, in another embodiment of the invention, reference is made to... Figure 6 , Figure 6 This is a schematic diagram of another trench MOSFET device provided in an embodiment of the present invention.

[0119] The Schottky contact layer 24 also extends onto the sidewall of the first-stage stepped source trench adjacent to the first structural portion of the n-stage stepped source trench.

[0120] The n-level stepped source trench is a two-level stepped source trench.

[0121] The ohmic contact layer 23 also extends to the sidewall of the second-level stepped source trench of the n-level stepped source trench.

[0122] The n-stage stepped source trench is located in the middle region of the gate trench, and the first structural portion is located on one side of the n-stage stepped source trench.

[0123] The trench MOSFET device further includes:

[0124] The second structural portion is located within the gate trench, and the second structural portion is located on the other side of the n-stage stepped source trench. The first structural portion and the second structural portion have the same structure.

[0125] The sixth doped region 27 and the seventh doped region 28 are located between the fourth doped region 21 and the second structural portion, and the sixth doped region 27 and the seventh doped region 28 are arranged sequentially in the first direction.

[0126] Specifically, in the embodiments of the present invention, based on Figure 4 The trench MOSFET device shown has a second structural portion added. The second structural portion has the same structure as the first structural portion, that is to say... Figure 6 The trench MOSFET device shown is a symmetrical structure. The second structural part and the first structural part can be an integral structure or two independent structures. This is not limited in the embodiments of the present invention.

[0127] Similarly, the third doped region 20 and the fourth doped region 21 can be a single doped region or two independent doped regions, which is not limited in this embodiment of the invention; the sixth doped region 27 and the first doped region 18 can be a single doped region or two independent doped regions, which is not limited in this embodiment of the invention; the seventh doped region 28 and the second doped region 19 can be a single doped region or two independent doped regions, which is not limited in this embodiment of the invention.

[0128] Figure 6 The trench MOSFET device shown is a symmetrical structure. The two sidewalls of the first step source trench of the n-stage stepped source trench are Schottky contacts. The bottom of the n-stage stepped source trench is injected with highly doped ions of the second doping type to form a fifth doped region 22. Here, an ohmic contact is formed with the source 25 through the ohmic contact layer 23.

[0129] In other words, Figure 6 The symmetrical trench MOSFET device shown also increases the Schottky contact area, which can effectively improve the reverse diode freewheeling capability.

[0130] Furthermore, the n-stage stepped source trench configuration allows for deeper implantation of the second doped type high-concentration doped ions at the bottom of the n-stage stepped source trench, i.e., a deeper implantation of the fifth doped region 22 of the second doped type, in order to better protect and optimize the electric field distribution at the bottom of the gate oxide layer 15 of the gate trench, thereby protecting the gate oxide layer 15. The bottom of the n-stage stepped source trench forms an ohmic contact with the source 25 through the ohmic contact layer 23.

[0131] Optionally, the sixth doped region 27 is a low-doped region of the second doping type; the doping concentration of the sixth doped region 27 is 1E16cm. -3 -1E18cm -3 The doping depth of the sixth doping region 27 is 0.2um-1.5um.

[0132] Optionally, the seventh doped region 28 is a highly doped region of the first doping type; the doping concentration of the seventh doped region 28 is 1E18cm⁻¹. -3 -5E20cm -3 The doping depth of the seventh doping region 28 is 0.1um-0.5um.

[0133] Wherein, the first doping type is N-type doping, and the second doping type is P-type doping.

[0134] Optionally, based on all the above embodiments of the present invention, another embodiment of the present invention also provides a method for fabricating a trench MOSFET device, used to fabricate the trench MOSFET device described in any of the above embodiments, referencing... Figure 7 , Figure 7 This is a schematic flowchart of a method for fabricating a trench MOSFET device according to an embodiment of the present invention. The fabrication method includes:

[0135] S101: Provide a substrate.

[0136] S102: In a first direction, a buffer layer, an epitaxial layer, and a current spreading layer are sequentially formed on one side of the substrate; the side of the current spreading layer opposite to the substrate has a gate trench and an n-level stepped source trench located at the bottom of the gate trench, where n is a positive integer greater than or equal to 1; the first direction is perpendicular to the plane where the substrate is located and points from the substrate to the current spreading layer.

[0137] S103: Fabricate a subsequent structure, wherein the subsequent structure includes a first structural portion located within the gate trench, the first structural portion including a gate oxide layer, a gate, and an isolation dielectric layer; wherein the gate oxide layer covers the bottom and sidewalls of the gate trench, the gate is located on the gate oxide layer, the isolation dielectric layer covers the surface of the gate facing away from the substrate, and covers the sidewall of the gate adjacent to the n-stage stepped source trench; the sidewall of the gate trench adjacent to the first structural portion has a first doped region, a second doped region, and a third doped region, the first doped region and the second doped region are located between the third doped region and the first structural portion, and the first doped region and the second doped region are sequentially arranged in the first direction; the sidewall of the gate trench adjacent to the n-stage stepped source trench has a fourth doped region, and the bottom of the n-stage stepped source trench has a fifth doped region; an ohmic contact layer is disposed at the bottom of the n-stage stepped source trench, and a Schottky contact layer is disposed on the sidewall of the first-stage stepped source trench adjacent to the gate trench.

[0138] S104: A source electrode is formed in the n-level stepped source trench, and a drain electrode is formed on the side of the substrate away from the buffer layer.

[0139] Specifically, in the embodiments of the present invention, such as Figure 8 As shown, a gate trench 29 and an n-level stepped source trench 30 located at the bottom of the gate trench 29 are formed on the side of the current spreading layer 14 away from the substrate 11. In this embodiment of the invention, a single-level stepped source trench is used as an example for illustration.

[0140] like Figure 9 As shown, ion doping is performed step by step to form the first doped region 18, the second doped region 19, the third doped region 20, the fourth doped region 21, and the fifth doped region 22.

[0141] Wherein, the first doped region 18 is a low-doped region of the second doping type; the doping concentration of the first doped region 18 is 1E16cm. -3 -1E18cm -3 The doping depth of the first doped region 18 is 0.2um-1.5um.

[0142] The second doped region 19 is a highly doped region of the first doping type; the doping concentration of the second doped region 19 is 1E18cm⁻¹. -3 -5E20cm -3 The doping depth of the second doped region 19 is 0.1um-0.5um.

[0143] The third doped region 20 is a highly doped region of the second doping type; the doping concentration of the third doped region 20 is 1E17cm⁻¹. -3 -8E20cm -3 The doping depth of the third doped region 20 is 0.3um-1.5um.

[0144] The fourth doped region 21 is a highly doped region of the second doping type; the doping concentration of the fourth doped region 21 is 1E17cm. -3 -8E20cm -3 The doping depth of the fourth doped region 21 is 0.3-1.5 μm.

[0145] The fifth doped region 22 is a highly doped region of the second doping type. The doping concentration of the fifth doped region 22 is 1E16cm⁻¹. -3 -5E20cm -3 The doping depth of the fifth doping region 22 is 0.2um-1.5um.

[0146] Wherein, the first doping type is N-type doping, and the second doping type is P-type doping.

[0147] It should be noted that the third doped region 20 and the fourth doped region 21 can be a single doped region or two independent doped regions, and this is not limited in the embodiments of the present invention.

[0148] It should be noted that after ion implantation, activation annealing is required at 1650-1750℃, followed by sacrificial oxidation.

[0149] like Figure 10 As shown, a gate oxide layer 15, a gate 16, and an isolation dielectric layer 17 are formed in the gate trench 29, and an open gate contact hole is formed.

[0150] like Figure 11 As shown, contact metal is deposited to form an ohmic contact layer 23 and a Schottky contact layer 24 in an n-stage stepped source trench, followed by the deposition of a thick metal layer to form the source 25.

[0151] like Figure 1 As shown, a drain 26 is formed on the side of the substrate 11 away from the buffer layer 12.

[0152] As described above, in the trench MOSFET device provided by this embodiment, the n-stage stepped source trench 30 is located at the bottom of the gate trench 29, which is equivalent to the gate trench 29 and the n-stage stepped source trench 30 being inside the same trench. This can reduce the cell size, and the setting of the n-stage stepped source trench 30 can also make the highly doped fifth doped region 22 implanted at the bottom of the n-stage stepped source trench 30 deeper, so as to better protect and optimize the electric field distribution at the bottom of the gate oxide layer 15 of the gate trench. The gate 16 and the source 25 are isolated by an isolation dielectric layer 17. When the trench MOSFET device is forward-biased, the bottom of the gate trench 29 is far from the highly doped third doped region implanted at the bottom and sidewall of the n-stage stepped source trench 30. The regions 20 are at a certain distance, and the n-stage stepped source trench 30 is deeper. This highly doped third doped region 20 will not affect the current path near the bottom of the trench. At the same time, under the influence of the current extension layer 14, the current path from the vicinity of the channel to the bottom of the n-stage stepped source trench 30 is unobstructed. When the device is reverse-biased, compared with the structure where the gate and source are in two trenches, the source 25 and gate 16 of the present invention are in the same trench, the lateral distance between the source 25 and gate 16 is closer, and the n-stage stepped source trench 30 where the source 25 is located allows the highly doped fifth doped region 22 injected at the bottom of the n-stage stepped source trench 30 to be deeper, which can effectively and significantly alleviate the electric field concentration at the bottom of the gate trench 29 and better protect the gate oxide layer 15.

[0153] Furthermore, a Schottky diode is connected in antiparallel near the source 25, which can significantly reduce the diode voltage drop of the MOSFET transistor without affecting the cell size, improve the chip integration, and reduce the manufacturing cost of MOSFET devices with integrated Schottky diodes. Further improvements through multiple structures can further increase the current density, reduce the specific on-resistance, and the integration of Schottky diodes can significantly improve the Schottky contact area, further enhancing the reverse freewheeling capability of the Schottky diodes.

[0154] The trench MOSFET device and its fabrication method provided by the present invention have been described in detail above. Specific examples have been used to illustrate the principle and implementation of the present invention. The description of the above embodiments is only for the purpose of helping to understand the method and core idea of ​​the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation and application scope based on the idea of ​​the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

[0155] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to in the method section.

[0156] It should also be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that elements inherent to a process, method, article, or apparatus that comprises a list of elements, or elements inherent to such processes, methods, articles, or apparatus, are also included. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0157] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A trench MOSFET device, characterized in that, The trench MOSFET device includes: Substrate; In a first direction, a buffer layer, an epitaxial layer, and a current spreading layer are sequentially located on one side of the substrate; the current spreading layer has a gate trench on the side opposite to the substrate and an n-level stepped source trench located at the bottom of the gate trench, where n is a positive integer greater than or equal to 1; the first direction is perpendicular to the plane where the substrate is located and points from the substrate to the current spreading layer; A first structural portion located within the gate trench, the first structural portion including a gate oxide layer, a gate, and an isolation dielectric layer; wherein the gate oxide layer covers the bottom and sidewalls of the gate trench, the gate is located on the gate oxide layer, and the isolation dielectric layer covers the surface of the gate facing away from the substrate, and covers the sidewall of the gate adjacent to the n-stage stepped source trench. The sidewalls of the gate trench adjacent to the first structural portion have a first doped region, a second doped region, and a third doped region. The first doped region and the second doped region are located between the third doped region and the first structural portion, and the first doped region and the second doped region are arranged sequentially in the first direction. The sidewalls of the gate trench adjacent to the n-level stepped source trench have a fourth doped region, and the bottom of the n-level stepped source trench has a fifth doped region. An ohmic contact layer is provided at the bottom of the n-level stepped source trench, and a Schottky contact layer is provided on the sidewall of the first-level stepped source trench adjacent to the gate trench. The source electrode is located within the n-level stepped source trench, and the drain electrode is located on the side of the substrate opposite to the buffer layer.

2. The trench MOSFET device according to claim 1, characterized in that, The ohmic contact layer also extends onto the sidewall of the first-level stepped source trench adjacent to the first structural portion of the n-level stepped source trench.

3. The trench MOSFET device according to claim 1, characterized in that, The Schottky contact layer also extends onto the sidewall of the first-level stepped source trench adjacent to the first structural portion of the n-level stepped source trench.

4. The trench MOSFET device according to claim 2 or 3, characterized in that, The n-level stepped source trench is a two-level stepped source trench; The ohmic contact layer also extends to the sidewall of the second-level stepped source trench in the n-level stepped source trench.

5. The trench MOSFET device according to claim 4, characterized in that, The n-level stepped source trench is located in the middle region of the gate trench, and the first structural portion is located on one side of the n-level stepped source trench. The trench MOSFET device further includes: A second structural portion is located within the gate trench, and the second structural portion is located on the other side of the n-stage stepped source trench. The first structural portion and the second structural portion have the same structure. The sixth and seventh doped regions are located between the fourth doped region and the second structural portion, and the sixth and seventh doped regions are arranged sequentially in the first direction.

6. The trench MOSFET device according to claim 5, characterized in that, The first doped region is a low-doped region of the second doping type; The second doped region is a highly doped region of the first doping type; The third doping region is a highly doped region of the second doping type; The fourth doping region is a highly doped region of the second doping type; The fifth doping region is a highly doped region of the second doping type; The sixth doping region is a low-doped region of the second doping type; The seventh doping region is a highly doped region of the first doping type.

7. The trench MOSFET device according to claim 6, characterized in that, The doping concentration of the first doped region is 1E16cm. -3 -1E18cm -3 ; The doping concentration of the second doped region is 1E18cm. -3 -5E20cm -3 ; The doping concentration of the third doped region is 1E17cm⁻¹. -3 -8E20cm -3 ; The doping concentration of the fourth doped region is 1E17cm⁻¹. -3 -8E20cm -3 ; The doping concentration of the fifth doped region is 1E16cm⁻¹. -3 -5E20cm -3 ; The doping concentration of the sixth doped region is 1E16cm⁻¹ -3 -1E18cm -3 ; The doping concentration of the seventh doped region is 1E18cm⁻¹. -3 -5E20cm -3 .

8. The trench MOSFET device according to claim 7, characterized in that, The doping depth of the first doped region is 0.2µm-1.5µm; The doping depth of the second doped region is 0.1µm-0.5µm; The doping depth of the third doped region is 0.3µm-1.5µm; The doping depth of the fourth doping region is 0.3-1.5 μm; The doping depth of the fifth doping region is 0.2µm-1.5µm; The doping depth of the sixth doping region is 0.2µm-1.5µm; The doping depth of the seventh doping region is 0.1um-0.5um.

9. The trench MOSFET device according to claim 8, characterized in that, The first doping type is N-type doping, and the second doping type is P-type doping.

10. A method for fabricating a trench MOSFET device, characterized in that, The method for fabricating the trench MOSFET device according to any one of claims 1-9 comprises: Provide a substrate; In a first direction, a buffer layer, an epitaxial layer, and a current spreading layer are sequentially formed on one side of the substrate; the current spreading layer has a gate trench on the side opposite to the substrate and an n-level stepped source trench located at the bottom of the gate trench, where n is a positive integer greater than or equal to 1; the first direction is perpendicular to the plane where the substrate is located and points from the substrate to the current spreading layer; A subsequent structure is fabricated, wherein the subsequent structure includes a first structural portion located within the gate trench, the first structural portion including a gate oxide layer, a gate, and an isolation dielectric layer; wherein the gate oxide layer covers the bottom and sidewalls of the gate trench, the gate is located on the gate oxide layer, the isolation dielectric layer covers the surface of the gate facing away from the substrate, and covers the sidewall of the gate adjacent to the n-stage stepped source trench; the sidewall of the gate trench adjacent to the first structural portion has a first doped region, a second doped region, and a third doped region, the first doped region and the second doped region are located between the third doped region and the first structural portion, and the first doped region and the second doped region are sequentially arranged in the first direction; the sidewall of the gate trench adjacent to the n-stage stepped source trench has a fourth doped region, and the bottom of the n-stage stepped source trench has a fifth doped region; an ohmic contact layer is disposed at the bottom of the n-stage stepped source trench, and a Schottky contact layer is disposed on the sidewall of the first-stage stepped source trench adjacent to the gate trench; A source electrode is formed within the n-level stepped source trench, and a drain electrode is formed on the side of the substrate away from the buffer layer.

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